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Copy pathARM.CMSIS-FreeRTOS.pdsc
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ARM.CMSIS-FreeRTOS.pdsc
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<?xml version="1.0" encoding="utf-8"?>
<package schemaVersion="1.7.40" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="https://raw.githubusercontent.com/Open-CMSIS-Pack/Open-CMSIS-Pack-Spec/v1.7.40/schema/PACK.xsd">
<vendor>ARM</vendor>
<name>CMSIS-FreeRTOS</name>
<description>Bundle of FreeRTOS for Cortex-M and Cortex-A</description>
<license>LICENSE</license>
<licenseSets>
<licenseSet id="all" default="true" gating="true">
<license title="Apache 2.0 for CMSIS extensions" name="./LICENSE" spdx="Apache-2.0"/>
<license title="MIT License for FreeRTOS kernel" name="./Source/LICENSE.md" spdx="MIT"/>
</licenseSet>
</licenseSets>
<url>https://www.keil.com/pack/</url>
<releases>
<release version="0.0.0">
Active Development ...
</release>
</releases>
<requirements>
<packages>
<package vendor="ARM" name="CMSIS" version="6.0.0-0"/>
</packages>
</requirements>
<conditions>
<condition id="ARMCC6">
<accept Tcompiler="ARMCC" Toptions="AC6"/>
<accept Tcompiler="ARMCC" Toptions="AC6LTO"/>
</condition>
<condition id="GCC">
<accept Tcompiler="GCC"/>
<accept Tcompiler="CLANG"/>
</condition>
<condition id="IAR">
<require Tcompiler="IAR"/>
</condition>
<condition id="CM0">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device</description>
<accept Dcore="Cortex-M0"/>
<accept Dcore="Cortex-M0+"/>
<accept Dcore="SC000"/>
</condition>
<condition id="CM3">
<description>Cortex-M3 or SC300 processor based device</description>
<accept Dcore="Cortex-M3"/>
<accept Dcore="SC300"/>
</condition>
<condition id="CM4">
<description>Cortex-M4 processor based device</description>
<require Dcore="Cortex-M4" Dfpu="NO_FPU"/>
</condition>
<condition id="CM4_FP">
<description>Cortex-M4 processor based device using Floating Point Unit</description>
<require Dcore="Cortex-M4" Dfpu="FPU"/>
</condition>
<condition id="CM7">
<description>Cortex-M7 processor based device</description>
<require Dcore="Cortex-M7" Dfpu="NO_FPU"/>
</condition>
<condition id="CM7_SP">
<description>Cortex-M7 processor based device using Floating Point Unit (SP)</description>
<require Dcore="Cortex-M7" Dfpu="SP_FPU"/>
</condition>
<condition id="CM7_DP">
<description>Cortex-M7 processor based device using Floating Point Unit (DP)</description>
<require Dcore="Cortex-M7" Dfpu="DP_FPU"/>
</condition>
<condition id="CM23">
<description>Cortex-M23 processor based device</description>
<require Dcore="Cortex-M23"/>
</condition>
<condition id="CM23_NoTZ">
<description>Cortex-M23 processor based device without TrustZone</description>
<require condition="CM23"/>
<require Dtz="NO_TZ"/>
</condition>
<condition id="CM23_TZ">
<description>Cortex-M23 processor based device with TrustZone</description>
<require condition="CM23"/>
<require Dtz="TZ"/>
</condition>
<condition id="CM33">
<description>Cortex-M33 processor based device</description>
<require Dcore="Cortex-M33"/>
</condition>
<condition id="CM33_NoTZ">
<description>Cortex-M33 processor based device without TrustZone</description>
<require condition="CM33"/>
<require Dtz="NO_TZ"/>
</condition>
<condition id="CM33_TZ">
<description>Cortex-M33 processor based device with TrustZone</description>
<require condition="CM33"/>
<require Dtz="TZ"/>
</condition>
<condition id="CM35P">
<description>Cortex-M35P processor based device</description>
<require Dcore="Cortex-M35P"/>
</condition>
<condition id="CM35P_NoTZ">
<description>Cortex-M35P processor based device without TrustZone</description>
<require condition="CM35P"/>
<require Dtz="NO_TZ"/>
</condition>
<condition id="CM35P_TZ">
<description>Cortex-M35P processor based device with TrustZone</description>
<require condition="CM35P"/>
<require Dtz="TZ"/>
</condition>
<condition id="CM55">
<description>Cortex-M55 processor based device</description>
<require Dcore="Cortex-M55"/>
</condition>
<condition id="CM55_TZ">
<description>Cortex-M55 processor based device with TrustZone</description>
<require condition="CM55"/>
<require Dtz="TZ"/>
</condition>
<condition id="CM85">
<description>Cortex-M85 processor based device</description>
<require Dcore="Cortex-M85"/>
</condition>
<condition id="CM85_TZ">
<description>Cortex-M85 processor based device with TrustZone</description>
<require condition="CM85"/>
<require Dtz="TZ"/>
</condition>
<condition id="CA9_DP">
<description>Cortex-A9 processor based device using Floating Point Unit (DP)</description>
<require Dcore="Cortex-A9" Dfpu="DP_FPU"/>
</condition>
<!-- TrustZone -->
<condition id="No TrustZone">
<description>No TrustZone</description>
<require Dtz="NO_TZ"/>
</condition>
<condition id="TZ Disabled">
<description>TrustZone (Disabled)</description>
<require Dtz="TZ"/>
<require Dsecure="TZ-disabled"/>
</condition>
<condition id="TZ Secure Only">
<description>TrustZone (Secure Only)</description>
<require Dtz="TZ"/>
<require Dsecure="Secure-only"/>
</condition>
<condition id="TZ Secure">
<description>TrustZone (Secure)</description>
<require Dtz="TZ"/>
<require Dsecure="Secure"/>
</condition>
<condition id="TZ Non-secure">
<description>TrustZone (Non-secure)</description>
<require Dtz="TZ"/>
<require Dsecure="Non-secure"/>
</condition>
<!-- Arm Compiler 6 and GCC -->
<condition id="CM0_AC6_GCC">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM0"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM3_AC6_GCC">
<description>Cortex-M3 or SC300 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM3"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM4_AC6_GCC">
<description>Cortex-M4 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM4"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM4_FP_AC6_GCC">
<description>Cortex-M4 processor based device using Floating Point Unit for the ARM Compiler 6 and GCC</description>
<require condition="CM4_FP"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM7_AC6_GCC">
<description>Cortex-M7 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM7"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM7_SP_AC6_GCC">
<description>Cortex-M7 processor based device using Floating Point Unit (SP) for the ARM Compiler 6 and GCC</description>
<require condition="CM7_SP"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM7_DP_AC6_GCC">
<description>Cortex-M7 processor based device using Floating Point Unit (DP) for the ARM Compiler 6 and GCC</description>
<require condition="CM7_DP"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM23_AC6_GCC">
<description>Cortex-M23 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM23"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM23_NoTZ_AC6_GCC">
<description>Cortex-M23 processor based device without TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM23_NoTZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM23_TZ_AC6_GCC">
<description>Cortex-M23 processor based device with TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM23_TZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM33_AC6_GCC">
<description>Cortex-M33 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM33"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM33_NoTZ_AC6_GCC">
<description>Cortex-M33 processor based device without TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM33_NoTZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM33_TZ_AC6_GCC">
<description>Cortex-M33 processor based device with TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM33_TZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM35P_AC6_GCC">
<description>Cortex-M35P processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM35P"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM35P_NoTZ_AC6_GCC">
<description>Cortex-M35P processor based device without TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM35P_NoTZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM35P_TZ_AC6_GCC">
<description>Cortex-M35P processor based device with TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM35P_TZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM55_AC6_GCC">
<description>Cortex-M55 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM55"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM55_TZ_AC6_GCC">
<description>Cortex-M55 processor based device with TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM55_TZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM85_AC6_GCC">
<description>Cortex-M85 processor based device for the ARM Compiler 6 and GCC</description>
<require condition="CM85"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CM85_TZ_AC6_GCC">
<description>Cortex-M85 processor based device with TrustZone for the ARM Compiler 6 and GCC</description>
<require condition="CM85_TZ"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<condition id="CA9_DP_AC6_GCC">
<description>Cortex-A9 processor based device using Floating Point Unit (DP) for the ARM Compiler 6 and GCC</description>
<require condition="CA9_DP"/>
<accept condition="ARMCC6"/>
<accept condition="GCC"/>
</condition>
<!-- IAR compiler -->
<condition id="CM0_IAR">
<description>Cortex-M0 or Cortex-M0+ or SC000 processor based device for the IAR Compiler</description>
<require condition="CM0"/>
<require condition="IAR"/>
</condition>
<condition id="CM3_IAR">
<description>Cortex-M3 or SC300 processor based device for the IAR Compiler</description>
<require condition="CM3"/>
<require condition="IAR"/>
</condition>
<condition id="CM4_IAR">
<description>Cortex-M4 processor based device for the IAR Compiler</description>
<require condition="CM4"/>
<require condition="IAR"/>
</condition>
<condition id="CM4_FP_IAR">
<description>Cortex-M4 processor based device using Floating Point Unit for the IAR Compiler</description>
<require condition="CM4_FP"/>
<require condition="IAR"/>
</condition>
<condition id="CM7_IAR">
<description>Cortex-M7 processor based device for the IAR Compiler</description>
<require condition="CM7"/>
<require condition="IAR"/>
</condition>
<condition id="CM7_SP_IAR">
<description>Cortex-M7 processor based device using Floating Point Unit (SP) for the IAR Compiler</description>
<require condition="CM7_SP"/>
<require condition="IAR"/>
</condition>
<condition id="CM7_DP_IAR">
<description>Cortex-M7 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
<require condition="CM7_DP"/>
<require condition="IAR"/>
</condition>
<condition id="CM23_IAR">
<description>Cortex-M23 processor based device for the IAR Compiler</description>
<require condition="CM23"/>
<require condition="IAR"/>
</condition>
<condition id="CM23_NoTZ_IAR">
<description>Cortex-M23 processor based device without TrustZone for the IAR Compiler</description>
<require condition="CM23_NoTZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM23_TZ_IAR">
<description>Cortex-M23 processor based device with TrustZone for the IAR Compiler</description>
<require condition="CM23_TZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM33_IAR">
<description>Cortex-M33 processor based device for the IAR Compiler</description>
<require condition="CM33"/>
<require condition="IAR"/>
</condition>
<condition id="CM33_NoTZ_IAR">
<description>Cortex-M33 processor based device without TrustZone for the IAR Compiler</description>
<require condition="CM33_NoTZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM33_TZ_IAR">
<description>Cortex-M33 processor based device with TrustZone for the IAR Compiler</description>
<require condition="CM33_TZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM35P_IAR">
<description>Cortex-M35P processor based device for the IAR Compiler</description>
<require condition="CM35P"/>
<require condition="IAR"/>
</condition>
<condition id="CM35P_NoTZ_IAR">
<description>Cortex-M35P processor based device without TrustZone for the IAR Compiler</description>
<require condition="CM35P_NoTZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM35P_TZ_IAR">
<description>Cortex-M35P processor based device with TrustZone for the IAR Compiler</description>
<require condition="CM35P_TZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM55_IAR">
<description>Cortex-M55 processor based device for the IAR Compiler</description>
<require condition="CM55"/>
<require condition="IAR"/>
</condition>
<condition id="CM55_TZ_IAR">
<description>Cortex-M55 processor based device with TrustZone for the IAR Compiler</description>
<require condition="CM55_TZ"/>
<require condition="IAR"/>
</condition>
<condition id="CM85_IAR">
<description>Cortex-M85 processor based device for the IAR Compiler</description>
<require condition="CM85"/>
<require condition="IAR"/>
</condition>
<condition id="CM85_TZ_IAR">
<description>Cortex-M85 processor based device with TrustZone for the IAR Compiler</description>
<require condition="CM85_TZ"/>
<require condition="IAR"/>
</condition>
<condition id="CA9_DP_IAR">
<description>Cortex-A9 processor based device using Floating Point Unit (DP) for the IAR Compiler</description>
<require condition="CA9_DP"/>
<require condition="IAR"/>
</condition>
<!-- FreeRTOS ports for the Arm Cortex core -->
<condition id="FreeRTOS Port Cortex-M0">
<description>Requirements for FreeRTOS port for Cortex-M0 and Cortex-M0+</description>
<accept condition="CM0_AC6_GCC"/>
<accept condition="CM0_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M0 MPU">
<description>Requirements for FreeRTOS port for Cortex-M0+ using MPU</description>
<accept condition="CM0_AC6_GCC"/>
</condition>
<condition id="FreeRTOS Port Cortex-M3">
<description>Requirements for FreeRTOS port for Cortex-M3</description>
<accept condition="CM3_AC6_GCC"/>
<accept condition="CM3_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M3 MPU">
<description>Requirements for FreeRTOS port for Cortex-M3 using MPU</description>
<accept condition="CM3_AC6_GCC"/>
</condition>
<condition id="FreeRTOS Port Cortex-M4">
<description>Requirements for FreeRTOS port for Cortex-M4</description>
<accept condition="CM4_AC6_GCC"/>
<accept condition="CM4_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M4 MPU">
<description>Requirements for FreeRTOS port for Cortex-M4 using MPU</description>
<accept condition="CM4_AC6_GCC"/>
</condition>
<condition id="FreeRTOS Port Cortex-M4 FPU">
<description>Requirements for FreeRTOS port for Cortex-M4 using FPU</description>
<accept condition="CM4_FP_AC6_GCC"/>
<accept condition="CM4_FP_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M4 FPU MPU">
<description>Requirements for FreeRTOS port for Cortex-M4 using FPU and MPU</description>
<accept condition="CM4_FP_AC6_GCC"/>
<accept condition="CM4_FP_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M7">
<description>Requirements for FreeRTOS port for Cortex-M7</description>
<accept condition="CM7_AC6_GCC"/>
<accept condition="CM7_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M7 FPU SP">
<description>Requirements for FreeRTOS port for Cortex-M7 using FPU (SP)</description>
<accept condition="CM7_SP_AC6_GCC"/>
<accept condition="CM7_SP_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M7 FPU DP">
<description>Requirements for FreeRTOS port for Cortex-M7 using FPU (DP)</description>
<accept condition="CM7_DP_AC6_GCC"/>
<accept condition="CM7_DP_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M23">
<description>Requirements for FreeRTOS port for Cortex-M23</description>
<accept condition="CM23_AC6_GCC"/>
<accept condition="CM23_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M23 NoTZ">
<description>Requirements for FreeRTOS port for Cortex-M23 without TrustZone</description>
<accept condition="CM23_NoTZ_AC6_GCC"/>
<accept condition="CM23_NoTZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M23 TZ">
<description>Requirements for FreeRTOS port for Cortex-M23 with TrustZone</description>
<accept condition="CM23_TZ_AC6_GCC"/>
<accept condition="CM23_TZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M33">
<description>Requirements for FreeRTOS port for Cortex-M33</description>
<accept condition="CM33_AC6_GCC"/>
<accept condition="CM33_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M33 NoTZ">
<description>Requirements for FreeRTOS port for Cortex-M33 without TrustZone</description>
<accept condition="CM33_NoTZ_AC6_GCC"/>
<accept condition="CM33_NoTZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M33 TZ">
<description>Requirements for FreeRTOS port for Cortex-M33 with TrustZone</description>
<accept condition="CM33_TZ_AC6_GCC"/>
<accept condition="CM33_TZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M35P">
<description>Requirements for FreeRTOS port for Cortex-M35P</description>
<accept condition="CM35P_AC6_GCC"/>
<accept condition="CM35P_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M35P NoTZ">
<description>Requirements for FreeRTOS port for Cortex-M35P without TrustZone</description>
<accept condition="CM35P_NoTZ_AC6_GCC"/>
<accept condition="CM35P_NoTZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M35P TZ">
<description>Requirements for FreeRTOS port for Cortex-M35P with TrustZone</description>
<accept condition="CM35P_TZ_AC6_GCC"/>
<accept condition="CM35P_TZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M55 TZ">
<description>Requirements for FreeRTOS port for Cortex-M55 with TrustZone</description>
<accept condition="CM55_TZ_AC6_GCC"/>
<accept condition="CM55_TZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M85 TZ">
<description>Requirements for FreeRTOS port for Cortex-M85 with TrustZone</description>
<accept condition="CM85_TZ_AC6_GCC"/>
<accept condition="CM85_TZ_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-A9 FPU DP">
<description>Requirements for FreeRTOS port for Cortex-A9 using FPU (DP)</description>
<accept condition="CA9_DP_AC6_GCC"/>
<accept condition="CA9_DP_IAR"/>
</condition>
<condition id="FreeRTOS Port Cortex-M v6_v7">
<description>Requirements for FreeRTOS port for Cortex-M v6 and v7</description>
<accept condition="FreeRTOS Port Cortex-M0"/>
<accept condition="FreeRTOS Port Cortex-M3"/>
<accept condition="FreeRTOS Port Cortex-M4"/>
<accept condition="FreeRTOS Port Cortex-M4 FPU"/>
<accept condition="FreeRTOS Port Cortex-M7"/>
<accept condition="FreeRTOS Port Cortex-M7 FPU SP"/>
<accept condition="FreeRTOS Port Cortex-M7 FPU DP"/>
</condition>
<condition id="FreeRTOS Port Cortex-M v6_v7 MPU">
<description>Requirements for FreeRTOS port for Cortex-M v6 and v7 using MPU</description>
<accept condition="FreeRTOS Port Cortex-M0 MPU"/>
<accept condition="FreeRTOS Port Cortex-M3 MPU"/>
<accept condition="FreeRTOS Port Cortex-M4 MPU"/>
<accept condition="FreeRTOS Port Cortex-M4 FPU MPU"/>
</condition>
<condition id="FreeRTOS Port Cortex-M v8">
<description>Requirements for FreeRTOS port for Cortex-M v8</description>
<accept condition="FreeRTOS Port Cortex-M23"/>
<accept condition="FreeRTOS Port Cortex-M23 NoTZ"/>
<accept condition="FreeRTOS Port Cortex-M23 TZ"/>
<accept condition="FreeRTOS Port Cortex-M33"/>
<accept condition="FreeRTOS Port Cortex-M33 NoTZ"/>
<accept condition="FreeRTOS Port Cortex-M33 TZ"/>
<accept condition="FreeRTOS Port Cortex-M35P"/>
<accept condition="FreeRTOS Port Cortex-M35P NoTZ"/>
<accept condition="FreeRTOS Port Cortex-M35P TZ"/>
<accept condition="FreeRTOS Port Cortex-M55 TZ"/>
<accept condition="FreeRTOS Port Cortex-M85 TZ"/>
</condition>
<condition id="FreeRTOS Port Cortex-M v8 TZ">
<description>Requirements for FreeRTOS port for Cortex-M v8 with TrustZone</description>
<accept condition="FreeRTOS Port Cortex-M23 TZ"/>
<accept condition="FreeRTOS Port Cortex-M33 TZ"/>
<accept condition="FreeRTOS Port Cortex-M35P TZ"/>
<accept condition="FreeRTOS Port Cortex-M55 TZ"/>
<accept condition="FreeRTOS Port Cortex-M85 TZ"/>
</condition>
<condition id="FreeRTOS Port Cortex-A">
<description>Requirements for FreeRTOS port for Cortex-A</description>
<accept condition="FreeRTOS Port Cortex-A9 FPU DP"/>
</condition>
<condition id="FreeRTOS Port Cortex-M">
<description>Requirements for FreeRTOS port for Cortex-M</description>
<accept condition="FreeRTOS Port Cortex-M v6_v7"/>
<accept condition="FreeRTOS Port Cortex-M v8"/>
</condition>
<condition id="FreeRTOS Port Cortex-M MPU">
<description>FreeRTOS ports for Arm Cortex that support MPU</description>
<accept condition="FreeRTOS Port Cortex-M v6_v7 MPU"/>
<accept condition="FreeRTOS Port Cortex-M v8"/>
</condition>
<condition id="FreeRTOS Port">
<description>FreeRTOS ports for Arm Cortex combined</description>
<accept condition="FreeRTOS Port Cortex-A"/>
<accept condition="FreeRTOS Port Cortex-M"/>
</condition>
<!-- Conditions for RTOS::FreeRTOS components -->
<condition id="FreeRTOS Message or Stream Buffer API">
<description>FreeRTOS Message or Stream Buffer component</description>
<accept Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Message Buffer"/>
<accept Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Stream Buffer"/>
</condition>
<condition id="FreeRTOS Core CA">
<description>Requirements for FreeRTOS Core for Cortex-A</description>
<require condition="FreeRTOS Port Cortex-A"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
</condition>
<condition id="FreeRTOS Core CM">
<description>Requirements for FreeRTOS Core for Cortex-M</description>
<require condition="FreeRTOS Port Cortex-M"/>
<accept condition="No TrustZone"/>
<accept condition="TZ Disabled"/>
<accept condition="TZ Secure Only"/>
<accept condition="TZ Secure"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
</condition>
<condition id="FreeRTOS Core CM TZ_NS">
<description>Requirements for FreeRTOS Core for Cortex-M with TrustZone in Non-Secure Domain</description>
<require condition="FreeRTOS Port Cortex-M v8 TZ"/>
<require condition="TZ Non-secure"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
</condition>
<condition id="FreeRTOS Core CM MPU">
<description>Requirements for FreeRTOS Core with MPU support for Cortex-M</description>
<require condition="FreeRTOS Port Cortex-M MPU"/>
<accept condition="No TrustZone"/>
<accept condition="TZ Disabled"/>
<accept condition="TZ Secure Only"/>
<accept condition="TZ Secure"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
<require condition="FreeRTOS Message or Stream Buffer API"/>
</condition>
<condition id="FreeRTOS Core CM MPU TZ_NS">
<description>Requirements for FreeRTOS Core for Cortex-M with MPU support and TrustZone in Non-Secure Domain</description>
<require condition="FreeRTOS Port Cortex-M v8 TZ"/>
<require condition="TZ Non-secure"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
<require condition="FreeRTOS Message or Stream Buffer API"/>
</condition>
<condition id="FreeRTOS Core TZ">
<description>Requirements for FreeRTOS Core with TrustZone support</description>
<require condition="FreeRTOS Port Cortex-M v8 TZ"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
</condition>
<condition id="FreeRTOS Core TZ MPU">
<description>Requirements for FreeRTOS Core with TrustZone and MPU support</description>
<require condition="FreeRTOS Port Cortex-M v8 TZ"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
<require condition="FreeRTOS Message or Stream Buffer API"/>
</condition>
<condition id="FreeRTOS Config Native">
<description>Components required for FreeRTOS Config Native variant</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Config CMSIS RTOS2">
<description>Components required for FreeRTOS Config CMSIS RTOS2 variant</description>
<require condition="FreeRTOS Port"/>
<require Cclass="CMSIS" Cgroup="RTOS2" Csub="FreeRTOS"/>
</condition>
<condition id="FreeRTOS Coroutines">
<description>Components required for FreeRTOS Coroutines</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Event Groups">
<description>Components required for FreeRTOS Event Groups</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Heap">
<description>Components required for FreeRTOS Heap</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Message Buffer">
<description>Components required for FreeRTOS Message Buffer</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Stream Buffer">
<description>Components required for FreeRTOS Stream Buffer</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS Timers">
<description>Components required for FreeRTOS Timers</description>
<require condition="FreeRTOS Port"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
</condition>
<condition id="FreeRTOS TrustZone">
<description>Components required for FreeRTOS TrustZone</description>
<require condition="FreeRTOS Port Cortex-M v8 TZ"/>
<!-- TrustZone Secure Context is a standalone component -->
<deny Cclass="CMSIS" Cgroup="RTOS2" Csub="FreeRTOS"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Coroutines"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Heap"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Message Buffer"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Stream Buffer"/>
<deny Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
</condition>
<condition id="CMSIS RTOS2 FreeRTOS CortexM">
<description>Components required for CMSIS RTOS2 API on top of FreeRTOS for Cortex-M</description>
<require condition="FreeRTOS Port Cortex-M"/>
<require Cclass="CMSIS" Cgroup="OS Tick"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config" Cvariant="CMSIS RTOS2"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
</condition>
<condition id="CMSIS RTOS2 FreeRTOS CortexA">
<description>Components required for CMSIS RTOS2 API on top of FreeRTOS for Cortex-A</description>
<require condition="FreeRTOS Port Cortex-A"/>
<require Cclass="CMSIS" Cgroup="OS Tick"/>
<require Cclass="Device" Cgroup="IRQ Controller"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Config" Cvariant="CMSIS RTOS2"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Core"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Event Groups"/>
<require Cclass="RTOS" Cbundle="FreeRTOS" Cgroup="Timers"/>
</condition>
</conditions>
<components>
<!-- CMSIS-RTOS2 FreeRTOS component -->
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="FreeRTOS" Cvariant="Cortex-M" Cversion="11.2.0" Capiversion="2.3.0" condition="CMSIS RTOS2 FreeRTOS CortexM">
<description>CMSIS-RTOS2 implementation for Cortex-M based on FreeRTOS</description>
<RTE_Components_h>
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_FreeRTOS /* CMSIS-RTOS2 FreeRTOS */
</RTE_Components_h>
<files>
<file category="doc" name="Documentation/html/index.html"/>
<file category="header" name="CMSIS/RTOS2/FreeRTOS/Include/freertos_mpool.h"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/cmsis_os2.c"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/clib_os.c"/>
</files>
</component>
<component Cclass="CMSIS" Cgroup="RTOS2" Csub="FreeRTOS" Cvariant="Cortex-A" Cversion="11.2.0" Capiversion="2.3.0" condition="CMSIS RTOS2 FreeRTOS CortexA">
<description>CMSIS-RTOS2 implementation for Cortex-A based on FreeRTOS</description>
<RTE_Components_h>
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_FreeRTOS /* CMSIS-RTOS2 FreeRTOS */
</RTE_Components_h>
<files>
<file category="doc" name="Documentation/html/index.html"/>
<file category="header" name="CMSIS/RTOS2/FreeRTOS/Include/freertos_mpool.h"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/cmsis_os2.c"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/clib_os.c"/>
<file category="source" attr="config" name="CMSIS/RTOS2/FreeRTOS/Source/handlers.c" version="9.1.0"/>
</files>
</component>
<bundle Cbundle="FreeRTOS" Cclass="RTOS" Cversion="11.2.0">
<description>FreeRTOS Real Time Kernel</description>
<doc>https://www.freertos.org/RTOS.html</doc>
<component Cgroup="Core" Cvariant="Cortex-M" isDefaultVariant="true" condition="FreeRTOS Core CM">
<description>Core API (Kernel, Tasks, Semaphores, Mutexes, Queues) for Cortex-M</description>
<RTE_Components_h>
#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */
</RTE_Components_h>
<files>
<file category="include" name="Source/include/"/>
<file category="header" name="Source/include/FreeRTOS.h"/>
<file category="header" name="Source/include/queue.h"/>
<file category="header" name="Source/include/semphr.h"/>
<file category="header" name="Source/include/task.h"/>
<file category="source" name="Source/list.c"/>
<file category="source" name="Source/queue.c"/>
<file category="source" name="Source/tasks.c"/>
<file category="include" condition="CM0_AC6_GCC" name="Source/portable/GCC/ARM_CM0/"/>
<file category="source" condition="CM0_AC6_GCC" name="Source/portable/GCC/ARM_CM0/port.c"/>
<file category="source" condition="CM0_AC6_GCC" name="Source/portable/GCC/ARM_CM0/portasm.c"/>
<file category="include" condition="CM3_AC6_GCC" name="Source/portable/GCC/ARM_CM3/"/>
<file category="source" condition="CM3_AC6_GCC" name="Source/portable/GCC/ARM_CM3/port.c"/>
<file category="include" condition="CM4_AC6_GCC" name="Source/portable/GCC/ARM_CM3/"/>
<file category="source" condition="CM4_AC6_GCC" name="Source/portable/GCC/ARM_CM3/port.c"/>
<file category="include" condition="CM4_FP_AC6_GCC" name="Source/portable/GCC/ARM_CM4F/"/>
<file category="source" condition="CM4_FP_AC6_GCC" name="Source/portable/GCC/ARM_CM4F/port.c"/>
<file category="include" condition="CM7_AC6_GCC" name="Source/portable/GCC/ARM_CM3/"/>
<file category="source" condition="CM7_AC6_GCC" name="Source/portable/GCC/ARM_CM3/port.c"/>
<file category="include" condition="CM7_DP_AC6_GCC" name="Source/portable/GCC/ARM_CM7/r0p1/"/>
<file category="source" condition="CM7_DP_AC6_GCC" name="Source/portable/GCC/ARM_CM7/r0p1/port.c"/>
<file category="include" condition="CM7_SP_AC6_GCC" name="Source/portable/GCC/ARM_CM7/r0p1/"/>
<file category="source" condition="CM7_SP_AC6_GCC" name="Source/portable/GCC/ARM_CM7/r0p1/port.c"/>
<file category="include" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23_NTZ/non_secure/"/>
<file category="source" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c"/>
<file category="source" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c"/>
<file category="include" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33_NTZ/non_secure/"/>
<file category="source" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c"/>
<file category="source" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c"/>
<file category="include" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P_NTZ/non_secure/"/>
<file category="source" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P_NTZ/non_secure/port.c"/>
<file category="source" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P_NTZ/non_secure/portasm.c"/>
<file category="include" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55_NTZ/non_secure/"/>
<file category="source" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55_NTZ/non_secure/port.c"/>
<file category="source" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55_NTZ/non_secure/portasm.c"/>
<file category="include" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85_NTZ/non_secure/"/>
<file category="source" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85_NTZ/non_secure/port.c"/>
<file category="source" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85_NTZ/non_secure/portasm.c"/>
<file category="include" condition="CM0_IAR" name="Source/portable/IAR/ARM_CM0/"/>
<file category="source" condition="CM0_IAR" name="Source/portable/IAR/ARM_CM0/port.c"/>
<file category="sourceAsm" condition="CM0_IAR" name="Source/portable/IAR/ARM_CM0/portasm.s"/>
<file category="include" condition="CM3_IAR" name="Source/portable/IAR/ARM_CM3/"/>
<file category="source" condition="CM3_IAR" name="Source/portable/IAR/ARM_CM3/port.c"/>
<file category="sourceAsm" condition="CM3_IAR" name="Source/portable/IAR/ARM_CM3/portasm.s"/>
<file category="include" condition="CM4_IAR" name="Source/portable/IAR/ARM_CM3/"/>
<file category="source" condition="CM4_IAR" name="Source/portable/IAR/ARM_CM3/port.c"/>
<file category="sourceAsm" condition="CM4_IAR" name="Source/portable/IAR/ARM_CM3/portasm.s"/>
<file category="include" condition="CM4_FP_IAR" name="Source/portable/IAR/ARM_CM4F/"/>
<file category="source" condition="CM4_FP_IAR" name="Source/portable/IAR/ARM_CM4F/port.c"/>
<file category="sourceAsm" condition="CM4_FP_IAR" name="Source/portable/IAR/ARM_CM4F/portasm.s"/>
<file category="include" condition="CM7_IAR" name="Source/portable/IAR/ARM_CM3/"/>
<file category="source" condition="CM7_IAR" name="Source/portable/IAR/ARM_CM3/port.c"/>
<file category="sourceAsm" condition="CM7_IAR" name="Source/portable/IAR/ARM_CM3/portasm.s"/>
<file category="include" condition="CM7_DP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/"/>
<file category="source" condition="CM7_DP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/port.c"/>
<file category="sourceAsm" condition="CM7_DP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/portasm.s"/>
<file category="include" condition="CM7_SP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/"/>
<file category="source" condition="CM7_SP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/port.c"/>
<file category="sourceAsm" condition="CM7_SP_IAR" name="Source/portable/IAR/ARM_CM7/r0p1/portasm.s"/>
<file category="include" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23_NTZ/non_secure/"/>
<file category="source" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c"/>
<file category="source" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s"/>
<file category="include" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33_NTZ/non_secure/"/>
<file category="source" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c"/>
<file category="source" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s"/>
<file category="include" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P_NTZ/non_secure/"/>
<file category="source" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P_NTZ/non_secure/port.c"/>
<file category="source" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P_NTZ/non_secure/portasm.s"/>
<file category="include" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55_NTZ/non_secure/"/>
<file category="source" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55_NTZ/non_secure/port.c"/>
<file category="source" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55_NTZ/non_secure/portasm.s"/>
<file category="include" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85_NTZ/non_secure/"/>
<file category="source" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85_NTZ/non_secure/port.c"/>
<file category="source" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85_NTZ/non_secure/portasm.s"/>
<file category="include" name="CMSIS/RTOS2/FreeRTOS/Include/"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/freertos_evr.c"/>
<file category="other" name="CMSIS/RTOS2/FreeRTOS/FreeRTOS.scvd"/>
</files>
</component>
<component Cgroup="Core" Cvariant="Cortex-M" condition="FreeRTOS Core CM TZ_NS">
<description>Core API (Kernel, Tasks, Semaphores, Mutexes, Queues) for Cortex-M in Non-Secure Domain (TrustZone)</description>
<RTE_Components_h>
#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */
#define RTE_RTOS_FreeRTOS_CORE_TZ_NS /* RTOS FreeRTOS Core with TrustZone Non-Secure Domain */
</RTE_Components_h>
<files>
<file category="include" name="Source/include/"/>
<file category="header" name="Source/include/FreeRTOS.h"/>
<file category="header" name="Source/include/queue.h"/>
<file category="header" name="Source/include/semphr.h"/>
<file category="header" name="Source/include/task.h"/>
<file category="source" name="Source/list.c"/>
<file category="source" name="Source/queue.c"/>
<file category="source" name="Source/tasks.c"/>
<file category="include" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23/secure/"/>
<file category="include" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23/non_secure/"/>
<file category="source" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23/non_secure/port.c"/>
<file category="source" condition="CM23_AC6_GCC" name="Source/portable/GCC/ARM_CM23/non_secure/portasm.c"/>
<file category="include" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33/secure/"/>
<file category="include" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33/non_secure/"/>
<file category="source" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33/non_secure/port.c"/>
<file category="source" condition="CM33_AC6_GCC" name="Source/portable/GCC/ARM_CM33/non_secure/portasm.c"/>
<file category="include" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P/secure/"/>
<file category="include" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P/non_secure/"/>
<file category="source" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P/non_secure/port.c"/>
<file category="source" condition="CM35P_AC6_GCC" name="Source/portable/GCC/ARM_CM35P/non_secure/portasm.c"/>
<file category="include" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55/secure/"/>
<file category="include" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55/non_secure/"/>
<file category="source" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55/non_secure/port.c"/>
<file category="source" condition="CM55_AC6_GCC" name="Source/portable/GCC/ARM_CM55/non_secure/portasm.c"/>
<file category="include" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85/secure/"/>
<file category="include" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85/non_secure/"/>
<file category="source" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85/non_secure/port.c"/>
<file category="source" condition="CM85_AC6_GCC" name="Source/portable/GCC/ARM_CM85/non_secure/portasm.c"/>
<file category="include" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23/secure/"/>
<file category="include" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23/non_secure/"/>
<file category="source" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23/non_secure/port.c"/>
<file category="sourceAsm" condition="CM23_IAR" name="Source/portable/IAR/ARM_CM23/non_secure/portasm.s"/>
<file category="include" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33/secure/"/>
<file category="include" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33/non_secure/"/>
<file category="source" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33/non_secure/port.c"/>
<file category="sourceAsm" condition="CM33_IAR" name="Source/portable/IAR/ARM_CM33/non_secure/portasm.s"/>
<file category="include" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P/secure/"/>
<file category="include" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P/non_secure/"/>
<file category="source" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P/non_secure/port.c"/>
<file category="sourceAsm" condition="CM35P_IAR" name="Source/portable/IAR/ARM_CM35P/non_secure/portasm.s"/>
<file category="include" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55/secure/"/>
<file category="include" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55/non_secure/"/>
<file category="source" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55/non_secure/port.c"/>
<file category="sourceAsm" condition="CM55_IAR" name="Source/portable/IAR/ARM_CM55/non_secure/portasm.s"/>
<file category="include" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85/secure/"/>
<file category="include" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85/non_secure/"/>
<file category="source" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85/non_secure/port.c"/>
<file category="sourceAsm" condition="CM85_IAR" name="Source/portable/IAR/ARM_CM85/non_secure/portasm.s"/>
<file category="include" name="CMSIS/RTOS2/FreeRTOS/Include/"/>
<file category="source" name="CMSIS/RTOS2/FreeRTOS/Source/freertos_evr.c"/>
<file category="other" name="CMSIS/RTOS2/FreeRTOS/FreeRTOS.scvd"/>
</files>
</component>
<component Cgroup="Core" Cvariant="Cortex-M MPU" condition="FreeRTOS Core CM MPU">
<description>Core API (Kernel, Tasks, Semaphores, Mutexes, Queues) for Cortex-M using MPU</description>
<RTE_Components_h>
#define RTE_RTOS_FreeRTOS_CORE /* RTOS FreeRTOS Core */
#define RTE_RTOS_FreeRTOS_CORE_MPU /* RTOS FreeRTOS Core with MPU support */
</RTE_Components_h>
<files>
<file category="include" name="Source/include/"/>
<file category="header" name="Source/include/FreeRTOS.h"/>
<file category="header" name="Source/include/queue.h"/>
<file category="header" name="Source/include/semphr.h"/>
<file category="header" name="Source/include/task.h"/>
<file category="source" name="Source/list.c"/>
<file category="source" name="Source/queue.c"/>
<file category="source" name="Source/tasks.c"/>
<file category="source" name="Source/portable/Common/mpu_wrappers.c"/>
<file category="source" name="Source/portable/Common/mpu_wrappers_v2.c"/>