diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt index 0a2f39ea0b3..5c9e756148a 100644 --- a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/CMakeLists.txt @@ -3,6 +3,8 @@ if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_DISCO_H747I) +elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_PORTENTA_H7) elseif("NUCLEO_H743ZI" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_NUCLEO_H743ZI) elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS) @@ -10,12 +12,12 @@ elseif("NUCLEO_H743ZI2" IN_LIST MBED_TARGET_LABELS) endif() target_include_directories(mbed-emac - PRIVATE + INTERFACE . ./lan8742 ) target_sources(mbed-emac - PRIVATE + INTERFACE lan8742/lan8742.c ) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/CMakeLists.txt b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/CMakeLists.txt new file mode 100644 index 00000000000..5e6c9d6be72 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-emac + INTERFACE + stm32h7_eth_init.c +) diff --git a/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c new file mode 100644 index 00000000000..4f674d0aef9 --- /dev/null +++ b/connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c @@ -0,0 +1,177 @@ +/* mbed Microcontroller Library + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#define ETHERNET 1 + +#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT + +#include "stm32h7xx_hal.h" +#include "portenta_power.h" + +#define ETH_TX_EN_Pin GPIO_PIN_11 +#define ETH_TX_EN_GPIO_Port GPIOG +#define ETH_TXD1_Pin GPIO_PIN_12 +#define ETH_TXD1_GPIO_Port GPIOG +#define ETH_TXD0_Pin GPIO_PIN_13 +#define ETH_TXD0_GPIO_Port GPIOG +#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1 +#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC +#define ETH_MDIO_Pin GPIO_PIN_2 +#define ETH_MDIO_GPIO_Port GPIOA +#define ETH_REF_CLK_Pin GPIO_PIN_1 +#define ETH_REF_CLK_GPIO_Port GPIOA +#define ETH_CRS_DV_Pin GPIO_PIN_7 +#define ETH_CRS_DV_GPIO_Port GPIOA +#define ETH_RXD0_Pin GPIO_PIN_4 +#define ETH_RXD0_GPIO_Port GPIOC +#define ETH_RXD1_Pin GPIO_PIN_5 +#define ETH_RXD1_GPIO_Port GPIOC + +/** + * Override HAL Eth Init function + */ +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + GPIO_InitTypeDef GPIO_InitStruct; + if(heth->Instance == ETH) + { + enableEthPowerSupply(); + + #if !(defined(DUAL_CORE) && defined(CORE_CM4)) + /* Disable DCache for STM32H7 family */ + SCB_DisableDCache(); + #endif + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOA_CLK_ENABLE(); + // __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOG_CLK_ENABLE(); + // __HAL_RCC_GPIOH_CLK_ENABLE(); + + /* Enable Peripheral clock */ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); + __HAL_RCC_ETH1TX_CLK_ENABLE(); + __HAL_RCC_ETH1RX_CLK_ENABLE(); + + /* Set pinstrap for 100mbit */ + // TODO + + /* Reset ETH Phy */ + __HAL_RCC_GPIOJ_CLK_ENABLE(); + GPIO_InitTypeDef gpio_eth_rst_init_structure; + gpio_eth_rst_init_structure.Pin = GPIO_PIN_15; + gpio_eth_rst_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_eth_rst_init_structure.Pull = GPIO_NOPULL; + gpio_eth_rst_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOJ, &gpio_eth_rst_init_structure); + + gpio_eth_rst_init_structure.Pin = ETH_RXD0_Pin | ETH_RXD1_Pin; + HAL_GPIO_Init(GPIOC, &gpio_eth_rst_init_structure); + HAL_GPIO_WritePin(GPIOC, ETH_RXD0_Pin, 1); + HAL_GPIO_WritePin(GPIOC, ETH_RXD1_Pin, 1); + gpio_eth_rst_init_structure.Pin = ETH_CRS_DV_Pin; + HAL_GPIO_Init(GPIOA, &gpio_eth_rst_init_structure); + HAL_GPIO_WritePin(GPIOA, ETH_CRS_DV_Pin, 1); + + HAL_Delay(25); + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); + HAL_Delay(100); + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 1); + + /**ETH GPIO Configuration + PG11 ------> ETH_TX_EN + PG12 ------> ETH_TXD1 + PG13 ------> ETH_TXD0 + PC1 ------> ETH_MDC + PA2 ------> ETH_MDIO + PA1 ------> ETH_REF_CLK + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + */ + GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + + GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF11_ETH; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + } +} + +/** + * Override HAL Eth DeInit function + */ +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + if(heth->Instance == ETH) + { + /* Peripheral clock disable */ + __HAL_RCC_ETH1MAC_CLK_DISABLE(); + __HAL_RCC_ETH1TX_CLK_DISABLE(); + __HAL_RCC_ETH1RX_CLK_DISABLE(); + + /**ETH GPIO Configuration + PG11 ------> ETH_TX_EN + PG12 ------> ETH_TXD1 + PG13 ------> ETH_TXD0 + PC1 ------> ETH_MDC + PA2 ------> ETH_MDIO + PA1 ------> ETH_REF_CLK + PA7 ------> ETH_CRS_DV + PC4 ------> ETH_RXD0 + PC5 ------> ETH_RXD1 + */ + HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin); + + HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin); + + HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin); + + HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0); + } +} + +#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */ diff --git a/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp b/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp index 9068ac697ee..356576dd21d 100644 --- a/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp +++ b/connectivity/drivers/emac/TARGET_STM/stm32xx_emac.cpp @@ -654,8 +654,10 @@ int STM32_EMAC::low_level_input(emac_mem_buf_t **buf) /* Build Rx descriptor to be ready for next data reception */ HAL_ETH_BuildRxDescriptors(&EthHandle); +#if !(defined(DUAL_CORE) && defined(CORE_CM4)) /* Invalidate data cache for ETH Rx Buffers */ SCB_InvalidateDCache_by_Addr((uint32_t *)RxBuff.buffer, frameLength); +#endif *buf = pbuf_alloc(PBUF_RAW, frameLength, PBUF_POOL); if (*buf) { diff --git a/connectivity/lwipstack/mbed_lib.json b/connectivity/lwipstack/mbed_lib.json index c94c4201530..c8829b6c5ce 100644 --- a/connectivity/lwipstack/mbed_lib.json +++ b/connectivity/lwipstack/mbed_lib.json @@ -210,6 +210,9 @@ "MIMXRT1050_EVK": { "mem-size": 36560 }, + "PORTENTA_H7": { + "mem-size": 16000 + }, "FVP_MPS2_M3": { "mem-size": 36560 }, diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/CMakeLists.txt index 52495298cac..a5cc6182bca 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/CMakeLists.txt @@ -3,12 +3,18 @@ if("DISCO_H747I" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_DISCO_H747I) -elseif("STM32H747xI_CM4" IN_LIST MBED_TARGET_LABELS) - add_subdirectory(TARGET_STM32H747xI_CM4) +elseif("PORTENTA_H7" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_PORTENTA_H7) elseif("STM32H7A3xIQ" IN_LIST MBED_TARGET_LABELS) add_subdirectory(TARGET_STM32H7A3xIQ) endif() +if("STM32H747xI_CM7" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_STM32H747xI_CM7) +elseif("STM32H747xI_CM4" IN_LIST MBED_TARGET_LABELS) + add_subdirectory(TARGET_STM32H747xI_CM4) +endif() + target_sources(mbed-core INTERFACE system_clock.c diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/CMakeLists.txt new file mode 100644 index 00000000000..583f0fa6e5a --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2020 ARM Limited. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +target_sources(mbed-core + INTERFACE + PeripheralPins.c + system_clock_override.c + portenta_power.cpp +) + +target_include_directories(mbed-core + INTERFACE + . +) + diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c new file mode 100644 index 00000000000..1daec1a199f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PeripheralPins.c @@ -0,0 +1,583 @@ +/* mbed Microcontroller Library + * SPDX-License-Identifier: BSD-3-Clause + ****************************************************************************** + * + * Copyright (c) 2016-2020 STMicroelectronics. + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + * + * Automatically generated from STM32CubeMX/db/mcu/STM32H747XIHx.xml + */ + +#include "PeripheralPins.h" +#include "mbed_toolchain.h" + +//============================================================================== +// Notes +// +// - The pins mentioned Px_y_ALTz are alternative possibilities which use other +// HW peripheral instances. You can use them the same way as any other "normal" +// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board +// pinout image on mbed.org. +// +// - The pins which are connected to other components present on the board have +// the comment "Connected to xxx". The pin function may not work properly in this +// case. These pins may not be displayed on the board pinout image on mbed.org. +// Please read the board reference manual and schematic for more information. +// +// - Warning: pins connected to the default STDIO_UART_TX and STDIO_UART_RX pins are commented +// See https://os.mbed.com/teams/ST/wiki/STDIO for more information. +// +//============================================================================== + + +//*** ADC *** + +MBED_WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INP16 + {PA_0C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_INP0 + {PA_0C_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INN1 + {PA_0C_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INN1 + {PA_0C_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC2_INP0 + {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC1_INN16 + {PA_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC1_INP17 + {PA_1C, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_INP1 + {PA_1C_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC2_INP1 + {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_INP14 + {PA_2_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC2_INP14 + {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_INP15 + {PA_3_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC2_INP15 + {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INP18 + {PA_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INP18 + {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC1_INN18 + {PA_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC1_INP19 + {PA_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC2_INN18 + {PA_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC2_INP19 + {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INP3 + {PA_6_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INP3 + {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_INN3 + {PA_7_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_INP7 + {PA_7_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC2_INN3 + {PA_7_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC2_INP7 + {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INN5 + {PB_0_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_INP9 + {PB_0_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INN5 + {PB_0_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC2_INP9 + {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_INP5 + {PB_1_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC2_INP5 + {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INP10 + {PC_0_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INP10 + {PC_0_ALT1, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INP10 + {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_INN10 + {PC_1_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INP11 + {PC_1_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC2_INN10 + {PC_1_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INP11 + {PC_1_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC3_INN10 + {PC_1_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INP11 + {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_INN11 + {PC_2_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INP12 + {PC_2_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC2_INN11 + {PC_2_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INP12 + {PC_2_ALT3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC3_INN11 + {PC_2_ALT4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC3_INP12 + {PC_2C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC3_INP0 + {PC_2C_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INN1 + {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_INN12 + {PC_3_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_INP13 + {PC_3_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC2_INN12 + {PC_3_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC2_INP13 + {PC_3C, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC3_INP1 + {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INP4 + {PC_4_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INP4 + {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_INN4 + {PC_5_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_INP8 + {PC_5_ALT1, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC2_INN4 + {PC_5_ALT2, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC2_INP8 + {PF_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INP5 + {PF_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC3_INN5 + {PF_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC3_INP9 + {PF_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INP4 + {PF_6, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC3_INN4 + {PF_6_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC3_INP8 + {PF_7, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INP3 + {PF_8, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC3_INP7 + {PF_8_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC3_INN3 + {PF_9, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INP2 + {PF_10, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC3_INP6 + {PF_10_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC3_INN2 + {PF_11, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INP2 + {PF_12, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_INN2 + {PF_12_ALT0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_INP6 + {PF_13, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INP2 + {PF_14, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC2_INN2 + {PF_14_ALT0, ADC_2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC2_INP6 + {PH_2, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INP13 + {PH_3, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC3_INN13 + {PH_3_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INP14 + {PH_4, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC3_INN14 + {PH_4_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INP15 + {PH_5, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC3_INN15 + {PH_5_ALT0, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // ADC3_INP16 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_ADC_Internal[] = { + {ADC_TEMP, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // ADC3_INP18 + {ADC_VREF, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 19, 0)}, // ADC3_INP19 + {ADC_VBAT, ADC_3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // ADC3_INP17 + {NC, NC, 0} +}; + +//*** DAC *** + +MBED_WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC1_OUT1 + {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC1_OUT2 + {NC, NC, 0} +}; + +//*** I2C *** + +MBED_WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_7_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_9_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PD_13, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_0, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_15, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_5, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_6_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)}, + {PB_8_ALT0, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C4)}, + {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PD_12, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PF_1, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PF_14, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {PH_4, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)}, + {PH_7, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)}, + {PH_11, I2C_4, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C4)}, + {NC, NC, 0} +}; + +//*** PWM *** + +// TIM5 cannot be used because already used by the us_ticker +// TIM2 cannot be used because already used by the us_ticker (DUAL_CORE) +MBED_WEAK const PinMap PinMap_PWM[] = { +// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 +// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 +// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N +// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 +// {PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 +// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 +// {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT0, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT2, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 +// {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 +// {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 +// {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT1, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PB_6_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PB_7_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PB_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PB_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 +// {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 +// {PB_11, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_14_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_14_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_15_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_15_ALT1, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 + {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PC_6_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PC_7_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PC_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PC_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 + {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 + {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 + {PE_4, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N + {PE_5, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 + {PE_6, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 + {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 + {PF_6, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 0)}, // TIM16_CH1 + {PF_7, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 0)}, // TIM17_CH1 + {PF_8, PWM_13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_8_ALT0, PWM_16, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM16, 1, 1)}, // TIM16_CH1N + {PF_9, PWM_14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PF_9_ALT0, PWM_17, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM17, 1, 1)}, // TIM17_CH1N + {PH_6, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 1, 0)}, // TIM12_CH1 + {PH_9, PWM_12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM12, 2, 0)}, // TIM12_CH2 +// {PH_10, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 +// {PH_11, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 +// {PH_12, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PH_13, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N +// {PI_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + {PI_5, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PI_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PI_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PJ_6, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_7, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PJ_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PJ_8_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 + {PJ_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 + {PJ_9_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PJ_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PJ_10_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 + {PJ_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 + {PJ_11_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PK_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PK_0_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 + {PK_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 + {PK_1_ALT0, PWM_8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {NC, NC, 0} +}; + +//*** SERIAL *** + +MBED_WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_9_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_12, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PA_15, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_4, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_6_ALT0, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_6_ALT1, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_13, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_14, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_10_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_8, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_1, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_14, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_13, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_8, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_10_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_UART4)}, + {PB_3, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF11_UART7)}, + {PB_5, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PB_7_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_LPUART)}, + {PB_8, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF14_UART5)}, + {PB_15, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)}, + {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PC_11_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PD_2, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_9, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PE_0, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_7, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_6, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_9, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PH_14, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PI_9, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PJ_9, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_12_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PA_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_14, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_14_ALT0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_8, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_12, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_15, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_8, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_8, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, + {PA_11_ALT0, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_LPUART)}, + {PB_0, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PB_13, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PB_15, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)}, + {PC_9, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)}, + {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)}, + {PD_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)}, + {PD_14, UART_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART8)}, + {PE_10, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PF_9, UART_7, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_UART7)}, + {PG_13, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {PG_15, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART6)}, + {NC, NC, 0} +}; + +//*** SPI *** + +MBED_WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_7_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_2, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI3)}, + {PB_5_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI3)}, + {PD_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_9, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PF_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_14, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PI_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_10, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_6_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_8, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_9, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_12, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PJ_11, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_5_ALT0, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, +// {PA_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PB_3_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_7, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PG_13, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PH_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_1, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_0, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_4_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF8_SPI6)}, + {PA_11, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)}, + {PA_15_ALT1, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI6)}, + {PB_4, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF7_SPI2)}, + {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)}, + {PF_6, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PG_8, SPI_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI6)}, + {PG_10, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)}, + {PH_5, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {PI_0, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)}, + {PK_1, SPI_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI5)}, + {NC, NC, 0} +}; + +//*** CAN *** + +MBED_WEAK const PinMap PinMap_CAN_RD[] = { + {PA_11, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_5, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_8, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_12, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_0, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_14, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PI_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_CAN_TD[] = { + {PA_12, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_6, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PB_9, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PB_13, CAN_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN2)}, + {PD_1, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {PH_13, CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_FDCAN1)}, + {NC, NC, 0} +}; + +//*** QUADSPI *** + +MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = { + {PC_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PD_11, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 + {PF_8, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = { + {PC_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PD_12, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 + {PF_9, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = { + {PE_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {PF_7, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = { + {PA_1, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PF_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = { + {PB_2, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {PF_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK + {NC, NC, 0} +}; + +MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = { + {PB_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {PB_10, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_NCS + {PG_6, QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_FS[] = { +// {PA_8, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_SOF +// {PA_9, USB_FS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS +// {PA_10, USB_FS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_ID + {PA_11, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DM + {PA_12, USB_FS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG1_FS)}, // USB_OTG_FS_DP + {NC, NC, 0} +}; + +//*** USBDEVICE *** + +MBED_WEAK const PinMap PinMap_USB_HS[] = { +#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) +// {PA_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_ID + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DM + {PB_15, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF12_OTG2_FS)}, // USB_OTG_HS_DP +#else /* MBED_CONF_TARGET_USB_SPEED */ + {PA_3, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D0 + {PA_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_CK + {PB_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D1 + {PB_1, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D2 + {PB_5, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D7 + {PB_10, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D3 + {PB_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D4 + {PB_12, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D5 + {PB_13, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_D6 + {PC_0, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_STP + {PH_4, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_NXT + {PI_11, USB_HS, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OTG2_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* MBED_CONF_TARGET_USB_SPEED */ + {NC, NC, 0} +}; diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h new file mode 100644 index 00000000000..bae7470d57b --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/PinNames.h @@ -0,0 +1,450 @@ +/* mbed Microcontroller Library + ******************************************************************************* + * Copyright (c) 2018, STMicroelectronics + * Copyright (c) 2020, Arduino SA + * + * SPDX-License-Identifier: BSD-3-Clause + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + ******************************************************************************* + */ +#ifndef MBED_PINNAMES_H +#define MBED_PINNAMES_H + +#include "cmsis.h" +#include "PinNamesTypes.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define ALTC 0xF00 + +typedef enum { + ALT0 = 0x100, + ALT1 = 0x200, + ALT2 = 0x300, + ALT3 = 0x400, + ALT4 = 0x500, +} ALTx; + +typedef enum { + + PA_0 = 0x00, + PA_0C = PA_0 | ALTC, // dual pad + PA_0C_ALT0 = PA_0C | ALT0, // same pin used for alternate HW + PA_0C_ALT1 = PA_0C | ALT1, // same pin used for alternate HW + PA_0C_ALT2 = PA_0C | ALT2, // same pin used for alternate HW + PA_1 = 0x01, + PA_1C = PA_1 | ALTC, // dual pad + PA_1C_ALT0 = PA_1C | ALT0, // same pin used for alternate HW + PA_1_ALT0 = PA_1 | ALT0, // same pin used for alternate HW + PA_2 = 0x02, + PA_2_ALT0 = PA_2 | ALT0, // same pin used for alternate HW + PA_3 = 0x03, + PA_3_ALT0 = PA_3 | ALT0, // same pin used for alternate HW + PA_4 = 0x04, + PA_4_ALT0 = PA_4 | ALT0, // same pin used for alternate HW + PA_4_ALT1 = PA_4 | ALT1, // same pin used for alternate HW + PA_5 = 0x05, + PA_5_ALT0 = PA_5 | ALT0, // same pin used for alternate HW + PA_5_ALT1 = PA_5 | ALT1, // same pin used for alternate HW + PA_5_ALT2 = PA_5 | ALT2, // same pin used for alternate HW + PA_6 = 0x06, + PA_6_ALT0 = PA_6 | ALT0, // same pin used for alternate HW + PA_7 = 0x07, + PA_7_ALT0 = PA_7 | ALT0, // same pin used for alternate HW + PA_7_ALT1 = PA_7 | ALT1, // same pin used for alternate HW + PA_7_ALT2 = PA_7 | ALT2, // same pin used for alternate HW + PA_8 = 0x08, + PA_9 = 0x09, + PA_9_ALT0 = PA_9 | ALT0, // same pin used for alternate HW + PA_10 = 0x0A, + PA_10_ALT0 = PA_10 | ALT0, // same pin used for alternate HW + PA_11 = 0x0B, + PA_11_ALT0 = PA_11 | ALT0, // same pin used for alternate HW + PA_12 = 0x0C, + PA_12_ALT0 = PA_12 | ALT0, // same pin used for alternate HW + PA_13 = 0x0D, + PA_14 = 0x0E, + PA_15 = 0x0F, + PA_15_ALT0 = PA_15 | ALT0, // same pin used for alternate HW + PA_15_ALT1 = PA_15 | ALT1, // same pin used for alternate HW + PB_0 = 0x10, + PB_0_ALT0 = PB_0 | ALT0, // same pin used for alternate HW + PB_0_ALT1 = PB_0 | ALT1, // same pin used for alternate HW + PB_0_ALT2 = PB_0 | ALT2, // same pin used for alternate HW + PB_1 = 0x11, + PB_1_ALT0 = PB_1 | ALT0, // same pin used for alternate HW + PB_1_ALT1 = PB_1 | ALT1, // same pin used for alternate HW + PB_2 = 0x12, + PB_3 = 0x13, + PB_3_ALT0 = PB_3 | ALT0, // same pin used for alternate HW + PB_3_ALT1 = PB_3 | ALT1, // same pin used for alternate HW + PB_4 = 0x14, + PB_4_ALT0 = PB_4 | ALT0, // same pin used for alternate HW + PB_4_ALT1 = PB_4 | ALT1, // same pin used for alternate HW + PB_5 = 0x15, + PB_5_ALT0 = PB_5 | ALT0, // same pin used for alternate HW + PB_5_ALT1 = PB_5 | ALT1, // same pin used for alternate HW + PB_6 = 0x16, + PB_6_ALT0 = PB_6 | ALT0, // same pin used for alternate HW + PB_6_ALT1 = PB_6 | ALT1, // same pin used for alternate HW + PB_7 = 0x17, + PB_7_ALT0 = PB_7 | ALT0, // same pin used for alternate HW + PB_8 = 0x18, + PB_8_ALT0 = PB_8 | ALT0, // same pin used for alternate HW + PB_9 = 0x19, + PB_9_ALT0 = PB_9 | ALT0, // same pin used for alternate HW + PB_10 = 0x1A, + PB_11 = 0x1B, + PB_12 = 0x1C, + PB_13 = 0x1D, + PB_14 = 0x1E, + PB_14_ALT0 = PB_14 | ALT0, // same pin used for alternate HW + PB_14_ALT1 = PB_14 | ALT1, // same pin used for alternate HW + PB_15 = 0x1F, + PB_15_ALT0 = PB_15 | ALT0, // same pin used for alternate HW + PB_15_ALT1 = PB_15 | ALT1, // same pin used for alternate HW + PC_0 = 0x20, + PC_0_ALT0 = PC_0 | ALT0, // same pin used for alternate HW + PC_0_ALT1 = PC_0 | ALT1, // same pin used for alternate HW + PC_1 = 0x21, + PC_1_ALT0 = PC_1 | ALT0, // same pin used for alternate HW + PC_1_ALT1 = PC_1 | ALT1, // same pin used for alternate HW + PC_1_ALT2 = PC_1 | ALT2, // same pin used for alternate HW + PC_1_ALT3 = PC_1 | ALT3, // same pin used for alternate HW + PC_1_ALT4 = PC_1 | ALT4, // same pin used for alternate HW + PC_2 = 0x22, + PC_2C = PC_2 | ALTC, // dual pad + PC_2C_ALT0 = PC_2C | ALT0, // same pin used for alternate HW + PC_2_ALT0 = PC_2 | ALT0, // same pin used for alternate HW + PC_2_ALT1 = PC_2 | ALT1, // same pin used for alternate HW + PC_2_ALT2 = PC_2 | ALT2, // same pin used for alternate HW + PC_2_ALT3 = PC_2 | ALT3, // same pin used for alternate HW + PC_2_ALT4 = PC_2 | ALT4, // same pin used for alternate HW + PC_3 = 0x23, + PC_3C = PC_3 | ALTC, // dual pad + PC_3_ALT0 = PC_3 | ALT0, // same pin used for alternate HW + PC_3_ALT1 = PC_3 | ALT1, // same pin used for alternate HW + PC_3_ALT2 = PC_3 | ALT2, // same pin used for alternate HW + PC_4 = 0x24, + PC_4_ALT0 = PC_4 | ALT0, // same pin used for alternate HW + PC_5 = 0x25, + PC_5_ALT0 = PC_5 | ALT0, // same pin used for alternate HW + PC_5_ALT1 = PC_5 | ALT1, // same pin used for alternate HW + PC_5_ALT2 = PC_5 | ALT2, // same pin used for alternate HW + PC_6 = 0x26, + PC_6_ALT0 = PC_6 | ALT0, // same pin used for alternate HW + PC_7 = 0x27, + PC_7_ALT0 = PC_7 | ALT0, // same pin used for alternate HW + PC_8 = 0x28, + PC_8_ALT0 = PC_8 | ALT0, // same pin used for alternate HW + PC_9 = 0x29, + PC_9_ALT0 = PC_9 | ALT0, // same pin used for alternate HW + PC_10 = 0x2A, + PC_10_ALT0 = PC_10 | ALT0, // same pin used for alternate HW + PC_11 = 0x2B, + PC_11_ALT0 = PC_11 | ALT0, // same pin used for alternate HW + PC_12 = 0x2C, + PC_13 = 0x2D, + PC_14 = 0x2E, + PC_15 = 0x2F, + PD_0 = 0x30, + PD_1 = 0x31, + PD_2 = 0x32, + PD_3 = 0x33, + PD_4 = 0x34, + PD_5 = 0x35, + PD_6 = 0x36, + PD_7 = 0x37, + PD_8 = 0x38, + PD_9 = 0x39, + PD_10 = 0x3A, + PD_11 = 0x3B, + PD_12 = 0x3C, + PD_13 = 0x3D, + PD_14 = 0x3E, + PD_15 = 0x3F, + PE_0 = 0x40, + PE_1 = 0x41, + PE_2 = 0x42, + PE_3 = 0x43, + PE_4 = 0x44, + PE_5 = 0x45, + PE_6 = 0x46, + PE_7 = 0x47, + PE_8 = 0x48, + PE_9 = 0x49, + PE_10 = 0x4A, + PE_11 = 0x4B, + PE_12 = 0x4C, + PE_13 = 0x4D, + PE_14 = 0x4E, + PE_15 = 0x4F, + PF_0 = 0x50, + PF_1 = 0x51, + PF_2 = 0x52, + PF_3 = 0x53, + PF_4 = 0x54, + PF_4_ALT0 = PF_4 | ALT0, // same pin used for alternate HW + PF_5 = 0x55, + PF_6 = 0x56, + PF_6_ALT0 = PF_6 | ALT0, // same pin used for alternate HW + PF_7 = 0x57, + PF_8 = 0x58, + PF_8_ALT0 = PF_8 | ALT0, // same pin used for alternate HW + PF_9 = 0x59, + PF_9_ALT0 = PF_9 | ALT0, // same pin used for alternate HW + PF_10 = 0x5A, + PF_10_ALT0 = PF_10 | ALT0, // same pin used for alternate HW + PF_11 = 0x5B, + PF_12 = 0x5C, + PF_12_ALT0 = PF_12 | ALT0, // same pin used for alternate HW + PF_13 = 0x5D, + PF_14 = 0x5E, + PF_14_ALT0 = PF_14 | ALT0, // same pin used for alternate HW + PF_15 = 0x5F, + PG_0 = 0x60, + PG_1 = 0x61, + PG_2 = 0x62, + PG_3 = 0x63, + PG_4 = 0x64, + PG_5 = 0x65, + PG_6 = 0x66, + PG_7 = 0x67, + PG_8 = 0x68, + PG_9 = 0x69, + PG_10 = 0x6A, + PG_11 = 0x6B, + PG_12 = 0x6C, + PG_13 = 0x6D, + PG_14 = 0x6E, + PG_15 = 0x6F, + PH_0 = 0x70, + PH_1 = 0x71, + PH_2 = 0x72, + PH_3 = 0x73, + PH_3_ALT0 = PH_3 | ALT0, // same pin used for alternate HW + PH_4 = 0x74, + PH_4_ALT0 = PH_4 | ALT0, // same pin used for alternate HW + PH_5 = 0x75, + PH_5_ALT0 = PH_5 | ALT0, // same pin used for alternate HW + PH_6 = 0x76, + PH_7 = 0x77, + PH_8 = 0x78, + PH_9 = 0x79, + PH_10 = 0x7A, + PH_11 = 0x7B, + PH_12 = 0x7C, + PH_13 = 0x7D, + PH_14 = 0x7E, + PH_15 = 0x7F, + PI_0 = 0x80, + PI_1 = 0x81, + PI_2 = 0x82, + PI_3 = 0x83, + PI_4 = 0x84, + PI_5 = 0x85, + PI_6 = 0x86, + PI_7 = 0x87, + PI_8 = 0x88, + PI_9 = 0x89, + PI_10 = 0x8A, + PI_11 = 0x8B, + PI_12 = 0x8C, + PI_13 = 0x8D, + PI_14 = 0x8E, + PI_15 = 0x8F, + PJ_0 = 0x90, + PJ_1 = 0x91, + PJ_2 = 0x92, + PJ_3 = 0x93, + PJ_4 = 0x94, + PJ_5 = 0x95, + PJ_6 = 0x96, + PJ_7 = 0x97, + PJ_8 = 0x98, + PJ_8_ALT0 = PJ_8 | ALT0, // same pin used for alternate HW + PJ_9 = 0x99, + PJ_9_ALT0 = PJ_9 | ALT0, // same pin used for alternate HW + PJ_10 = 0x9A, + PJ_10_ALT0 = PJ_10 | ALT0, // same pin used for alternate HW + PJ_11 = 0x9B, + PJ_11_ALT0 = PJ_11 | ALT0, // same pin used for alternate HW + PJ_12 = 0x9C, + PJ_13 = 0x9D, + PJ_14 = 0x9E, + PJ_15 = 0x9F, + PK_0 = 0xA0, + PK_0_ALT0 = PK_0 | ALT0, // same pin used for alternate HW + PK_1 = 0xA1, + PK_1_ALT0 = PK_1 | ALT0, // same pin used for alternate HW + PK_2 = 0xA2, + PK_3 = 0xA3, + PK_4 = 0xA4, + PK_5 = 0xA5, + PK_6 = 0xA6, + PK_7 = 0xA7, + + WL_REG_ON = PJ_1, + WL_HOST_WAKE = PJ_5, + WL_SDIO_0 = PC_8, + WL_SDIO_1 = PC_9, + WL_SDIO_2 = PC_10, + WL_SDIO_3 = PC_11, + WL_SDIO_CMD = PD_2, + WL_SDIO_CLK = PC_12, + + // ADC internal channels + ADC_TEMP = 0xF0, + ADC_VREF = 0xF1, + ADC_VBAT = 0xF2, + + // STDIO for console print +#ifdef MBED_CONF_TARGET_STDIO_UART_TX + STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX, +#else + STDIO_UART_TX = PA_9, +#endif +#ifdef MBED_CONF_TARGET_STDIO_UART_RX + STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX, +#else + STDIO_UART_RX = PA_10, +#endif + + //Led mappings + LED_RED = PK_5, //Red + LED_GREEN = PK_6, //Green + LED_BLUE = PK_7, //Blue + + //mbed original LED naming + LED1 = LED_RED, + LED2 = LED_GREEN, + LED3 = LED_BLUE, + + CYBSP_BT_UART_RX = PF_6, + CYBSP_BT_UART_TX = PA_15, + CYBSP_BT_UART_RTS = PF_8, + CYBSP_BT_UART_CTS = PF_9, + + CYBSP_BT_POWER = PJ_12, + CYBSP_BT_HOST_WAKE = PJ_13, + CYBSP_BT_DEVICE_WAKE = PJ_14, + + USER_BUTTON = PC_13, + // Standardized button names + BUTTON1 = USER_BUTTON, + SERIAL_TX = STDIO_UART_TX, // Virtual Com Port + SERIAL_RX = STDIO_UART_RX, // Virtual Com Port + USBTX = STDIO_UART_TX, // Virtual Com Port + USBRX = STDIO_UART_RX, // Virtual Com Port + I2C_SCL = PB_6, + I2C_SDA = PB_7, + PWM_OUT = PD_15, + + /**** QSPI FLASH pins ****/ + QSPI_FLASH1_IO0 = PD_11, + QSPI_FLASH1_IO1 = PD_12, + QSPI_FLASH1_IO2 = PF_7, + QSPI_FLASH1_IO3 = PD_13, + QSPI_FLASH1_SCK = PF_10, + QSPI_FLASH1_CSN = PG_6, + + /**** USB pins ****/ + USB_OTG_FS_DM = PA_11, + USB_OTG_FS_DP = PA_12, + USB_OTG_FS_ID = PA_10, + USB_OTG_FS_SOF = PA_8, + USB_OTG_FS_VBUS = PA_9, + USB_OTG_HS_DM = PB_14, + USB_OTG_HS_DP = PB_15, + USB_OTG_HS_ID = PB_12, + USB_OTG_HS_SOF = PA_4, + USB_OTG_HS_ULPI_CK = PA_5, + USB_OTG_HS_ULPI_D0 = PA_3, + USB_OTG_HS_ULPI_D1 = PB_0, + USB_OTG_HS_ULPI_D2 = PB_1, + USB_OTG_HS_ULPI_D3 = PB_10, + USB_OTG_HS_ULPI_D4 = PB_11, + USB_OTG_HS_ULPI_D5 = PB_12, + USB_OTG_HS_ULPI_D6 = PB_13, + USB_OTG_HS_ULPI_D7 = PB_5, + USB_OTG_HS_ULPI_DIR = PC_2, + USB_OTG_HS_ULPI_NXT = PC_3, + USB_OTG_HS_ULPI_STP = PC_0, + USB_OTG_HS_VBUS = PB_13, + + /**** ETHERNET pins ****/ + ETH_MDC = PC_1, + ETH_MDIO = PA_2, + ETH_CRS_DV = PA_7, + ETH_REF_CLK = PA_1, + ETH_RXD0 = PC_4, + ETH_RXD1 = PC_5, + ETH_RX_CLK = PA_1, + ETH_TXD0 = PG_13, + ETH_TXD1 = PG_12, + ETH_TX_EN = PG_11, + + /**** OSCILLATOR pins ****/ + RCC_OSC32_IN = PC_14, + RCC_OSC32_OUT = PC_15, + RCC_OSC_IN = PH_0, + RCC_OSC_OUT = PH_1, + + /**** DEBUG pins ****/ + SYS_JTCK_SWCLK = PA_14, + SYS_JTDI = PA_15, + SYS_JTDO_SWO = PB_3, + SYS_JTMS_SWDIO = PA_13, + SYS_JTRST = PB_4, + SYS_PVD_IN = PB_7, + SYS_TRACECLK = PE_2, + SYS_TRACED0 = PE_3, + SYS_TRACED0_ALT0 = PC_1, + SYS_TRACED0_ALT1 = PG_13, + SYS_TRACED1 = PE_4, + SYS_TRACED1_ALT0 = PC_8, + SYS_TRACED1_ALT1 = PG_14, + SYS_TRACED2 = PE_5, + SYS_TRACED2_ALT0 = PD_2, + SYS_TRACED3 = PE_6, + SYS_TRACED3_ALT0 = PC_12, + SYS_TRGIO = PC_7, + SYS_WKUP0 = PA_0, + SYS_WKUP1 = PA_2, + SYS_WKUP2 = PC_13, + SYS_WKUP5 = PC_1, + + // Not connected + NC = (int)0xFFFFFFFF +} PinName; + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp new file mode 100644 index 00000000000..0d430bfc95d --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp @@ -0,0 +1,52 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +/****************************************************************************** + INCLUDE + ******************************************************************************/ + +#include "mbed.h" +#include "portenta_power.h" + +/****************************************************************************** + PUBLIC MEMBER FUNCTIONS + ******************************************************************************/ +void enableEthPowerSupply(void) +{ + /* Ensure ETH power supply */ + mbed::I2C i2c(PB_7, PB_6); + + char data[2]; + + // LDO3 to 1.2V + data[0]=0x52; + data[1]=0x9; + i2c.write(8 << 1, data, sizeof(data)); + data[0]=0x53; + data[1]=0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW2 to 3.3V (SW2_VOLT) + data[0]=0x3B; + data[1]=0xF; + i2c.write(8 << 1, data, sizeof(data)); + + // SW1 to 3.0V (SW1_VOLT) + data[0]=0x35; + data[1]=0xF; + i2c.write(8 << 1, data, sizeof(data)); + +} diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.h new file mode 100644 index 00000000000..ca8a4e48383 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.h @@ -0,0 +1,31 @@ +/* + Copyright (c) 2019-2020, Arduino SA + SPDX-License-Identifier: Apache-2.0 + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + + You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, + either express or implied. + + See the License for the specific language governing permissions and limitations under the License. +*/ + +#ifndef PORTENTA_POWER +#define PORTENTA_POWER + + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +extern void enableEthPowerSupply(void); + +#if defined(__cplusplus) +} +#endif + +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c new file mode 100644 index 00000000000..3b2a5304620 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c @@ -0,0 +1,306 @@ +/* + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2019 STMicroelectronics. + *

© Copyright (c) 2020 Arduino SA. + * All rights reserved.

+ * + * SPDX-License-Identifier: BSD-3-Clause + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** +*/ + +/** + * This file configures the system clock as follows: + *-------------------------------------------------------------------- + * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock) + * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal) + * | 3- USE_PLL_HSI (internal 64 MHz clock) + *-------------------------------------------------------------------- + * SYSCLK(MHz) | 480 + * AHBCLK (MHz) | 240 + * APB1CLK (MHz) | 120 + * APB2CLK (MHz) | 120 + * APB3CLK (MHz) | 120 + * APB4CLK (MHz) | 120 + * USB capable (48 MHz) | YES + *-------------------------------------------------------------------- +**/ + +#include "stm32h7xx.h" +#include "nvic_addr.h" +#include "mbed_error.h" + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + +// clock source is selected with CLOCK_SOURCE in json config +#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO) +#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default) +#define USE_PLL_HSI 0x2 // Use HSI internal clock + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +uint8_t SetSysClock_PLL_HSI(void); +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ + +void SetSysClock(void) +{ + + bool lowspeed = false; +#if defined(LOWSPEED) && (LOWSPEED == 1) + lowspeed = true; +#endif + +#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) + /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ + if (SetSysClock_PLL_HSE(1, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) + /* 2- If fail try to start with HSE and external xtal */ + if (SetSysClock_PLL_HSE(0, lowspeed) == 0) +#endif + { +#if ((CLOCK_SOURCE) & USE_PLL_HSI) + /* 3- If fail start with HSI clock */ + if (SetSysClock_PLL_HSI() == 0) +#endif + { + error("SetSysClock failed\n"); + } + } + } +} + +static const uint32_t _keep; +bool isBootloader() { + return ((uint32_t)&_keep < 0x8040000); +} + +bool isBetaBoard() { + uint8_t* bootloader_data = (uint8_t*)(0x801F000); + if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { + return true; + } else { + return (bootloader_data[10] == 27); + } +} + +#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) ) +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration + if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) { + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) + { + return 0; + } + } + + /* Enable oscillator pin */ + __HAL_RCC_GPIOH_CLK_ENABLE(); + GPIO_InitTypeDef gpio_osc_init_structure; + gpio_osc_init_structure.Pin = GPIO_PIN_1; + gpio_osc_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + gpio_osc_init_structure.Pull = GPIO_PULLUP; + gpio_osc_init_structure.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOH, &gpio_osc_init_structure); + HAL_Delay(10); + HAL_GPIO_WritePin(GPIOH, GPIO_PIN_1, 1); + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO); +#endif + /* Configure the main internal regulator output voltage */ + + if (lowspeed) { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3); + } else { + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + } + + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; + if (bypass) { + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; + } else { + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + } + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 40; + } else { + RCC_OscInitStruct.PLL.PLLN = 160; + } + +#if HSE_VALUE == 27000000 + RCC_OscInitStruct.PLL.PLLM = 9; + if (lowspeed) { + RCC_OscInitStruct.PLL.PLLN = 80; + } else { + RCC_OscInitStruct.PLL.PLLN = 300; + } +#endif + + RCC_OscInitStruct.PLL.PLLFRACN = 0; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | + RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | + RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (lowspeed) { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + return 0; // FAIL + } else { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) + return 0; // FAIL + } + + // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); + +#if DEVICE_USBDEVICE + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + return 0; // FAIL + } + + HAL_PWREx_EnableUSBVoltageDetector(); +#endif /* DEVICE_USBDEVICE */ + + __HAL_RCC_CSI_ENABLE() ; + + __HAL_RCC_SYSCFG_CLK_ENABLE() ; + + HAL_EnableCompensationCell(); + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */ + +#if ((CLOCK_SOURCE) & USE_PLL_HSI) +/******************************************************************************/ +/* PLL (clocked by HSI) used as System clock source */ +/******************************************************************************/ +uint8_t SetSysClock_PLL_HSI(void) +{ + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Supply configuration update enable */ +#if HSE_VALUE == 27000000 + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_EXT); +#else + HAL_PWREx_ConfigSupply(PWR_SMPS_1V8_SUPPLIES_LDO); +#endif + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value + regarding system frequency refer to product datasheet. */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Enable HSI oscillator and activate PLL with HSI as source + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSEState = RCC_HSE_OFF; + RCC_OscInitStruct.CSIState = RCC_CSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 100; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 10; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_3; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + return 0; // FAIL + } + + /* Select PLL as system clock source and configure bus clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | \ + RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) { + return 0; // FAIL + } + + return 1; // OK +} +#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */ + +#if defined (CORE_CM4) +void HSEM2_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif + +#if defined (CORE_CM7) +void HSEM1_IRQHandler(void) +{ + HAL_HSEM_IRQHandler(); +} +#endif diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld index 5f479936c85..ea81a18b117 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_STM32H747xI_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld @@ -39,6 +39,7 @@ MEMORY { FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE RAM (rwx) : ORIGIN = MBED_RAM_START + VECTORS_SIZE, LENGTH = MBED_RAM_SIZE - VECTORS_SIZE + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K } /* Linker script to place sections and symbol values. Should be used together diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c index 464494148e8..b2e1661388d 100644 --- a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/system_clock.c @@ -55,7 +55,7 @@ uint8_t SetSysClock_PLL_HSI(void); * @retval None */ -void SetSysClock(void) +MBED_WEAK void SetSysClock(void) { #if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */ @@ -158,7 +158,7 @@ MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass) /******************************************************************************/ /* PLL (clocked by HSI) used as System clock source */ /******************************************************************************/ -uint8_t SetSysClock_PLL_HSI(void) +MBED_WEAK uint8_t SetSysClock_PLL_HSI(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; diff --git a/targets/TARGET_STM/USBPhy_STM32.cpp b/targets/TARGET_STM/USBPhy_STM32.cpp index 6a4b0ea8a88..97edb406f3e 100644 --- a/targets/TARGET_STM/USBPhy_STM32.cpp +++ b/targets/TARGET_STM/USBPhy_STM32.cpp @@ -235,6 +235,8 @@ void USBPhyHw::init(USBPhyEvents *events) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); + __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE(); + __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE(); map = PinMap_USB_HS; #elif (MBED_CONF_TARGET_USB_SPEED == USE_USB_HS_IN_FS) @@ -298,7 +300,9 @@ void USBPhyHw::init(USBPhyEvents *events) map++; } +#if !defined(TARGET_STM32H7) __HAL_RCC_PWR_CLK_ENABLE(); +#endif #if !defined(TARGET_STM32WB) __HAL_RCC_SYSCFG_CLK_ENABLE(); diff --git a/targets/TARGET_STM/gpio_irq_api.c b/targets/TARGET_STM/gpio_irq_api.c index 635d1cb8e3b..7e036c5d3ad 100644 --- a/targets/TARGET_STM/gpio_irq_api.c +++ b/targets/TARGET_STM/gpio_irq_api.c @@ -149,9 +149,13 @@ static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line) #else /* TARGET_STM32L5 */ // Clear interrupt flag +#if defined(DUAL_CORE) && defined(CORE_CM4) + if (__HAL_GPIO_EXTID2_GET_FLAG(pin) != RESET) { + __HAL_GPIO_EXTID2_CLEAR_FLAG(pin); +#else if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) { __HAL_GPIO_EXTI_CLEAR_FLAG(pin); - +#endif if (gpio_channel->channel_ids[gpio_idx] == 0) { continue; } @@ -499,7 +503,11 @@ void gpio_irq_enable(gpio_irq_t *obj) SYSCFG->EXTICR[pin_index >> 2] = temp; #endif +#if defined(DUAL_CORE) && defined(CORE_CM4) + LL_C2_EXTI_EnableIT_0_31(1 << pin_index); +#else LL_EXTI_EnableIT_0_31(1 << pin_index); +#endif /* Restore previous edge interrupt configuration if applicable */ if (obj->event & IRQ_RISE) { @@ -523,7 +531,12 @@ void gpio_irq_disable(gpio_irq_t *obj) /* Clear EXTI line configuration */ LL_EXTI_DisableRisingTrig_0_31(1 << pin_index); LL_EXTI_DisableFallingTrig_0_31(1 << pin_index); + +#if defined(DUAL_CORE) && defined(CORE_CM4) + LL_C2_EXTI_DisableIT_0_31(1 << pin_index); +#else LL_EXTI_DisableIT_0_31(1 << pin_index); +#endif uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx])); diff --git a/targets/TARGET_STM/mbed_overrides.c b/targets/TARGET_STM/mbed_overrides.c index 22d50dd96b5..3f13af5d9d2 100644 --- a/targets/TARGET_STM/mbed_overrides.c +++ b/targets/TARGET_STM/mbed_overrides.c @@ -252,6 +252,7 @@ void mbed_sdk_init() SetSysClock(); SystemCoreClockUpdate(); +#ifndef CM4_BOOT_BY_APPLICATION /* Check wether CM4 boot in parallel with CM7. If CM4 was gated but CM7 trigger the CM4 boot. No need to wait for synchronization. otherwise CM7 should wakeup CM4 when system clocks initialization is done. */ if (READ_BIT(SYSCFG->UR1, SYSCFG_UR1_BCM4)) { @@ -263,6 +264,7 @@ void mbed_sdk_init() } /* wait until CPU2 wakes up from stop mode */ while (LL_RCC_D2CK_IsReady() == 0); +#endif /* CM4_BOOT_BY_APPLICATION */ #endif /* CORE_M4 */ #else /* Single core */ diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c index 911262c1224..5e252229c13 100644 --- a/targets/TARGET_STM/qspi_api.c +++ b/targets/TARGET_STM/qspi_api.c @@ -557,7 +557,11 @@ static qspi_status_t _qspi_init_direct(qspi_t *obj, const qspi_pinmap_t *pinmap, // Set default QSPI handle values obj->handle.Init.ClockPrescaler = 1; obj->handle.Init.FifoThreshold = 1; +#if defined(QSPI_NO_SAMPLE_SHIFT) + obj->handle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_NONE; +#else obj->handle.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; +#endif obj->handle.Init.FlashSize = POSITION_VAL(QSPI_FLASH_SIZE_DEFAULT) - 1; obj->handle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_5_CYCLE; obj->handle.Init.ClockMode = QSPI_CLOCK_MODE_0; diff --git a/targets/targets.json b/targets/targets.json index 719d80e500b..eb903b21cc9 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2996,6 +2996,78 @@ ], "device_name": "STM32H747XIHx" }, + "PORTENTA_H7": { + "public": false, + "inherits": ["MCU_STM32H747xI"], + "config": { + "hse_value": { + "help": "HSE default value is 25MHz in HAL", + "value": "25000000", + "macro_name": "HSE_VALUE" + }, + "lse_bypass": { + "help": "1 to use an oscillator (not a crystal) on 32k LSE", + "value": "1" + }, + "usb_speed": { + "help": "USE_USB_OTG_FS or USE_USB_OTG_HS or USE_USB_HS_IN_FS", + "value": "USE_USB_OTG_HS" + } + }, + "macros_add": [ + "CM4_BOOT_BY_APPLICATION", + "QSPI_NO_SAMPLE_SHIFT" + ], + "detect_code": ["0813"], + "components_add": [ + "QSPIF" + ], + "device_has_add": [ + "USBDEVICE", + "EMAC", + "QSPI" + ], + "overrides": { + "system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO", + "clock_source": "USE_PLL_HSE_EXTC", + "lse_available": 1, + "lpticker_delay_ticks": 0, + "network-default-interface-type": "ETHERNET" + }, + "device_name": "STM32H747XIHx" + }, + "PORTENTA_H7_M7": { + "inherits": ["PORTENTA_H7"], + "core": "Cortex-M7FD", + "mbed_rom_start": "0x08000000", + "mbed_rom_size" : "0x100000", + "mbed_ram_start": "0x24000000", + "mbed_ram_size" : "0x80000", + "extra_labels_add": [ + "STM32H747xI_CM7" + ], + "macros_add": [ + "CORE_CM7" + ] + }, + "PORTENTA_H7_M4": { + "inherits": ["PORTENTA_H7"], + "core": "Cortex-M4F", + "mbed_rom_start": "0x08100000", + "mbed_rom_size" : "0x100000", + "mbed_ram_start": "0x10000000", + "mbed_ram_size" : "0x48000", + "extra_labels_add": [ + "STM32H747xI_CM4" + ], + "macros_add": [ + "CORE_CM4", + "MBED_MPU_CUSTOM" + ], + "device_has_remove": [ + "MPU" + ] + }, "MCU_STM32H7A3xIQ": { "inherits": [ "MCU_STM32H7"