Don't try to apply aliasing decoration to SPIR-V instruction without return id

Signed-off-by: Dmitry Sidorov <[email protected]>

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@403a943

Author: MrSidims

llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

@@ -122,25 +122,6 @@ static SPIRVMemoryModelKind getMemoryModel(Module &M) {
   return SPIRVMemoryModelKind::MemoryModelMax;
 }
 
-static bool shouldTryToAddMemAliasingDecoration(Instruction *Inst) {
-  // Limit translation of aliasing metadata with only this set of instructions
-  // gracefully considering others as compilation mistakes and ignoring them
-  if (!Inst->mayReadOrWriteMemory())
-    return false;
-  // Loads and Stores are handled during memory access mask addition
-  if (isa<StoreInst>(Inst) || isa<LoadInst>(Inst))
-    return false;
-  CallInst *CI = dyn_cast<CallInst>(Inst);
-  if (!CI)
-    return true;
-  // Calls to intrinsics are skipped. At some point lifetime start/end will be
-  // handled separately, but specification isn't ready.
-  if (Function *Fun = CI->getCalledFunction())
-    if (Fun->isIntrinsic())
-      return false;
-  return true;
-}
-
 LLVMToSPIRVBase::LLVMToSPIRVBase(SPIRVModule *SMod)
     : M(nullptr), Ctx(nullptr), BM(SMod), SrcLang(0), SrcLangVer(0) {
   DbgTran = std::make_unique<LLVMToSPIRVDbgTran>(nullptr, SMod, this);
@@ -1982,6 +1963,31 @@ SPIRVValue *LLVMToSPIRVBase::mapValue(Value *V, SPIRVValue *BV) {
   return BV;
 }
 
+bool LLVMToSPIRVBase::shouldTryToAddMemAliasingDecoration(Instruction *Inst) {
+  // Limit translation of aliasing metadata with only this set of instructions
+  // gracefully considering others as compilation mistakes and ignoring them
+  if (!Inst->mayReadOrWriteMemory())
+    return false;
+  // Loads and Stores are handled during memory access mask addition
+  if (isa<StoreInst>(Inst) || isa<LoadInst>(Inst))
+    return false;
+  CallInst *CI = dyn_cast<CallInst>(Inst);
+  if (!CI)
+    return true;
+  if (Function *Fun = CI->getCalledFunction()) {
+    // Calls to intrinsics are skipped. At some point lifetime start/end will be
+    // handled separately, but specification isn't ready.
+    if (Fun->isIntrinsic())
+      return false;
+    // Also skip SPIR-V instructions that don't have result id to attach the
+    // decorations
+    if (isBuiltinTransToInst(Fun))
+      if (Fun->getReturnType()->isVoidTy())
+        return false;
+  }
+  return true;
+}
+
 bool LLVMToSPIRVBase::transDecoration(Value *V, SPIRVValue *BV) {
   if (!transAlign(V, BV))
     return false;

llvm-spirv/lib/SPIRV/SPIRVWriter.h

@@ -103,6 +103,7 @@ class LLVMToSPIRVBase {
   SPIRVValue *transAsmINTEL(InlineAsm *Asm);
   SPIRVValue *transAsmCallINTEL(CallInst *Call, SPIRVBasicBlock *BB);
   bool transDecoration(Value *V, SPIRVValue *BV);
+  bool shouldTryToAddMemAliasingDecoration(Instruction *V);
   void transMemAliasingINTELDecorations(Instruction *V, SPIRVValue *BV);
   SPIRVWord transFunctionControlMask(Function *);
   SPIRVFunction *transFunctionDecl(Function *F);

llvm-spirv/test/transcoding/SPV_INTEL_memory_access_aliasing/intel-alias-barrier.ll

@@ -0,0 +1,23 @@
+; The test checks if the translator won't crash
+
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_memory_access_aliasing -o %t.spv
+
+; ModuleID = 'main'
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+%class.anon = type { i8 }
+
+; Function Attrs: nounwind
+define spir_kernel void @barrier_simple()
+{
+  tail call spir_func void @_Z22__spirv_ControlBarrierjjj(i32 2, i32 2, i32 272), !noalias !1
+  ret void
+}
+
+declare dso_local spir_func void @_Z22__spirv_ControlBarrierjjj(i32, i32, i32)
+
+!1 = !{!2}
+!2 = distinct !{!2, !3}
+!3 = distinct !{!3}