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[AArch64] Prepare for changes to STEP_VECTOR.
Rewrite patterns to assume that the operand of STEP_VECTOR is a constant. The old patterns will stop working when the operand is changed from a Constant to a TargetConstant. (See D105673.) Add test coverage for certain patterns that weren't exercised by existing regression tests. Differential Revision: https://reviews.llvm.org/D105847
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‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 61 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -4852,29 +4852,29 @@ class sve_int_index_ii<bits<2> sz8_64, string asm, ZPRRegOp zprty,
48524852
let Inst{4-0} = Zd;
48534853
}
48544854

4855-
multiclass sve_int_index_ii<string asm, SDPatternOperator op, SDPatternOperator oneuseop> {
4855+
multiclass sve_int_index_ii<string asm, SDPatternOperator step_vector, SDPatternOperator step_vector_oneuse> {
48564856
def _B : sve_int_index_ii<0b00, asm, ZPR8, simm5_8b>;
48574857
def _H : sve_int_index_ii<0b01, asm, ZPR16, simm5_16b>;
48584858
def _S : sve_int_index_ii<0b10, asm, ZPR32, simm5_32b>;
48594859
def _D : sve_int_index_ii<0b11, asm, ZPR64, simm5_64b>;
48604860

4861-
def : Pat<(nxv16i8 (op simm5_8b:$imm5b)),
4861+
def : Pat<(nxv16i8 (step_vector simm5_8b:$imm5b)),
48624862
(!cast<Instruction>(NAME # "_B") (i32 0), simm5_8b:$imm5b)>;
4863-
def : Pat<(nxv8i16 (op simm5_16b:$imm5b)),
4863+
def : Pat<(nxv8i16 (step_vector simm5_16b:$imm5b)),
48644864
(!cast<Instruction>(NAME # "_H") (i32 0), simm5_16b:$imm5b)>;
4865-
def : Pat<(nxv4i32 (op simm5_32b:$imm5b)),
4865+
def : Pat<(nxv4i32 (step_vector simm5_32b:$imm5b)),
48664866
(!cast<Instruction>(NAME # "_S") (i32 0), simm5_32b:$imm5b)>;
4867-
def : Pat<(nxv2i64 (op simm5_64b:$imm5b)),
4867+
def : Pat<(nxv2i64 (step_vector simm5_64b:$imm5b)),
48684868
(!cast<Instruction>(NAME # "_D") (i64 0), simm5_64b:$imm5b)>;
48694869

48704870
// add(step_vector(step), dup(X)) -> index(X, step).
4871-
def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4871+
def : Pat<(add (nxv16i8 (step_vector_oneuse simm5_8b:$imm5b)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
48724872
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, simm5_8b:$imm5b)>;
4873-
def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4873+
def : Pat<(add (nxv8i16 (step_vector_oneuse simm5_16b:$imm5b)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
48744874
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, simm5_16b:$imm5b)>;
4875-
def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4875+
def : Pat<(add (nxv4i32 (step_vector_oneuse simm5_32b:$imm5b)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
48764876
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, simm5_32b:$imm5b)>;
4877-
def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4877+
def : Pat<(add (nxv2i64 (step_vector_oneuse simm5_64b:$imm5b)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
48784878
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, simm5_64b:$imm5b)>;
48794879
}
48804880

@@ -4895,49 +4895,53 @@ class sve_int_index_ir<bits<2> sz8_64, string asm, ZPRRegOp zprty,
48954895
let Inst{4-0} = Zd;
48964896
}
48974897

4898-
multiclass sve_int_index_ir<string asm, SDPatternOperator op, SDPatternOperator oneuseop, SDPatternOperator mulop, SDPatternOperator muloneuseop> {
4898+
multiclass sve_int_index_ir<string asm, SDPatternOperator step_vector, SDPatternOperator step_vector_oneuse, SDPatternOperator mulop, SDPatternOperator muloneuseop> {
48994899
def _B : sve_int_index_ir<0b00, asm, ZPR8, GPR32, simm5_8b>;
49004900
def _H : sve_int_index_ir<0b01, asm, ZPR16, GPR32, simm5_16b>;
49014901
def _S : sve_int_index_ir<0b10, asm, ZPR32, GPR32, simm5_32b>;
49024902
def _D : sve_int_index_ir<0b11, asm, ZPR64, GPR64, simm5_64b>;
49034903

4904-
def : Pat<(nxv16i8 (op GPR32:$Rm)),
4905-
(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
4906-
def : Pat<(nxv8i16 (op GPR32:$Rm)),
4907-
(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
4908-
def : Pat<(nxv4i32 (op GPR32:$Rm)),
4909-
(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
4910-
def : Pat<(nxv2i64 (op GPR64:$Rm)),
4911-
(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
4904+
def : Pat<(nxv16i8 (step_vector (i32 imm:$imm))),
4905+
(!cast<Instruction>(NAME # "_B") (i32 0), (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4906+
def : Pat<(nxv8i16 (step_vector (i32 imm:$imm))),
4907+
(!cast<Instruction>(NAME # "_H") (i32 0), (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4908+
def : Pat<(nxv4i32 (step_vector (i32 imm:$imm))),
4909+
(!cast<Instruction>(NAME # "_S") (i32 0), (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4910+
def : Pat<(nxv2i64 (step_vector (i64 imm:$imm))),
4911+
(!cast<Instruction>(NAME # "_D") (i64 0), (!cast<Instruction>("MOVi64imm") imm:$imm))>;
4912+
def : Pat<(nxv2i64 (step_vector (i64 !cast<ImmLeaf>("i64imm_32bit"):$imm))),
4913+
(!cast<Instruction>(NAME # "_D") (i64 0), (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("trunc_imm") imm:$imm)), sub_32))>;
49124914

49134915
// add(step_vector(step), dup(X)) -> index(X, step).
4914-
def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4915-
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
4916-
def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4917-
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
4918-
def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4919-
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
4920-
def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4921-
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
4916+
def : Pat<(add (nxv16i8 (step_vector_oneuse (i32 imm:$imm))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4917+
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4918+
def : Pat<(add (nxv8i16 (step_vector_oneuse (i32 imm:$imm))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4919+
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4920+
def : Pat<(add (nxv4i32 (step_vector_oneuse (i32 imm:$imm))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4921+
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
4922+
def : Pat<(add (nxv2i64 (step_vector_oneuse (i64 imm:$imm))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4923+
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, (!cast<Instruction>("MOVi64imm") imm:$imm))>;
4924+
def : Pat<(add (nxv2i64 (step_vector_oneuse (i64 !cast<ImmLeaf>("i64imm_32bit"):$imm))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4925+
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("trunc_imm") imm:$imm)), sub_32))>;
49224926

49234927
// mul(step_vector(1), dup(Y)) -> index(0, Y).
4924-
def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
4928+
def : Pat<(mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (step_vector_oneuse (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
49254929
(!cast<Instruction>(NAME # "_B") (i32 0), GPR32:$Rm)>;
4926-
def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
4930+
def : Pat<(mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (step_vector_oneuse (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
49274931
(!cast<Instruction>(NAME # "_H") (i32 0), GPR32:$Rm)>;
4928-
def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
4932+
def : Pat<(mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (step_vector_oneuse (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
49294933
(!cast<Instruction>(NAME # "_S") (i32 0), GPR32:$Rm)>;
4930-
def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
4934+
def : Pat<(mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (step_vector_oneuse (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
49314935
(!cast<Instruction>(NAME # "_D") (i64 0), GPR64:$Rm)>;
49324936

4933-
// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
4934-
def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
4937+
// add(mul(step_vector(1), dup(Y)), dup(X)) -> index(X, Y).
4938+
def : Pat<(add (muloneuseop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (step_vector_oneuse (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(simm5_8b:$imm5)))),
49354939
(!cast<Instruction>(NAME # "_B") simm5_8b:$imm5, GPR32:$Rm)>;
4936-
def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
4940+
def : Pat<(add (muloneuseop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (step_vector_oneuse (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))), (nxv8i16 (AArch64dup(simm5_16b:$imm5)))),
49374941
(!cast<Instruction>(NAME # "_H") simm5_16b:$imm5, GPR32:$Rm)>;
4938-
def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
4942+
def : Pat<(add (muloneuseop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (step_vector_oneuse (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))), (nxv4i32 (AArch64dup(simm5_32b:$imm5)))),
49394943
(!cast<Instruction>(NAME # "_S") simm5_32b:$imm5, GPR32:$Rm)>;
4940-
def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
4944+
def : Pat<(add (muloneuseop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (step_vector_oneuse (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))), (nxv2i64 (AArch64dup(simm5_64b:$imm5)))),
49414945
(!cast<Instruction>(NAME # "_D") simm5_64b:$imm5, GPR64:$Rm)>;
49424946
}
49434947

@@ -4958,20 +4962,20 @@ class sve_int_index_ri<bits<2> sz8_64, string asm, ZPRRegOp zprty,
49584962
let Inst{4-0} = Zd;
49594963
}
49604964

4961-
multiclass sve_int_index_ri<string asm, SDPatternOperator op, SDPatternOperator oneuseop> {
4965+
multiclass sve_int_index_ri<string asm, SDPatternOperator step_vector, SDPatternOperator step_vector_oneuse> {
49624966
def _B : sve_int_index_ri<0b00, asm, ZPR8, GPR32, simm5_8b>;
49634967
def _H : sve_int_index_ri<0b01, asm, ZPR16, GPR32, simm5_16b>;
49644968
def _S : sve_int_index_ri<0b10, asm, ZPR32, GPR32, simm5_32b>;
49654969
def _D : sve_int_index_ri<0b11, asm, ZPR64, GPR64, simm5_64b>;
49664970

49674971
// add(step_vector(step), dup(X)) -> index(X, step).
4968-
def : Pat<(add (nxv16i8 (oneuseop simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
4972+
def : Pat<(add (nxv16i8 (step_vector_oneuse simm5_8b:$imm5)), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))),
49694973
(!cast<Instruction>(NAME # "_B") GPR32:$Rm, simm5_8b:$imm5)>;
4970-
def : Pat<(add (nxv8i16 (oneuseop simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
4974+
def : Pat<(add (nxv8i16 (step_vector_oneuse simm5_16b:$imm5)), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),
49714975
(!cast<Instruction>(NAME # "_H") GPR32:$Rm, simm5_16b:$imm5)>;
4972-
def : Pat<(add (nxv4i32 (oneuseop simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
4976+
def : Pat<(add (nxv4i32 (step_vector_oneuse simm5_32b:$imm5)), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),
49734977
(!cast<Instruction>(NAME # "_S") GPR32:$Rm, simm5_32b:$imm5)>;
4974-
def : Pat<(add (nxv2i64 (oneuseop simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
4978+
def : Pat<(add (nxv2i64 (step_vector_oneuse simm5_64b:$imm5)), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),
49754979
(!cast<Instruction>(NAME # "_D") GPR64:$Rm, simm5_64b:$imm5)>;
49764980
}
49774981

@@ -4992,30 +4996,32 @@ class sve_int_index_rr<bits<2> sz8_64, string asm, ZPRRegOp zprty,
49924996
let Inst{4-0} = Zd;
49934997
}
49944998

4995-
multiclass sve_int_index_rr<string asm, SDPatternOperator op, SDPatternOperator oneuseop, SDPatternOperator mulop> {
4999+
multiclass sve_int_index_rr<string asm, SDPatternOperator step_vector, SDPatternOperator step_vector_oneuse, SDPatternOperator mulop> {
49965000
def _B : sve_int_index_rr<0b00, asm, ZPR8, GPR32>;
49975001
def _H : sve_int_index_rr<0b01, asm, ZPR16, GPR32>;
49985002
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
49995003
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
50005004

50015005
// add(step_vector(step), dup(X)) -> index(X, step).
5002-
def : Pat<(add (nxv16i8 (oneuseop GPR32:$Rm)), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
5003-
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
5004-
def : Pat<(add (nxv8i16 (oneuseop GPR32:$Rm)), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
5005-
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
5006-
def : Pat<(add (nxv4i32 (oneuseop GPR32:$Rm)), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
5007-
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
5008-
def : Pat<(add (nxv2i64 (oneuseop GPR64:$Rm)), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
5009-
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
5010-
5011-
// add(mul(step_vector(1), dup(Y), dup(X)) -> index(X, Y).
5012-
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (oneuseop (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
5006+
def : Pat<(add (nxv16i8 (step_vector_oneuse (i32 imm:$imm))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
5007+
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
5008+
def : Pat<(add (nxv8i16 (step_vector_oneuse (i32 imm:$imm))), (nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
5009+
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
5010+
def : Pat<(add (nxv4i32 (step_vector_oneuse (i32 imm:$imm))), (nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
5011+
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, (!cast<Instruction>("MOVi32imm") imm:$imm))>;
5012+
def : Pat<(add (nxv2i64 (step_vector_oneuse (i64 imm:$imm))), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
5013+
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, (!cast<Instruction>("MOVi64imm") imm:$imm))>;
5014+
def : Pat<(add (nxv2i64 (step_vector_oneuse (i64 !cast<ImmLeaf>("i64imm_32bit"):$imm))), (nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
5015+
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, (SUBREG_TO_REG (i64 0), (!cast<Instruction>("MOVi32imm") (!cast<SDNodeXForm>("trunc_imm") imm:$imm)), sub_32))>;
5016+
5017+
// add(mul(step_vector(1), dup(Y)), dup(X)) -> index(X, Y).
5018+
def : Pat<(add (mulop (nxv16i1 (AArch64ptrue 31)), (nxv16i8 (step_vector_oneuse (i32 1))), (nxv16i8 (AArch64dup(i32 GPR32:$Rm)))), (nxv16i8 (AArch64dup(i32 GPR32:$Rn)))),
50135019
(!cast<Instruction>(NAME # "_B") GPR32:$Rn, GPR32:$Rm)>;
5014-
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (oneuseop (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
5020+
def : Pat<(add (mulop (nxv8i1 (AArch64ptrue 31)), (nxv8i16 (step_vector_oneuse (i32 1))), (nxv8i16 (AArch64dup(i32 GPR32:$Rm)))),(nxv8i16 (AArch64dup(i32 GPR32:$Rn)))),
50155021
(!cast<Instruction>(NAME # "_H") GPR32:$Rn, GPR32:$Rm)>;
5016-
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (oneuseop (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
5022+
def : Pat<(add (mulop (nxv4i1 (AArch64ptrue 31)), (nxv4i32 (step_vector_oneuse (i32 1))), (nxv4i32 (AArch64dup(i32 GPR32:$Rm)))),(nxv4i32 (AArch64dup(i32 GPR32:$Rn)))),
50175023
(!cast<Instruction>(NAME # "_S") GPR32:$Rn, GPR32:$Rm)>;
5018-
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (oneuseop (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
5024+
def : Pat<(add (mulop (nxv2i1 (AArch64ptrue 31)), (nxv2i64 (step_vector_oneuse (i64 1))), (nxv2i64 (AArch64dup(i64 GPR64:$Rm)))),(nxv2i64 (AArch64dup(i64 GPR64:$Rn)))),
50195025
(!cast<Instruction>(NAME # "_D") GPR64:$Rn, GPR64:$Rm)>;
50205026
}
50215027

‎llvm/test/CodeGen/AArch64/sve-stepvector.ll

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -246,6 +246,86 @@ entry:
246246
ret <vscale x 8 x i8> %3
247247
}
248248

249+
define <vscale x 2 x i64> @mul_stepvector_nxv2i64() {
250+
; CHECK-LABEL: mul_stepvector_nxv2i64:
251+
; CHECK: // %bb.0: // %entry
252+
; CHECK-NEXT: mov w8, #2222
253+
; CHECK-NEXT: index z0.d, #0, x8
254+
; CHECK-NEXT: ret
255+
entry:
256+
%0 = insertelement <vscale x 2 x i64> poison, i64 2222, i32 0
257+
%1 = shufflevector <vscale x 2 x i64> %0, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
258+
%2 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
259+
%3 = mul <vscale x 2 x i64> %2, %1
260+
ret <vscale x 2 x i64> %3
261+
}
262+
263+
define <vscale x 2 x i64> @mul_stepvector_bigconst_nxv2i64() {
264+
; CHECK-LABEL: mul_stepvector_bigconst_nxv2i64:
265+
; CHECK: // %bb.0: // %entry
266+
; CHECK-NEXT: mov x8, #146028888064
267+
; CHECK-NEXT: index z0.d, #0, x8
268+
; CHECK-NEXT: ret
269+
entry:
270+
%0 = insertelement <vscale x 2 x i64> poison, i64 146028888064, i32 0
271+
%1 = shufflevector <vscale x 2 x i64> %0, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
272+
%2 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
273+
%3 = mul <vscale x 2 x i64> %2, %1
274+
ret <vscale x 2 x i64> %3
275+
}
276+
277+
define <vscale x 2 x i64> @mul_add_stepvector_nxv2i64(i64 %x) {
278+
; CHECK-LABEL: mul_add_stepvector_nxv2i64:
279+
; CHECK: // %bb.0: // %entry
280+
; CHECK-NEXT: mov w8, #2222
281+
; CHECK-NEXT: index z0.d, x0, x8
282+
; CHECK-NEXT: ret
283+
entry:
284+
%0 = insertelement <vscale x 2 x i64> poison, i64 2222, i32 0
285+
%1 = shufflevector <vscale x 2 x i64> %0, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
286+
%2 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
287+
%3 = mul <vscale x 2 x i64> %2, %1
288+
%4 = insertelement <vscale x 2 x i64> poison, i64 %x, i32 0
289+
%5 = shufflevector <vscale x 2 x i64> %4, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
290+
%6 = add <vscale x 2 x i64> %3, %5
291+
ret <vscale x 2 x i64> %6
292+
}
293+
294+
define <vscale x 2 x i64> @mul_add_stepvector_bigconst_nxv2i64(i64 %x) {
295+
; CHECK-LABEL: mul_add_stepvector_bigconst_nxv2i64:
296+
; CHECK: // %bb.0: // %entry
297+
; CHECK-NEXT: mov x8, #146028888064
298+
; CHECK-NEXT: index z0.d, x0, x8
299+
; CHECK-NEXT: ret
300+
entry:
301+
%0 = insertelement <vscale x 2 x i64> poison, i64 146028888064, i32 0
302+
%1 = shufflevector <vscale x 2 x i64> %0, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
303+
%2 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
304+
%3 = mul <vscale x 2 x i64> %2, %1
305+
%4 = insertelement <vscale x 2 x i64> poison, i64 %x, i32 0
306+
%5 = shufflevector <vscale x 2 x i64> %4, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
307+
%6 = add <vscale x 2 x i64> %3, %5
308+
ret <vscale x 2 x i64> %6
309+
}
310+
311+
define <vscale x 2 x i64> @mul_mul_add_stepvector_nxv2i64(i64 %x, i64 %y) {
312+
; CHECK-LABEL: mul_mul_add_stepvector_nxv2i64:
313+
; CHECK: // %bb.0: // %entry
314+
; CHECK-NEXT: add x8, x0, x0, lsl #1
315+
; CHECK-NEXT: index z0.d, x1, x8
316+
; CHECK-NEXT: ret
317+
entry:
318+
%xmul = mul i64 %x, 3
319+
%0 = insertelement <vscale x 2 x i64> poison, i64 %xmul, i32 0
320+
%1 = shufflevector <vscale x 2 x i64> %0, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
321+
%2 = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
322+
%3 = mul <vscale x 2 x i64> %2, %1
323+
%4 = insertelement <vscale x 2 x i64> poison, i64 %y, i32 0
324+
%5 = shufflevector <vscale x 2 x i64> %4, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
325+
%6 = add <vscale x 2 x i64> %3, %5
326+
ret <vscale x 2 x i64> %6
327+
}
328+
249329
define <vscale x 8 x i8> @shl_stepvector_nxv8i8() {
250330
; CHECK-LABEL: shl_stepvector_nxv8i8:
251331
; CHECK: // %bb.0: // %entry

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