@@ -411,15 +411,19 @@ static int bcm2835_i2s_hw_params(struct snd_pcm_substream *substream,
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divf = dividend & BCM2835_CLK_DIVF_MASK ;
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}
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- /* Set clock divider */
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- regmap_write (dev -> clk_regmap , BCM2835_CLK_PCMDIV_REG , BCM2835_CLK_PASSWD
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- | BCM2835_CLK_DIVI (divi )
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- | BCM2835_CLK_DIVF (divf ));
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-
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- /* Setup clock, but don't start it yet */
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- regmap_write (dev -> clk_regmap , BCM2835_CLK_PCMCTL_REG , BCM2835_CLK_PASSWD
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- | BCM2835_CLK_MASH (mash )
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- | BCM2835_CLK_SRC (clk_src ));
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+ /* Clock should only be set up here if CPU is clock master */
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+ if (((dev -> fmt & SND_SOC_DAIFMT_MASTER_MASK ) == SND_SOC_DAIFMT_CBS_CFS ) ||
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+ ((dev -> fmt & SND_SOC_DAIFMT_MASTER_MASK ) == SND_SOC_DAIFMT_CBS_CFM )) {
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+ /* Set clock divider */
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+ regmap_write (dev -> clk_regmap , BCM2835_CLK_PCMDIV_REG , BCM2835_CLK_PASSWD
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+ | BCM2835_CLK_DIVI (divi )
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+ | BCM2835_CLK_DIVF (divf ));
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+
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+ /* Setup clock, but don't start it yet */
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+ regmap_write (dev -> clk_regmap , BCM2835_CLK_PCMCTL_REG , BCM2835_CLK_PASSWD
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+ | BCM2835_CLK_MASH (mash )
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+ | BCM2835_CLK_SRC (clk_src ));
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+ }
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/* Setup the frame format */
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format = BCM2835_I2S_CHEN ;
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