Add support for SPV_INTEL_fpga_buffer_location extension

This extension adds a function parameter decoration that is useful
for FPGA targets. This decoration indicates that a particular global
memory pointer can only access a articular physical memory location.
Knowing this information at compile time can allow FPGA compilers to
generate load store units of lower area for accesses done through such
a pointer.

Specification: intel/llvm#2084

Signed-off-by: Dmitry Sidorov <[email protected]>

Author: MrSidims

include/LLVMSPIRVExtensions.inc

@@ -22,3 +22,4 @@ EXT(SPV_INTEL_optimization_hints)
 EXT(SPV_INTEL_float_controls2)
 EXT(SPV_INTEL_vector_compute)
 EXT(SPV_INTEL_usm_storage_classes)
+EXT(SPV_INTEL_fpga_buffer_location)

lib/SPIRV/SPIRVReader.cpp

@@ -168,6 +168,20 @@ static void addOCLKernelArgumentMetadata(
   Fn->setMetadata(MDName, MDNode::get(*Context, ValueVec));
 }
 
+static void addBufferLocationMetadata(
+    LLVMContext *Context, SPIRVFunction *BF, llvm::Function *Fn,
+    std::function<Metadata *(SPIRVFunctionParameter *)> Func) {
+  std::vector<Metadata *> ValueVec;
+  BF->foreachArgument([&](SPIRVFunctionParameter *Arg) {
+    if (Arg->getType()->isTypePointer() &&
+        Arg->hasDecorate(DecorationBufferLocationINTEL))
+      ValueVec.push_back(Func(Arg));
+  });
+  if (ValueVec.size())
+    Fn->setMetadata("kernel_arg_buffer_location",
+                    MDNode::get(*Context, ValueVec));
+}
+
 Value *SPIRVToLLVM::getTranslatedValue(SPIRVValue *BV) {
   auto Loc = ValueMap.find(BV);
   if (Loc != ValueMap.end())
@@ -3443,6 +3457,15 @@ bool SPIRVToLLVM::transOCLMetadata(SPIRVFunction *BF) {
                                                         Arg->getName());
                                  });
   }
+  // Generate metadata for kernel_arg_buffer_location
+  addBufferLocationMetadata(Context, BF, F, [=](SPIRVFunctionParameter *Arg) {
+    auto Literals = Arg->getDecorationLiterals(DecorationBufferLocationINTEL);
+    assert(Literals.size() == 1 &&
+           "BufferLocationINTEL decoration shall have 1 ID literal");
+
+    return ConstantAsMetadata::get(
+        ConstantInt::get(Type::getInt32Ty(*Context), Literals[0]));
+  });
   return true;
 }
 

lib/SPIRV/SPIRVWriter.cpp

@@ -525,6 +525,14 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {
     BM->addEntryPoint(ExecutionModelKernel, BF->getId());
   else if (F->getLinkage() != GlobalValue::InternalLinkage)
     BF->setLinkageType(transLinkageType(F));
+
+  // Translate OpenCL/SYCL buffer_location metadata if it's attached to the
+  // translated function declaration
+  MDNode *BufferLocation = nullptr;
+  if (BM->isAllowedToUseExtension(
+        ExtensionID::SPV_INTEL_fpga_buffer_location))
+    BufferLocation = ((*F).getMetadata("kernel_arg_buffer_location"));
+
   auto Attrs = F->getAttributes();
 
   for (Function::arg_iterator I = F->arg_begin(), E = F->arg_end(); I != E;
@@ -550,6 +558,13 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {
       BA->addDecorate(DecorationMaxByteOffset,
                       Attrs.getAttribute(ArgNo + 1, Attribute::Dereferenceable)
                           .getDereferenceableBytes());
+    if (BufferLocation) {
+      // Order of integer numbers in MD node follows the order of function
+      // parameters on which we shall attach the appropriate decoration
+      BM->addCapability(CapabilityFPGABufferLocationINTEL);
+      size_t LocID = getMDOperandAsInt(BufferLocation, ArgNo);
+      BA->addDecorate(DecorationBufferLocationINTEL, LocID);
+    }
   }
   if (Attrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt))
     BF->addDecorate(DecorationFuncParamAttr, FunctionParameterAttributeZext);

lib/SPIRV/libSPIRV/SPIRVDecorate.h

@@ -159,6 +159,8 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
       return getSet(ExtensionID::SPV_INTEL_function_pointers);
     case DecorationIOPipeStorageINTEL:
       return getSet(ExtensionID::SPV_INTEL_io_pipes);
+    case DecorationBufferLocationINTEL:
+      return getSet(ExtensionID::SPV_INTEL_fpga_buffer_location);
     default:
       return SPIRVExtSet();
     }
@@ -257,6 +259,8 @@ class SPIRVMemberDecorate : public SPIRVDecorateGeneric {
       return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
     case DecorationIOPipeStorageINTEL:
       return getSet(ExtensionID::SPV_INTEL_io_pipes);
+    case DecorationBufferLocationINTEL:
+      return getSet(ExtensionID::SPV_INTEL_fpga_buffer_location);
     default:
       return SPIRVExtSet();
     }

lib/SPIRV/libSPIRV/SPIRVEnum.h

@@ -393,6 +393,8 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
                {CapabilityVectorComputeINTEL});
   ADD_VEC_INIT(DecorationFuncParamIOKind, {CapabilityVectorComputeINTEL});
   ADD_VEC_INIT(DecorationStackCallINTEL, {CapabilityVectorComputeINTEL});
+  ADD_VEC_INIT(DecorationBufferLocationINTEL,
+               {CapabilityFPGABufferLocationINTEL});
 }
 
 template <> inline void SPIRVMap<BuiltIn, SPIRVCapVec>::init() {

lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

@@ -369,6 +369,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
   add(DecorationVectorComputeVariableINTEL, "VectorComputeVariableINTEL");
   add(DecorationGlobalVariableOffsetINTEL, "GlobalVariableOffsetINTEL");
   add(DecorationFuncParamIOKind, "FuncParamIOKind");
+  add(DecorationBufferLocationINTEL, "BufferLocationINTEL");
 }
 SPIRV_DEF_NAMEMAP(Decoration, SPIRVDecorationNameMap)
 
@@ -552,6 +553,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
       "GroupNonUniformShuffleRelative");
   add(CapabilityGroupNonUniformClustered, "GroupNonUniformClustered");
   add(CapabilityUSMStorageClassesINTEL, "USMStorageClassesINTEL");
+  add(CapabilityFPGABufferLocationINTEL, "FPGABufferLocationINTEL");
 }
 SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
 

lib/SPIRV/libSPIRV/spirv.hpp

@@ -501,6 +501,7 @@ enum Decoration {
   DecorationMergeINTEL = 5834,
   DecorationBankBitsINTEL = 5835,
   DecorationForcePow2DepthINTEL = 5836,
+  DecorationBufferLocationINTEL = 5921,
   DecorationIOPipeStorageINTEL = 5944,
   DecorationMax = 0x7fffffff,
 };
@@ -956,6 +957,7 @@ enum Capability {
   CapabilityKernelAttributesINTEL = 5892,
   CapabilityFPGAKernelAttributesINTEL = 5897,
   CapabilityUSMStorageClassesINTEL = 5935,
+  CapabilityFPGABufferLocationINTEL = 5920,
   CapabilityIOPipeINTEL = 5943,
   CapabilityMax = 0x7fffffff,
 };

test/transcoding/FPGABufferLocation.ll

@@ -0,0 +1,54 @@
+; RUN: llvm-as %s -o %t.bc
+; RUN: llvm-spirv %t.bc --spirv-ext=+SPV_INTEL_fpga_buffer_location -o %t.spv
+; RUN: llvm-spirv %t.spv -to-text -o %t.spt
+; RUN: FileCheck < %t.spt %s --check-prefix=CHECK-SPIRV
+
+; RUN: llvm-spirv -r %t.spv -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; RUN: llvm-spirv -spirv-text -r %t.spt -o %t.rev.bc
+; RUN: llvm-dis < %t.rev.bc | FileCheck %s --check-prefix=CHECK-LLVM
+
+; CHECK-SPIRV: 2 Capability FPGABufferLocationINTEL
+; CHECK-SPIRV: 9 Extension "SPV_INTEL_fpga_buffer_location"
+; CHECK-SPIRV: 3 Name [[ARGA:[0-9]+]] "a"
+; CHECK-SPIRV: 3 Name [[ARGB:[0-9]+]] "b"
+; CHECK-SPIRV: 3 Name [[ARGC:[0-9]+]] "c"
+; CHECK-SPIRV: 4 Decorate [[ARGC]] BufferLocationINTEL 0
+; CHECK-SPIRV: 4 Decorate [[ARGA]] BufferLocationINTEL 1
+; CHECK-SPIRV: 4 Decorate [[ARGB]] BufferLocationINTEL 2
+
+; CHECK-SPIRV: 5 Function
+; CHECK-SPIRV: 3 FunctionParameter {{[0-9]+}} [[ARGA]]
+; CHECK-SPIRV: 3 FunctionParameter {{[0-9]+}} [[ARGB]]
+; CHECK-SPIRV: 3 FunctionParameter {{[0-9]+}} [[ARGC]]
+
+; CHECK-LLVM: define spir_kernel void @test{{.*}} !kernel_arg_buffer_location ![[BUFLOC_MD:[0-9]+]] {{.*}}
+; CHECK-LLVM: ![[BUFLOC_MD]] = !{i32 1, i32 2, i32 0}
+
+; ModuleID = 'buffer_location.cl'
+source_filename = "buffer_location.cl"
+target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
+target triple = "spir64-unknown-unknown"
+
+; Function Attrs: norecurse nounwind readnone
+define spir_kernel void @test(i32 addrspace(1)* %a, float addrspace(1)* %b, i32 addrspace(1)* %c) local_unnamed_addr !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_buffer_location !6 {
+entry:
+  ret void
+}
+
+!opencl.enable.FP_CONTRACT = !{}
+!opencl.ocl.version = !{!0}
+!opencl.spir.version = !{!0}
+!opencl.used.extensions = !{!1}
+!opencl.used.optional.core.features = !{!1}
+!opencl.compiler.options = !{!1}
+!llvm.ident = !{!2}
+
+!0 = !{i32 2, i32 0}
+!1 = !{}
+!2 = !{!""}
+!3 = !{i32 1, i32 1, i32 1}
+!4 = !{!"none", !"none", !"none"}
+!5 = !{!"int*", !"float*", !"int*"}
+!6 = !{i32 1, i32 2, i32 0}