@@ -480,7 +480,7 @@ void DMA1_Stream2_IRQHandler(void)
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struct stm32f4_spi stm32f4_spi4 =
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{
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/* .spi_handle = */ {
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- /* .Instance = */ SPI4 ,
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+ /* .Instance = */ SPI5 ,
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},
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/* .hdma_rx = */ {
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DMA2_Stream0 ,
@@ -526,6 +526,7 @@ struct stm32f4_spi stm32f4_spi5 =
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/* .spi_handle = */ {
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/* .Instance = */ SPI5 ,
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},
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+ #ifdef SPI_USE_DMA
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/* .hdma_rx = */ {
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DMA2_Stream3 ,
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DMA_CHANNEL_2 ,
@@ -537,6 +538,7 @@ struct stm32f4_spi stm32f4_spi5 =
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DMA_CHANNEL_2 ,
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},
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/* .hdma_tx_irq = */ DMA2_Stream4_IRQn ,
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+ #endif /* SPI_USE_DMA */
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};
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static struct rt_spi_bus spi5_bus ;
@@ -703,6 +705,7 @@ rt_err_t stm32_spi_bus_register(SPI_TypeDef * SPI,
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return RT_ENOSYS ;
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}
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+ #ifdef SPI_USE_DMA
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/* Configure the DMA handler for Transmission process */
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p_spi_bus -> hdma_tx .Init .Direction = DMA_MEMORY_TO_PERIPH ;
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p_spi_bus -> hdma_tx .Init .PeriphInc = DMA_PINC_DISABLE ;
@@ -727,6 +730,7 @@ rt_err_t stm32_spi_bus_register(SPI_TypeDef * SPI,
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p_spi_bus -> hdma_rx .Init .FIFOThreshold = DMA_FIFO_THRESHOLD_FULL ;
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p_spi_bus -> hdma_rx .Init .MemBurst = DMA_MBURST_INC4 ;
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p_spi_bus -> hdma_rx .Init .PeriphBurst = DMA_PBURST_INC4 ;
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+ #endif /* SPI_USE_DMA */
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spi_bus -> parent .user_data = & stm32f4_spi5 ;
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