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xinyigaomysterywolf
xinyigao
authored and
mysterywolf
committed
[bsp][nxp][imxrt1020] update to support Keil AC6
1 parent e865b5b commit 3b91391

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Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/.config

+47-409
Large diffs are not rendered by default.

Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/board/MCUX_Config/dcd.c

+302
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Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/board/MCUX_Config/dcd.h

+32
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
/*
2+
* Copyright 2020 NXP
3+
* All rights reserved.
4+
*
5+
* SPDX-License-Identifier: BSD-3-Clause
6+
*/
7+
8+
/***********************************************************************************************************************
9+
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10+
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11+
**********************************************************************************************************************/
12+
13+
#ifndef __DCD__
14+
#define __DCD__
15+
16+
#include <stdint.h>
17+
18+
/*! @name Driver version */
19+
/*@{*/
20+
/*! @brief XIP_BOARD driver version 2.0.1. */
21+
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22+
/*@}*/
23+
24+
/*************************************
25+
* DCD Data
26+
*************************************/
27+
#define DCD_TAG_HEADER (0xD2)
28+
#define DCD_VERSION (0x41)
29+
#define DCD_TAG_HEADER_SHIFT (24)
30+
#define DCD_ARRAY_SIZE 1
31+
32+
#endif /* __DCD__ */

Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/board/SConscript

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
1-
1+
Import('RTT_ROOT')
2+
Import('rtconfig')
23
from building import *
34

45
cwd = GetCurrentDir()
@@ -8,6 +9,7 @@ src = Split("""
89
board.c
910
MCUX_Config/clock_config.c
1011
MCUX_Config/pin_mux.c
12+
MCUX_Config/dcd.c
1113
""")
1214

1315
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']

Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/board/board.c

+68-36
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,28 @@
3333
/* MPU configuration. */
3434
void BOARD_ConfigMPU(void)
3535
{
36+
#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
37+
extern uint32_t Image$$RW_m_ncache$$Base[];
38+
/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
39+
extern uint32_t Image$$RW_m_ncache_unused$$Base[];
40+
extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
41+
uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
42+
uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
43+
0 :
44+
((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
45+
#elif defined(__MCUXPRESSO)
46+
extern uint32_t __base_NCACHE_REGION;
47+
extern uint32_t __top_NCACHE_REGION;
48+
uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
49+
uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
50+
#elif defined(__ICCARM__) || defined(__GNUC__)
51+
extern uint32_t __NCACHE_REGION_START[];
52+
extern uint32_t __NCACHE_REGION_SIZE[];
53+
uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
54+
uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
55+
#endif
56+
volatile uint32_t i = 0;
57+
3658
/* Disable I cache and D cache */
3759
if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
3860
{
@@ -85,59 +107,69 @@ void BOARD_ConfigMPU(void)
85107
* mpu_armv7.h.
86108
*/
87109

88-
/* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
89-
MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
90-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
110+
/*
111+
* Add default region to deny access to whole address space to workaround speculative prefetch.
112+
* Refer to Arm errata 1013783-B for more details.
113+
*
114+
*/
115+
/* Region 0 setting: Instruction access disabled, No data access permission. */
116+
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
117+
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
91118

92-
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
119+
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
93120
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
94-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
121+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
95122

96-
/* Region 2 setting */
97-
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
98-
/* Setting Memory with Normal type, not shareable, outer/inner write back. */
123+
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
99124
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
125+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
126+
127+
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
128+
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
129+
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
100130
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
101-
#else
102-
/* Setting Memory with Device type, not shareable, non-cacheable. */
103-
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
104-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB);
105131
#endif
106132

107-
/* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
108-
MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
109-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
110-
111-
/* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
133+
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
112134
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
113-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
135+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
114136

115137
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
116-
MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
138+
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
117139
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
118140

119141
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
120-
MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
121-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
142+
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
143+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
122144

123-
/* The define sets the cacheable memory to shareable,
124-
* this suggestion is referred from chapter 2.2.1 Memory regions,
125-
* types and attributes in Cortex-M7 Devices, Generic User Guide */
126-
#if defined(SDRAM_IS_SHAREABLE)
127-
/* Region 7 setting: Memory with Normal type, shareable, outer/inner write back */
128-
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
129-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
130-
#else
131145
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
132-
MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
146+
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
147+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
148+
149+
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
150+
MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
133151
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
134-
#endif
135152

136-
/* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
137-
* accessed by cache can be put here */
138-
/* Memory with Normal type, not shareable, non-cacheable */
139-
MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
140-
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
153+
while ((size >> i) > 0x1U)
154+
{
155+
i++;
156+
}
157+
158+
if (i != 0)
159+
{
160+
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
161+
assert(!(nonCacheStart % size));
162+
assert(size == (uint32_t)(1 << i));
163+
assert(i >= 5);
164+
165+
/* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
166+
MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
167+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
168+
}
169+
170+
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
171+
MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
172+
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
141173

142174
/* Enable MPU */
143175
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);

Diff for: ‎bsp/imxrt/imxrt1021-nxp-evk/board/linker_scripts/link.sct

+80-93
Original file line numberDiff line numberDiff line change
@@ -1,134 +1,121 @@
1-
#! armcc -E
1+
#!armclang --target=arm-arm-none-eabi -mcpu=cortex-m7 -E -x c
22
/*
33
** ###################################################################
4-
** Processors: MIMXRT1052CVL5A
5-
** MIMXRT1052DVL6A
4+
** Processors: MIMXRT1021CAF4A
5+
** MIMXRT1021CAG4A
6+
** MIMXRT1021DAF5A
7+
** MIMXRT1021DAG5A
68
**
79
** Compiler: Keil ARM C/C++ Compiler
8-
** Reference manual: IMXRT1050RM Rev.C, 08/2017
9-
** Version: rev. 0.1, 2017-01-10
10-
** Build: b170927
10+
** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
11+
** Version: rev. 0.1, 2017-06-06
12+
** Build: b210709
1113
**
1214
** Abstract:
1315
** Linker file for the Keil ARM C/C++ Compiler
1416
**
1517
** Copyright 2016 Freescale Semiconductor, Inc.
16-
** Copyright 2016-2017 NXP
17-
** Redistribution and use in source and binary forms, with or without modification,
18-
** are permitted provided that the following conditions are met:
18+
** Copyright 2016-2021 NXP
19+
** All rights reserved.
1920
**
20-
** 1. Redistributions of source code must retain the above copyright notice, this list
21-
** of conditions and the following disclaimer.
22-
**
23-
** 2. Redistributions in binary form must reproduce the above copyright notice, this
24-
** list of conditions and the following disclaimer in the documentation and/or
25-
** other materials provided with the distribution.
26-
**
27-
** 3. Neither the name of the copyright holder nor the names of its
28-
** contributors may be used to endorse or promote products derived from this
29-
** software without specific prior written permission.
30-
**
31-
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
32-
** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
33-
** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34-
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
35-
** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36-
** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37-
** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
38-
** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39-
** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
40-
** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21+
** SPDX-License-Identifier: BSD-3-Clause
4122
**
4223
** http: www.nxp.com
4324
** mail: [email protected]
4425
**
4526
** ###################################################################
4627
*/
4728

29+
#if (defined(__ram_vector_table__))
30+
#define __ram_vector_table_size__ 0x00000400
31+
#else
32+
#define __ram_vector_table_size__ 0x00000000
33+
#endif
34+
4835
#define m_flash_config_start 0x60000000
4936
#define m_flash_config_size 0x00001000
5037

5138
#define m_ivt_start 0x60001000
5239
#define m_ivt_size 0x00001000
5340

54-
#define m_text_start 0x60002000
55-
#define m_text_size 0x007FE000
41+
#define m_interrupts_start 0x60002000
42+
#define m_interrupts_size 0x00000400
43+
44+
#define m_text_start 0x60002400
45+
#define m_text_size 0x007FDC00
46+
47+
#define m_qacode_start 0x00000000
48+
#define m_qacode_size 0x00010000
5649

57-
#define m_data_start 0x20000000
58-
#define m_data_size 0x00020000
50+
#define m_interrupts_ram_start 0x20000000
51+
#define m_interrupts_ram_size __ram_vector_table_size__
5952

60-
#define m_ncache_start 0x81E00000
61-
#define m_ncache_size 0x00200000
53+
#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
54+
#define m_data_size (0x00010000 - m_interrupts_ram_size)
55+
56+
#define m_data2_start 0x20200000
57+
#define m_data2_size 0x00020000
6258

6359
/* Sizes */
6460
#if (defined(__stack_size__))
6561
#define Stack_Size __stack_size__
6662
#else
67-
#define Stack_Size 0x1000
63+
#define Stack_Size 0x2000
6864
#endif
6965

7066
#if (defined(__heap_size__))
7167
#define Heap_Size __heap_size__
7268
#else
73-
#define Heap_Size 0x0400
69+
#define Heap_Size 0x6000
7470
#endif
7571

76-
#include "../../rtconfig.h"
77-
;BSP_USING_HYPERFLASH
78-
#if (defined(BOARD_USING_QSPIFLASH))
79-
LR_m_rom_config m_flash_config_start m_flash_config_size ; load region size_region
80-
{
81-
RW_m_config_text m_flash_config_start m_flash_config_size ; load address = execution address
82-
{
83-
* (.boot_hdr.conf, +FIRST)
84-
}
85-
}
72+
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
8673

87-
LR_m_rom_ivt m_ivt_start m_ivt_size ; load region size_region
88-
{
89-
RW_m_ivt_text m_ivt_start m_ivt_size ; load address = execution address
90-
{
91-
* (.boot_hdr.ivt, +FIRST)
92-
* (.boot_hdr.boot_data)
93-
* (.boot_hdr.dcd_data)
94-
}
95-
}
96-
#endif
74+
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
75+
LR_m_text m_flash_config_start m_text_start+m_text_size-m_flash_config_start { ; load region size_region
76+
RW_m_config_text m_flash_config_start FIXED m_flash_config_size { ; load address = execution address
77+
* (.boot_hdr.conf, +FIRST)
78+
}
9779

98-
#define RTT_HEAP_SIZE (m_data_size-ImageLength(RW_m_data)-ImageLength(ARM_LIB_HEAP)-ImageLength(ARM_LIB_STACK))
80+
RW_m_ivt_text m_ivt_start FIXED m_ivt_size { ; load address = execution address
81+
* (.boot_hdr.ivt, +FIRST)
82+
* (.boot_hdr.boot_data)
83+
* (.boot_hdr.dcd_data)
84+
}
85+
#else
86+
LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
87+
#endif
88+
VECTOR_ROM m_interrupts_start FIXED m_interrupts_size { ; load address = execution address
89+
* (.isr_vector,+FIRST)
90+
}
91+
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
92+
* (InRoot$$Sections)
93+
.ANY (+RO)
94+
}
95+
#if (defined(__ram_vector_table__))
96+
VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
97+
}
98+
#else
99+
VECTOR_RAM m_interrupts_start EMPTY 0 {
100+
}
101+
#endif
102+
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
103+
.ANY (+RW +ZI)
104+
* (RamFunction)
105+
* (NonCacheable.init)
106+
* (*NonCacheable)
107+
* (DataQuickAccess)
108+
}
109+
ARM_LIB_HEAP +0 EMPTY Heap_Size {}
110+
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
111+
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
99112

100-
; load region size_region
101-
LR_IROM1 m_text_start m_text_size
102-
{
103-
ER_IROM1 m_text_start m_text_size ; load address = execution address
104-
{
105-
* (RESET,+FIRST)
106-
* (InRoot$$Sections)
107-
.ANY (+RO)
108-
}
109-
110-
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size ; RW data
111-
{
112-
.ANY (+RW +ZI)
113-
}
114-
115-
ARM_LIB_HEAP +0 EMPTY Heap_Size{} ; Heap region growing up
116-
ARM_LIB_STACK +0 EMPTY Stack_Size{} ; Stack region growing down
117-
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
118-
119-
; ncache RW data
120-
RW_m_ncache m_ncache_start m_ncache_size
121-
{
122-
* (NonCacheable.init)
123-
* (NonCacheable)
124-
}
125-
ITCM 0x400 0xFBFF {
126-
;drv_flexspi_hyper.o(+RO)
127-
;fsl_flexspi.o(+RO)
128-
* (*CLOCK_DisableClock)
129-
* (*CLOCK_ControlGate)
130-
* (*CLOCK_EnableClock)
131-
* (*CLOCK_SetDiv)
132-
* (itcm)
133-
}
113+
RW_m_ram_text m_qacode_start m_qacode_size { ;
114+
* (CodeQuickAccess)
115+
}
116+
RW_m_ncache m_data2_start EMPTY 0 {
117+
}
118+
RW_m_ncache_unused +0 EMPTY m_data2_size-ImageLength(RW_m_ncache) { ; Empty region added for MPU configuration
119+
}
134120
}
121+

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