Skip to content

Commit 874f6c8

Browse files
GuozhanxinGuozhanxin
authored
Merge pull request #5389 from mysterywolf/master
[qemu][lvgl] 优化lvgl显示驱动
2 parents 1390f7d + df474d7 commit 874f6c8

26 files changed

+112
-176
lines changed

‎bsp/qemu-vexpress-a9/drivers/Kconfig

-2
Original file line numberDiff line numberDiff line change
@@ -36,12 +36,10 @@ config BSP_DRV_MOUSE
3636
if BSP_DRV_CLCD
3737
config BSP_LCD_WIDTH
3838
int "Width of LCD panel"
39-
default 480 if PKG_USING_LV_MUSIC_DEMO
4039
default 640
4140

4241
config BSP_LCD_HEIGHT
4342
int "Height of LCD panel"
44-
default 272 if PKG_USING_LV_MUSIC_DEMO
4543
default 480
4644
endif
4745

‎bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/audio/drv_ac97.h

+28-28
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -12,33 +12,33 @@
1212
#define __DRV_AC97_H__
1313

1414
/* Register offsets */
15-
#define AC97_RESET 0x00
16-
#define AC97_MASTER 0x02
17-
#define AC97_HEADPHONE 0x04
18-
#define AC97_MASTER_MONO 0x06
19-
#define AC97_MASTER_TONE 0x08
20-
#define AC97_PC_BEEP 0x0A //mixer volume
21-
#define AC97_PHONE 0x0C
22-
#define AC97_MIC 0x0E //qwert db
23-
#define AC97_LINE 0x10
24-
#define AC97_CD 0x12
25-
#define AC97_VIDEO 0x14
26-
#define AC97_AUX 0x16
27-
#define AC97_PCM 0x18
28-
#define AC97_REC_SEL 0x1A //0 represent mic
29-
#define AC97_REC_GAIN 0x1C
30-
#define AC97_REC_GAIN_MIC 0x1E
31-
#define AC97_GENERAL_PURPOSE 0x20
32-
#define AC97_3D_CONTROL 0x22
33-
#define AC97_INT_PAGING 0x24 //qwert
34-
#define AC97_POWERDOWN 0x26
35-
#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
36-
#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
37-
#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
38-
#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
39-
#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
40-
#define AC97_DAC_SLOT_MAP 0x6C
41-
#define AC97_ADC_SLOT_MAP 0x6E
15+
#define AC97_RESET 0x00
16+
#define AC97_MASTER 0x02
17+
#define AC97_HEADPHONE 0x04
18+
#define AC97_MASTER_MONO 0x06
19+
#define AC97_MASTER_TONE 0x08
20+
#define AC97_PC_BEEP 0x0A //mixer volume
21+
#define AC97_PHONE 0x0C
22+
#define AC97_MIC 0x0E //qwert db
23+
#define AC97_LINE 0x10
24+
#define AC97_CD 0x12
25+
#define AC97_VIDEO 0x14
26+
#define AC97_AUX 0x16
27+
#define AC97_PCM 0x18
28+
#define AC97_REC_SEL 0x1A //0 represent mic
29+
#define AC97_REC_GAIN 0x1C
30+
#define AC97_REC_GAIN_MIC 0x1E
31+
#define AC97_GENERAL_PURPOSE 0x20
32+
#define AC97_3D_CONTROL 0x22
33+
#define AC97_INT_PAGING 0x24 //qwert
34+
#define AC97_POWERDOWN 0x26
35+
#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
36+
#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
37+
#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
38+
#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
39+
#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
40+
#define AC97_DAC_SLOT_MAP 0x6C
41+
#define AC97_ADC_SLOT_MAP 0x6E
4242

4343
void ac97_reset(void);
4444
rt_err_t ac97_set_vol(int vol);

‎bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/audio/drv_pl041.h

+26-26
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -14,11 +14,11 @@
1414
#define PL041_BASE_ADDR (0x10004000)
1515

1616
/* offsets in CTRL_CH */
17-
#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */
18-
#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */
19-
#define AACI_SR 0x08 /* 12 bits Status */
20-
#define AACI_ISR 0x0C /* 7 bits Int Status */
21-
#define AACI_IE 0x10 /* 7 bits Int Enable */
17+
#define AACI_RXCR 0x00 /* 29 bits Control Rx FIFO */
18+
#define AACI_TXCR 0x04 /* 17 bits Control Tx FIFO */
19+
#define AACI_SR 0x08 /* 12 bits Status */
20+
#define AACI_ISR 0x0C /* 7 bits Int Status */
21+
#define AACI_IE 0x10 /* 7 bits Int Enable */
2222

2323
/* both for AACI_RXCR and AACI_TXCR */
2424
#define AACI_CR_FEN (1 << 16) /* fifo enable */
@@ -39,7 +39,7 @@
3939
#define AACI_CR_SL3 (1 << 3)
4040
#define AACI_CR_SL2 (1 << 2)
4141
#define AACI_CR_SL1 (1 << 1)
42-
#define AACI_CR_EN (1 << 0) /* receive enable */
42+
#define AACI_CR_EN (1 << 0) /* receive enable */
4343

4444
/* status register bits */
4545
#define AACI_SR_RXTOFE (1 << 11) /* rx timeout fifo empty */
@@ -66,29 +66,29 @@
6666
/* interrupt enable */
6767
#define AACI_IE_RXTOIE (1 << 6) /*rx timeout interrupt enable*/
6868
#define AACI_IE_URIE (1 << 5) /*Transmit underrun interrupt enable*/
69-
#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/
69+
#define AACI_IE_ORIE (1 << 4) /*Overrun receive interrupt enable*/
7070
#define AACI_IE_RXIE (1 << 3) /*Receive interrupt enable*/
7171
#define AACI_IE_TXIE (1 << 2) /*Transmit interrupt enable*/
7272
#define AACI_IE_RXTIE (1 << 1) /*Receive timeout interrupt enable*/
73-
#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/
73+
#define AACI_IE_TXCIE (1 << 0) /*Transmit complete interrupt enable*/
7474

7575
/* interrupt status */
76-
#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
77-
#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */
78-
#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */
79-
#define AACI_ISR_RX (1 << 3) /* rx interrupt status */
80-
#define AACI_ISR_TX (1 << 2) /* tx interrupt status */
81-
#define AACI_ISR_RXTO (1 << 1) /* rx timeout */
82-
#define AACI_ISR_TXC (1 << 0) /* tx complete */
76+
#define AACI_ISR_RXTOFE (1 << 6) /* rx timeout fifo empty */
77+
#define AACI_ISR_UR (1 << 5) /* tx fifo underrun */
78+
#define AACI_ISR_OR (1 << 4) /* rx fifo overrun */
79+
#define AACI_ISR_RX (1 << 3) /* rx interrupt status */
80+
#define AACI_ISR_TX (1 << 2) /* tx interrupt status */
81+
#define AACI_ISR_RXTO (1 << 1) /* rx timeout */
82+
#define AACI_ISR_TXC (1 << 0) /* tx complete */
8383

8484
/* interrupt enable */
85-
#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
86-
#define AACI_IE_UR (1 << 5) /* tx fifo underrun */
87-
#define AACI_IE_OR (1 << 4) /* rx fifo overrun */
88-
#define AACI_IE_RX (1 << 3) /* rx interrupt status */
89-
#define AACI_IE_TX (1 << 2) /* tx interrupt status */
90-
#define AACI_IE_RXTO (1 << 1) /* rx timeout */
91-
#define AACI_IE_TXC (1 << 0) /* tx complete */
85+
#define AACI_IE_RXTOFE (1 << 6) /* rx timeout fifo empty */
86+
#define AACI_IE_UR (1 << 5) /* tx fifo underrun */
87+
#define AACI_IE_OR (1 << 4) /* rx fifo overrun */
88+
#define AACI_IE_RX (1 << 3) /* rx interrupt status */
89+
#define AACI_IE_TX (1 << 2) /* tx interrupt status */
90+
#define AACI_IE_RXTO (1 << 1) /* rx timeout */
91+
#define AACI_IE_TXC (1 << 0) /* tx complete */
9292

9393
/* slot flag register bits */
9494
#define AACI_SLFR_RWIS (1 << 13) /* raw wake-up interrupt status */
@@ -120,7 +120,7 @@
120120
#define AACI_ICLR_RXOEC2 (1 << 2) /* Receive overrun error clear */
121121
#define AACI_ICLR_RXOEC1 (1 << 1) /* Receive overrun error clear */
122122
#define AACI_ICLR_WISC (1 << 0) /* Wake-up interrupt status clear */
123-
123+
124124
/* Main control register bits AACI_MAINCR */
125125
#define AACI_MAINCR_SCRA(x) ((x) << 10) /* secondary codec reg access */
126126
#define AACI_MAINCR_DMAEN (1 << 9) /* dma enable */
@@ -141,8 +141,8 @@
141141
#define SYNC_FORCE (1 << 0)
142142

143143
/* Main flag register bits. P66 */
144-
#define MAINFR_TXB (1 << 1) /* transmit busy */
145-
#define MAINFR_RXB (1 << 0) /* receive busy */
144+
#define MAINFR_TXB (1 << 1) /* transmit busy */
145+
#define MAINFR_RXB (1 << 0) /* receive busy */
146146

147147
#define PL041_CHANNEL_LEFT_DAC (0x1 << 3)
148148
#define PL041_CHANNEL_RIGHT_DAC (0x1 << 3)

‎bsp/qemu-vexpress-a9/drivers/audio/drv_sound.c

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
3-
*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
66
* Date Author Notes

‎bsp/qemu-vexpress-a9/drivers/audio/drv_sound.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
3-
*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
66
* Date Author Notes

‎bsp/qemu-vexpress-a9/drivers/board.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/board.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/drv_clcd.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -88,7 +88,7 @@ static rt_err_t drv_clcd_control(struct rt_device *device, int cmd, void *args)
8888
}
8989

9090
#ifdef RT_USING_DEVICE_OPS
91-
const static struct rt_device_ops clcd_ops =
91+
const static struct rt_device_ops clcd_ops =
9292
{
9393
drv_clcd_init,
9494
RT_NULL,
@@ -109,7 +109,7 @@ int drv_clcd_hw_init(void)
109109

110110
_lcd.width = CLCD_WIDTH;
111111
_lcd.height = CLCD_HEIGHT;
112-
_lcd.fb = rt_malloc (_lcd.width * _lcd.height * 2);
112+
_lcd.fb = rt_malloc_align(_lcd.width * _lcd.height * 2, 32);
113113
if (_lcd.fb == NULL)
114114
{
115115
rt_kprintf("initialize frame buffer failed!\n");

‎bsp/qemu-vexpress-a9/drivers/drv_clcd.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/drv_keyboard.c

+4-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -141,7 +141,7 @@ static const struct keymap map[] = {
141141
{0x74, RTGUIK_RIGHT, 0, "RIGHT" },
142142
{0x0d, RTGUIK_TAB, 0, "TAB" },
143143
{0x76, RTGUIK_ESCAPE, 0, "ESC" },
144-
{0x37, RTGUIK_POWER, 0, "POWER" },
144+
{0x37, RTGUIK_POWER, 0, "POWER" },
145145
{0x5a, RTGUIK_KP_ENTER, 0, "ENTER"},
146146
{0x66, RTGUIK_BACKSPACE, 0, "BACKSPACE"},
147147
};
@@ -433,12 +433,12 @@ int rt_hw_keyboard_init(void)
433433
struct keyboard_pl050_pdata_t *pdat;
434434
virtual_addr_t virt = (virtual_addr_t)KEYBOARD_ADDRESS;
435435
int irq = KEYBOARD_IRQ_NUM;
436-
436+
437437
id = (((read32(virt + 0xfec) & 0xff) << 24) |
438438
((read32(virt + 0xfe8) & 0xff) << 16) |
439439
((read32(virt + 0xfe4) & 0xff) << 8) |
440440
((read32(virt + 0xfe0) & 0xff) << 0));
441-
441+
442442
if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x050)
443443
{
444444
LOG_E("read id fail id:0x%08x", id);

‎bsp/qemu-vexpress-a9/drivers/drv_keyboard.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/drv_mouse.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/drv_mouse.h

+2-2
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -12,4 +12,4 @@
1212

1313
int rt_hw_mouse_init(void);
1414

15-
#endif
15+
#endif

‎bsp/qemu-vexpress-a9/drivers/drv_sdio.c

+3-3
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -295,7 +295,7 @@ static rt_err_t sdhci_pl180_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
295295
if(clock)
296296
{
297297
temp = read32(pdat->virt + PL180_CLOCK) | (0x1<<8);
298-
temp = temp; // skip warning
298+
temp = temp; // skip warning
299299
write32(pdat->virt + PL180_CLOCK, 0x100);
300300
}
301301
else
@@ -388,7 +388,7 @@ static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io
388388
LOG_D("clock:%d bus_width:%d", io_cfg->clock, io_cfg->bus_width);
389389
}
390390

391-
static const struct rt_mmcsd_host_ops ops =
391+
static const struct rt_mmcsd_host_ops ops =
392392
{
393393
mmc_request_send,
394394
mmc_set_iocfg,

‎bsp/qemu-vexpress-a9/drivers/drv_sdio.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2020, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/qemu-vexpress-a9/drivers/drv_timer.c

+5-5
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -89,7 +89,7 @@ void timer_init(int timer, unsigned int preload)
8989
{
9090
uint32_t val;
9191

92-
if (timer == 0)
92+
if (timer == 0)
9393
{
9494
/* Setup Timer0 for generating irq */
9595
val = TIMER_CTRL(TIMER01_HW_BASE);
@@ -101,8 +101,8 @@ void timer_init(int timer, unsigned int preload)
101101

102102
/* enable timer */
103103
TIMER_CTRL(TIMER01_HW_BASE) |= TIMER_CTRL_ENABLE;
104-
}
105-
else
104+
}
105+
else
106106
{
107107
/* Setup Timer1 for generating irq */
108108
val = TIMER_CTRL(TIMER23_HW_BASE);
@@ -122,7 +122,7 @@ void timer_clear_pending(int timer)
122122
if (timer == 0)
123123
{
124124
TIMER_INTCLR(TIMER01_HW_BASE) = 0x01;
125-
}
125+
}
126126
else
127127
{
128128
TIMER_INTCLR(TIMER23_HW_BASE) = 0x01;

‎bsp/qemu-vexpress-a9/drivers/drv_timer.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

0 commit comments

Comments
 (0)