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.travis.yml

+5
Original file line numberDiff line numberDiff line change
@@ -81,6 +81,11 @@ env:
8181
- RTT_BSP='stm32l475-iot-disco' RTT_TOOL_CHAIN='sourcery-arm'
8282
- RTT_BSP='stm32l476-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
8383
- RTT_BSP='stm32h743-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
84+
- RTT_BSP='stm32/stm32f103-atk-nano' RTT_TOOL_CHAIN='sourcery-arm'
85+
- RTT_BSP='stm32/stm32f103-fire-arbitrary' RTT_TOOL_CHAIN='sourcery-arm'
86+
- RTT_BSP='stm32/stm32f407-atk-explorer' RTT_TOOL_CHAIN='sourcery-arm'
87+
- RTT_BSP='stm32/stm32f429-atk-apollo' RTT_TOOL_CHAIN='sourcery-arm'
88+
- RTT_BSP='stm32/stm32f429-fire-challenger' RTT_TOOL_CHAIN='sourcery-arm'
8489
# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
8590
# - RTT_BSP='upd70f3454' # iar
8691
# - RTT_BSP='x86' # x86

bsp/CME_M7/rtconfig.h

+8-2
Original file line numberDiff line numberDiff line change
@@ -100,8 +100,14 @@
100100
/* Enable DHCP */
101101
// #define RT_LWIP_DHCP
102102

103-
/* the number of simulatenously active TCP connections*/
104-
#define RT_LWIP_TCP_PCB_NUM 3
103+
#define RT_MEMP_NUM_NETCONN 12
104+
#define RT_LWIP_PBUF_NUM 3
105+
#define RT_LWIP_RAW_PCB_NUM 2
106+
#define RT_LWIP_UDP_PCB_NUM 4
107+
#define RT_LWIP_TCP_PCB_NUM 8
108+
#define RT_LWIP_TCP_SEG_NUM 40
109+
#define RT_LWIP_TCP_SND_BUF 4380
110+
#define RT_LWIP_TCP_WND 4380
105111

106112
/* ip address of target */
107113
#define RT_LWIP_IPADDR "192.168.1.30"

bsp/CME_M7/rtconfig.py

+8-7
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,10 @@
1515
PLATFORM = 'armcc'
1616
EXEC_PATH = 'C:/Keil'
1717
elif CROSS_TOOL == 'iar':
18-
PLATFORM = 'iar'
19-
EXEC_PATH = 'C:/Program Files/IAR Systems/Embedded Workbench 6.0 Evaluation'
18+
print('================ERROR============================')
19+
print('Not support iar yet!')
20+
print('=================================================')
21+
exit(0)
2022

2123
if os.getenv('RTT_EXEC_PATH'):
2224
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
@@ -64,15 +66,14 @@
6466
LINK = 'armlink'
6567
TARGET_EXT = 'axf'
6668

67-
DEVICE = ' --cortex-m3'
69+
DEVICE = ' --cpu Cortex-M3'
6870
CFLAGS = DEVICE + ' --c99 --apcs=interwork'
6971
AFLAGS = DEVICE
70-
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter nuc472_flash.sct'
72+
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter CME_M7.sct'
7173

72-
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
73-
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
74+
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
7475

75-
EXEC_PATH += '/arm/bin40/'
76+
EXEC_PATH += '/ARM/ARMCC/bin'
7677

7778
if BUILD == 'debug':
7879
CFLAGS += ' -g -O0'

bsp/apollo2/rtconfig.py

+5-7
Original file line numberDiff line numberDiff line change
@@ -64,16 +64,14 @@
6464
LINK = 'armlink'
6565
TARGET_EXT = 'axf'
6666

67-
DEVICE = ' --device DARMSTM'
68-
CFLAGS = DEVICE + ' --apcs=interwork'
67+
DEVICE = ' --cpu Cortex-M4'
68+
CFLAGS = DEVICE + ' --c99 --apcs=interwork'
6969
AFLAGS = DEVICE
70-
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread-apollo2.sct'
70+
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-apollo2.map --scatter rtthread.sct'
7171

72-
CFLAGS += ' --c99'
73-
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
74-
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
72+
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
7573

76-
EXEC_PATH += '/arm/bin40/'
74+
EXEC_PATH += '/ARM/ARMCC/bin'
7775

7876
if BUILD == 'debug':
7977
CFLAGS += ' -g -O0'

bsp/frdm-k64f/MK64F.sct

+1-1
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ LR_IROM1 0x00000000 0x100000 { ; load region size_region (1000k)
77
}
88
; 8_byte_aligned(62 vect * 4 bytes) = 8_byte_aligned(0x194) = 0x198
99
; 0x40000 - 0x198 = 0x3FE68
10-
RW_IRAM1 0x1FFF0198 0x3FE68 {
10+
RW_IRAM2 0x20000000 0x30000 {
1111
.ANY (+RW +ZI)
1212
}
1313
}

bsp/frdm-k64f/rtconfig.py

+4-5
Original file line numberDiff line numberDiff line change
@@ -64,17 +64,16 @@
6464
TARGET_EXT = 'axf'
6565

6666
DEVICE = ' --cpu Cortex-M4.fp '
67-
CFLAGS = DEVICE + ' --apcs=interwork'
67+
CFLAGS = DEVICE + ' --c99 --apcs=interwork'
6868
AFLAGS = DEVICE
6969
LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-k64f.map --scatter MK64F.sct'
7070

71-
CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
72-
LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
71+
LFLAGS += ' --keep *.o(.rti_fn.*) --keep *.o(FSymTab) --keep *.o(VSymTab)'
7372

74-
EXEC_PATH += '/arm/bin40/'
73+
EXEC_PATH += '/ARM/ARMCC/bin'
7574

7675
if BUILD == 'debug':
77-
CFLAGS += ' --c99 -g -O0'
76+
CFLAGS += ' -g -O0'
7877
AFLAGS += ' -g'
7978
else:
8079
CFLAGS += ' -O2'

bsp/lpc176x/SConstruct

-1
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@ TARGET = 'rtthread-lpc17xx.' + rtconfig.TARGET_EXT
1414
env = Environment(tools = ['mingw'],
1515
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
1616
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
17-
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
1817
AR = rtconfig.AR, ARFLAGS = '-rc',
1918
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
2019

bsp/lpc54114-lite/Kconfig

+27
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
mainmenu "RT-Thread Configuration"
2+
3+
config $BSP_DIR
4+
string
5+
option env="BSP_ROOT"
6+
default "."
7+
8+
config $RTT_DIR
9+
string
10+
option env="RTT_ROOT"
11+
default "../.."
12+
13+
config $PKGS_DIR
14+
string
15+
option env="PKGS_ROOT"
16+
default "packages"
17+
18+
source "$RTT_DIR/Kconfig"
19+
source "$PKGS_DIR/Kconfig"
20+
21+
config SOC_LPC54114
22+
bool
23+
select ARCH_ARM_CORTEX_M4
24+
default y
25+
26+
source "$BSP_DIR/drivers/Kconfig"
27+
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
Import('RTT_ROOT')
2+
Import('rtconfig')
3+
from building import *
4+
5+
cwd = GetCurrentDir()
6+
src = Glob('*.c')
7+
8+
CPPPATH = [cwd]
9+
10+
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH)
11+
12+
Return('group')
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,121 @@
1+
/* ----------------------------------------------------------------------
2+
* Project: CMSIS DSP Library
3+
* Title: arm_common_tables.h
4+
* Description: Extern declaration for common tables
5+
*
6+
* $Date: 27. January 2017
7+
* $Revision: V.1.5.1
8+
*
9+
* Target Processor: Cortex-M cores
10+
* -------------------------------------------------------------------- */
11+
/*
12+
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
13+
*
14+
* SPDX-License-Identifier: Apache-2.0
15+
*
16+
* Licensed under the Apache License, Version 2.0 (the License); you may
17+
* not use this file except in compliance with the License.
18+
* You may obtain a copy of the License at
19+
*
20+
* www.apache.org/licenses/LICENSE-2.0
21+
*
22+
* Unless required by applicable law or agreed to in writing, software
23+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
24+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
25+
* See the License for the specific language governing permissions and
26+
* limitations under the License.
27+
*/
28+
29+
#ifndef _ARM_COMMON_TABLES_H
30+
#define _ARM_COMMON_TABLES_H
31+
32+
#include "arm_math.h"
33+
34+
extern const uint16_t armBitRevTable[1024];
35+
extern const q15_t armRecipTableQ15[64];
36+
extern const q31_t armRecipTableQ31[64];
37+
extern const float32_t twiddleCoef_16[32];
38+
extern const float32_t twiddleCoef_32[64];
39+
extern const float32_t twiddleCoef_64[128];
40+
extern const float32_t twiddleCoef_128[256];
41+
extern const float32_t twiddleCoef_256[512];
42+
extern const float32_t twiddleCoef_512[1024];
43+
extern const float32_t twiddleCoef_1024[2048];
44+
extern const float32_t twiddleCoef_2048[4096];
45+
extern const float32_t twiddleCoef_4096[8192];
46+
#define twiddleCoef twiddleCoef_4096
47+
extern const q31_t twiddleCoef_16_q31[24];
48+
extern const q31_t twiddleCoef_32_q31[48];
49+
extern const q31_t twiddleCoef_64_q31[96];
50+
extern const q31_t twiddleCoef_128_q31[192];
51+
extern const q31_t twiddleCoef_256_q31[384];
52+
extern const q31_t twiddleCoef_512_q31[768];
53+
extern const q31_t twiddleCoef_1024_q31[1536];
54+
extern const q31_t twiddleCoef_2048_q31[3072];
55+
extern const q31_t twiddleCoef_4096_q31[6144];
56+
extern const q15_t twiddleCoef_16_q15[24];
57+
extern const q15_t twiddleCoef_32_q15[48];
58+
extern const q15_t twiddleCoef_64_q15[96];
59+
extern const q15_t twiddleCoef_128_q15[192];
60+
extern const q15_t twiddleCoef_256_q15[384];
61+
extern const q15_t twiddleCoef_512_q15[768];
62+
extern const q15_t twiddleCoef_1024_q15[1536];
63+
extern const q15_t twiddleCoef_2048_q15[3072];
64+
extern const q15_t twiddleCoef_4096_q15[6144];
65+
extern const float32_t twiddleCoef_rfft_32[32];
66+
extern const float32_t twiddleCoef_rfft_64[64];
67+
extern const float32_t twiddleCoef_rfft_128[128];
68+
extern const float32_t twiddleCoef_rfft_256[256];
69+
extern const float32_t twiddleCoef_rfft_512[512];
70+
extern const float32_t twiddleCoef_rfft_1024[1024];
71+
extern const float32_t twiddleCoef_rfft_2048[2048];
72+
extern const float32_t twiddleCoef_rfft_4096[4096];
73+
74+
/* floating-point bit reversal tables */
75+
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
76+
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
77+
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
78+
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
79+
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
80+
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
81+
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
82+
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
83+
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
84+
85+
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
86+
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
87+
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
88+
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
89+
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
90+
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
91+
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
92+
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
93+
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
94+
95+
/* fixed-point bit reversal tables */
96+
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
97+
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
98+
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
99+
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
100+
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
101+
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
102+
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
103+
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
104+
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
105+
106+
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
107+
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
108+
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
109+
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
110+
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
111+
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
112+
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
113+
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
114+
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
115+
116+
/* Tables for Fast Math Sine and Cosine */
117+
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
118+
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
119+
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
120+
121+
#endif /* ARM_COMMON_TABLES_H */
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,66 @@
1+
/* ----------------------------------------------------------------------
2+
* Project: CMSIS DSP Library
3+
* Title: arm_const_structs.h
4+
* Description: Constant structs that are initialized for user convenience.
5+
* For example, some can be given as arguments to the arm_cfft_f32() function.
6+
*
7+
* $Date: 27. January 2017
8+
* $Revision: V.1.5.1
9+
*
10+
* Target Processor: Cortex-M cores
11+
* -------------------------------------------------------------------- */
12+
/*
13+
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
14+
*
15+
* SPDX-License-Identifier: Apache-2.0
16+
*
17+
* Licensed under the Apache License, Version 2.0 (the License); you may
18+
* not use this file except in compliance with the License.
19+
* You may obtain a copy of the License at
20+
*
21+
* www.apache.org/licenses/LICENSE-2.0
22+
*
23+
* Unless required by applicable law or agreed to in writing, software
24+
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
25+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
26+
* See the License for the specific language governing permissions and
27+
* limitations under the License.
28+
*/
29+
30+
#ifndef _ARM_CONST_STRUCTS_H
31+
#define _ARM_CONST_STRUCTS_H
32+
33+
#include "arm_math.h"
34+
#include "arm_common_tables.h"
35+
36+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
37+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
38+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
39+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
40+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
41+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
42+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
43+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
44+
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
45+
46+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
47+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
48+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
49+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
50+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
51+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
52+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
53+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
54+
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
55+
56+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
57+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
58+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
59+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
60+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
61+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
62+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
63+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
64+
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
65+
66+
#endif

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