diff --git a/bsp/phytium/.gitignore b/bsp/phytium/.gitignore
index f577e88ffe5..a93827b5720 100644
--- a/bsp/phytium/.gitignore
+++ b/bsp/phytium/.gitignore
@@ -1 +1,11 @@
-*.dis
\ No newline at end of file
+*.dis
+*.asm
+/aarch32/tools/gnu_gcc/*
+/aarch32/tools/ci.py
+/aarch32/tools/get_toolchain.py
+/aarch32/smart-env.sh
+/aarch64/tools/gnu_gcc/*
+/aarch64/tools/ci.py
+/aarch64/tools/get_toolchain.py
+/aarch64/smart-env.sh
+**/**/makefile
\ No newline at end of file
diff --git a/bsp/phytium/aarch32/.config b/bsp/phytium/aarch32/.config
index c85d79e0f98..e78d576898c 100644
--- a/bsp/phytium/aarch32/.config
+++ b/bsp/phytium/aarch32/.config
@@ -6,12 +6,12 @@
 #
 # RT-Thread Kernel
 #
-CONFIG_RT_NAME_MAX=8
+CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
-# CONFIG_RT_USING_SMART is not set
+CONFIG_RT_USING_SMART=y
 CONFIG_RT_USING_SMP=y
-CONFIG_RT_CPUS_NR=4
-CONFIG_RT_ALIGN_SIZE=8
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
@@ -22,11 +22,11 @@ CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
-CONFIG_SYSTEM_THREAD_STACK_SIZE=256
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
-CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
 
 #
 # kservice optimization
@@ -35,7 +35,7 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y
 # CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
 # CONFIG_RT_USING_TINY_FFS is not set
-# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
 CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_COLOR is not set
 # CONFIG_RT_DEBUG_INIT_CONFIG is not set
@@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_MEM_CONFIG is not set
 # CONFIG_RT_DEBUG_SLAB_CONFIG is not set
 # CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
 # CONFIG_RT_DEBUG_MODULE_CONFIG is not set
 
 #
@@ -66,7 +67,9 @@ CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
 CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
 # CONFIG_RT_USING_SLAB_AS_HEAP is not set
@@ -84,9 +87,9 @@ CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
-CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLEBUF_SIZE=256
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x50000
+CONFIG_RT_VER_NUM=0x50001
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_RT_USING_CACHE=y
 CONFIG_RT_USING_HW_ATOMIC=y
@@ -96,6 +99,8 @@ CONFIG_RT_USING_CPU_FFS=y
 CONFIG_ARCH_MM_MMU=y
 CONFIG_ARCH_ARM=y
 CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xc0000000
+# CONFIG_RT_IOREMAP_LATE is not set
 CONFIG_ARCH_ARM_CORTEX_A=y
 # CONFIG_RT_SMP_AUTO_BOOT is not set
 # CONFIG_RT_USING_GIC_V2 is not set
@@ -108,7 +113,7 @@ CONFIG_RT_USING_GIC_V3=y
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
 CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # CONFIG_RT_USING_LEGACY is not set
 CONFIG_RT_USING_MSH=y
@@ -126,49 +131,70 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_POSIX=y
 CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
 CONFIG_DFS_FILESYSTEMS_MAX=4
 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
 # CONFIG_RT_USING_DFS_ELMFAT is not set
-# CONFIG_RT_USING_DFS_DEVFS is not set
+CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_CROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
 # CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_LWP_ENABLE_ASID=y
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
 
 #
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_UNAMED_PIPE_NUMBER=64
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
 CONFIG_RT_SERIAL_USING_DMA=y
-CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
-CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PIN is not set
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_NULL is not set
-# CONFIG_RT_USING_ZERO is not set
-# CONFIG_RT_USING_RANDOM is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_FDT is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
@@ -198,19 +224,28 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # POSIX (Portable Operating System Interface) layer
 #
-# CONFIG_RT_USING_POSIX_FS is not set
-# CONFIG_RT_USING_POSIX_DELAY is not set
-# CONFIG_RT_USING_POSIX_CLOCK is not set
-# CONFIG_RT_USING_POSIX_TIMER is not set
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
 # CONFIG_RT_USING_PTHREADS is not set
 # CONFIG_RT_USING_MODULE is not set
 
 #
 # Interprocess Communication (IPC)
 #
-# CONFIG_RT_USING_POSIX_PIPE is not set
-# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
-# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
 
 #
 # Socket is in the 'Network' category
@@ -228,9 +263,13 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Utilities
 #
-# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
 # CONFIG_RT_USING_ULOG is not set
-# CONFIG_RT_USING_UTEST is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
 # CONFIG_RT_USING_VAR_EXPORT is not set
 CONFIG_RT_USING_ADT=y
 # CONFIG_RT_USING_RT_LINK is not set
@@ -627,7 +666,6 @@ CONFIG_RT_USING_ADT=y
 # CONFIG_PKG_USING_LKDGUI is not set
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_WM_LIBRARIES is not set
 
 #
 # Kendryte SDK
@@ -685,7 +723,6 @@ CONFIG_RT_USING_ADT=y
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
-# CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
@@ -1000,6 +1037,9 @@ CONFIG_RT_USING_ADT=y
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART1=y
 # CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
 
 #
 # Board extended module Drivers
@@ -1017,8 +1057,8 @@ CONFIG_USE_AARCH64_L1_TO_AARCH32=y
 #
 # CONFIG_TARGET_F2000_4 is not set
 # CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
 # CONFIG_TARGET_E2000S is not set
 CONFIG_TARGET_E2000=y
 CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
@@ -1055,6 +1095,8 @@ CONFIG_ENABLE_Pl011_UART=y
 # CONFIG_USE_ADC is not set
 # CONFIG_USE_PWM is not set
 # CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
 # CONFIG_LOG_VERBOS is not set
 # CONFIG_LOG_DEBUG is not set
 # CONFIG_LOG_INFO is not set
@@ -1065,4 +1107,5 @@ CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
 CONFIG_INTERRUPT_ROLE_MASTER=y
 # CONFIG_INTERRUPT_ROLE_SLAVE is not set
 # CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
 # CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/.configs b/bsp/phytium/aarch32/.configs
new file mode 100644
index 00000000000..149babc8c19
--- /dev/null
+++ b/bsp/phytium/aarch32/.configs
@@ -0,0 +1,1152 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xc0000000
+# CONFIG_RT_IOREMAP_LATE is not set
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_SMP_AUTO_BOOT is not set
+# CONFIG_RT_USING_GIC_V2 is not set
+CONFIG_RT_USING_GIC_V3=y
+# CONFIG_ARCH_ARM_SECURE_MODE is not set
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_LWP_ENABLE_ASID=y
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+CONFIG_RT_USING_UTESTCASES=y
+
+#
+# Utest Self Testcase
+#
+CONFIG_UTEST_SELF_PASS_TC=y
+
+#
+# Kernel Testcase
+#
+CONFIG_UTEST_MEMHEAP_TC=y
+CONFIG_UTEST_SMALL_MEM_TC=y
+CONFIG_UTEST_IRQ_TC=y
+CONFIG_UTEST_SEMAPHORE_TC=y
+CONFIG_UTEST_EVENT_TC=y
+CONFIG_UTEST_TIMER_TC=y
+CONFIG_UTEST_MESSAGEQUEUE_TC=y
+# CONFIG_UTEST_SIGNAL_TC is not set
+CONFIG_UTEST_MUTEX_TC=y
+CONFIG_UTEST_MAILBOX_TC=y
+CONFIG_UTEST_THREAD_TC=y
+CONFIG_UTEST_ATOMIC_TC=y
+
+#
+# CPP11 Testcase
+#
+# CONFIG_UTEST_CPP11_THREAD_TC is not set
+
+#
+# Utest Serial Testcase
+#
+# CONFIG_UTEST_SERIAL_TC is not set
+
+#
+# RTT Posix Testcase
+#
+# CONFIG_RTT_POSIX_TESTCASE is not set
+
+#
+# Memory Management Subsytem Testcase
+#
+# CONFIG_UTEST_MM_API_TC is not set
+# CONFIG_UTEST_MM_LWP_TC is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_PHYTIUM_ARCH_AARCH32=y
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/Kconfig b/bsp/phytium/aarch32/Kconfig
index 8293bc245dc..cc9a3fe042a 100644
--- a/bsp/phytium/aarch32/Kconfig
+++ b/bsp/phytium/aarch32/Kconfig
@@ -38,14 +38,14 @@ menu "Standalone Setting"
     config TARGET_ARMV8_AARCH32
         bool "Armv8 Aarch32"
         default y
-
+    
     config USE_AARCH64_L1_TO_AARCH32
         bool
         prompt "Use Aarch64 L1 to Aarch32 code"
         default y
         help
             Use the Aarch64 to Aarch32 mode function
-
+    
     source "$STANDALONE_DIR/board/Kconfig"
     source "$STANDALONE_DIR/drivers/Kconfig"
     source "$STANDALONE_DIR/common/Kconfig"
diff --git a/bsp/phytium/aarch32/README.md b/bsp/phytium/aarch32/README.md
index 7dcd689949a..4c2e5944bd1 100644
--- a/bsp/phytium/aarch32/README.md
+++ b/bsp/phytium/aarch32/README.md
@@ -1,18 +1,48 @@
-
 # AARCH32 工作模式使用
 
 - 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
 
+## 1. 准备编译环境
+
+- 在 aarch32 目录下创建 tools 目录，后续用于存放 RT-Thread 编译工具链
+
+```sh
+cd ./aarch32
+mkdir tools
+```
+
+- 在 tools 目录下下载两个 python 脚本，get_toolchain.py 和 ci.py，下载完后给两个脚本添加执行权限
 
-## 1. 如何选择芯片
+```shell
+cd ./tools
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/get_toolchain.py
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/ci.py
+chmod +x get_toolchain.py ci.py
+```
 
-- Windows Env 环境下
+- 然后运行 get_toolchain.py 脚本，拉取 aarch32 交叉编译链`arm-linux-musleabi_for_x86_64-pc-linux-gnu`
 
 ```shell
-    menuconfig
+python3 ./get_toolchain.py arm
 ```
 
-- Linux 环境下
+> RT-Thread 5.0 后必须使用这个带 musl-libc 的编译链，不能使用`arm-none-eabi`
+
+- 在 aarch32 目录下下载脚本 smart-env.sh ，然后运行脚本生效环境变量
+
+```shell
+cd ./aarch32
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/smart-env.sh
+source ./smart-env.sh arm
+```
+
+- 如下所示是 aarch32 编译相关的环境变量，运行 scons 前要确保环境变量设置正确
+
+![aarch32_env](./figures/aarch32_env.png)
+
+## 2. 如何选择芯片
+
+- 以 E2000Q RT-Smart为例，Linux 环境下，运行 make load_e2000q_rtsmart 加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置，
 
 ```shell
     scons --menuconfig
@@ -27,8 +57,7 @@ Standalone Setting > Board Configuration > Chip
 ![](./figures/chip_select.png)
 ![](./figures/phytium_cpu_select.png)
 
-## 2. 如何选择驱动
-
+## 3. 如何选择驱动
 
 ```shell
     scons --menuconfig
@@ -42,9 +71,7 @@ Hardware Drivers > On-chip Peripheral Drivers
 
 ![](./figures/select_driver.png)
 
-
-## 3. 开启SDK中内部调试信息
-
+## 4. 开启SDK中内部调试信息
 
 ```shell
     scons --menuconfig
@@ -55,8 +82,19 @@ Hardware Drivers > On-chip Peripheral Drivers
 ![](./figures/select_debug_info.png)
 
 
+## 4. 如何切换至RT-Thread Smart 工作模式
+
+```shell
+
+ scons --menuconfig
+
+```
+
+![1682477587050](figures/1682477587050.png)
 
-## 4. 编译程序
+开发者通过以上配置开启RT-Thread Smart 功能
+
+## 5. 编译程序
 
 ```shell
     scons -c
@@ -71,18 +109,36 @@ rtthread_a32.elf
 rtthread_a32.map
 ```
 
-## 5. 打包导出工程源代码
+## 6. 启动镜像程序
+
+- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
+
+- 首先在 Phytium 开发板上输入，上传 bin 文件
 
+```
+loadx 80080000
+```
+
+![](./figures/ymodem_upload.png)
+
+- 加载 bin 文件完成后，输入下列命令启动
+
+```
+go 80080000
+```
+
+## 7. 打包导出工程源代码
 
 - 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
+
 ```
 python ./export_project.py -n=phytium-a32 -o=D:/proj/rt-thread-e2000/phytium-a32
 ```
 
 ![](./figures/export_project.png)
 
+- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
 
-- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR 
 > env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
 
 ```
@@ -99,10 +155,12 @@ config STANDALONE_DIR
 
 - 输入 menuconfig 和 scons 完成编译
 
+## 8. 将工程导入 RT-Studio
 
-## 6. 将工程导入 RT-Studio
-
-- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
+- 在 RT-Studio 使用功能 `RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
 - 设置 BSP 工程的交叉编译链后进行后续开发
 
-![](./figures/import_project.png)
\ No newline at end of file
+![](./figures/import_project.png)
+
+python get_toolchain.py arm
+./smart-env.bat
diff --git a/bsp/phytium/aarch32/SConstruct b/bsp/phytium/aarch32/SConstruct
index 2d1eaf98f7e..f0bd9488389 100644
--- a/bsp/phytium/aarch32/SConstruct
+++ b/bsp/phytium/aarch32/SConstruct
@@ -53,6 +53,11 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma
     # include board
     objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
 
+
+if GetDepend('RT_USING_SMART'):
+    # use smart link.lds
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
+
 # make a building
 DoBuilding(TARGET, objs)
 
diff --git a/bsp/phytium/aarch32/applications/main.c b/bsp/phytium/aarch32/applications/main.c
index e19779e1132..5abc3130b02 100644
--- a/bsp/phytium/aarch32/applications/main.c
+++ b/bsp/phytium/aarch32/applications/main.c
@@ -70,7 +70,7 @@ void demo_core(void)
 int main(void)
 {
 #ifdef RT_USING_SMP
-    demo_core();
+    // demo_core();
 #endif
     return RT_EOK;
 }
diff --git a/bsp/phytium/aarch32/applications/mnt.c b/bsp/phytium/aarch32/applications/mnt.c
new file mode 100644
index 00000000000..447f518f78d
--- /dev/null
+++ b/bsp/phytium/aarch32/applications/mnt.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-04-27     huanghe      first version
+ *
+ */
+
+#include <rtthread.h>
+#ifdef RT_USING_DFS_RAMFS
+#include <dfs_fs.h>
+
+extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
+
+int mnt_init(void)
+{
+    rt_uint8_t *pool = RT_NULL;
+    rt_size_t size = 8*1024*1024;
+
+    pool = rt_malloc(size);
+    if (pool == RT_NULL)
+        return 0;
+
+    if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
+        rt_kprintf("RAM file system initializated!\n");
+    else
+        rt_kprintf("RAM file system initializate failed!\n");
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
+#ifdef BSP_USING_SDCARD_FATFS
+#include <dfs_fs.h>
+#include <dfs_file.h>
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+static int filesystem_mount(void)
+{
+    while(rt_device_find("sd0") == RT_NULL)
+    {
+        rt_thread_mdelay(1);
+    }
+
+    int ret = dfs_mount("sd0", "/", "elm", 0, 0);
+    if (ret != 0)
+    {
+        rt_kprintf("ret: %d\n",ret);
+        LOG_E("sd0 mount to '/' failed!");
+        return ret;
+    }
+
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(filesystem_mount);
+#endif
diff --git a/bsp/phytium/aarch32/configs/e2000d_rtsmart b/bsp/phytium/aarch32/configs/e2000d_rtsmart
new file mode 100644
index 00000000000..e78d576898c
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000d_rtsmart
@@ -0,0 +1,1111 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xc0000000
+# CONFIG_RT_IOREMAP_LATE is not set
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_SMP_AUTO_BOOT is not set
+# CONFIG_RT_USING_GIC_V2 is not set
+CONFIG_RT_USING_GIC_V3=y
+# CONFIG_ARCH_ARM_SECURE_MODE is not set
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_LWP_ENABLE_ASID=y
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_PHYTIUM_ARCH_AARCH32=y
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/configs/e2000d_rtsmart.h b/bsp/phytium/aarch32/configs/e2000d_rtsmart.h
new file mode 100644
index 00000000000..913e053bd75
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000d_rtsmart.h
@@ -0,0 +1,319 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMART
+#define RT_USING_SMP
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define KERNEL_VADDR_START 0xc0000000
+#define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define LWP_ENABLE_ASID
+#define RT_LWP_SHM_MAX_NR 64
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 1024
+#define RT_USING_TTY
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+#define RT_USING_POSIX_MESSAGE_QUEUE
+#define RT_USING_POSIX_MESSAGE_SEMAPHORE
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define PHYTIUM_ARCH_AARCH32
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH32
+#define USE_AARCH64_L1_TO_AARCH32
+
+/* Board Configuration */
+
+#define TARGET_E2000D
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_GIC
+#define ENABLE_GICV3
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+#define USE_DEFAULT_INTERRUPT_CONFIG
+#define INTERRUPT_ROLE_MASTER
+
+#endif
diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread b/bsp/phytium/aarch32/configs/e2000d_rtthread
new file mode 100644
index 00000000000..9ccf9ae3b7c
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000d_rtthread
@@ -0,0 +1,1098 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_SMP_AUTO_BOOT is not set
+# CONFIG_RT_USING_GIC_V2 is not set
+CONFIG_RT_USING_GIC_V3=y
+# CONFIG_ARCH_ARM_SECURE_MODE is not set
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_PHYTIUM_ARCH_AARCH32=y
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread.h b/bsp/phytium/aarch32/configs/e2000d_rtthread.h
new file mode 100644
index 00000000000..9d6a4ca7936
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000d_rtthread.h
@@ -0,0 +1,308 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMP
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 1024
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+#define RT_USING_POSIX_MESSAGE_QUEUE
+#define RT_USING_POSIX_MESSAGE_SEMAPHORE
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define PHYTIUM_ARCH_AARCH32
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH32
+#define USE_AARCH64_L1_TO_AARCH32
+
+/* Board Configuration */
+
+#define TARGET_E2000D
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_GIC
+#define ENABLE_GICV3
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+#define USE_DEFAULT_INTERRUPT_CONFIG
+#define INTERRUPT_ROLE_MASTER
+
+#endif
diff --git a/bsp/phytium/aarch32/configs/e2000q_rtsmart b/bsp/phytium/aarch32/configs/e2000q_rtsmart
new file mode 100644
index 00000000000..e844590ed2a
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000q_rtsmart
@@ -0,0 +1,1111 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xc0000000
+# CONFIG_RT_IOREMAP_LATE is not set
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_SMP_AUTO_BOOT is not set
+# CONFIG_RT_USING_GIC_V2 is not set
+CONFIG_RT_USING_GIC_V3=y
+# CONFIG_ARCH_ARM_SECURE_MODE is not set
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_LWP_ENABLE_ASID=y
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_PHYTIUM_ARCH_AARCH32=y
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/configs/e2000q_rtsmart.h b/bsp/phytium/aarch32/configs/e2000q_rtsmart.h
new file mode 100644
index 00000000000..3e169f917da
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000q_rtsmart.h
@@ -0,0 +1,319 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMART
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define KERNEL_VADDR_START 0xc0000000
+#define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define LWP_ENABLE_ASID
+#define RT_LWP_SHM_MAX_NR 64
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 1024
+#define RT_USING_TTY
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+#define RT_USING_POSIX_MESSAGE_QUEUE
+#define RT_USING_POSIX_MESSAGE_SEMAPHORE
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define PHYTIUM_ARCH_AARCH32
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH32
+#define USE_AARCH64_L1_TO_AARCH32
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_GIC
+#define ENABLE_GICV3
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+#define USE_DEFAULT_INTERRUPT_CONFIG
+#define INTERRUPT_ROLE_MASTER
+
+#endif
diff --git a/bsp/phytium/aarch32/configs/e2000q_rtthread b/bsp/phytium/aarch32/configs/e2000q_rtthread
new file mode 100644
index 00000000000..1ecf99a540b
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000q_rtthread
@@ -0,0 +1,1098 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=4096
+CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=256
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+CONFIG_RT_USING_CPU_FFS=y
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARM_CORTEX_A=y
+# CONFIG_RT_SMP_AUTO_BOOT is not set
+# CONFIG_RT_USING_GIC_V2 is not set
+CONFIG_RT_USING_GIC_V3=y
+# CONFIG_ARCH_ARM_SECURE_MODE is not set
+# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=1024
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+CONFIG_RT_USING_POSIX_PIPE=y
+CONFIG_RT_USING_POSIX_PIPE_SIZE=512
+CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y
+CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+CONFIG_RT_USING_UTEST=y
+CONFIG_UTEST_THR_STACK_SIZE=4096
+CONFIG_UTEST_THR_PRIORITY=20
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_PHYTIUM_ARCH_AARCH32=y
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH32=y
+CONFIG_USE_AARCH64_L1_TO_AARCH32=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+# CONFIG_USE_SPI is not set
+# CONFIG_USE_QSPI is not set
+CONFIG_USE_GIC=y
+CONFIG_ENABLE_GICV3=y
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y
+CONFIG_INTERRUPT_ROLE_MASTER=y
+# CONFIG_INTERRUPT_ROLE_SLAVE is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch32/configs/e2000q_rtthread.h b/bsp/phytium/aarch32/configs/e2000q_rtthread.h
new file mode 100644
index 00000000000..39be678f076
--- /dev/null
+++ b/bsp/phytium/aarch32/configs/e2000q_rtthread.h
@@ -0,0 +1,308 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 256
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define RT_USING_CPU_FFS
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define ARCH_ARM_CORTEX_A
+#define RT_USING_GIC_V3
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 1024
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+#define RT_USING_POSIX_MESSAGE_QUEUE
+#define RT_USING_POSIX_MESSAGE_SEMAPHORE
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define PHYTIUM_ARCH_AARCH32
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH32
+#define USE_AARCH64_L1_TO_AARCH32
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_GIC
+#define ENABLE_GICV3
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+#define USE_DEFAULT_INTERRUPT_CONFIG
+#define INTERRUPT_ROLE_MASTER
+
+#endif
diff --git a/bsp/phytium/aarch32/export_project.py b/bsp/phytium/aarch32/export_project.py
index d28e6d74304..9b326e9f36d 100644
--- a/bsp/phytium/aarch32/export_project.py
+++ b/bsp/phytium/aarch32/export_project.py
@@ -1,3 +1,18 @@
+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+#
+# Copyright (c) 2022, RT-Thread Development Team
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Email: opensource_embedded@phytium.com.cn
+#
+#
+# Change Logs:
+# Date           Author       Notes
+# 2022-11-15     zhugengyu    The first version
+#
+
 import os
 import shutil
 import argparse
diff --git a/bsp/phytium/aarch32/figures/1682477587050.png b/bsp/phytium/aarch32/figures/1682477587050.png
new file mode 100644
index 00000000000..b4cd94f336a
Binary files /dev/null and b/bsp/phytium/aarch32/figures/1682477587050.png differ
diff --git a/bsp/phytium/aarch32/figures/aarch32_env.png b/bsp/phytium/aarch32/figures/aarch32_env.png
new file mode 100644
index 00000000000..4f02aa25748
Binary files /dev/null and b/bsp/phytium/aarch32/figures/aarch32_env.png differ
diff --git a/bsp/phytium/aarch32/figures/ymodem_upload.png b/bsp/phytium/aarch32/figures/ymodem_upload.png
new file mode 100644
index 00000000000..9d166a09e83
Binary files /dev/null and b/bsp/phytium/aarch32/figures/ymodem_upload.png differ
diff --git a/bsp/phytium/aarch32/link.lds b/bsp/phytium/aarch32/link.lds
index 0e7194b9eaa..5f8645485b3 100644
--- a/bsp/phytium/aarch32/link.lds
+++ b/bsp/phytium/aarch32/link.lds
@@ -5,18 +5,25 @@ ENTRY(_boot)
 
 SECTIONS
 {
-    . = 0x80100000;
+    . = 0x80080000;
 
     .text :
     {
 
         *(.boot)
         . = ALIGN(64);
-
+        
         *(.vectors)
         *(.text)
         *(.text.*)
 
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+
         /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
@@ -42,6 +49,13 @@ SECTIONS
     } =0
     __text_end = .;
 
+    .ARM.exidx   :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
     __rodata_start = .;
     .rodata   : { *(.rodata) *(.rodata.*) }
     __rodata_end = .;
diff --git a/bsp/phytium/aarch32/link_smart.lds b/bsp/phytium/aarch32/link_smart.lds
new file mode 100644
index 00000000000..209468d4a43
--- /dev/null
+++ b/bsp/phytium/aarch32/link_smart.lds
@@ -0,0 +1,120 @@
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+
+ENTRY(_boot)
+
+SECTIONS
+{
+    /* . = 0x80080000; */
+    . = 0xc0080000;
+
+    .text :
+    {
+
+        *(.boot)
+        . = ALIGN(64);
+        
+        *(.vectors)
+        *(.text)
+        *(.text.*)
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+    } =0
+    __text_end = .;
+
+    .ARM.exidx   :
+    {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    }
+
+    __rodata_start = .;
+    .rodata   : { *(.rodata) *(.rodata.*) }
+    __rodata_end = .;
+
+    . = ALIGN(4);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        /* new GCC version uses .init_array */
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    }
+
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16 * 1024);
+    .l1_page_table :
+    {
+        __l1_page_table_start = .;
+        . += 16K;
+    }
+
+    . = ALIGN(8);
+    __data_start = .;
+    .data :
+    {
+        *(.data)
+        *(.data.*)
+    }
+    __data_end = .;
+
+    . = ALIGN(8);
+    __bss_start = .;
+    .bss       :
+    {
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    }
+    . = ALIGN(4);
+    __bss_end = .;
+
+    /* Stabs debugging sections.  */
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+
+    _end = .;
+}
diff --git a/bsp/phytium/aarch32/makefile b/bsp/phytium/aarch32/makefile
new file mode 100644
index 00000000000..13f412d6dfb
--- /dev/null
+++ b/bsp/phytium/aarch32/makefile
@@ -0,0 +1,78 @@
+.PHONY: debug boot all clean menuconfig
+
+CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
+CXX = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)g++
+CPP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc -E -P -x c
+STRIP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)strip --strip-unneeded
+OBJCOPY = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objcopy
+OBJDUMP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
+LD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ld
+AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
+NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
+OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
+
+include .config
+
+ifdef CONFIG_TARGET_E2000Q
+RTCONFIG := e2000q
+endif
+
+ifdef CONFIG_TARGET_E2000D
+RTCONFIG := e2000d
+endif
+
+ifdef CONFIG_RT_USING_SMART
+RTCONFIG := $(RTCONFIG)_rtsmart
+else
+RTCONFIG := $(RTCONFIG)_rtthread
+endif
+
+boot:
+	make all
+	cp rtthread_a32.elf /mnt/d/tftboot
+	cp rtthread_a32.bin /mnt/d/tftboot
+
+debug:
+	@$(OD) -D rtthread_a32.elf > rtthread_a32.asm
+	@$(OD) -S rtthread_a32.elf > rtthread_a32.dis
+	
+all:
+	@echo "Build started..."
+	scons -j1024
+
+clean:
+	@echo "Cleaning..."
+	scons -c
+
+menuconfig:
+	@echo "Running menuconfig..."
+	scons --menuconfig
+
+saveconfig:
+	@echo "Save configs to" ./configs/$(RTCONFIG)
+	@cp ./.config ./configs/$(RTCONFIG) -f
+	@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
+
+load_e2000q_rtsmart:
+	@echo "Load configs from ./configs/e2000q_rtsmart"
+	@cp ./configs/e2000q_rtsmart ./.config -f
+	@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000q_rtthread:
+	@echo "Load configs from ./configs/e2000q_rtthread"
+	@cp ./configs/e2000q_rtthread ./.config -f
+	@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000d_rtsmart:
+	@echo "Load configs from ./configs/e2000d_rtsmart"
+	@cp ./configs/e2000d_rtsmart ./.config -f
+	@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000d_rtthread:
+	@echo "Load configs from ./configs/e2000d_rtthread"
+	@cp ./configs/e2000d_rtthread ./.config -f
+	@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
+	scons -c
\ No newline at end of file
diff --git a/bsp/phytium/aarch32/rtconfig.h b/bsp/phytium/aarch32/rtconfig.h
index b6e58d09ea8..913e053bd75 100644
--- a/bsp/phytium/aarch32/rtconfig.h
+++ b/bsp/phytium/aarch32/rtconfig.h
@@ -6,10 +6,11 @@
 
 /* RT-Thread Kernel */
 
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 16
+#define RT_USING_SMART
 #define RT_USING_SMP
-#define RT_CPUS_NR 4
-#define RT_ALIGN_SIZE 8
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
 #define RT_TICK_PER_SECOND 1000
@@ -18,15 +19,16 @@
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 256
-#define SYSTEM_THREAD_STACK_SIZE 256
+#define IDLE_THREAD_STACK_SIZE 4096
+#define SYSTEM_THREAD_STACK_SIZE 4096
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 512
+#define RT_TIMER_THREAD_STACK_SIZE 4096
 
 /* kservice optimization */
 
 #define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
 #define RT_DEBUG
 
 /* Inter-Thread communication */
@@ -42,6 +44,8 @@
 #define RT_PAGE_MAX_ORDER 11
 #define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
 
@@ -49,15 +53,16 @@
 
 #define RT_USING_DEVICE
 #define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLEBUF_SIZE 256
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x50000
+#define RT_VER_NUM 0x50001
 #define RT_USING_CACHE
 #define RT_USING_HW_ATOMIC
 #define RT_USING_CPU_FFS
 #define ARCH_MM_MMU
 #define ARCH_ARM
 #define ARCH_ARM_MMU
+#define KERNEL_VADDR_START 0xc0000000
 #define ARCH_ARM_CORTEX_A
 #define RT_USING_GIC_V3
 
@@ -65,7 +70,7 @@
 
 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_STACK_SIZE 8192
 #define RT_MAIN_THREAD_PRIORITY 10
 #define RT_USING_MSH
 #define RT_USING_FINSH
@@ -80,22 +85,43 @@
 #define MSH_USING_BUILT_IN_COMMANDS
 #define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
 #define RT_USING_DFS
 #define DFS_USING_POSIX
 #define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
 #define DFS_FILESYSTEMS_MAX 4
 #define DFS_FILESYSTEM_TYPES_MAX 4
-#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define LWP_ENABLE_ASID
+#define RT_LWP_SHM_MAX_NR 64
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
 #define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
-#define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_PIN
+#define RT_SERIAL_RB_BUFSZ 1024
+#define RT_USING_TTY
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
 
 /* Using USB */
 
@@ -106,9 +132,23 @@
 
 /* POSIX (Portable Operating System Interface) layer */
 
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_POLL
+#define RT_USING_POSIX_SELECT
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_AIO
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
 
 /* Interprocess Communication (IPC) */
 
+#define RT_USING_POSIX_PIPE
+#define RT_USING_POSIX_PIPE_SIZE 512
+#define RT_USING_POSIX_MESSAGE_QUEUE
+#define RT_USING_POSIX_MESSAGE_SEMAPHORE
 
 /* Socket is in the 'Network' category */
 
@@ -118,6 +158,11 @@
 
 /* Utilities */
 
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_UTEST
+#define UTEST_THR_STACK_SIZE 4096
+#define UTEST_THR_PRIORITY 20
 #define RT_USING_ADT
 
 /* RT-Thread Utestcases */
@@ -254,7 +299,7 @@
 
 /* Board Configuration */
 
-#define TARGET_E2000Q
+#define TARGET_E2000D
 #define TARGET_E2000
 #define DEFAULT_DEBUG_PRINT_UART1
 
diff --git a/bsp/phytium/aarch32/rtconfig.py b/bsp/phytium/aarch32/rtconfig.py
index a5202911db0..507716031f8 100644
--- a/bsp/phytium/aarch32/rtconfig.py
+++ b/bsp/phytium/aarch32/rtconfig.py
@@ -2,67 +2,53 @@
 import rtconfig
 
 # toolchains options
-ARCH='arm'
-CPU='cortex-a'
-CROSS_TOOL='gcc'
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = r'../../..'
-
-if os.getenv('RTT_CC'):
-    CROSS_TOOL = os.getenv('RTT_CC')
-
-# only support GNU GCC compiler.
+ARCH        ='arm'
+CPU         ='cortex-a'
+CROSS_TOOL  = 'gcc'
 PLATFORM    = 'gcc'
-EXEC_PATH   = r'/usr/lib/arm-none-eabi/bin'
-if os.getenv('AARCH32_CROSS_PATH'):
-    EXEC_PATH = os.getenv('AARCH32_CROSS_PATH')
-    print('EXEC_PATH = {}'.format(EXEC_PATH))
-else:
-    print('AARCH32_CROSS_PATH not found')
+EXEC_PATH   = os.getenv('RTT_EXEC_PATH') or r'/usr/bin'
+BUILD       = 'debug'
 
-BUILD = 'debug'
+LINK_SCRIPT = 'link.lds'
 
-LIBPATH = EXEC_PATH + r'/../lib'
 
 if PLATFORM == 'gcc':
-    # toolchains
-    PREFIX = 'arm-none-eabi-'
-    CC = PREFIX + 'gcc'
-    CXX = PREFIX + 'g++'
-    AS = PREFIX + 'gcc'
-    AR = PREFIX + 'ar'
-    LINK = PREFIX + 'gcc'
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
     TARGET_EXT = 'elf'
-    SIZE = PREFIX + 'size'
+    SIZE    = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
-    OBJCPY = PREFIX + 'objcopy'
-    STRIP = PREFIX + 'strip'
-
-    DEVICE = ' -g -DGUEST  -ffreestanding  -Wextra -g -mfpu=crypto-neon-fp-armv8 -mfloat-abi=softfp -march=armv8-a -fdiagnostics-color=always'
-
-    # CFLAGS = DEVICE + ' -Wall'
-    CFLAGS = DEVICE
-    AFLAGS = ' -c'+ DEVICE + ' -fsingle-precision-constant  -fno-builtin -x assembler-with-cpp -D__ASSEMBLY__'    
-    LINK_SCRIPT = 'link.lds'
-    LFLAGS = DEVICE + '  -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors'+\
-                      ' -T %s' % LINK_SCRIPT
-
-    CPATH = ''
-    LPATH = LIBPATH
-
-    # generate debug info in all cases
-    AFLAGS += ' -gdwarf-2'
-    CFLAGS += ' -g -gdwarf-2'
+    OBJCPY  = PREFIX + 'objcopy'
+    STRIP   = PREFIX + 'strip'
+    CFPFLAGS = ' -msoft-float'
+    AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon'
+    DEVICE   = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
+
+    CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
+    CFLAGS  = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -D_POSIX_SOURCE -fdiagnostics-color=always'
+    AFLAGS  = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp'    
+    LFLAGS  = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a32.map,-cref,-u,system_vectors -T '+ LINK_SCRIPT + ' -lsupc++ -lgcc -static'
+    CPATH   = ''
+    LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0'
+        CFLAGS   += ' -O0 -gdwarf-2'
+        CXXFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS   += ' -gdwarf-2'
     else:
-        CFLAGS += ' -O2'
-
-    CXXFLAGS = CFLAGS
-
-    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' +\
-                  SIZE + ' $TARGET \n'
+        CFLAGS   += ' -Os'
+        CXXFLAGS += ' -Os'
+    CXXFLAGS += ' -Woverloaded-virtual -fno-rtti'
+
+    M_CFLAGS = CFLAGS + ' -mlong-calls -fPIC '
+    M_CXXFLAGS = CXXFLAGS + ' -mlong-calls -fPIC'
+    M_LFLAGS = DEVICE + CXXFLAGS + ' -Wl,--gc-sections,-z,max-page-size=0x4' +\
+                                    ' -shared -fPIC -nostartfiles -nostdlib -static-libgcc'
+    M_POST_ACTION = STRIP + ' -R .hash $TARGET\n' + SIZE + ' $TARGET \n'
+
+    DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a32.asm\n'
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a32.bin\n' + SIZE + ' $TARGET \n'
diff --git a/bsp/phytium/aarch32/sdkconfig.h b/bsp/phytium/aarch32/sdkconfig.h
deleted file mode 100644
index 8913e55fd97..00000000000
--- a/bsp/phytium/aarch32/sdkconfig.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: sdkconfig.h
- * Date: 2022-10-13 15:53:46
- * LastEditTime: 2022-10-13 15:53:46
- * Description:  This file is for
- *
- * Modify History:
- *  Ver   Who  Date   Changes
- * ----- ------  -------- --------------------------------------
- */
-
-#ifndef SDK_CONFIG_H__
-#define SDK_CONFIG_H__
-
-#include "rtconfig.h"
-
-
-/* arch */
-
-#if defined(TARGET_ARMV8_AARCH32)
-    #define CONFIG_TARGET_ARMV8_AARCH32
-#endif
-
-#if defined(USE_AARCH64_L1_TO_AARCH32)
-    #define CONFIG_USE_AARCH64_L1_TO_AARCH32
-#endif
-
-/* board */
-
-/*  E2000 */
-
-#if defined(TARGET_E2000)
-    #define CONFIG_TARGET_E2000
-#endif
-
-
-/* debug */
-
-#ifdef LOG_VERBOS
-    #define CONFIG_LOG_VERBOS
-#endif
-
-#ifdef LOG_ERROR
-    #define CONFIG_LOG_ERROR
-#endif
-
-#ifdef LOG_WARN
-    #define CONFIG_LOG_WARN
-#endif
-
-#ifdef LOG_INFO
-    #define CONFIG_LOG_INFO
-#endif
-
-#ifdef LOG_DEBUG
-    #define CONFIG_LOG_DEBUG
-#endif
-
-#ifdef BOOTUP_DEBUG_PRINTS
-    #define CONFIG_BOOTUP_DEBUG_PRINTS
-#endif
-
-#endif
diff --git a/bsp/phytium/aarch64/.config b/bsp/phytium/aarch64/.config
index 400a6c38f3e..c63a196b1f3 100644
--- a/bsp/phytium/aarch64/.config
+++ b/bsp/phytium/aarch64/.config
@@ -10,20 +10,20 @@ CONFIG_RT_NAME_MAX=16
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMART is not set
 CONFIG_RT_USING_SMP=y
-CONFIG_RT_CPUS_NR=4
-CONFIG_RT_ALIGN_SIZE=8
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
 CONFIG_RT_THREAD_PRIORITY_MAX=32
-CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_TICK_PER_SECOND=1000
 CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=4096
-CONFIG_SYSTEM_THREAD_STACK_SIZE=4096
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
 CONFIG_RT_USING_TIMER_SOFT=y
 CONFIG_RT_TIMER_THREAD_PRIO=4
 CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
@@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y
 # CONFIG_RT_DEBUG_MEM_CONFIG is not set
 # CONFIG_RT_DEBUG_SLAB_CONFIG is not set
 # CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_PAGE_LEAK is not set
 # CONFIG_RT_DEBUG_MODULE_CONFIG is not set
 
 #
@@ -66,7 +67,9 @@ CONFIG_RT_PAGE_MAX_ORDER=11
 CONFIG_RT_USING_MEMPOOL=y
 CONFIG_RT_USING_SMALL_MEM=y
 # CONFIG_RT_USING_SLAB is not set
-# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
 CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
 # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
 # CONFIG_RT_USING_SLAB_AS_HEAP is not set
@@ -86,12 +89,12 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x50000
+CONFIG_RT_VER_NUM=0x50001
 # CONFIG_RT_USING_STDC_ATOMIC is not set
 CONFIG_ARCH_CPU_64BIT=y
 CONFIG_RT_USING_CACHE=y
 CONFIG_RT_USING_HW_ATOMIC=y
-# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_MM_MMU=y
@@ -104,7 +107,7 @@ CONFIG_ARCH_ARMV8=y
 #
 CONFIG_RT_USING_COMPONENTS_INIT=y
 CONFIG_RT_USING_USER_MAIN=y
-CONFIG_RT_MAIN_THREAD_STACK_SIZE=4096
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # CONFIG_RT_USING_LEGACY is not set
 CONFIG_RT_USING_MSH=y
@@ -122,18 +125,24 @@ CONFIG_FINSH_USING_DESCRIPTION=y
 # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
 # CONFIG_FINSH_USING_AUTH is not set
 CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
 CONFIG_RT_USING_DFS=y
 CONFIG_DFS_USING_POSIX=y
 CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
 CONFIG_DFS_FILESYSTEMS_MAX=4
 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
-CONFIG_DFS_FD_MAX=16
-# CONFIG_RT_USING_DFS_MNTTABLE is not set
 # CONFIG_RT_USING_DFS_ELMFAT is not set
-# CONFIG_RT_USING_DFS_DEVFS is not set
+CONFIG_RT_USING_DFS_DEVFS=y
 # CONFIG_RT_USING_DFS_ROMFS is not set
 # CONFIG_RT_USING_DFS_CROMFS is not set
-# CONFIG_RT_USING_DFS_RAMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
 # CONFIG_RT_USING_DFS_TMPFS is not set
 # CONFIG_RT_USING_FAL is not set
 
@@ -155,18 +164,20 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CPUTIME is not set
 # CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_USING_PHY is not set
-CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PIN is not set
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-# CONFIG_RT_USING_NULL is not set
-# CONFIG_RT_USING_ZERO is not set
-# CONFIG_RT_USING_RANDOM is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
 # CONFIG_RT_USING_FDT is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
@@ -196,10 +207,18 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # POSIX (Portable Operating System Interface) layer
 #
-# CONFIG_RT_USING_POSIX_FS is not set
-# CONFIG_RT_USING_POSIX_DELAY is not set
-# CONFIG_RT_USING_POSIX_CLOCK is not set
-# CONFIG_RT_USING_POSIX_TIMER is not set
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
 # CONFIG_RT_USING_PTHREADS is not set
 # CONFIG_RT_USING_MODULE is not set
 
@@ -226,7 +245,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Utilities
 #
-# CONFIG_RT_USING_RYM is not set
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
 # CONFIG_RT_USING_VAR_EXPORT is not set
@@ -624,7 +645,6 @@ CONFIG_RT_USING_ADT=y
 # CONFIG_PKG_USING_LKDGUI is not set
 # CONFIG_PKG_USING_NRF5X_SDK is not set
 # CONFIG_PKG_USING_NRFX is not set
-# CONFIG_PKG_USING_WM_LIBRARIES is not set
 
 #
 # Kendryte SDK
@@ -682,7 +702,6 @@ CONFIG_RT_USING_ADT=y
 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set
 # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
 # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
-# CONFIG_PKG_USING_BL_MCU_SDK is not set
 # CONFIG_PKG_USING_SOFT_SERIAL is not set
 # CONFIG_PKG_USING_MB85RS16 is not set
 # CONFIG_PKG_USING_RFM300 is not set
@@ -721,7 +740,31 @@ CONFIG_RT_USING_ADT=y
 #
 # samples: kernel and components samples
 #
-# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
 # CONFIG_PKG_USING_NETWORK_SAMPLES is not set
 # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
@@ -997,6 +1040,9 @@ CONFIG_RT_USING_ADT=y
 CONFIG_BSP_USING_UART=y
 CONFIG_RT_USING_UART1=y
 # CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
 
 #
 # Board extended module Drivers
@@ -1004,6 +1050,7 @@ CONFIG_RT_USING_UART1=y
 CONFIG_BSP_USING_GIC=y
 CONFIG_BSP_USING_GICV3=y
 CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=0
 
 #
 # Standalone Setting
@@ -1015,8 +1062,8 @@ CONFIG_TARGET_ARMV8_AARCH64=y
 #
 # CONFIG_TARGET_F2000_4 is not set
 # CONFIG_TARGET_D2000 is not set
-CONFIG_TARGET_E2000Q=y
-# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
 # CONFIG_TARGET_E2000S is not set
 CONFIG_TARGET_E2000=y
 CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
@@ -1026,8 +1073,14 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
 #
 # Components Configuration
 #
-# CONFIG_USE_SPI is not set
-# CONFIG_USE_QSPI is not set
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
 # CONFIG_USE_GIC is not set
 CONFIG_USE_SERIAL=y
 
@@ -1052,6 +1105,8 @@ CONFIG_ENABLE_Pl011_UART=y
 # CONFIG_USE_ADC is not set
 # CONFIG_USE_PWM is not set
 # CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
 # CONFIG_LOG_VERBOS is not set
 # CONFIG_LOG_DEBUG is not set
 # CONFIG_LOG_INFO is not set
@@ -1060,4 +1115,5 @@ CONFIG_LOG_ERROR=y
 # CONFIG_LOG_NONE is not set
 # CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
 # CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
 # CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/.configs b/bsp/phytium/aarch64/.configs
new file mode 100644
index 00000000000..c1497e82e5c
--- /dev/null
+++ b/bsp/phytium/aarch64/.configs
@@ -0,0 +1,1116 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV3=y
+CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=0
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH64=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
+# CONFIG_USE_GIC is not set
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/Kconfig b/bsp/phytium/aarch64/Kconfig
index 973bc46fe14..25f6b180c35 100644
--- a/bsp/phytium/aarch64/Kconfig
+++ b/bsp/phytium/aarch64/Kconfig
@@ -38,7 +38,21 @@ config PHYTIUM_ARCH_AARCH64
     select RT_USING_USER_MAIN
     select ARCH_CPU_64BIT
     select TARGET_ARMV8_AARCH64
+    select ARCH_ARM_BOOTWITH_FLUSH_CACHE
     default y
+    
+
+if TARGET_E2000Q
+    config ARM_SPI_BIND_CPU_ID
+        int 
+        default 2
+endif
+
+if TARGET_E2000D
+    config ARM_SPI_BIND_CPU_ID
+        int 
+        default 0
+endif
 
 menu "Standalone Setting"
     config TARGET_ARMV8_AARCH64
diff --git a/bsp/phytium/aarch64/README.md b/bsp/phytium/aarch64/README.md
index 8ca947b5d85..94dace980d2 100644
--- a/bsp/phytium/aarch64/README.md
+++ b/bsp/phytium/aarch64/README.md
@@ -1,31 +1,52 @@
-<!--
- * Copyright : (C) 2022 Phytium Information Technology, Inc. 
- * All Rights Reserved.
- *  
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
- * either version 1.0 of the License, or (at your option) any later version. 
- *  
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details. 
- *  
- * 
- * FilePath: README.md
- * Date: 2022-10-17 15:16:12
- * LastEditTime: 2022-10-17 15:16:12
- * Description:  This file is for 
- * 
- * Modify History: 
- *  Ver   Who  Date   Changes
- * ----- ------  -------- --------------------------------------
--->
-
 # AARCH64 工作模式使用
 
 - 当开发者需要基于 Phytium 系列芯片进行开发时，可以从以下几个步骤出发配置芯片
 
-## 1. 如何选择芯片
+## 1. 准备编译环境
+
+- 在 aarch64 目录下创建 tools 目录，后续用于存放 RT-Thread 编译工具链
+
+```sh
+cd ./aarch64
+mkdir tools
+```
+
+- 在 tools 目录下下载两个 python 脚本，get_toolchain.py 和 ci.py，下载完后给两个脚本添加执行权限
+
+```shell
+cd ./tools
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/get_toolchain.py
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/tools/ci.py
+chmod +x get_toolchain.py ci.py
+```
+
+- 然后运行 get_toolchain.py 脚本，拉取 aarch64 交叉编译链`aarch64-linux-musleabi_for_x86_64-pc-linux-gnu`
+
+```shell
+python3 ./get_toolchain.py aarch64
+```
+
+> RT-Thread 5.0 后必须使用这个带 musl-libc 的编译链，不能使用`aarch64-none-elf`
+
+- 在 aarch64 目录下下载脚本 smart_env.sh ，然后运行脚本生效环境变量
+
+```shell
+cd ./aarch64
+wget https://gitee.com/rtthread/ART-Pi-smart/raw/master/smart-env.sh
+source ./smart-env.sh aarch64
+```
+
+- 如下所示是 aarch64 编译相关的环境变量，运行 scons 前要确保环境变量设置正确
+
+![aarch64_env](./figures/aarch64_env.png)
+
+## NOTE
+
+- 请使用ubuntu20.04 开发环境进行上述操作，其他开发环境没有进行测试
+
+## 2. 如何选择芯片
+
+- 以 E2000Q RT-Smart为例，Linux 环境下，运行 make load_e2000q_rtsmart 加载默认的 rtconfig, 然后输入下列命令，进入 menuconfig 进一步配置，
 
 ```shell
     scons --menuconfig
@@ -40,8 +61,7 @@ Standalone Setting > Board Configuration > Chip
 ![](./figures/chip_select.png)
 ![](./figures/phytium_cpu_select.png)
 
-## 2. 如何选择驱动
-
+## 3. 如何选择驱动
 
 ```shell
     scons --menuconfig
@@ -55,9 +75,17 @@ Hardware Drivers Config > On-chip Peripheral Drivers
 
 ![](./figures/select_driver.png)
 
+## 4. 如何切换至RT-Thread Smart 工作模式
+
+```shell
+ scons --menuconfig
+```
+
+![1682474861110](./figures/1682474861110.png)
 
-## 3. 开启SDK中内部调试信息
+开发者通过以上配置开启RT-Thread Smart 功能
 
+## 5. 开启SDK中内部调试信息
 
 ```shell
     scons --menuconfig
@@ -67,9 +95,7 @@ Hardware Drivers Config > On-chip Peripheral Drivers
 
 ![](./figures/select_debug_info.png)
 
-
-
-## 4. 编译程序
+## 6. 编译程序
 
 ```shell
     scons -c
@@ -84,18 +110,38 @@ rtthread_a64.elf
 rtthread_a64.map
 ```
 
-## 5. 打包导出工程源代码
+## 7. 启动镜像程序
+
+- 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动，
 
+- 首先在 Phytium 开发板上输入，上传 bin 文件
+
+```
+loadx 80080000
+```
+
+![](./figures/ymodem_upload.png)
+
+- 加载 bin 文件完成后，输入下列命令启动
+
+```
+go 80080000
+```
+
+> RT-Smart 模式下，64 位不能用 bootelf 启动 elf 文件
+
+## 8. 打包导出工程源代码
 
 - 指定工程名和路径，打包RT-Thread内核和Phytium BSP代码，可以导出一个工程工程
+
 ```
 python ./export_project.py -n=phytium-a64 -o=D:/proj/rt-thread-e2000/phytium-a64
 ```
 
 ![](./figures/export_project.png)
 
+- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR
 
-- 进入打包工程的目录，修改工程根目录 Kconfig 中的路径 BSP_DIR 和 STANDALONE_DIR 
 > env 环境中的 menuconfig 不会调用 SConstruct 修改路径环境变量，因此需要手动修改路径
 
 ```
@@ -112,10 +158,9 @@ config STANDALONE_DIR
 
 - 输入 menuconfig 和 scons 完成编译
 
+## 9. 将工程导入 RT-Studio
 
-## 6. 将工程导入 RT-Studio
-
-- 在 RT-Studio 使用功能`RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
+- 在 RT-Studio 使用功能 `RT-Thread Bsp 到工作空间`，导入 5. 中导出的 BSP 工程
 - 设置 BSP 工程的交叉编译链后进行后续开发
 
-![](./figures/import_project.png)
\ No newline at end of file
+![](./figures/import_project.png)
diff --git a/bsp/phytium/aarch64/SConstruct b/bsp/phytium/aarch64/SConstruct
index ae659dfb217..8132cd8deff 100644
--- a/bsp/phytium/aarch64/SConstruct
+++ b/bsp/phytium/aarch64/SConstruct
@@ -53,6 +53,10 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma
     # include board
     objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript')))
 
+if GetDepend('RT_USING_SMART'):
+    # use smart link.lds
+    env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds')
+
 # make a building
 DoBuilding(TARGET, objs)
 
diff --git a/bsp/phytium/aarch64/applications/SConscript b/bsp/phytium/aarch64/applications/SConscript
index 5206463fe9d..01eb940dfb3 100644
--- a/bsp/phytium/aarch64/applications/SConscript
+++ b/bsp/phytium/aarch64/applications/SConscript
@@ -3,7 +3,7 @@ Import('rtconfig')
 from building import *
 
 cwd     = os.path.join(str(Dir('#')), 'applications')
-src = Glob('*.c')
+src	= Glob('*.c')
 CPPPATH = [cwd, str(Dir('#'))]
 
 group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
diff --git a/bsp/phytium/aarch64/applications/main.c b/bsp/phytium/aarch64/applications/main.c
index 96c5ad2dc00..24379b50c05 100644
--- a/bsp/phytium/aarch64/applications/main.c
+++ b/bsp/phytium/aarch64/applications/main.c
@@ -30,7 +30,7 @@ static char *core_thread_name[8] =
     "core6_test",
     "core7_test"
 };
-static rt_uint8_t core_stack[RT_CPUS_NR][1024];
+static rt_uint8_t core_stack[RT_CPUS_NR][4096];
 
 static void demo_core_thread(void *parameter)
 {
@@ -41,7 +41,7 @@ static void demo_core_thread(void *parameter)
         level = rt_cpus_lock();
         rt_kprintf("Hi, core%d \r\n", rt_hw_cpu_id());
         rt_cpus_unlock(level);
-        rt_thread_mdelay(2000000);
+        rt_thread_mdelay(200000);
     }
 }
 
@@ -57,7 +57,7 @@ void demo_core(void)
                        demo_core_thread,
                        RT_NULL,
                        &core_stack[i],
-                       1024,
+                       4096,
                        20,
                        32);
 
diff --git a/bsp/phytium/aarch64/applications/mnt.c b/bsp/phytium/aarch64/applications/mnt.c
new file mode 100644
index 00000000000..447f518f78d
--- /dev/null
+++ b/bsp/phytium/aarch64/applications/mnt.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-04-27     huanghe      first version
+ *
+ */
+
+#include <rtthread.h>
+#ifdef RT_USING_DFS_RAMFS
+#include <dfs_fs.h>
+
+extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size);
+
+int mnt_init(void)
+{
+    rt_uint8_t *pool = RT_NULL;
+    rt_size_t size = 8*1024*1024;
+
+    pool = rt_malloc(size);
+    if (pool == RT_NULL)
+        return 0;
+
+    if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0)
+        rt_kprintf("RAM file system initializated!\n");
+    else
+        rt_kprintf("RAM file system initializate failed!\n");
+
+    return 0;
+}
+INIT_ENV_EXPORT(mnt_init);
+#endif
+
+#ifdef BSP_USING_SDCARD_FATFS
+#include <dfs_fs.h>
+#include <dfs_file.h>
+#define DBG_TAG "app.filesystem"
+#define DBG_LVL DBG_INFO
+#include <rtdbg.h>
+static int filesystem_mount(void)
+{
+    while(rt_device_find("sd0") == RT_NULL)
+    {
+        rt_thread_mdelay(1);
+    }
+
+    int ret = dfs_mount("sd0", "/", "elm", 0, 0);
+    if (ret != 0)
+    {
+        rt_kprintf("ret: %d\n",ret);
+        LOG_E("sd0 mount to '/' failed!");
+        return ret;
+    }
+
+    return RT_EOK;
+}
+INIT_ENV_EXPORT(filesystem_mount);
+#endif
diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart b/bsp/phytium/aarch64/configs/e2000d_rtsmart
new file mode 100644
index 00000000000..d938d301eab
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart
@@ -0,0 +1,1129 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xffff000000000000
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV3=y
+CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=0
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH64=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
+# CONFIG_USE_GIC is not set
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart.h b/bsp/phytium/aarch64/configs/e2000d_rtsmart.h
new file mode 100644
index 00000000000..d20b661fbb1
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart.h
@@ -0,0 +1,316 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMART
+#define RT_USING_SMP
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 40960
+#define SYSTEM_THREAD_STACK_SIZE 40960
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define KERNEL_VADDR_START 0xffff000000000000
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_TTY
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+#define PKG_USING_KERNEL_SAMPLES
+#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
+#define PKG_USING_KERNEL_SAMPLES_EN
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define BSP_USING_GIC
+#define BSP_USING_GICV3
+#define PHYTIUM_ARCH_AARCH64
+#define ARM_SPI_BIND_CPU_ID 0
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH64
+
+/* Board Configuration */
+
+#define TARGET_E2000D
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_SPI
+#define USE_FSPIM
+#define USE_QSPI
+
+/* Qspi Configuration */
+
+#define USE_FQSPI
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+
+#endif
diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread b/bsp/phytium/aarch64/configs/e2000d_rtthread
new file mode 100644
index 00000000000..b228d85dfcf
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000d_rtthread
@@ -0,0 +1,1118 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=2
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV3=y
+CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=0
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH64=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+# CONFIG_TARGET_E2000Q is not set
+CONFIG_TARGET_E2000D=y
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
+# CONFIG_USE_GIC is not set
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread.h b/bsp/phytium/aarch64/configs/e2000d_rtthread.h
new file mode 100644
index 00000000000..76b14cfc287
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000d_rtthread.h
@@ -0,0 +1,306 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMP
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 40960
+#define SYSTEM_THREAD_STACK_SIZE 40960
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+#define PKG_USING_KERNEL_SAMPLES
+#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
+#define PKG_USING_KERNEL_SAMPLES_EN
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define BSP_USING_GIC
+#define BSP_USING_GICV3
+#define PHYTIUM_ARCH_AARCH64
+#define ARM_SPI_BIND_CPU_ID 0
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH64
+
+/* Board Configuration */
+
+#define TARGET_E2000D
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_SPI
+#define USE_FSPIM
+#define USE_QSPI
+
+/* Qspi Configuration */
+
+#define USE_FQSPI
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+
+#endif
diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart b/bsp/phytium/aarch64/configs/e2000q_rtsmart
new file mode 100644
index 00000000000..de04313cc94
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart
@@ -0,0 +1,1129 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+CONFIG_RT_USING_SMART=y
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_KERNEL_VADDR_START=0xffff000000000000
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+CONFIG_RT_USING_LWP=y
+CONFIG_RT_LWP_MAX_NR=30
+CONFIG_LWP_TASK_STACK_SIZE=16384
+CONFIG_RT_CH_MSG_MAX_NR=1024
+CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024
+CONFIG_LWP_TID_MAX_NR=64
+CONFIG_RT_LWP_SHM_MAX_NR=64
+# CONFIG_LWP_UNIX98_PTY is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_USING_TTY=y
+# CONFIG_RT_TTY_DEBUG is not set
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV3=y
+CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=2
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH64=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
+# CONFIG_USE_GIC is not set
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart.h b/bsp/phytium/aarch64/configs/e2000q_rtsmart.h
new file mode 100644
index 00000000000..7b4988e9a1a
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart.h
@@ -0,0 +1,316 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMART
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 40960
+#define SYSTEM_THREAD_STACK_SIZE 40960
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define KERNEL_VADDR_START 0xffff000000000000
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+#define RT_USING_LWP
+#define RT_LWP_MAX_NR 30
+#define LWP_TASK_STACK_SIZE 16384
+#define RT_CH_MSG_MAX_NR 1024
+#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024
+#define LWP_TID_MAX_NR 64
+#define RT_LWP_SHM_MAX_NR 64
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_TTY
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+#define PKG_USING_KERNEL_SAMPLES
+#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
+#define PKG_USING_KERNEL_SAMPLES_EN
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define BSP_USING_GIC
+#define BSP_USING_GICV3
+#define PHYTIUM_ARCH_AARCH64
+#define ARM_SPI_BIND_CPU_ID 2
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH64
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_SPI
+#define USE_FSPIM
+#define USE_QSPI
+
+/* Qspi Configuration */
+
+#define USE_FQSPI
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+
+#endif
diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread b/bsp/phytium/aarch64/configs/e2000q_rtthread
new file mode 100644
index 00000000000..8edc0d37f33
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000q_rtthread
@@ -0,0 +1,1118 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=16
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMART is not set
+CONFIG_RT_USING_SMP=y
+CONFIG_RT_CPUS_NR=4
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=40960
+CONFIG_SYSTEM_THREAD_STACK_SIZE=40960
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+CONFIG_RT_KPRINTF_USING_LONGLONG=y
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+CONFIG_RT_USING_MEMHEAP=y
+CONFIG_RT_MEMHEAP_FAST_MODE=y
+# CONFIG_RT_MEMHEAP_BEST_MODE is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50001
+# CONFIG_RT_USING_STDC_ATOMIC is not set
+CONFIG_ARCH_CPU_64BIT=y
+CONFIG_RT_USING_CACHE=y
+CONFIG_RT_USING_HW_ATOMIC=y
+CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_MM_MMU=y
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_MMU=y
+CONFIG_ARCH_ARMV8=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# DFS: device virtual file system
+#
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+CONFIG_DFS_FD_MAX=16
+CONFIG_RT_USING_DFS_V1=y
+# CONFIG_RT_USING_DFS_V2 is not set
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_CROMFS is not set
+CONFIG_RT_USING_DFS_RAMFS=y
+# CONFIG_RT_USING_DFS_TMPFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+# CONFIG_RT_USING_PIN is not set
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_NULL=y
+CONFIG_RT_USING_ZERO=y
+CONFIG_RT_USING_RANDOM=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+CONFIG_RT_USING_POSIX_STDIO=y
+# CONFIG_RT_USING_POSIX_POLL is not set
+# CONFIG_RT_USING_POSIX_SELECT is not set
+# CONFIG_RT_USING_POSIX_SOCKET is not set
+CONFIG_RT_USING_POSIX_TERMIOS=y
+# CONFIG_RT_USING_POSIX_AIO is not set
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+CONFIG_RT_USING_RYM=y
+# CONFIG_YMODEM_USING_CRC_TABLE is not set
+CONFIG_YMODEM_USING_FILE_TRANSFER=y
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+CONFIG_RT_USING_ADT=y
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+# CONFIG_PKG_USING_ZEPHYR_POLLING is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_3GPP_AMRNB is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_ILI9341 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+CONFIG_PKG_USING_KERNEL_SAMPLES=y
+CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples"
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set
+# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set
+CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y
+CONFIG_PKG_KERNEL_SAMPLES_VER="latest"
+CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y
+# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set
+# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set
+# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set
+# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set
+# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set
+# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set
+# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set
+# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set
+# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set
+# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set
+# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set
+# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set
+# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set
+# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_MORSE is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+
+#
+# Hardware Drivers
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_RT_USING_UART1=y
+# CONFIG_RT_USING_UART0 is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_QSPI is not set
+
+#
+# Board extended module Drivers
+#
+CONFIG_BSP_USING_GIC=y
+CONFIG_BSP_USING_GICV3=y
+CONFIG_PHYTIUM_ARCH_AARCH64=y
+CONFIG_ARM_SPI_BIND_CPU_ID=2
+
+#
+# Standalone Setting
+#
+CONFIG_TARGET_ARMV8_AARCH64=y
+
+#
+# Board Configuration
+#
+# CONFIG_TARGET_F2000_4 is not set
+# CONFIG_TARGET_D2000 is not set
+CONFIG_TARGET_E2000Q=y
+# CONFIG_TARGET_E2000D is not set
+# CONFIG_TARGET_E2000S is not set
+CONFIG_TARGET_E2000=y
+CONFIG_DEFAULT_DEBUG_PRINT_UART1=y
+# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set
+# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set
+
+#
+# Components Configuration
+#
+CONFIG_USE_SPI=y
+CONFIG_USE_FSPIM=y
+CONFIG_USE_QSPI=y
+
+#
+# Qspi Configuration
+#
+CONFIG_USE_FQSPI=y
+# CONFIG_USE_GIC is not set
+CONFIG_USE_SERIAL=y
+
+#
+# Usart Configuration
+#
+CONFIG_ENABLE_Pl011_UART=y
+# CONFIG_USE_GPIO is not set
+# CONFIG_USE_ETH is not set
+# CONFIG_USE_CAN is not set
+# CONFIG_USE_I2C is not set
+# CONFIG_USE_TIMER is not set
+# CONFIG_USE_MIO is not set
+# CONFIG_USE_SDMMC is not set
+# CONFIG_USE_PCIE is not set
+# CONFIG_USE_WDT is not set
+# CONFIG_USE_DMA is not set
+# CONFIG_USE_NAND is not set
+# CONFIG_USE_RTC is not set
+# CONFIG_USE_SATA is not set
+# CONFIG_USE_USB is not set
+# CONFIG_USE_ADC is not set
+# CONFIG_USE_PWM is not set
+# CONFIG_USE_IPC is not set
+# CONFIG_USE_MEDIA is not set
+# CONFIG_USE_SCMI_MHU is not set
+# CONFIG_LOG_VERBOS is not set
+# CONFIG_LOG_DEBUG is not set
+# CONFIG_LOG_INFO is not set
+# CONFIG_LOG_WARN is not set
+CONFIG_LOG_ERROR=y
+# CONFIG_LOG_NONE is not set
+# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set
+# CONFIG_LOG_EXTRA_INFO is not set
+# CONFIG_LOG_DISPALY_CORE_NUM is not set
+# CONFIG_BOOTUP_DEBUG_PRINTS is not set
diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread.h b/bsp/phytium/aarch64/configs/e2000q_rtthread.h
new file mode 100644
index 00000000000..556c088f1f9
--- /dev/null
+++ b/bsp/phytium/aarch64/configs/e2000q_rtthread.h
@@ -0,0 +1,306 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 16
+#define RT_USING_SMP
+#define RT_CPUS_NR 4
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 40960
+#define SYSTEM_THREAD_STACK_SIZE 40960
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 4096
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_KPRINTF_USING_LONGLONG
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50001
+#define ARCH_CPU_64BIT
+#define RT_USING_CACHE
+#define RT_USING_HW_ATOMIC
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
+#define ARCH_MM_MMU
+#define ARCH_ARM
+#define ARCH_ARM_MMU
+#define ARCH_ARMV8
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 8192
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
+#define RT_USING_ADT
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+#define PKG_USING_KERNEL_SAMPLES
+#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
+#define PKG_USING_KERNEL_SAMPLES_EN
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+/* Hardware Drivers */
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define RT_USING_UART1
+
+/* Board extended module Drivers */
+
+#define BSP_USING_GIC
+#define BSP_USING_GICV3
+#define PHYTIUM_ARCH_AARCH64
+#define ARM_SPI_BIND_CPU_ID 2
+
+/* Standalone Setting */
+
+#define TARGET_ARMV8_AARCH64
+
+/* Board Configuration */
+
+#define TARGET_E2000Q
+#define TARGET_E2000
+#define DEFAULT_DEBUG_PRINT_UART1
+
+/* Components Configuration */
+
+#define USE_SPI
+#define USE_FSPIM
+#define USE_QSPI
+
+/* Qspi Configuration */
+
+#define USE_FQSPI
+#define USE_SERIAL
+
+/* Usart Configuration */
+
+#define ENABLE_Pl011_UART
+#define LOG_ERROR
+
+#endif
diff --git a/bsp/phytium/aarch64/export_project.py b/bsp/phytium/aarch64/export_project.py
index d4c690c7cbc..700c60b173f 100644
--- a/bsp/phytium/aarch64/export_project.py
+++ b/bsp/phytium/aarch64/export_project.py
@@ -1,3 +1,18 @@
+#!/usr/bin/env python
+# -*- coding: utf-8 -*-
+#
+# Copyright (c) 2022, RT-Thread Development Team
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# Email: opensource_embedded@phytium.com.cn
+#
+#
+# Change Logs:
+# Date           Author       Notes
+# 2022-11-15     zhugengyu    The first version
+#
+
 import os
 import shutil
 import argparse
diff --git a/bsp/phytium/aarch64/figures/1682474861110.png b/bsp/phytium/aarch64/figures/1682474861110.png
new file mode 100644
index 00000000000..b42699bde85
Binary files /dev/null and b/bsp/phytium/aarch64/figures/1682474861110.png differ
diff --git a/bsp/phytium/aarch64/figures/aarch64_env.png b/bsp/phytium/aarch64/figures/aarch64_env.png
new file mode 100644
index 00000000000..73010c82d3b
Binary files /dev/null and b/bsp/phytium/aarch64/figures/aarch64_env.png differ
diff --git a/bsp/phytium/aarch64/link.lds b/bsp/phytium/aarch64/link.lds
index 2e4b2ef10b9..2fbf19407bf 100644
--- a/bsp/phytium/aarch64/link.lds
+++ b/bsp/phytium/aarch64/link.lds
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,7 +11,7 @@
 
 SECTIONS
 {
-    . = 0x80100000;
+    . = 0x80080000 ;
     . = ALIGN(4096);
     .text :
     {
@@ -28,6 +28,12 @@ SECTIONS
 
         *(COMMON)
 
+        /* section information for utest */
+        . = ALIGN(8);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
         /* section information for finsh shell */
         . = ALIGN(16);
         __fsymtab_start = .;
@@ -102,14 +108,6 @@ SECTIONS
         PROVIDE(__bss_end = .);
     }
 
-    . = ALIGN(4);
-    .heap :
-    {
-        PROVIDE(__heap_start = .);
-        . = ALIGN(8);
-        PROVIDE(end = .);
-    }
-
     _end = .;
 
     /* Stabs debugging sections.  */
@@ -147,4 +145,4 @@ SECTIONS
     .debug_varnames  0 : { *(.debug_varnames) }
 }
 
-__bss_size = SIZEOF(.bss);
+__bss_size = SIZEOF(.bss);
\ No newline at end of file
diff --git a/bsp/phytium/aarch64/link_smart.lds b/bsp/phytium/aarch64/link_smart.lds
new file mode 100644
index 00000000000..f9aa24b24a6
--- /dev/null
+++ b/bsp/phytium/aarch64/link_smart.lds
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * 2017-5-30     bernard       first version
+ */
+
+/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */
+
+SECTIONS
+{
+    /* . = 0x80080000 ; */
+    . = 0xffff000000080000 ;
+    . = ALIGN(4096);
+    .text :
+    {
+        KEEP(*(.text.entrypoint))       /* The entry point */
+        *(.vectors)
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        *(COMMON)
+
+        /* section information for utest */
+        . = ALIGN(8);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+        /* section information for finsh shell */
+        . = ALIGN(16);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(16);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(16);
+
+        /* section information for initial. */
+        . = ALIGN(16);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(16);
+
+        . = ALIGN(16);
+        _etext = .;
+    }
+    . = ALIGN(4);
+    .eh_frame_hdr :
+    {
+         *(.eh_frame_hdr)
+         *(.eh_frame_entry)
+    }
+    .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+    . = ALIGN(16);
+    .data :
+    {
+     *(.data)
+     *(.data.*)
+
+     *(.data1)
+     *(.data1.*)
+
+     . = ALIGN(16);
+     _gp = ABSOLUTE(.);     /* Base of small data */
+
+     *(.sdata)
+     *(.sdata.*)
+    }
+
+    . = ALIGN(16);
+    .ctors :
+    {
+        PROVIDE(__ctors_start__ = .);
+        /* new GCC version uses .init_array */
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+    }
+    . = ALIGN(4);
+    .dtors :
+    {
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+    }
+
+    . = ALIGN(16);
+    .bss :
+    {
+        PROVIDE(__bss_start = .);
+        *(.bss)
+        *(.bss.*)
+        *(.dynbss)
+        . = ALIGN(32);
+        PROVIDE(__bss_end = .);
+    }
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+
+__bss_size = SIZEOF(.bss);
\ No newline at end of file
diff --git a/bsp/phytium/aarch64/makefile b/bsp/phytium/aarch64/makefile
new file mode 100644
index 00000000000..d97df767343
--- /dev/null
+++ b/bsp/phytium/aarch64/makefile
@@ -0,0 +1,79 @@
+.PHONY: debug boot all clean menuconfig
+
+CC = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc
+CXX = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)g++
+CPP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)gcc -E -P -x c
+STRIP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)strip --strip-unneeded
+OBJCOPY = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objcopy
+OBJDUMP = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
+LD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ld
+AR = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)ar rcs
+NM = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)nm
+OD = $(RTT_EXEC_PATH)/$(RTT_CC_PREFIX)objdump
+RTCONFIG =
+
+include .config
+
+ifdef CONFIG_TARGET_E2000Q
+RTCONFIG := e2000q
+endif
+
+ifdef CONFIG_TARGET_E2000D
+RTCONFIG := e2000d
+endif
+
+ifdef CONFIG_RT_USING_SMART
+RTCONFIG := $(RTCONFIG)_rtsmart
+else
+RTCONFIG := $(RTCONFIG)_rtthread
+endif
+
+boot:
+	make all
+	cp rtthread_a64.elf /mnt/d/tftboot
+	cp rtthread_a64.bin /mnt/d/tftboot
+
+debug:
+	@$(OD) -D rtthread_a64.elf > rtthread_a64.asm
+	@$(OD) -S rtthread_a64.elf > rtthread_a64.dis
+	
+all:
+	@echo "Build started..."
+	scons -j1024
+
+clean:
+	@echo "Cleaning..."
+	scons -c
+
+menuconfig:
+	@echo "Running menuconfig..."
+	scons --menuconfig
+
+saveconfig:
+	@echo "Save configs to" ./configs/$(RTCONFIG)
+	@cp ./.config ./configs/$(RTCONFIG) -f
+	@cp ./rtconfig.h ./configs/$(RTCONFIG).h -f
+
+load_e2000q_rtsmart:
+	@echo "Load configs from ./configs/e2000q_rtsmart"
+	@cp ./configs/e2000q_rtsmart ./.config -f
+	@cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000q_rtthread:
+	@echo "Load configs from ./configs/e2000q_rtthread"
+	@cp ./configs/e2000q_rtthread ./.config -f
+	@cp ./configs/e2000q_rtthread.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000d_rtsmart:
+	@echo "Load configs from ./configs/e2000d_rtsmart"
+	@cp ./configs/e2000d_rtsmart ./.config -f
+	@cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f
+	@scons -c
+
+load_e2000d_rtthread:
+	@echo "Load configs from ./configs/e2000d_rtthread"
+	@cp ./configs/e2000d_rtthread ./.config -f
+	@cp ./configs/e2000d_rtthread.h ./rtconfig.h -f
+	@scons -c
diff --git a/bsp/phytium/aarch64/rtconfig.h b/bsp/phytium/aarch64/rtconfig.h
index 1a5d523b5be..76b14cfc287 100644
--- a/bsp/phytium/aarch64/rtconfig.h
+++ b/bsp/phytium/aarch64/rtconfig.h
@@ -8,18 +8,18 @@
 
 #define RT_NAME_MAX 16
 #define RT_USING_SMP
-#define RT_CPUS_NR 4
-#define RT_ALIGN_SIZE 8
+#define RT_CPUS_NR 2
+#define RT_ALIGN_SIZE 4
 #define RT_THREAD_PRIORITY_32
 #define RT_THREAD_PRIORITY_MAX 32
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 1000
 #define RT_USING_OVERFLOW_CHECK
 #define RT_USING_HOOK
 #define RT_HOOK_USING_FUNC_PTR
 #define RT_USING_IDLE_HOOK
 #define RT_IDLE_HOOK_LIST_SIZE 4
-#define IDLE_THREAD_STACK_SIZE 4096
-#define SYSTEM_THREAD_STACK_SIZE 4096
+#define IDLE_THREAD_STACK_SIZE 40960
+#define SYSTEM_THREAD_STACK_SIZE 40960
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
 #define RT_TIMER_THREAD_STACK_SIZE 4096
@@ -43,6 +43,8 @@
 #define RT_PAGE_MAX_ORDER 11
 #define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
+#define RT_USING_MEMHEAP
+#define RT_MEMHEAP_FAST_MODE
 #define RT_USING_SMALL_MEM_AS_HEAP
 #define RT_USING_HEAP
 
@@ -52,10 +54,11 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x50000
+#define RT_VER_NUM 0x50001
 #define ARCH_CPU_64BIT
 #define RT_USING_CACHE
 #define RT_USING_HW_ATOMIC
+#define ARCH_ARM_BOOTWITH_FLUSH_CACHE
 #define ARCH_MM_MMU
 #define ARCH_ARM
 #define ARCH_ARM_MMU
@@ -65,7 +68,7 @@
 
 #define RT_USING_COMPONENTS_INIT
 #define RT_USING_USER_MAIN
-#define RT_MAIN_THREAD_STACK_SIZE 4096
+#define RT_MAIN_THREAD_STACK_SIZE 8192
 #define RT_MAIN_THREAD_PRIORITY 10
 #define RT_USING_MSH
 #define RT_USING_FINSH
@@ -80,12 +83,18 @@
 #define MSH_USING_BUILT_IN_COMMANDS
 #define FINSH_USING_DESCRIPTION
 #define FINSH_ARG_MAX 10
+
+/* DFS: device virtual file system */
+
 #define RT_USING_DFS
 #define DFS_USING_POSIX
 #define DFS_USING_WORKDIR
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_V1
 #define DFS_FILESYSTEMS_MAX 4
 #define DFS_FILESYSTEM_TYPES_MAX 4
-#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
+#define RT_USING_DFS_RAMFS
 
 /* Device Drivers */
 
@@ -98,7 +107,10 @@
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
-#define RT_USING_PIN
+#define RT_USING_NULL
+#define RT_USING_ZERO
+#define RT_USING_RANDOM
+#define RT_USING_RTC
 
 /* Using USB */
 
@@ -109,6 +121,13 @@
 
 /* POSIX (Portable Operating System Interface) layer */
 
+#define RT_USING_POSIX_FS
+#define RT_USING_POSIX_DEVIO
+#define RT_USING_POSIX_STDIO
+#define RT_USING_POSIX_TERMIOS
+#define RT_USING_POSIX_DELAY
+#define RT_USING_POSIX_CLOCK
+#define RT_USING_POSIX_TIMER
 
 /* Interprocess Communication (IPC) */
 
@@ -121,6 +140,8 @@
 
 /* Utilities */
 
+#define RT_USING_RYM
+#define YMODEM_USING_FILE_TRANSFER
 #define RT_USING_ADT
 
 /* RT-Thread Utestcases */
@@ -201,6 +222,9 @@
 
 /* samples: kernel and components samples */
 
+#define PKG_USING_KERNEL_SAMPLES
+#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION
+#define PKG_USING_KERNEL_SAMPLES_EN
 
 /* entertainment: terminal games and other interesting software packages */
 
@@ -251,6 +275,7 @@
 #define BSP_USING_GIC
 #define BSP_USING_GICV3
 #define PHYTIUM_ARCH_AARCH64
+#define ARM_SPI_BIND_CPU_ID 0
 
 /* Standalone Setting */
 
@@ -258,12 +283,19 @@
 
 /* Board Configuration */
 
-#define TARGET_E2000Q
+#define TARGET_E2000D
 #define TARGET_E2000
 #define DEFAULT_DEBUG_PRINT_UART1
 
 /* Components Configuration */
 
+#define USE_SPI
+#define USE_FSPIM
+#define USE_QSPI
+
+/* Qspi Configuration */
+
+#define USE_FQSPI
 #define USE_SERIAL
 
 /* Usart Configuration */
diff --git a/bsp/phytium/aarch64/rtconfig.py b/bsp/phytium/aarch64/rtconfig.py
index 9bb9671efb9..26c597293de 100644
--- a/bsp/phytium/aarch64/rtconfig.py
+++ b/bsp/phytium/aarch64/rtconfig.py
@@ -3,26 +3,14 @@
 # toolchains options
 ARCH        ='aarch64'
 CPU         ='cortex-a'
-CROSS_TOOL  ='gcc'
-
-if os.getenv('RTT_ROOT'):
-    RTT_ROOT = os.getenv('RTT_ROOT')
-else:
-    RTT_ROOT = r'../../..'
-
+CROSS_TOOL  = 'gcc'
 PLATFORM    = 'gcc'
-EXEC_PATH   = r'/opt/gcc-arm-8.3-2019.03-x86_64-aarch64-elf/bin/' 
-if os.getenv('AARCH64_CROSS_PATH'):
-    EXEC_PATH = os.getenv('AARCH64_CROSS_PATH')
-    print('EXEC_PATH = {}'.format(EXEC_PATH))
-else:
-    print('AARCH64_CROSS_PATH not found')
-
-BUILD = 'debug'
+EXEC_PATH   = os.getenv('RTT_EXEC_PATH') or '/usr/bin'
+BUILD       = 'debug'
 
 if PLATFORM == 'gcc':
     # toolchains
-    PREFIX  = 'aarch64-none-elf-'
+    PREFIX  = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-'
     CC      = PREFIX + 'gcc'
     CXX     = PREFIX + 'g++'
     AS      = PREFIX + 'gcc'
@@ -32,21 +20,26 @@
     SIZE    = PREFIX + 'size'
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
-
-    DEVICE = ' -march=armv8-a -mtune=cortex-a72'
-    CFLAGS = DEVICE + ' -Wall'
-    AFLAGS = ' -c' + ' -x assembler-with-cpp -D__ASSEMBLY__'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds -fdiagnostics-color=always'
+    STRIP   = PREFIX + 'strip'
+    CFPFLAGS = ' '
+    AFPFLAGS = ' '
+    DEVICE   = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing'
+
+    CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always'
+    CFLAGS  = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always'
+    AFLAGS  = ' -c' + AFPFLAGS + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static'
     CPATH   = ''
     LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf-2'
-        AFLAGS += ' -gdwarf-2'
+        CFLAGS   += ' -O0 -gdwarf-2'
+        CXXFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS   += ' -gdwarf-2'
     else:
-        CFLAGS += ' -O2'
-
-    CXXFLAGS = CFLAGS
+        CFLAGS   += ' -Os'
+        CXXFLAGS += ' -Os'
+    CXXFLAGS += ' -Woverloaded-virtual -fno-exceptions -fno-rtti'
 
-DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.dis\n'
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtthread_a64.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_a64.bin\n' + SIZE + ' $TARGET \n'
\ No newline at end of file
diff --git a/bsp/phytium/aarch64/sdkconfig.h b/bsp/phytium/aarch64/sdkconfig.h
deleted file mode 100644
index d799f850539..00000000000
--- a/bsp/phytium/aarch64/sdkconfig.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: sdkconfig.h
- * Date: 2022-10-09 15:04:36
- * LastEditTime: 2022-10-09 15:04:37
- * Description:  This file is for
- *
- * Modify History:
- *  Ver   Who  Date   Changes
- * ----- ------  -------- --------------------------------------
- */
-
-#ifndef SDK_CONFIG_H__
-#define SDK_CONFIG_H__
-
-#include "rtconfig.h"
-
-/* board */
-
-/*  E2000 */
-
-#if defined(TARGET_E2000)
-    #define CONFIG_TARGET_E2000
-#endif
-
-#if defined(TARGET_E2000Q)
-    #define CONFIG_TARGET_E2000Q
-#endif
-
-#if defined(TARGET_ARMV8_AARCH64)
-    #define CONFIG_TARGET_ARMV8_AARCH64
-#endif
-
-/* debug */
-
-#ifdef LOG_VERBOS
-    #define CONFIG_LOG_VERBOS
-#endif
-
-#ifdef LOG_ERROR
-    #define CONFIG_LOG_ERROR
-#endif
-
-#ifdef LOG_WARN
-    #define CONFIG_LOG_WARN
-#endif
-
-#ifdef LOG_INFO
-    #define CONFIG_LOG_INFO
-#endif
-
-#ifdef LOG_DEBUG
-    #define CONFIG_LOG_DEBUG
-#endif
-
-#ifdef BOOTUP_DEBUG_PRINTS
-    #define CONFIG_BOOTUP_DEBUG_PRINTS
-#endif
-
-#endif
diff --git a/bsp/phytium/board/SConscript b/bsp/phytium/board/SConscript
index 0cf8e847217..2742d80f1a4 100644
--- a/bsp/phytium/board/SConscript
+++ b/bsp/phytium/board/SConscript
@@ -2,21 +2,24 @@ from building import *
 
 cwd = GetCurrentDir()
 src = Glob('*.S')
-src += Glob('*.c')
+src	+= Glob('*.c')
 
 if GetDepend(['TARGET_E2000']):
+    src	+= Glob(cwd + '/e2000/memory_map.c')
     if GetDepend(['TARGET_E2000Q']):
-        src += Glob(cwd + '/e2000/q/parameters.c')
+        src	+= Glob(cwd + '/e2000/q/parameters.c')
     elif GetDepend(['TARGET_E2000D']):
-        src += Glob(cwd + '/e2000/d/parameters.c')
+        src	+= Glob(cwd + '/e2000/d/parameters.c')
     elif GetDepend(['TARGET_E2000S']):
-        src += Glob(cwd + '/e2000/s/parameters.c')
+        src	+= Glob(cwd + '/e2000/s/parameters.c')
 
 if GetDepend(['TARGET_F2000_4']):
-    src += Glob(cwd + '/d2000/parameters.c')
+    src	+= Glob(cwd + '/ft2004/memory_map.c')
+    src	+= Glob(cwd + '/d2000/parameters.c')
 
 if GetDepend(['TARGET_D2000']):
-    src += Glob(cwd + '/ft2004/parameters.c')
+    src	+= Glob(cwd + '/d2000/memory_map.c')
+    src	+= Glob(cwd + '/ft2004/parameters.c')
 
 CPPPATH = [cwd]
 
diff --git a/bsp/phytium/board/board.c b/bsp/phytium/board/board.c
index b02fd10b139..fe9aba293bd 100644
--- a/bsp/phytium/board/board.c
+++ b/bsp/phytium/board/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,6 +9,7 @@
  * Date        Author       Notes
  * 2022-10-26  huanghe      first commit
  * 2022-10-26  zhugengyu    support aarch64
+ * 2023-04-13  zhugengyu    support RT-Smart
  *
  */
 
@@ -17,6 +18,13 @@
 #include <rtthread.h>
 
 #include <mmu.h>
+#include <mm_aspace.h> /* TODO: why need application space when RT_SMART off */
+#include <mm_page.h>
+
+#ifdef RT_USING_SMART
+#include <page.h>
+#include <lwp_arch.h>
+#endif
 
 #include <gicv3.h>
 #if defined(TARGET_ARMV8_AARCH64)
@@ -33,7 +41,6 @@
 #include "fprintk.h"
 #include "fearly_uart.h"
 #include "fcpu_info.h"
-#include "fpsci.h"
 
 #define LOG_DEBUG_TAG "BOARD"
 #define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -42,142 +49,36 @@
 #define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__)
 
 /* mmu config */
-struct mem_desc platform_mem_desc[] =
-#if defined(TARGET_E2000)
-{
-    {
-        0x00U,
-        0x00U + 0x40000000U,
-        0x00U,
-        DEVICE_MEM
-    },
-    {
-        0x40000000U,
-        0x40000000U + 0x10000000U,
-        0x40000000U,
-        DEVICE_MEM
-    },
-    {
-        0x50000000U,
-        0x50000000U + 0x30000000U,
-        0x50000000U,
-        DEVICE_MEM
-    },
-    {
-        0x80000000U,
-        0xffffffffU,
-        0x80000000U,
-        NORMAL_MEM
-    },
-#if defined(TARGET_ARMV8_AARCH64)
-    {
-        0x1000000000,
-        0x1000000000 + 0x1000000000,
-        0x1000000000,
-        DEVICE_MEM
-    },
-    {
-        0x2000000000,
-        0x2000000000 + 0x2000000000,
-        0x2000000000,
-        NORMAL_MEM
-    },
-#endif
-};
-#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
-{
-    {
-        0x80000000,
-        0xFFFFFFFF,
-        0x80000000,
-        DDR_MEM
-    },
-    {
-        0, //< QSPI
-        0x1FFFFFFF,
-        0,
-        DEVICE_MEM
-    },
-    {
-        0x20000000, //<! LPC
-        0x27FFFFFF,
-        0x20000000,
-        DEVICE_MEM
-    },
-    {
-        FT_DEV_BASE_ADDR, //<! Device register
-        FT_DEV_END_ADDR,
-        FT_DEV_BASE_ADDR,
-        DEVICE_MEM
-    },
-    {
-        0x30000000, //<! debug
-        0x39FFFFFF,
-        0x30000000,
-        DEVICE_MEM
-    },
-    {
-        0x3A000000, //<! Internal register space in the on-chip network
-        0x3AFFFFFF,
-        0x3A000000,
-        DEVICE_MEM
-    },
-    {
-        FT_PCI_CONFIG_BASEADDR,
-        FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
-        FT_PCI_CONFIG_BASEADDR,
-        DEVICE_MEM
-    },
-    {
-        FT_PCI_IO_CONFIG_BASEADDR,
-        FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
-        FT_PCI_IO_CONFIG_BASEADDR,
-        DEVICE_MEM
-    },
-    {
-        FT_PCI_MEM32_BASEADDR,
-        FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
-        FT_PCI_MEM32_BASEADDR,
-        DEVICE_MEM
-    }
-#if defined(TARGET_ARMV8_AARCH64)
-    {
-        0x1000000000,
-        0x1000000000 + 0x1000000000,
-        0x1000000000,
-        DEVICE_MEM
-    },
-    {
-        0x2000000000,
-        0x2000000000 + 0x2000000000,
-        0x2000000000,
-        NORMAL_MEM
-    },
-#endif
-};
-#endif
-
+extern struct mem_desc platform_mem_desc[];
+extern const rt_uint32_t platform_mem_desc_size;
 
-const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+void idle_wfi(void)
+{
+    asm volatile("wfi");
+}
 
+/**
+ * This function will initialize board
+ */
+extern size_t MMUTable[];
 
+rt_region_t init_page_region = {
+    PAGE_START,
+    PAGE_END
+};
 
 #if defined(TARGET_ARMV8_AARCH64) /* AARCH64 */
 
 /* aarch64 use kernel gtimer */
 
-void idle_wfi(void)
-{
-    asm volatile("wfi");
-}
-
 #else /* AARCH32 */
 
-static rt_uint32_t timerStep;
+/* aarch32 implment gtimer by bsp */
+static rt_uint32_t timer_step;
 
 void rt_hw_timer_isr(int vector, void *parameter)
 {
-    GenericTimerCompare(timerStep);
+    GenericTimerCompare(timer_step);
     rt_tick_increase();
 }
 
@@ -185,10 +86,10 @@ int rt_hw_timer_init(void)
 {
     rt_hw_interrupt_install(GENERIC_TIMER_NS_IRQ_NUM, rt_hw_timer_isr, RT_NULL, "tick");
     rt_hw_interrupt_umask(GENERIC_TIMER_NS_IRQ_NUM);
-    timerStep = GenericTimerFrequecy();
-    timerStep /= RT_TICK_PER_SECOND;
+    timer_step = GenericTimerFrequecy();
+    timer_step /= RT_TICK_PER_SECOND;
 
-    GenericTimerCompare(timerStep);
+    GenericTimerCompare(timer_step);
     GenericTimerInterruptEnable();
     GenericTimerStart();
     return 0;
@@ -196,96 +97,149 @@ int rt_hw_timer_init(void)
 INIT_BOARD_EXPORT(rt_hw_timer_init);
 #endif
 
-
 #ifdef RT_USING_SMP
     void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
 #endif
 
-/**
- * This function will initialize hardware board
- */
-void rt_hw_board_init(void)
-{
 
-    /* mmu init */
 #if defined(TARGET_ARMV8_AARCH64)
-    rt_hw_init_mmu_table(platform_mem_desc, platform_mem_desc_size);
-    rt_hw_mmu_init();
+void rt_hw_board_aarch64_init(void)
+{
+    /* AARCH64 */
+    #if defined(RT_USING_SMART)
+        /* 1. init rt_kernel_space table  (aspace.start = KERNEL_VADDR_START ,  aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3.   */
+        rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET);
+    #else
+        rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
+    #endif
+    rt_page_init(init_page_region);
+
+    rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size);
+
+        /* init memory pool */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 
-    /* interrupt init */
-#if defined(TARGET_ARMV8_AARCH64)
-    f_printk("aarch64 interrupt init \r\n");
+    rt_hw_interrupt_init();
+
+    rt_hw_gtimer_init();
+
+
+
+    /* compoent init */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    /* shell init */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    rt_thread_idle_sethook(idle_wfi);
+
+#ifdef RT_USING_SMP
+    /* install IPI handle */
+    rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16);
+    rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
+    rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
+#endif
+
+}
 #else
-    f_printk("aarch32 interrupt init \r\n");
+
+void rt_hw_board_aarch32_init(void)
+{
+
+#if defined(RT_USING_SMART)
+
+    /* set io map range is 0xf0000000 ~ 0x10000000  , Memory Protection start address is 0xf0000000  - rt_mpr_size */
+    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET);
+
+    rt_page_init(init_page_region);
+
+    /* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */
+    rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000);
+    /*  */
+    arch_kuser_init(&rt_kernel_space, (void*)0xffff0000);
+#else
+    /*
+       map kernel space memory (totally 1GB = 0x10000000), pv_offset = 0 if not RT_SMART:
+         0x80000000 ~ 0x80100000: kernel stack
+         0x80100000 ~ __bss_end: kernel code and data
+    */
+    rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0);
+    rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0x80000000, 0x10000000);
+#endif
+
+        /* init memory pool */
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
 
     extern int rt_hw_cpu_id(void);
 
     u32 cpu_id, cpu_offset = 0;
     GetCpuId(&cpu_id);
-    f_printk("cpu_id is %d \r\n", cpu_id);
 
 #if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
     cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
 #endif
-    f_printk("cpu_offset  is %d \r\n", cpu_offset);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
+    rt_uint32_t redist_addr = 0;
+
+#if defined(RT_USING_SMART)
+    redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128*1024);
+#else
+    redist_addr = GICV3_RD_BASE_ADDR;
+#endif
+
+    arm_gic_redist_address_set(0, redist_addr + (cpu_id + cpu_offset) * GICV3_RD_OFFSET, rt_hw_cpu_id());
 
 #if defined(TARGET_E2000Q)
 
 #if RT_CPUS_NR == 2
-    f_printk("arm_gic_redist_address_set is 2 \r\n");
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
 #elif RT_CPUS_NR == 3
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
+    arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr, 2);
 #elif RT_CPUS_NR == 4
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + 3 * GICV3_RD_OFFSET, 1);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS, 2);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + GICV3_RD_OFFSET, 3);
+    arm_gic_redist_address_set(0, redist_addr + 3 * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr, 2);
+    arm_gic_redist_address_set(0, redist_addr + GICV3_RD_OFFSET, 3);
 #endif
 
 #else
 
 #if RT_CPUS_NR == 2
-    f_printk("arm_gic_redist_address_set is 2 \r\n");
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
 #elif RT_CPUS_NR == 3
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+    arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
 #elif RT_CPUS_NR == 4
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
-    arm_gic_redist_address_set(0, GICV3_RD_BASEADDRESS + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
+    arm_gic_redist_address_set(0, redist_addr + (1 + cpu_offset) * GICV3_RD_OFFSET, 1);
+    arm_gic_redist_address_set(0, redist_addr + (2 + cpu_offset) * GICV3_RD_OFFSET, 2);
+    arm_gic_redist_address_set(0, redist_addr + (3 + cpu_offset) * GICV3_RD_OFFSET, 3);
 #endif
 
 #endif
 
-#endif
     rt_hw_interrupt_init();
 
 
-    /* gtimer init  */
-#if defined(TARGET_ARMV8_AARCH64)
-    rt_hw_gtimer_init();
-#endif
-
     /* compoent init */
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
 
     /* shell init */
-
 #if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
     /* set console device */
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-    /* init memory pool */
-#ifdef RT_USING_HEAP
-    rt_system_heap_init(HEAP_BEGIN, HEAP_END);
-#endif
+    rt_thread_idle_sethook(idle_wfi);
 
 #ifdef RT_USING_SMP
     /* install IPI handle */
@@ -293,13 +247,20 @@ void rt_hw_board_init(void)
     rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler);
     rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
 #endif
-}
 
+}
+#endif
 
-static void ft_reset(void)
+/**
+ * This function will initialize hardware board
+ */
+void rt_hw_board_init(void)
 {
-    PsciCpuReset();
+
+#if defined(TARGET_ARMV8_AARCH64)
+    rt_hw_board_aarch64_init();
+#else
+    rt_hw_board_aarch32_init();
+#endif
 }
-MSH_CMD_EXPORT_ALIAS(ft_reset, ft_reset, ft_reset);
 
-/*@}*/
diff --git a/bsp/phytium/board/board.h b/bsp/phytium/board/board.h
index b65fe18bf83..35ada57347c 100644
--- a/bsp/phytium/board/board.h
+++ b/bsp/phytium/board/board.h
@@ -8,6 +8,7 @@
  * Change Logs:
  * Date        Author       Notes
  * 2022-10-26  huanghe      first commit
+ * 2022-04-13  zhugengyu    support RT-Smart
  *
  */
 
@@ -17,6 +18,11 @@
 #include "fparameters.h"
 #include "phytium_cpu.h"
 
+#include "mmu.h"
+#ifdef RT_USING_SMART
+#include "ioremap.h"
+#endif
+
 #if defined(__CC_ARM)
     extern int Image$$RW_IRAM1$$ZI$$Limit;
     #define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
@@ -25,7 +31,18 @@
     #define HEAP_BEGIN ((void *)&__bss_end)
 #endif
 
-#define HEAP_END (void *)(0x80000000 + 1024 * 1024 * 1024)
+#ifdef RT_USING_SMART
+#define HEAP_END        (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 64 * 1024 * 1024)
+#define PAGE_START      HEAP_END + 1 * 1024 * 1024
+#define PAGE_END        (rt_size_t)((rt_size_t)KERNEL_VADDR_START + 128 * 1024 * 1024)
+#else
+#define HEAP_END        (rt_size_t)(HEAP_BEGIN + 64*1024*1024)
+#define KERNEL_VADDR_START (rt_size_t)0x80000000
+#define DDR_END_ADDRESS (KERNEL_VADDR_START + 1024*1024*1024 - 1 )
+#define PAGE_POOL_SIZE  (8ul << 20)
+#define PAGE_START      (rt_size_t)(HEAP_END)
+#define PAGE_END        (PAGE_START +PAGE_POOL_SIZE)
+#endif
 
 void rt_hw_board_init(void);
 
diff --git a/bsp/phytium/board/d2000/memory_map.c b/bsp/phytium/board/d2000/memory_map.c
new file mode 100644
index 00000000000..34aa214030b
--- /dev/null
+++ b/bsp/phytium/board/d2000/memory_map.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-04-27     huanghe      first version
+ *
+ */
+
+#include "rtconfig.h"
+#include <board.h>
+#include <mmu.h>
+
+
+/* mmu config */
+#ifdef RT_USING_SMART
+#if defined(TARGET_ARMV8_AARCH64)
+struct mem_desc platform_mem_desc[] =
+{
+    {   KERNEL_VADDR_START,
+        KERNEL_VADDR_START + 0x0fffffff,
+        (rt_size_t)ARCH_MAP_FAILED,
+        NORMAL_MEM
+    }
+};
+#else
+struct mem_desc platform_mem_desc[] =
+{
+    {   KERNEL_VADDR_START,
+        KERNEL_VADDR_START + 0x10000000,
+        (rt_size_t)ARCH_MAP_FAILED,
+        NORMAL_MEM
+    }
+};
+#endif
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+#else
+
+/* mmu config */
+struct mem_desc platform_mem_desc[] =
+{
+    {
+        0x80000000,
+        0xFFFFFFFF,
+        0x80000000,
+        DDR_MEM
+    },
+    {
+        0, //< QSPI
+        0x1FFFFFFF,
+        0,
+        DEVICE_MEM
+    },
+    {
+        0x20000000, //<! LPC
+        0x27FFFFFF,
+        0x20000000,
+        DEVICE_MEM
+    },
+    {
+        FT_DEV_BASE_ADDR, //<! Device register
+        FT_DEV_END_ADDR,
+        FT_DEV_BASE_ADDR,
+        DEVICE_MEM
+    },
+    {
+        0x30000000, //<! debug
+        0x39FFFFFF,
+        0x30000000,
+        DEVICE_MEM
+    },
+    {
+        0x3A000000, //<! Internal register space in the on-chip network
+        0x3AFFFFFF,
+        0x3A000000,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_CONFIG_BASEADDR,
+        FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
+        FT_PCI_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_IO_CONFIG_BASEADDR,
+        FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
+        FT_PCI_IO_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_MEM32_BASEADDR,
+        FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
+        FT_PCI_MEM32_BASEADDR,
+        DEVICE_MEM
+    }
+#if defined(TARGET_ARMV8_AARCH64)
+    {
+        0x1000000000,
+        0x1000000000 + 0x1000000000,
+        0x1000000000,
+        DEVICE_MEM
+    },
+    {
+        0x2000000000,
+        0x2000000000 + 0x2000000000,
+        0x2000000000,
+        NORMAL_MEM
+    },
+#endif
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
+
+#endif
diff --git a/bsp/phytium/board/d2000/parameters.c b/bsp/phytium/board/d2000/parameters.c
index 4beb68127d3..297e5565869 100644
--- a/bsp/phytium/board/d2000/parameters.c
+++ b/bsp/phytium/board/d2000/parameters.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -112,4 +112,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
     }
 
     return 1;
-}
\ No newline at end of file
+}
diff --git a/bsp/phytium/board/e2000/memory_map.c b/bsp/phytium/board/e2000/memory_map.c
new file mode 100644
index 00000000000..4222a4855aa
--- /dev/null
+++ b/bsp/phytium/board/e2000/memory_map.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-04-27     huanghe      first version
+ *
+ */
+
+#include "rtconfig.h"
+#include <board.h>
+#include <mmu.h>
+
+/* mmu config */
+#ifdef RT_USING_SMART
+#if defined(TARGET_ARMV8_AARCH64)
+struct mem_desc platform_mem_desc[] =
+{
+    {   KERNEL_VADDR_START,
+        KERNEL_VADDR_START + 0x0fffffff,
+        (rt_size_t)ARCH_MAP_FAILED,
+        NORMAL_MEM
+    }
+};
+#else
+struct mem_desc platform_mem_desc[] =
+{
+    {   KERNEL_VADDR_START,
+        KERNEL_VADDR_START + 0x10000000,
+        (rt_size_t)ARCH_MAP_FAILED,
+        NORMAL_MEM
+    }
+};
+#endif
+#else
+
+#if defined(TARGET_ARMV8_AARCH64)
+
+struct mem_desc platform_mem_desc[] = {
+    {KERNEL_VADDR_START, DDR_END_ADDRESS , KERNEL_VADDR_START, NORMAL_MEM},
+    {
+        0x28000000U,
+        0x32B36FFFU,
+        0x28000000U,
+        DEVICE_MEM
+    },
+};
+#else
+struct mem_desc platform_mem_desc[] =
+{
+    {
+        0x00U,
+        0x00U + 0x40000000U,
+        0x00U,
+        DEVICE_MEM
+    },
+    {
+        0x40000000U,
+        0x40000000U + 0x10000000U,
+        0x40000000U,
+        DEVICE_MEM
+    },
+    {
+        0x50000000U,
+        0x50000000U + 0x30000000U,
+        0x50000000U,
+        DEVICE_MEM
+    },
+    {
+        0x80000000U,
+        0xffffffffU,
+        0x80000000U,
+        NORMAL_MEM
+    },
+#if defined(TARGET_ARMV8_AARCH64)
+    {
+        0x1000000000,
+        0x1000000000 + 0x1000000000,
+        0x1000000000,
+        DEVICE_MEM
+    },
+    {
+        0x2000000000,
+        0x2000000000 + 0x2000000000,
+        0x2000000000,
+        NORMAL_MEM
+    },
+#endif
+};
+
+#endif
+
+#endif
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
diff --git a/bsp/phytium/board/e2000/q/parameters.c b/bsp/phytium/board/e2000/q/parameters.c
index d3d3432c156..ed3fb0453ea 100644
--- a/bsp/phytium/board/e2000/q/parameters.c
+++ b/bsp/phytium/board/e2000/q/parameters.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -72,4 +72,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
     }
 
     return 1;
-}
\ No newline at end of file
+}
diff --git a/bsp/phytium/board/ft2004/memory_map.c b/bsp/phytium/board/ft2004/memory_map.c
new file mode 100644
index 00000000000..6dd42b01156
--- /dev/null
+++ b/bsp/phytium/board/ft2004/memory_map.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-04-27     huanghe      first version
+ *
+ */
+
+#include "rtconfig.h"
+#include <board.h>
+#include <mmu.h>
+
+/* mmu config */
+struct mem_desc platform_mem_desc[] =
+{
+    {
+        0x80000000,
+        0xFFFFFFFF,
+        0x80000000,
+        DDR_MEM
+    },
+    {
+        0, //< QSPI
+        0x1FFFFFFF,
+        0,
+        DEVICE_MEM
+    },
+    {
+        0x20000000, //<! LPC
+        0x27FFFFFF,
+        0x20000000,
+        DEVICE_MEM
+    },
+    {
+        FT_DEV_BASE_ADDR, //<! Device register
+        FT_DEV_END_ADDR,
+        FT_DEV_BASE_ADDR,
+        DEVICE_MEM
+    },
+    {
+        0x30000000, //<! debug
+        0x39FFFFFF,
+        0x30000000,
+        DEVICE_MEM
+    },
+    {
+        0x3A000000, //<! Internal register space in the on-chip network
+        0x3AFFFFFF,
+        0x3A000000,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_CONFIG_BASEADDR,
+        FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH,
+        FT_PCI_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_IO_CONFIG_BASEADDR,
+        FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH,
+        FT_PCI_IO_CONFIG_BASEADDR,
+        DEVICE_MEM
+    },
+    {
+        FT_PCI_MEM32_BASEADDR,
+        FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH,
+        FT_PCI_MEM32_BASEADDR,
+        DEVICE_MEM
+    }
+#if defined(TARGET_ARMV8_AARCH64)
+    {
+        0x1000000000,
+        0x1000000000 + 0x1000000000,
+        0x1000000000,
+        DEVICE_MEM
+    },
+    {
+        0x2000000000,
+        0x2000000000 + 0x2000000000,
+        0x2000000000,
+        NORMAL_MEM
+    },
+#endif
+};
+
+const rt_uint32_t platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]);
diff --git a/bsp/phytium/board/ft2004/parameters.c b/bsp/phytium/board/ft2004/parameters.c
index 8bf9da3f518..0d17ca63a20 100644
--- a/bsp/phytium/board/ft2004/parameters.c
+++ b/bsp/phytium/board/ft2004/parameters.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -68,4 +68,4 @@ u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
     }
 
     return 1;
-}
\ No newline at end of file
+}
diff --git a/bsp/phytium/board/phytium_cpu.c b/bsp/phytium/board/phytium_cpu.c
index d4dac0a31ee..8d52681c928 100644
--- a/bsp/phytium/board/phytium_cpu.c
+++ b/bsp/phytium/board/phytium_cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,9 +20,20 @@
 
 #include "phytium_cpu.h"
 
+
+#if defined(TARGET_ARMV8_AARCH64)
+
+/**
+@name: phytium_cpu_id_mapping
+@msg: Map Phytium CPU ID
+@brief: Map the input CPU ID to a new CPU ID based on the type and quantity of CPUs on the target board.
+@param {int} cpu_id Input CPU ID
+@return {int} Mapped CPU ID
+*/
 int phytium_cpu_id_mapping(int cpu_id)
 {
 #if defined(TARGET_E2000Q)
+#if RT_CPUS_NR <= 2
     switch (cpu_id)
     {
     case 0:
@@ -41,10 +52,11 @@ int phytium_cpu_id_mapping(int cpu_id)
 #else
     return (int)cpu_id;
 #endif
+#else
+    return (int)cpu_id;
+#endif
 }
 
-#if defined(TARGET_ARMV8_AARCH64)
-
 int phytium_cpu_id(void)
 {
     FError ret;
@@ -56,9 +68,46 @@ int phytium_cpu_id(void)
         RT_ASSERT(0);
     }
     return phytium_cpu_id_mapping(cpu_id);
-};
+}
+
+int rt_hw_cpu_id(void)
+{
+    FError ret;
+    u32 cpu_id;
+    ret = GetCpuId(&cpu_id);
+
+    if (ret != ERR_SUCCESS)
+    {
+        RT_ASSERT(0);
+    }
+    return phytium_cpu_id_mapping(cpu_id);
+}
+
+
+#else
 
+int phytium_cpu_id_mapping(int cpu_id)
+{
+#if defined(TARGET_E2000Q)
+    switch (cpu_id)
+    {
+    case 0:
+        return 2;
+    case 1:
+        return 3;
+    case 2:
+        return 0;
+    case 3:
+        return 1;
+    default:
+        RT_ASSERT(0);
+        return 0;
+        break;
+    }
 #else
+    return (int)cpu_id;
+#endif
+}
 
 int rt_hw_cpu_id(void)
 {
@@ -72,7 +121,7 @@ int rt_hw_cpu_id(void)
     }
 
     return phytium_cpu_id_mapping(cpu_id);
-};
+}
 
 
 
@@ -110,4 +159,4 @@ MSH_CMD_EXPORT(send_core_isg, send_core_isg);
 #endif
 
 
-#endif
\ No newline at end of file
+#endif
diff --git a/bsp/phytium/board/phytium_cpu.h b/bsp/phytium/board/phytium_cpu.h
index d0d16dff0e1..0e52b2826e8 100644
--- a/bsp/phytium/board/phytium_cpu.h
+++ b/bsp/phytium/board/phytium_cpu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,7 +19,16 @@
 #include "fparameters.h"
 
 #define ARM_GIC_MAX_NR 1
+
+#if defined(TARGET_FT2000_4) || defined(TARGET_D2000)
 #define MAX_HANDLERS 160
+#endif
+
+#if defined(TARGET_E2000)
+#define MAX_HANDLERS 270
+#define ARM_GIC_CPU_NUM 4
+#endif
+
 #define GIC_IRQ_START 0
 #define GIC_ACK_INTID_MASK 0x000003ff
 
@@ -28,7 +37,7 @@ rt_uint64_t get_main_cpu_affval(void);
 
 rt_inline rt_uint32_t platform_get_gic_dist_base(void)
 {
-    return GICV3_DISTRIBUTOR_BASEADDRESS;
+    return GICV3_DISTRIBUTOR_BASE_ADDR;
 }
 
 #if defined(TARGET_ARMV8_AARCH64)
@@ -38,6 +47,7 @@ rt_inline rt_uint32_t platform_get_gic_redist_base(void)
 {
     extern int phytium_cpu_id(void);
 
+#if RT_CPUS_NR <= 2
     s32 cpu_offset = 0;
 #if defined(FT_GIC_REDISTRUBUTIOR_OFFSET)
     cpu_offset = FT_GIC_REDISTRUBUTIOR_OFFSET ;
@@ -59,10 +69,15 @@ rt_inline rt_uint32_t platform_get_gic_redist_base(void)
     default:
         break;
     }
+
+    rt_kprintf("cpu_id is %d \r\n",cpu_id);
 #endif
+    rt_kprintf("offset  is %d\n", cpu_offset);
 
-    rt_kprintf("offset  is %x\n",  cpu_offset);
-    return (GICV3_RD_BASEADDRESS + (cpu_offset) * GICV3_RD_OFFSET);
+    return (GICV3_RD_BASE_ADDR + (cpu_offset) * GICV3_RD_OFFSET);
+#else
+    return (GICV3_RD_BASE_ADDR);
+#endif
 }
 
 rt_inline rt_uint32_t platform_get_gic_cpu_base(void)
@@ -77,4 +92,4 @@ int phytium_cpu_id_mapping(int cpu_id);
 
 
 
-#endif // !
\ No newline at end of file
+#endif // !
diff --git a/bsp/phytium/board/phytium_cpu_id.S b/bsp/phytium/board/phytium_cpu_id.S
new file mode 100644
index 00000000000..b25da4421f4
--- /dev/null
+++ b/bsp/phytium/board/phytium_cpu_id.S
@@ -0,0 +1,218 @@
+#include "fparameters.h"
+#include "sdkconfig.h"
+
+#ifndef __aarch64__
+.globl cpu_id_mapping
+cpu_id_mapping:
+#if defined(CONFIG_TARGET_E2000Q)
+cmp r0, #0 // compare cpu_id with 0
+beq map_cpu_id_0
+cmp r0, #1 // compare cpu_id with 1
+beq map_cpu_id_1
+cmp r0, #2 // compare cpu_id with 2
+beq map_cpu_id_2
+cmp r0, #3 // compare cpu_id with 3
+beq map_cpu_id_3
+mov pc, lr // no mapping needed
+#endif
+mov pc, lr // no mapping needed
+
+// Mapping for E2000Q
+map_cpu_id_0:
+mov r0, #2
+mov pc, lr
+
+map_cpu_id_1:
+mov r0, #3
+mov pc, lr
+
+map_cpu_id_2:
+mov r0, #0
+mov pc, lr
+
+map_cpu_id_3:
+mov r0, #1
+mov pc, lr
+
+.globl rt_asm_cpu_id 
+rt_asm_cpu_id:
+// read MPIDR
+    mov r9, lr
+    mrc p15, 0, r0, c0, c0, 5 
+    ubfx r0, r0, #0, #12
+    ldr r1,= CORE0_AFF
+    cmp r0, r1
+    beq core0
+
+#if defined(CORE1_AFF)
+    ldr r1,= CORE1_AFF
+    cmp r0, r1
+    beq core1
+#endif
+
+#if defined(CORE2_AFF)
+    ldr r1,= CORE2_AFF
+    cmp r0, r1
+    beq core2
+#endif
+
+#if defined(CORE3_AFF)
+    ldr r1,= CORE3_AFF
+    cmp r0, r1
+    beq core3
+#endif
+
+    b default
+
+core0:
+    mov r0, #0
+    b return 
+
+core1: 
+    mov r0, #1
+    b return 
+
+core2: 
+    mov r0, #2
+    b return 
+
+core3: 
+    mov r0, #3
+    b return 
+
+core4: 
+    mov r0, #4
+    b return 
+
+core5: 
+    mov r0, #5
+    b return 
+
+core6: 
+    mov r0, #6
+    b return 
+
+core8: 
+    mov r0, #8
+    b return 
+
+default: 
+    and r0, r0, #15
+
+return: 
+
+    bl cpu_id_mapping
+
+    mov pc, r9
+
+#else
+
+.globl cpu_id_mapping
+cpu_id_mapping:
+#if defined(CONFIG_TARGET_E2000Q)
+cmp x0, #0 // compare cpu_id with 0
+beq map_cpu_id_0
+cmp x0, #1 // compare cpu_id with 1
+beq map_cpu_id_1
+cmp x0, #2 // compare cpu_id with 2
+beq map_cpu_id_2
+cmp x0, #3 // compare cpu_id with 3
+beq map_cpu_id_3
+RET // no mapping needed
+#endif
+RET // no mapping needed
+
+// Mapping for E2000Q
+map_cpu_id_0:
+mov x0, #2
+RET
+
+map_cpu_id_1:
+mov x0, #3
+RET
+
+map_cpu_id_2:
+mov x0, #0
+RET
+
+map_cpu_id_3:
+mov x0, #1
+RET
+
+
+.globl rt_hw_cpu_id_set 
+rt_hw_cpu_id_set:
+    mov x9, lr 
+    mrs x0,MPIDR_EL1
+    and x1, x0, #15
+    msr tpidr_el1, x1
+
+    ubfx x0, x0, #0, #12
+    ldr x1,= CORE0_AFF
+    cmp x0, x1
+    beq core0
+
+#if defined(CORE1_AFF)
+    ldr x1,= CORE1_AFF
+    cmp x0, x1
+    beq core1
+#endif
+
+#if defined(CORE2_AFF)
+    ldr x1,= CORE2_AFF
+    cmp x0, x1
+    beq core2
+#endif
+
+#if defined(CORE3_AFF)
+    ldr x1,= CORE3_AFF
+    cmp x0, x1
+    beq core3
+#endif
+
+    b default
+
+core0:
+    mov x0, #0
+    b return 
+
+core1: 
+    mov x0, #1
+    b return 
+
+core2: 
+    mov x0, #2
+    b return 
+
+core3: 
+    mov x0, #3
+    b return 
+
+core4: 
+    mov x0, #4
+    b return 
+
+core5: 
+    mov x0, #5
+    b return 
+
+core6: 
+    mov x0, #6
+    b return 
+
+core8: 
+    mov x0, #8
+    b return 
+
+default: 
+    and x0, x0, #15
+
+return: 
+
+    //bl cpu_id_mapping
+    mov lr, x9
+    RET
+
+
+#endif
+
diff --git a/bsp/phytium/board/secondary_cpu.c b/bsp/phytium/board/secondary_cpu.c
index 1e46537e599..feffab4b50c 100644
--- a/bsp/phytium/board/secondary_cpu.c
+++ b/bsp/phytium/board/secondary_cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,6 +22,7 @@
     #include "cpuport.h"
     #include "gtimer.h"
     #include "mmu.h"
+    #include "cp15.h"
 #endif
 
 #ifdef RT_USING_SMP
@@ -29,6 +30,9 @@
 
 #if defined(TARGET_ARMV8_AARCH64)
     #include "psci.h"
+    extern void _secondary_cpu_entry(void);
+#else
+    extern void rt_secondary_cpu_entry(void);
 #endif
 
 #include "fpsci.h"
@@ -39,10 +43,10 @@ rt_uint64_t rt_cpu_mpidr_early[] =
     [0] = 0x80000200,
     [1] = 0x80000201,
 #elif defined(TARGET_E2000Q)
-    [0] = 0x80000200,
-    [1] = 0x80000201,
-    [2] = 0x80000000,
-    [3] = 0x80000100,
+    [0] = 0x80000000,
+    [1] = 0x80000100,
+    [2] = 0x80000200,
+    [3] = 0x80000201,
 #elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
     [0] = 0x80000000,
     [1] = 0x80000001,
@@ -59,53 +63,66 @@ rt_uint64_t rt_cpu_mpidr_early[] =
 };
 
 extern int rt_hw_timer_init(void);
-extern void secondary_cpu_start(void);
-
+#include "fcache.h"
 void rt_hw_secondary_cpu_up(void)
 {
     rt_uint32_t i;
     rt_uint32_t cpu_mask = 0;
-
+    int cpu_id;
+    cpu_id = rt_hw_cpu_id();
     rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
-    for (i = 1; i < RT_CPUS_NR; i++)
+    for (i = 0; i < RT_CPUS_NR;i++)
     {
-
+        if(i == cpu_id)
+        {
+            continue;
+        }
         cpu_mask = 1 << phytium_cpu_id_mapping(i);
 
-        /* code */
-        PsciCpuOn(cpu_mask, (uintptr)secondary_cpu_start);
-
 
 #if defined(TARGET_ARMV8_AARCH64)
+        /* code */
+        char *entry = (char *)_secondary_cpu_entry;
+        entry += PV_OFFSET;
+        PsciCpuOn(cpu_mask, (uintptr)entry);
         __DSB();
 #else
+            /* code */
+        PsciCpuOn(cpu_mask, (uintptr)rt_secondary_cpu_entry);
         __asm__ volatile("dsb" ::: "memory");
 #endif
+
     }
 }
 
-void secondary_cpu_c_start(void)
+void rt_hw_secondary_cpu_bsp_start(void)
 {
+    /*  spin lock init */
+    rt_hw_spin_lock(&_cpus_lock);
+
     /* mmu init */
 #if defined(TARGET_ARMV8_AARCH64)
-    rt_hw_mmu_init();
+    extern unsigned long MMUTable[];
+    rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
 #endif
-    /*  spin lock init */
-    rt_hw_spin_lock(&_cpus_lock);
+
+    /* vector init */
+    rt_hw_vector_init();
     /* interrupt init */
 #if defined(TARGET_ARMV8_AARCH64)
-    arm_gic_cpu_init(0, platform_get_gic_cpu_base());
-    arm_gic_redist_init(0, platform_get_gic_redist_base());
+    arm_gic_cpu_init(0, 0);
+
+    arm_gic_redist_init(0, 0);
+    rt_kprintf("arm_gic_redist_init is over rt_hw_cpu_id() is %d \r\n", rt_hw_cpu_id());
 #else
     arm_gic_cpu_init(0);
     arm_gic_redist_init(0);
 #endif
 
-    /* vector init */
-    rt_hw_vector_init();
+
     /* gtimer init */
 #if defined(TARGET_ARMV8_AARCH64)
-    rt_hw_gtimer_local_enable();
+    rt_hw_gtimer_init();
 #else
     rt_hw_timer_init();
 #endif
diff --git a/bsp/phytium/libraries/.ignore_format.yml b/bsp/phytium/libraries/.ignore_format.yml
new file mode 100644
index 00000000000..f0bb1733947
--- /dev/null
+++ b/bsp/phytium/libraries/.ignore_format.yml
@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- standalone
diff --git a/bsp/phytium/libraries/SConscript b/bsp/phytium/libraries/SConscript
index e387424fab0..e7184b93779 100644
--- a/bsp/phytium/libraries/SConscript
+++ b/bsp/phytium/libraries/SConscript
@@ -8,66 +8,83 @@ STANDALONE_DIR = cwd + '/standalone'
 
 # common source
 src  = Glob(STANDALONE_DIR+'/common/*.c')
-
 path = [STANDALONE_DIR + '/common']
 
-# arch
-path += [STANDALONE_DIR + '/arch/common']
+# port
+src += Glob(STANDALONE_DIR+'/port/*.c')
+path += [STANDALONE_DIR + '/port'] + [STANDALONE_DIR + '/port/arch']
 
 if GetDepend(['TARGET_ARMV8_AARCH32']):
-    src += Glob(STANDALONE_DIR+'/arch/armv8/aarch32/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch32/gcc/*.S')
-    path += [STANDALONE_DIR + '/arch/armv8/aarch32']
+    src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch32/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch32/*.S')
+    path += [STANDALONE_DIR + '/port/arch/armv8/aarch32']
 elif GetDepend(['TARGET_ARMV8_AARCH64']):
-    src += Glob(STANDALONE_DIR+'/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/arch/armv8/aarch64/gcc/*.S')
-    path += [STANDALONE_DIR + '/arch/armv8/aarch64']
+    src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.S')
+    path += [STANDALONE_DIR + '/port/arch/armv8/aarch64']    
 
 # board
 src += Glob(STANDALONE_DIR+'/board/common/*.c') + Glob(STANDALONE_DIR+'/board/common/*.S')
-path += [STANDALONE_DIR + '/board/common']
+path += [STANDALONE_DIR + '/board/common'] 
 
 if GetDepend(['TARGET_F2000_4']):
     src += Glob(STANDALONE_DIR+'/board/ft2004/*.c')
-    path += [STANDALONE_DIR + '/board/ft2004']
+    path += [STANDALONE_DIR + '/board/ft2004'] 
 
 if GetDepend(['TARGET_E2000']):
     src += Glob(STANDALONE_DIR+'/board/e2000/*.c')
-    path += [STANDALONE_DIR + '/board/e2000']
+    path += [STANDALONE_DIR + '/board/e2000'] 
 
     if GetDepend(['TARGET_E2000Q']):
         src += Glob(STANDALONE_DIR+'/board/e2000/q/*.c')
-        path += [STANDALONE_DIR + '/board/e2000/q']
+        path += [STANDALONE_DIR + '/board/e2000/q'] 
 
     if GetDepend(['TARGET_E2000D']):
         src += Glob(STANDALONE_DIR+'/board/e2000/d/*.c')
-        path += [STANDALONE_DIR + '/board/e2000/d']
-
+        path += [STANDALONE_DIR + '/board/e2000/d'] 
+    
     if GetDepend(['ARGET_E2000S']):
         src += Glob(STANDALONE_DIR+'/board/e2000/s/*.c')
-        path += [STANDALONE_DIR + '/board/e2000/s']
-
+        path += [STANDALONE_DIR + '/board/e2000/s'] 
+    
 if GetDepend(['TARGET_D2000']):
-    src += Glob(STANDALONE_DIR+'/board/d2000/*.c')
-    path += [STANDALONE_DIR + '/board/d2000']
+    path += [STANDALONE_DIR + '/board/d2000'] 
 
 # driver
 
+## spim
+if GetDepend(['BSP_USING_SPI']):
+    src += Glob(STANDALONE_DIR+'/drivers/spi/fspim/*.c')
+    path += [STANDALONE_DIR + '/drivers/spi/fspim'] 
+
 ## serial
-if GetDepend(['ENABLE_Pl011_UART']):
+if GetDepend(['BSP_USING_UART']):
     src += Glob(STANDALONE_DIR+'/drivers/serial/fpl011/*.c')
-    path += [STANDALONE_DIR + '/drivers/serial/fpl011']
+    path += [STANDALONE_DIR + '/drivers/serial/fpl011'] 
 
-## gicv3
-if GetDepend(['ENABLE_GICV3']):
-    src += Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.c') + Glob(STANDALONE_DIR+'/drivers/gic/fgic/*.S')
-    path += [STANDALONE_DIR + '/drivers/gic/fgic']
+## can
+if GetDepend(['BSP_USING_CAN']):
+    src += Glob(STANDALONE_DIR+'/drivers/can/fcan/*.c') + Glob(STANDALONE_DIR+'/drivers/can/fcan/*.S')
+    path += [STANDALONE_DIR + '/drivers/can/fcan/'] 
 
+## qspi
+if GetDepend(['BSP_USING_QSPI']):
+    src += Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.c') + Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.S')
+    path += [STANDALONE_DIR + '/drivers/qspi/fqspi/']
 
 # phytium ports rt-thread drivers
 PORT_DRV_DIR = cwd + '/drivers'
 
 src += Glob(PORT_DRV_DIR + '/*.S')
-src += Glob(PORT_DRV_DIR + '/*.c')
+src	+= Glob(PORT_DRV_DIR + '/*.c')
+
+# phytium ports rt-thread examples
+PORT_DRV_DIR = cwd + '/examples'
+
+src	+= Glob(PORT_DRV_DIR + '/*.c')
+
+# sdkcomfig.h
+path += [cwd]
 
+# add group
 ASFLAGS = ''
 group = DefineGroup('FT_DRIVER', src, depend=[
                     ''], CPPPATH=path, ASFLAGS = ASFLAGS)
diff --git a/bsp/phytium/libraries/drivers/Kconfig b/bsp/phytium/libraries/drivers/Kconfig
index 9714fdd0980..ddbbb9b5ffd 100644
--- a/bsp/phytium/libraries/drivers/Kconfig
+++ b/bsp/phytium/libraries/drivers/Kconfig
@@ -5,20 +5,53 @@ menu "On-chip Peripheral Drivers"
         bool "Enable UART"
         default y
         select USE_SERIAL # sdk serial component
-        select ENABLE_Pl011_UART # select sdk pl011 driver
         select RT_USING_SERIAL
         if BSP_USING_UART
             config RT_USING_UART1
                 bool "Enable UART1"
                 default y
-
+            
             config RT_USING_UART0
                 bool "Enable UART0"
                 default n
 
         endif
 
+    menuconfig BSP_USING_SPI
+        bool "Enable Spi"
+        default y
+        select USE_SPI # sdk spi component
+        select RT_USING_SPI
+        if BSP_USING_SPI
+            config RT_USING_SPIM0
+                bool "Enable spim0"
+                default n
+
+            config RT_USING_SPIM1
+                bool "Enable spim1"
+                default n
+            
+            config RT_USING_SPIM2
+                bool "Enable spim2"
+                default y
+
+            config RT_USING_SPIM3
+                bool "Enable spim3"
+                default n
+        endif
+
+    menuconfig BSP_USING_CAN
+        bool "Enable CAN"
+        default y
+        select RT_USING_CAN
+        select RT_CAN_USING_HDR
+        select RT_CAN_USING_CANFD
 
+    menuconfig BSP_USING_QSPI
+        bool "Enable QSPI"
+        default y
+        select RT_USING_QSPI
+        select RT_USING_SPI
 
 endmenu
 
diff --git a/bsp/phytium/libraries/drivers/drv_can.c b/bsp/phytium/libraries/drivers/drv_can.c
new file mode 100644
index 00000000000..194cd599f8d
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_can.c
@@ -0,0 +1,594 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-20     zhangyan     first version
+ *
+ */
+
+#include "drv_can.h"
+#include "sdkconfig.h"
+
+#ifdef RT_USING_CAN
+#include "fdebug.h"
+#include "fpinctrl.h"
+
+#define FCAN_TEST_DEBUG_TAG "FCAN_TEST"
+#define FCAN_TEST_DEBUG(format, ...) FT_DEBUG_PRINT_D(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FCAN_TEST_INFO(format, ...) FT_DEBUG_PRINT_I(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FCAN_TEST_WARN(format, ...) FT_DEBUG_PRINT_W(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FCAN_TEST_ERROR(format, ...) FT_DEBUG_PRINT_E(FCAN_TEST_DEBUG_TAG, format, ##__VA_ARGS__)
+
+struct phytium_can
+{
+    const char *name;
+    FCanCtrl can_handle;
+    FCanIdMaskConfig filter;
+    struct rt_can_device device; /* inherit from can device */
+};
+
+static struct phytium_can drv_can[FCAN_NUM] =
+{
+{
+    .name = "CAN0",
+    .can_handle.config.instance_id = 0,
+},
+{
+    .name = "CAN1",
+    .can_handle.config.instance_id = 1,
+},
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
+{
+    .name = "CAN2",
+    .can_handle.config.instance_id = 2,
+},
+#endif
+};
+
+static void CanRxIrqCallback(void *args)
+{
+    FCanCtrl *instance_p = (FCanCtrl *)args;
+    rt_hw_can_isr(&drv_can[instance_p->config.instance_id].device, RT_CAN_EVENT_RX_IND);
+    FCAN_TEST_DEBUG("CAN%d irq recv frame callback.", instance_p->config.instance_id);
+}
+
+static void CanErrorCallback(void *args)
+{
+    FCanCtrl *instance_p = (FCanCtrl *)args;
+    uintptr base_addr = instance_p->config.base_address;
+    FCAN_TEST_DEBUG("CAN %d is under error.", instance_p->config.instance_id);
+    FCAN_TEST_DEBUG("error_status is %x.", FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
+    FCAN_TEST_DEBUG("rxerr_cnt is %x.", FCAN_ERR_CNT_RFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET)));
+    FCAN_TEST_DEBUG("txerr_cnt is %x.", FCAN_ERR_CNT_TFN_GET(FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET)));
+}
+
+static void CanTxIrqCallback(void *args)
+{
+    FCanCtrl *instance_p = (FCanCtrl *)args;
+    rt_hw_can_isr(&drv_can[instance_p->config.instance_id].device, RT_CAN_EVENT_TX_DONE);
+    FCAN_TEST_DEBUG("CAN%d irq send frame callback.", instance_p->config.instance_id);
+}
+
+static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg)
+{
+    RT_ASSERT(can);
+    RT_ASSERT(cfg);
+    struct phytium_can *drv_can;
+    drv_can = (struct phytium_can *)can->parent.user_data;
+    RT_ASSERT(drv_can);
+    FError status = FT_SUCCESS;
+    rt_kprintf("CAN%d begin to config.\n", drv_can->can_handle.config.instance_id);
+
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
+    if(drv_can->can_handle.config.instance_id == FCAN_INSTANCE_0)
+    {
+        FPinSetFunc(FIOCTRL_TJTAG_TDI_PAD, FPIN_FUNC1); /* can0-tx: func 1 */
+        FPinSetFunc(FIOCTRL_SWDITMS_SWJ_PAD, FPIN_FUNC1); /* can0-rx: func 1 */
+    }
+    else if(drv_can->can_handle.config.instance_id == FCAN_INSTANCE_1)
+    {
+        FPinSetFunc(FIOCTRL_NTRST_SWJ_PAD, FPIN_FUNC1); /* can1-tx: func 1 */
+        FPinSetFunc(FIOCTRL_SWDO_SWJ_PAD, FPIN_FUNC1); /* can1-rx: func 1 */
+    }
+    else
+    {
+        FCAN_TEST_ERROR("CAN id is under error.");
+        return RT_ERROR;
+    }
+#elif defined(CONFIG_TARGET_E2000)
+    FIOPadSetCanMux(drv_can->can_handle.config.instance_id);
+#endif
+
+    /*CAN config init*/
+    status = FCanCfgInitialize(&(drv_can->can_handle), FCanLookupConfig(drv_can->can_handle.config.instance_id));
+    if (status != FT_SUCCESS)
+    {
+        FCAN_TEST_DEBUG("CAN %d initialize error, status = %#x.", drv_can->can_handle.config.instance_id, status);
+        return RT_ERROR;
+    }
+
+    /*Set the baudrate*/
+    FCanBaudrateConfig arb_segment_config;
+    FCanBaudrateConfig data_segment_config;
+    memset(&arb_segment_config, 0, sizeof(arb_segment_config));
+    memset(&data_segment_config, 0, sizeof(data_segment_config));
+#if defined(RT_CAN_USING_CANFD)
+    arb_segment_config.auto_calc = TRUE;
+    arb_segment_config.baudrate = CAN1MBaud; /*CANFD arb baud defaults to 1M ,allowed to be modified*/
+    arb_segment_config.segment = FCAN_ARB_SEGMENT;
+    status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
+    if (status != RT_EOK)
+    {
+        FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+    data_segment_config.auto_calc = TRUE;
+    data_segment_config.baudrate = cfg->baud_rate_fd;
+    data_segment_config.segment = FCAN_DATA_SEGMENT;
+    status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
+    if (status != RT_EOK)
+    {
+        FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+#else
+    arb_segment_config.auto_calc = TRUE;
+    arb_segment_config.baudrate = cfg->baud_rate;
+    arb_segment_config.segment = FCAN_ARB_SEGMENT;
+    status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
+    if (status != FT_SUCCESS)
+    {
+        FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+    data_segment_config.auto_calc = TRUE;
+    data_segment_config.baudrate = cfg->baud_rate;
+    data_segment_config.segment = FCAN_DATA_SEGMENT;
+    status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
+    if (status != FT_SUCCESS)
+    {
+        FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+#endif
+
+    /*CAN filter function init*/
+    for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
+    {
+        drv_can->filter.filter_index = i;
+        drv_can->filter.id = 0;
+        drv_can->filter.mask = FCAN_ACC_IDN_MASK;
+        status |= FCanIdMaskFilterSet(&(drv_can->can_handle), &(drv_can->filter));
+    }
+    if (status != FT_SUCCESS)
+    {
+        FCAN_TEST_ERROR("CAN%d set mask filter failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+    /* Identifier mask enable */
+    FCanIdMaskFilterEnable(&(drv_can->can_handle));
+    /* Transmit mode init , the default setting is normal mode */
+    FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_NORMAL_MODE);
+    /* enable can transfer */
+    FCanEnable(&(drv_can->can_handle), RT_TRUE);
+
+    return RT_EOK;
+}
+
+static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
+{
+    RT_ASSERT(can);
+    rt_uint32_t argval;
+    struct phytium_can *drv_can;
+    drv_can = (struct phytium_can *)can->parent.user_data;
+    RT_ASSERT(drv_can != RT_NULL);
+    rt_uint32_t cpu_id;
+    FCanIntrEventConfig intr_event;
+    FError status = FT_SUCCESS;
+
+#ifdef RT_CAN_USING_HDR
+    struct rt_can_filter_config *filter_cfg;
+#endif
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_SET_INT:
+        GetCpuId(&cpu_id);
+        rt_hw_interrupt_set_target_cpus(drv_can->can_handle.config.irq_num, cpu_id);
+        argval = (rt_uint32_t) arg;
+        /*Open different interrupts*/
+        if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            intr_event.type = FCAN_INTR_EVENT_ERROR;
+            intr_event.handler = CanErrorCallback;
+            intr_event.param = (void *)(&(drv_can->can_handle));
+            FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
+            FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
+        }
+        if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            intr_event.type = FCAN_INTR_EVENT_SEND;
+            intr_event.handler = CanTxIrqCallback;
+            intr_event.param = (void *)(&(drv_can->can_handle));
+            FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
+            FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
+        }
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            intr_event.type = FCAN_INTR_EVENT_RECV;
+            intr_event.handler = CanRxIrqCallback;
+            intr_event.param = (void *)(&(drv_can->can_handle));
+            FCanRegisterInterruptHandler(&(drv_can->can_handle), &intr_event);
+            FCanInterruptEnable(&(drv_can->can_handle), intr_event.type);
+        }
+        rt_hw_interrupt_set_priority(drv_can->can_handle.config.irq_num, 16);
+        rt_hw_interrupt_install(drv_can->can_handle.config.irq_num, FCanIntrHandler, &(drv_can->can_handle), drv_can->name);
+        rt_hw_interrupt_umask(drv_can->can_handle.config.irq_num);
+        break;
+
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        FCanEnable(&(drv_can->can_handle), RT_FALSE);
+        if (argval == RT_CAN_MODE_LISTEN)
+        {
+            FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_MONITOR_MODE);
+            drv_can->device.config.mode = RT_CAN_MODE_LISTEN;
+        }
+        else if (argval == RT_CAN_MODE_NORMAL)
+        {
+            FCanSetMode(&(drv_can->can_handle), FCAN_PROBE_NORMAL_MODE);
+            drv_can->device.config.mode = RT_CAN_MODE_NORMAL;
+        }
+        FCanEnable(&(drv_can->can_handle), RT_TRUE);
+        break;
+
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud   &&
+            argval != CAN800kBaud &&
+            argval != CAN500kBaud &&
+            argval != CAN250kBaud &&
+            argval != CAN125kBaud &&
+            argval != CAN100kBaud &&
+            argval != CAN50kBaud  &&
+            argval != CAN20kBaud  &&
+            argval != CAN10kBaud)
+        {
+            return RT_ERROR;
+        }
+        if (argval != drv_can->device.config.baud_rate)
+        {
+            FCanBaudrateConfig arb_segment_config;
+            FCanBaudrateConfig data_segment_config;
+            memset(&arb_segment_config, 0, sizeof(arb_segment_config));
+            memset(&data_segment_config, 0, sizeof(data_segment_config));
+            drv_can->device.config.baud_rate = argval;
+            FCanEnable(&(drv_can->can_handle), RT_FALSE);
+            arb_segment_config.auto_calc = TRUE;
+            arb_segment_config.baudrate = drv_can->device.config.baud_rate;
+            arb_segment_config.segment = FCAN_ARB_SEGMENT;
+            status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
+            if (status != FT_SUCCESS)
+            {
+                FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
+                return RT_ERROR;
+            }
+            data_segment_config.auto_calc = TRUE;
+            data_segment_config.baudrate = drv_can->device.config.baud_rate;
+            data_segment_config.segment = FCAN_DATA_SEGMENT;
+            status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
+            if (status != FT_SUCCESS)
+            {
+                FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
+                return RT_ERROR;
+            }
+            FCanEnable(&(drv_can->can_handle), RT_TRUE);
+        }
+        break;
+
+    case RT_CAN_CMD_SET_BAUD_FD:
+    #if defined RT_CAN_USING_CANFD
+        argval = (rt_uint32_t) arg;
+        if (argval != drv_can->device.config.baud_rate_fd)
+        {
+            FCanBaudrateConfig arb_segment_config;
+            FCanBaudrateConfig data_segment_config;
+            memset(&arb_segment_config, 0, sizeof(arb_segment_config));
+            memset(&data_segment_config, 0, sizeof(data_segment_config));
+            drv_can->device.config.baud_rate = argval;
+            FCanEnable(&(drv_can->can_handle), RT_FALSE);
+            arb_segment_config.auto_calc = TRUE;
+            arb_segment_config.baudrate = CAN1MBaud;
+            arb_segment_config.segment = FCAN_ARB_SEGMENT;
+            status = FCanBaudrateSet(&(drv_can->can_handle), &arb_segment_config);
+            if (status != FT_SUCCESS)
+            {
+                FCAN_TEST_DEBUG("CAN%d set arb segment baudrate failed.", drv_can->can_handle.config.instance_id);
+                return RT_ERROR;
+            }
+            data_segment_config.auto_calc = TRUE;
+            data_segment_config.baudrate = drv_can->device.config.baud_rate_fd;
+            data_segment_config.segment = FCAN_DATA_SEGMENT;
+            status = FCanBaudrateSet(&(drv_can->can_handle), &data_segment_config);
+            if (status != FT_SUCCESS)
+            {
+                FCAN_TEST_DEBUG("CAN%d set data segment baudrate failed.", drv_can->can_handle.config.instance_id);
+                return RT_ERROR;
+            }
+            FCanEnable(&(drv_can->can_handle), RT_TRUE);
+        }
+    #endif
+    break;
+
+    case RT_CAN_CMD_SET_FILTER:
+    #ifdef RT_CAN_USING_HDR
+        filter_cfg = (struct rt_can_filter_config *)arg;
+        FCanEnable(&(drv_can->can_handle), RT_FALSE);
+        for (int i = 0; i < filter_cfg->count; i++)
+        {
+            drv_can->filter.filter_index = i;
+            drv_can->filter.mask = filter_cfg->items[i].mask;
+            drv_can->filter.id = filter_cfg->items[i].id;
+            drv_can->filter.type = FCAN_STANDARD_FRAME;
+            status = FCanIdMaskFilterSet(&(drv_can->can_handle), &(drv_can->filter));
+            if (status != FT_SUCCESS)
+            {
+                FCAN_TEST_ERROR("CAN%d set mask filter failed.", drv_can->can_handle.config.instance_id);
+                return RT_ERROR;
+            }
+        }
+        FCanEnable(&(drv_can->can_handle), RT_TRUE);
+    #endif
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+    RT_ASSERT(can);
+    RT_ASSERT(buf);
+    struct phytium_can *drv_can;
+    drv_can = (struct phytium_can *)can->parent.user_data;
+    RT_ASSERT(drv_can);
+    struct rt_can_msg *pmsg = (struct rt_can_msg *)buf;
+    FCanFrame can_frame = {0};
+
+    /* Check the parameters */
+    RT_ASSERT(pmsg->len <= 8U);
+
+    if (RT_CAN_STDID == pmsg->ide)
+    {
+        can_frame.canid = pmsg->id;
+    }
+    else
+    {
+        can_frame.canid = pmsg->id;
+        can_frame.canid |= CAN_EFF_FLAG;
+    }
+    if (RT_CAN_DTR == pmsg->rtr)
+    {
+
+    }
+    else
+    {
+        can_frame.canid |= CAN_RTR_FLAG;
+    }
+
+    can_frame.candlc = pmsg->len ;
+
+    memcpy(can_frame.data, pmsg->data, 8);
+    return (FCanSend(&drv_can->can_handle, &can_frame) == RT_EOK) ? RT_EOK : -RT_ERROR;
+}
+
+static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+    RT_ASSERT(can);
+    RT_ASSERT(buf);
+    struct phytium_can *drv_can;
+    drv_can = (struct phytium_can *)can->parent.user_data;
+    RT_ASSERT(drv_can);
+    struct rt_can_msg *pmsg = (struct rt_can_msg *)buf;
+    FCanFrame recv_frame;
+    FError status = FT_SUCCESS;
+
+    status = FCanRecv(&(drv_can->can_handle), &recv_frame);
+    if (status != FT_SUCCESS)
+    {
+        FCAN_TEST_DEBUG("CAN%d recv data failed.", drv_can->can_handle.config.instance_id);
+        return RT_ERROR;
+    }
+    if (CAN_EFF_FLAG & recv_frame.canid)
+    {
+        pmsg->ide = RT_CAN_EXTID;
+        pmsg->id = (recv_frame.canid & ~(RT_CAN_EXTID));
+    }
+    else
+    {
+        pmsg->ide = RT_CAN_STDID;
+        pmsg->id = recv_frame.canid;
+    }
+
+    if (CAN_RTR_FLAG & recv_frame.canid)
+    {
+        pmsg->id &= ~CAN_RTR_FLAG;
+        pmsg->rtr = RT_CAN_RTR;
+    }
+    else
+    {
+        pmsg->rtr = RT_CAN_DTR;
+    }
+
+    /* get len */
+    pmsg->len = recv_frame.candlc;
+    for (int i = 0; i < pmsg->len; i++)
+    {
+        pmsg->data[i] = recv_frame.data[i];
+    }
+    /* get hdr */
+    pmsg->hdr = 0;
+
+    return RT_EOK;
+}
+
+static const struct rt_can_ops _can_ops =
+{
+    _can_config,
+    _can_control,
+    _can_sendmsg,
+    _can_recvmsg,
+};
+
+int rt_hw_can_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    for (int i = 0; i < (u32)FCAN_NUM; i++)
+    {
+        drv_can[i].device.config.ticks = 20000;
+        drv_can[i].device.config.baud_rate = 800000;
+    #ifdef RT_CAN_USING_CANFD
+        drv_can[i].device.config.baud_rate_fd = 800000;
+    #endif
+        drv_can[i].device.config.mode = RT_CAN_MODE_NORMAL;
+        drv_can[i].device.config.sndboxnumber = 1;
+        drv_can[i].device.config.msgboxsz = 1;
+    #ifdef RT_CAN_USING_HDR
+        drv_can[i].device.config.maxhdr = 1;
+    #endif
+        ret = rt_hw_can_register(&drv_can[i].device,
+                       drv_can[i].name,
+                       &_can_ops,
+                       &drv_can[i]);
+        RT_ASSERT(ret == RT_EOK);
+    }
+    return (int)ret;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+/*can test example*/
+static rt_device_t can_dev;            /* CAN device handle */
+static struct rt_semaphore rx_sem;
+static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
+{
+    /* The CAN generates an interrupt after receiving data, calls this callback function, and then sends the received semaphore */
+    rt_sem_release(&rx_sem);
+    return RT_EOK;
+}
+static void can_rx_thread(void *parameter)
+{
+    int i;
+    rt_err_t res = RT_EOK;
+    struct rt_can_msg rxmsg = {0};
+    rt_device_set_rx_indicate(can_dev, can_rx_call);
+    while (1)
+    {
+        /* The hdr value is - 1, which means reading data directly from the uselist */
+        rxmsg.hdr = -1;
+        /* Blocking waiting to receive semaphore */
+        res = rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
+        RT_ASSERT(res == RT_EOK);
+        /* Read a frame of data from CAN */
+        rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
+        /* Print data ID and conten */
+        rt_kprintf("ID:%x\n", rxmsg.id);
+        rt_kprintf("DATA: ");
+        for (i = 0; i < 8; i++)
+        {
+            rt_kprintf("%2x ", rxmsg.data[i]);
+        }
+
+        rt_kprintf("\n");
+    }
+}
+
+int can_sample(int argc, char *argv[])
+{
+    struct rt_can_msg msg = {0};
+    rt_err_t res = RT_EOK;;
+    rt_size_t  size;
+    rt_thread_t thread;
+    char can_name[RT_NAME_MAX];
+
+    if (argc == 2)
+    {
+        rt_strncpy(can_name, argv[1], RT_NAME_MAX);
+    }
+    else
+    {
+        rt_strncpy(can_name, "CAN0", RT_NAME_MAX);
+    }
+    /* Find CAN device */
+    can_dev = rt_device_find(can_name);
+    if (!can_dev)
+    {
+        rt_kprintf("Find %s failed.\n", can_name);
+        return RT_ERROR;
+    }
+
+    /* Initialize CAN receive signal quantity */
+    res = rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
+    RT_ASSERT(res == RT_EOK);
+
+    /* Open the CAN device in the way of interrupt reception and transmission */
+    res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
+    rt_device_control(can_dev,RT_CAN_CMD_SET_BAUD, CAN1MBaud);
+    RT_ASSERT(res == RT_EOK);
+
+    #ifdef RT_CAN_USING_HDR
+    struct rt_can_filter_item items[4] =
+    {
+        RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
+        RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
+        RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL),
+        RT_CAN_FILTER_ITEM_INIT(0x3, 0, 0, 0, 0, RT_NULL, RT_NULL)
+
+    };
+    struct rt_can_filter_config cfg = {4, 1, items}; /* There are 4 filter tables in total */
+
+    /* Set the hardware filter table. After setting, only frames with id=0x03 can be received*/
+    res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
+    RT_ASSERT(res == RT_EOK);
+    #endif
+
+    /* Create data receiving thread */
+    thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
+    if (thread != RT_NULL)
+    {
+        res = rt_thread_startup(thread);
+        RT_ASSERT(res == RT_EOK);
+    }
+    else
+    {
+        rt_kprintf("Create can_rx thread failed.\n");
+    }
+
+    msg.id = 0x78;              /* ID = 0x78 */
+    msg.ide = RT_CAN_STDID;     /* Standard format */
+    msg.rtr = RT_CAN_RTR;       /* Data frame */
+    msg.len = 8;                /* Data length is 8 */
+    /* Send CAN data */
+    for (int i = 0; i < 10; i++)
+    {
+    /* 8-byte data to be sent */
+        msg.data[0] = 0x00+i;
+        msg.data[1] = 0x11+i;
+        msg.data[2] = 0x22+i;
+        msg.data[3] = 0x33+i;
+        msg.data[4] = 0x44+i;
+        msg.data[5] = 0x55+i;
+        msg.data[6] = 0x66+i;
+        msg.data[7] = 0x77+i;
+        rt_device_write(can_dev, 0, &msg, sizeof(msg));
+    }
+
+    return res;
+}
+/* Enter can_sample command for testing */
+MSH_CMD_EXPORT(can_sample, can device sample);
+#endif
diff --git a/bsp/phytium/libraries/drivers/drv_can.h b/bsp/phytium/libraries/drivers/drv_can.h
new file mode 100644
index 00000000000..cc21da0383f
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_can.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-20     zhangyan     first version
+ *
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#include <rtdevice.h>
+
+#ifdef RT_USING_CAN
+
+#include "fcan.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+int rt_hw_can_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif /* __DRV_CAN_H__ */
diff --git a/bsp/phytium/libraries/drivers/drv_qspi.c b/bsp/phytium/libraries/drivers/drv_qspi.c
new file mode 100644
index 00000000000..bdd76a2eb1c
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_qspi.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-20     zhangyan     first version
+ *
+ */
+
+#include "drv_qspi.h"
+#include "sdkconfig.h"
+
+#ifdef RT_USING_QSPI
+#include <rtthread.h>
+#include "rtdevice.h"
+#include "fqspi_flash.h"
+#include "fdebug.h"
+#include "fpinctrl.h"
+
+#define FQSPI_DEBUG_TAG "FQSPI"
+#define FQSPI_ERROR(format, ...)    FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_WARN(format, ...)     FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_INFO(format, ...)     FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FQSPI_DEBUG(format, ...)    FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define DAT_LENGTH 128
+struct phytium_qspi_bus
+{
+    char *name;
+    rt_uint32_t init; /* 0 is init already */
+    FQspiCtrl fqspi;
+    struct rt_spi_bus qspi_bus;
+};
+
+static struct phytium_qspi_bus phytium_qspi;      /* phytium qspi bus handle */
+static struct rt_qspi_device *qspi_device;        /* phytium device bus handle */
+static char qspi_bus_name[RT_NAME_MAX] = "QSPIBUS";
+static char qspi_dev_name[RT_NAME_MAX] = "QSPIDEV";
+
+rt_err_t FQspiInit(FQspiCtrl *fqspi)
+{
+    u32 qspi_id = FQSPI0_ID;
+    FError ret = FT_SUCCESS;
+
+#if defined(CONFIG_TARGET_E2000)
+    FIOPadSetQspiMux(qspi_id, FQSPI_CS_0);
+    FIOPadSetQspiMux(qspi_id, FQSPI_CS_1);
+#endif
+
+    FQspiDeInitialize(fqspi);
+    FQspiConfig pconfig = *FQspiLookupConfig(qspi_id);
+
+    /* Norflash init, include reset and read flash_size */
+    ret = FQspiCfgInitialize(fqspi, &pconfig);
+    if (FT_SUCCESS != ret)
+    {
+        FQSPI_DEBUG("Qspi init failed.\n");
+        return RT_ERROR;
+    }
+    else
+    {
+        FQSPI_DEBUG("Qspi init successfully.\n");
+    }
+
+    /* Detect connected flash infomation */
+    ret = FQspiFlashDetect(fqspi);
+    if (FT_SUCCESS != ret)
+    {
+        FQSPI_DEBUG("Qspi flash detect failed.\n");
+        return RT_ERROR;
+    }
+    else
+    {
+        FQSPI_DEBUG("Qspi flash detect successfully.\n");
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration)
+{
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+    struct phytium_qspi_bus *qspi_bus;
+    qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
+    rt_err_t ret = RT_EOK;
+
+    ret = FQspiInit(&(qspi_bus->fqspi));
+    if (RT_EOK != ret)
+    {
+        qspi_bus->init = RT_FALSE;
+        FQSPI_DEBUG("Qspi init failed!!!\n");
+        return RT_ERROR;
+    }
+    qspi_bus->init = RT_EOK;
+
+    return RT_EOK;
+}
+
+static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+    struct phytium_qspi_bus *qspi_bus;
+    struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message;
+    rt_uint32_t cmd = qspi_message->instruction.content;
+    rt_uint32_t flash_addr = qspi_message->address.content;
+    rt_uint8_t *rcvb = message->recv_buf;
+    rt_uint8_t *sndb = message->send_buf;
+    FError ret = FT_SUCCESS;
+
+    qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data;
+
+    /*Distinguish the write mode according to different commands*/
+    if (cmd == FQSPI_FLASH_CMD_PP||cmd == FQSPI_FLASH_CMD_QPP||cmd ==FQSPI_FLASH_CMD_4PP||cmd ==FQSPI_FLASH_CMD_4QPP )
+    {
+        char *strs = (char *)message->send_buf;
+        rt_uint8_t len = strlen(strs) + 1;
+        rt_uint8_t *wr_buf = NULL;
+        wr_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
+
+        rt_memcpy(wr_buf, strs, len);
+        message->length = len;
+        ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr);
+        if (FT_SUCCESS != ret)
+        {
+            FQSPI_DEBUG("Failed to erase mem, test result 0x%x.\r\n", ret);
+            return RT_ERROR;
+        }
+        /* write norflash data */
+        ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, flash_addr, wr_buf, len);
+
+        if (FT_SUCCESS != ret)
+        {
+            FQSPI_DEBUG("Failed to write mem, test result 0x%x.\r\n", ret);
+            return RT_ERROR;
+        }
+        else
+        {
+            rt_kprintf("Write successfully!!!\r\n");
+        }
+        rt_free(wr_buf);
+
+        return RT_EOK;
+    }
+
+    /*Distinguish the read mode according to different commands*/
+    if (cmd == FQSPI_FLASH_CMD_READ||cmd == FQSPI_FLASH_CMD_4READ||cmd == FQSPI_FLASH_CMD_FAST_READ||cmd == FQSPI_FLASH_CMD_4FAST_READ||
+        cmd == FQSPI_FLASH_CMD_DUAL_READ||cmd == FQSPI_FLASH_CMD_QIOR||cmd == FQSPI_FLASH_CMD_4QIOR)
+    {
+        rt_uint8_t *rd_buf = NULL;
+        rd_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t));
+
+        ret |= FQspiFlashReadDataConfig(&(qspi_bus->fqspi), cmd);
+
+        if (FT_SUCCESS != ret)
+        {
+            FQSPI_DEBUG("Failed to config read, test result 0x%x.\r\n", ret);
+            return RT_ERROR;
+        }
+        /* read norflash data */
+        size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, rd_buf, DAT_LENGTH);
+        message->length = read_len;
+        if (read_len != DAT_LENGTH)
+        {
+            FQSPI_DEBUG("Failed to read mem, read len = %d.\r\n", read_len);
+            return RT_ERROR;
+        }
+        else
+        {
+            rt_kprintf("Read successfully!!!\r\n");
+            message->recv_buf = rd_buf;
+            rt_free(rd_buf);
+        }
+        FtDumpHexByte(message->recv_buf, DAT_LENGTH);
+
+       return RT_EOK;
+    }
+
+    if (rcvb)
+    {
+        if (cmd == FQSPI_FLASH_CMD_RDID||cmd == FQSPI_FLASH_CMD_RDSR1||cmd == FQSPI_FLASH_CMD_RDSR2 ||cmd == FQSPI_FLASH_CMD_RDSR3)
+        {
+            ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, rcvb, sizeof(rcvb));
+            if (FT_SUCCESS != ret)
+            {
+                FQSPI_DEBUG("Failed to read flash information.\n");
+                return RT_ERROR;
+            }
+        }
+
+        return RT_EOK;
+    }
+
+    if (sndb)
+    {
+        ret |= FQspiFlashEnableWrite(&(qspi_bus->fqspi));
+        if (FT_SUCCESS != ret)
+        {
+            FQSPI_DEBUG("Failed to enable flash reg write.\n");
+            return RT_ERROR;
+        }
+
+        ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, sndb, 1);
+        if (FT_SUCCESS != ret)
+        {
+            FQSPI_DEBUG("Failed to write flash reg.\n");
+            return RT_ERROR;
+        }
+
+        return RT_EOK;
+    }
+}
+
+static struct rt_spi_ops phytium_qspi_ops =
+{
+    .configure = phytium_qspi_configure,
+    .xfer = phytium_qspi_xfer,
+};
+
+rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name)
+{
+    struct rt_qspi_device *qspi_device;
+    rt_err_t result = RT_EOK;
+    RT_ASSERT(bus_name != RT_NULL);
+    RT_ASSERT(device_name != RT_NULL);
+
+    qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device));
+    if (qspi_device == RT_NULL)
+    {
+        FQSPI_DEBUG("Qspi bus attach device failed.");
+        result = RT_ENOMEM;
+        goto __exit;
+    }
+
+    result = rt_spi_bus_attach_device(&(qspi_device->parent), device_name, bus_name, RT_NULL);
+__exit:
+    if (result != RT_EOK)
+    {
+        if (qspi_device)
+        {
+            rt_free(qspi_device);
+
+        }
+
+    return  result;
+}
+}
+
+int rt_hw_qspi_init(void)
+{
+    int i = 0;
+    int result = RT_EOK;
+    phytium_qspi.qspi_bus.parent.user_data = &phytium_qspi;
+
+    if(rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name , &phytium_qspi_ops) == RT_EOK)
+    {
+        rt_kprintf("Qspi bus register successfully!!!\n");
+    }
+    else
+    {
+        FQSPI_DEBUG("Qspi bus register Failed!!!\n");
+        result = -RT_ERROR;
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_qspi_init);
+
+/*example*/
+struct rt_spi_message write_message;
+struct rt_spi_message read_message;
+
+rt_err_t qspi_init()
+{
+    rt_err_t res = RT_EOK;
+    res = phytium_qspi_bus_attach_device(qspi_bus_name, qspi_dev_name);
+    RT_ASSERT(res == RT_EOK);
+    qspi_device = (struct rt_qspi_device *)rt_device_find(qspi_dev_name);
+
+    return res;
+}
+
+/*read cmd example message improvement*/
+void ReadCmd(struct rt_spi_message *spi_message)
+{
+    struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
+    message->address.content = 0x360000 ;/*Flash address*/
+    message->instruction.content = 0x03 ;/*read cmd*/
+    rt_qspi_transfer_message(qspi_device, message);
+}
+
+/*write cmd example message improvement*/
+void WriteCmd(struct rt_spi_message *spi_message)
+{
+    struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message;
+    message->address.content = 0x360000 ;/*Flash address*/
+    message->instruction.content = 0x02 ;/*write cmd*/
+    rt_qspi_transfer_message(qspi_device, message);
+}
+
+/*write cmd example message improvement*/
+void qspi_thread(void *parameter)
+{
+    rt_err_t res;
+
+    qspi_init();
+    /*Read and write flash chip fixed area repeatedly*/
+    write_message.send_buf = "111111111111111111111111";
+    WriteCmd(&write_message);
+    ReadCmd(&read_message);
+
+    write_message.send_buf = "222222222222222222222222";
+    WriteCmd(&write_message);
+    ReadCmd(&read_message);
+
+    write_message.send_buf = "333333333333333333333333";
+    WriteCmd(&write_message);
+    ReadCmd(&read_message);
+
+    rt_uint8_t recv;
+    rt_uint8_t cmd = 0x9F;/*read the flash status reg2*/
+    res = rt_qspi_send_then_recv(qspi_device, &cmd, sizeof(cmd), &recv, sizeof(recv));
+    RT_ASSERT(res!=RT_EOK);
+
+    rt_kprintf("The status reg = %x \n" ,recv);
+
+    return 0;
+}
+
+rt_err_t qspi_sample(int argc, char *argv[])
+{
+    rt_thread_t thread;
+    rt_err_t res;
+    thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 1024, 25, 10);
+    res = rt_thread_startup(thread);
+    RT_ASSERT(res==RT_EOK);
+
+    return res;
+
+}
+/* Enter qspi_sample command for testing */
+MSH_CMD_EXPORT(qspi_sample, qspi sample);
+#endif
diff --git a/bsp/phytium/libraries/drivers/drv_qspi.h b/bsp/phytium/libraries/drivers/drv_qspi.h
new file mode 100644
index 00000000000..32af7f34bb5
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_qspi.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023-03-20     zhangyan     first version
+ *
+ */
+
+#ifndef __DRT_QSPI_H__
+#define __DRT_QSPI_H__
+
+#include <rtthread.h>
+#ifdef RT_USING_QSPI
+#define PHYTIUM_QSPI_NAME "qspi"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+#endif // !DRT_QSPI_H
+
diff --git a/bsp/phytium/libraries/drivers/drv_spi.c b/bsp/phytium/libraries/drivers/drv_spi.c
new file mode 100644
index 00000000000..f7d537256d0
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_spi.c
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-11-10  liqiaozhong  first commit
+ * 2023-03-08  liqiaozhong  support 4 spis and qspi working together
+ *
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "interrupt.h"
+
+#include <string.h>
+#include "fdebug.h"
+
+#if defined(TARGET_E2000)
+#include "fparameters.h"
+#endif
+
+#include "fcpu_info.h"
+#include "fkernel.h"
+#include "ftypes.h"
+#include "fsleep.h"
+
+#ifdef RT_USING_SPI
+
+#include <dfs_file.h>
+
+#include "fspim.h"
+#include "fspim_hw.h" /* include low-level header file for internal probe */
+#include "drv_spi.h"
+/************************** Constant Definitions *****************************/
+/**************************** Type Definitions *******************************/
+/************************** Variable Definitions *****************************/
+#ifdef RT_USING_SPIM0
+    static struct drv_spi _RTSpim0;
+#endif
+
+#ifdef RT_USING_SPIM1
+    static struct drv_spi _RTSpim1;
+#endif
+
+#ifdef RT_USING_SPIM2
+    static struct drv_spi _RTSpim2;
+#endif
+
+#ifdef RT_USING_SPIM3
+    static struct drv_spi _RTSpim3;
+#endif
+
+static struct rt_spi_device *spi_device = RT_NULL;
+static struct rt_event rx_done_event;
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FSPIM_DEBUG_TAG "SPIM"
+#define FSPIM_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_WARN(format, ...)   FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_INFO(format, ...)    FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define EVENT_RX_DONE (1 << 1)
+/*******************************Api Functions*********************************/
+static rt_err_t spim_configure(struct rt_spi_device* device, struct rt_spi_configuration* configuration);
+static rt_uint32_t spim_xfer(struct rt_spi_device* device, struct rt_spi_message* message);
+
+static FError FSpimSetupInterrupt(FSpim *instance_p)
+{
+    FASSERT(instance_p);
+    FSpimConfig *config_p = &instance_p->config;
+    uintptr base_addr = config_p->base_addr;
+    u32 cpu_id = 0;
+
+    GetCpuId(&cpu_id);
+    FSPIM_DEBUG("cpu_id is %d, irq_num is %d\n", cpu_id, config_p->irq_num);
+    config_p->irq_prority = 0xd0;
+    rt_hw_interrupt_set_target_cpus(config_p->irq_num, cpu_id);
+    rt_hw_interrupt_set_priority(config_p->irq_num, config_p->irq_prority);
+
+    /* register intr callback */
+    rt_hw_interrupt_install(config_p->irq_num,
+                    FSpimInterruptHandler,
+                    instance_p,
+                    NULL);
+
+    /* enable tx fifo overflow / rx overflow / rx full */
+    FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
+
+    /* enable irq */
+    rt_hw_interrupt_umask(config_p->irq_num);
+
+    return FSPIM_SUCCESS;
+}
+
+static void rt_ft_send_event_done(void *instance_p, void *param)
+{
+    FASSERT(instance_p);
+    rt_event_send(&rx_done_event, EVENT_RX_DONE);
+    return;
+}
+
+static const struct rt_spi_ops spim_ops =
+{
+    .configure = spim_configure,
+    .xfer = spim_xfer
+};
+
+static rt_err_t spim_configure(struct rt_spi_device *device,
+                              struct rt_spi_configuration *configuration)
+{
+    FError ret = FSPIM_SUCCESS;
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(configuration != RT_NULL);
+    struct drv_spi *user_data_cfg = device->parent.user_data;
+    FSpimConfig input_cfg = *FSpimLookupConfig(user_data_cfg->spi_id);
+    FSpimConfig *set_input_cfg = &input_cfg;
+
+    /* set fspim device according to configuration */
+    if (configuration->mode & RT_SPI_CPOL)
+    {
+        set_input_cfg->cpol = FSPIM_CPOL_HIGH;
+    }
+    else
+    {
+        set_input_cfg->cpol = FSPIM_CPOL_LOW;
+    }
+    if (configuration->mode & RT_SPI_CPHA)
+    {
+        set_input_cfg->cpha = FSPIM_CPHA_2_EDGE;
+    }
+    else
+    {
+        set_input_cfg->cpha = FSPIM_CPHA_1_EDGE;
+    }
+
+    if (configuration->data_width == 8)
+    {
+        set_input_cfg->n_bytes = FSPIM_1_BYTE;
+    }
+    else if (configuration->data_width == 16)
+    {
+        set_input_cfg->n_bytes = FSPIM_2_BYTE;
+    }
+
+    /* send spi_cfg to RT-Thread sys */
+    ret = FSpimCfgInitialize(&user_data_cfg->spim_instance, &input_cfg);
+    if (FSPIM_SUCCESS != ret)
+        return RT_ERROR;
+
+    /* irq setting */
+    ret = FSpimSetupInterrupt(&user_data_cfg->spim_instance);
+    if (FSPIM_SUCCESS != ret)
+        return RT_ERROR;
+    FSpimRegisterIntrruptHandler(&user_data_cfg->spim_instance, FSPIM_INTR_EVT_RX_DONE, rt_ft_send_event_done, NULL);
+
+    return ret;
+}
+
+static rt_uint32_t spim_xfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->parent.user_data != RT_NULL);
+    RT_ASSERT(message != RT_NULL);
+    rt_size_t message_length;
+    rt_uint8_t *recv_buf;
+    const rt_uint8_t *send_buf;
+
+    /* recv spi_cfg from RT-Thread sys */
+    struct drv_spi *user_data_xfer = device->parent.user_data;
+    FSpim *xfer_spim_instance = &user_data_xfer->spim_instance;
+
+    FError tx_rx_result = FSPIM_SUCCESS;
+    message_length = message->length;
+    recv_buf = message->recv_buf;
+    send_buf = message->send_buf;
+
+    if (message->cs_take)
+    {
+        FSpimSetChipSelection(xfer_spim_instance, TRUE);
+    }
+
+    if (message_length > 0)
+    {
+        if (send_buf == RT_NULL && recv_buf != RT_NULL)
+        {
+            /* receive message */
+            tx_rx_result = FSpimTransferByInterrupt(xfer_spim_instance, RT_NULL, recv_buf, message_length);
+        }
+        else if (send_buf != RT_NULL && recv_buf == RT_NULL)
+        {
+            /* send message */
+            tx_rx_result = FSpimTransferByInterrupt(xfer_spim_instance, send_buf, RT_NULL, message_length);
+        }
+        else if (send_buf != RT_NULL && recv_buf != RT_NULL)
+        {
+            /* not supported yet */
+            rt_kprintf("Do not support the situation that send_buf and recv_buf both not equal to 0.");
+        }
+    }
+
+    if (FSPIM_SUCCESS != tx_rx_result)
+    {
+        rt_kprintf("FSpimTransferByInterrupt() fail!!!");
+        message_length = 0;
+    }
+
+    if (rt_event_recv(&rx_done_event, (EVENT_RX_DONE),
+                      (RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR),
+                      RT_WAITING_FOREVER, RT_NULL) != RT_EOK)
+    {
+        rt_kprintf("Wait rx timeout!!!\n");
+        message_length = 0;
+    }
+
+    if (message->cs_release)
+    {
+        FSpimSetChipSelection(xfer_spim_instance, FALSE);
+    }
+
+    return message_length;
+}
+
+int ft_spi_init(void)
+{
+    rt_err_t result;
+    static struct rt_spi_bus spim_bus;
+
+    /* event creat */
+    if (RT_EOK != rt_event_init(&rx_done_event, "rx_done_event", RT_IPC_FLAG_FIFO))
+    {
+        rt_kprintf("Create event failed.\n");
+        return RT_ERROR;
+    }
+
+    /* spi bus init */
+    result = rt_spi_bus_register(&spim_bus, "spi0", &spim_ops);
+    RT_ASSERT((struct rt_spi_device *)rt_device_find("spi0"));
+    rt_kprintf("Spi bus spi0 init\n");
+
+    /* spi device init and attach to bus */
+    #ifdef RT_USING_SPIM0
+        _RTSpim0.spi_id = FSPI0_ID;
+        result = rt_spi_bus_attach_device(&_RTSpim0.device, "spi00", "spi0", &_RTSpim0);
+        spi_device = (struct rt_spi_device *)rt_device_find("spi00");
+        if (RT_NULL == spi_device)
+        {
+            rt_kprintf("Spi init failed -> can't find spi00 device!\n");
+            return RT_ERROR;
+        }
+        rt_kprintf("Spi master device spi00 init.\n");
+    #endif
+
+    #ifdef RT_USING_SPIM1
+        _RTSpim1.spi_id = FSPI1_ID;
+        result = rt_spi_bus_attach_device(&_RTSpim1.device, "spi01", "spi0", &_RTSpim1);
+        spi_device = (struct rt_spi_device *)rt_device_find("spi01");
+        if (RT_NULL == spi_device)
+        {
+            rt_kprintf("Spi init failed -> can't find spi01 device!\n");
+            return RT_ERROR;
+        }
+        rt_kprintf("Spi master device spi01 init.\n");
+    #endif
+
+    #ifdef RT_USING_SPIM2
+        _RTSpim2.spi_id = FSPI2_ID;
+        result = rt_spi_bus_attach_device(&_RTSpim2.device, "spi02", "spi0", &_RTSpim2);
+        spi_device = (struct rt_spi_device *)rt_device_find("spi02");
+        if (RT_NULL == spi_device)
+        {
+            rt_kprintf("Spi init failed -> can't find spi02 device!\n");
+            return RT_ERROR;
+        }
+        rt_kprintf("Spi master device spi02 init.\n");
+    #endif
+
+    #ifdef RT_USING_SPIM3
+        _RTSpim3.spi_id = FSPI3_ID;
+        result = rt_spi_bus_attach_device(&_RTSpim3.device, "spi03", "spi0", &_RTSpim3);
+        spi_device = (struct rt_spi_device *)rt_device_find("spi03");
+        if (RT_NULL == spi_device)
+        {
+            rt_kprintf("Spi init failed -> can't find spi03 device!\n");
+            return RT_ERROR;
+        }
+        rt_kprintf("Spi master device spi03 init.\n");
+    #endif
+
+
+    return result;
+}
+INIT_DEVICE_EXPORT(ft_spi_init);
+
+/* spi test example */
+static void fspim_test_sample(int argc, char *argv[])
+{
+    rt_uint8_t send_to_flash_id = 0x9f; /* Flash cmd */
+    rt_uint8_t recv_from_falsh_id1[5] = {0};
+    rt_uint8_t recv_from_falsh_id2[5] = {0};
+
+    /* find the spi device to get the device handle */
+    spi_device = (struct rt_spi_device *)rt_device_find("spi02");
+    if (!spi_device)
+    {
+        rt_kprintf("fspim_test_sample run failed! can't find spi02 device!\n");
+    }
+    else
+    {
+        static struct rt_spi_message msg1, msg2;
+
+        msg1.send_buf   = &send_to_flash_id;
+        msg1.recv_buf   = RT_NULL;
+        msg1.length     = 1;
+        msg1.cs_take    = 1;
+        msg1.cs_release = 0;
+        msg1.next       = &msg2;
+
+        msg2.send_buf   = RT_NULL;
+        msg2.recv_buf   = recv_from_falsh_id2;
+        msg2.length     = 5;
+        msg2.cs_take    = 0;
+        msg2.cs_release = 1;
+        msg2.next       = RT_NULL;
+
+        /* send the command to read the ID using rt_spi_send_then_recv() */
+        rt_spi_send_then_recv(spi_device, &send_to_flash_id, 1, recv_from_falsh_id1, 5);
+        rt_kprintf("use rt_spi_send_then_recv() read flash ID is:0x%x 0x%x 0x%x 0x%x 0x%x\n", recv_from_falsh_id1[0], recv_from_falsh_id1[1], recv_from_falsh_id1[2], recv_from_falsh_id1[3], recv_from_falsh_id1[4]);
+
+        /* send the command to read the ID using rt_spi_transfer_message() */
+        rt_spi_transfer_message(spi_device, &msg1);
+        rt_kprintf("use rt_spi_transfer_message() read flash ID is:0x%x 0x%x 0x%x 0x%x 0x%x\n", recv_from_falsh_id2[0], recv_from_falsh_id2[1], recv_from_falsh_id2[2], recv_from_falsh_id2[3], recv_from_falsh_id2[4]);
+    }
+}
+MSH_CMD_EXPORT(fspim_test_sample, "fspim test sample");
+#endif
diff --git a/bsp/phytium/libraries/drivers/drv_spi.h b/bsp/phytium/libraries/drivers/drv_spi.h
new file mode 100644
index 00000000000..be5a6aab7bd
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_spi.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-11-10  liqiaozhong  first commit
+ * 2023-03-08  liqiaozhong  support 4 spis and qspi working together
+ */
+#ifndef __DRV_SPI_H__
+#define __DRV_SPI_H__
+
+#include <rtthread.h>
+
+struct drv_spi
+{
+    u32 spi_id;
+    FSpim spim_instance;
+    struct rt_spi_device device;
+};
+
+
+#endif
+
+
diff --git a/bsp/phytium/libraries/drivers/drv_usart.c b/bsp/phytium/libraries/drivers/drv_usart.c
index 788456040ac..7601346b5f4 100644
--- a/bsp/phytium/libraries/drivers/drv_usart.c
+++ b/bsp/phytium/libraries/drivers/drv_usart.c
@@ -8,10 +8,13 @@
  * Change Logs:
  * Date        Author       Notes
  * 2022-10-26  huanghe      first commit
- *
+ * 2023-04-27  huanghe      support RT-Smart
  */
 
 #include "board.h"
+
+#include <mmu.h>
+
 #include "drv_usart.h"
 #include "interrupt.h"
 #include "fpl011.h"
@@ -42,6 +45,10 @@ static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_co
     uart_hw = uart->handle;
     config = *(const FPl011Config *)FPl011LookupConfig(uart->config.uart_instance);
 
+#ifdef RT_USING_SMART
+    config.base_address = (uintptr)rt_ioremap((void*)config.base_address, 0x1000);
+#endif
+
     RT_ASSERT(FPl011CfgInitialize(uart_hw, &config) == FT_SUCCESS);
     FPl011SetHandler(uart_hw, Ft_Os_Uart_Callback, serial);
 
@@ -129,13 +136,13 @@ static int uart_putc(struct rt_serial_device *serial, char c)
     return 1;
 }
 
-u8 FPl011RecvByteNoBlocking(u32 addr)
+u32 FPl011RecvByteNoBlocking(uintptr addr)
 {
     u32 recieved_byte;
 
-    while (FUART_ISRECEIVEDATA(addr))
+    while (FUART_RECEIVEDATAEMPTY(addr))
     {
-        return 0xff;
+        return 0xffff;
     }
     recieved_byte = FUART_READREG32(addr, FPL011DR_OFFSET);
     return recieved_byte;
@@ -152,14 +159,13 @@ static int uart_getc(struct rt_serial_device *serial)
     uart_ptr = uart->handle;
 
     ch = FPl011RecvByteNoBlocking(uart_ptr->config.base_address);
-    if (ch == 0xff)
+    if (ch == 0xffff)
     {
         ch = -1;
-        rt_kprintf("") ;
     }
     else
     {
-        //
+        ch &= 0xff;
     }
 
     return ch;
@@ -176,6 +182,7 @@ static const struct rt_uart_ops _uart_ops =
 
 #define RT_USING_UART0
 #define RT_USING_UART1
+#define RT_USING_UART2
 
 
 #ifdef RT_USING_UART0
@@ -188,6 +195,11 @@ static const struct rt_uart_ops _uart_ops =
     static struct drv_usart _RtUart1;
 #endif
 
+#ifdef RT_USING_UART2
+    static FPl011 Ft_Uart2;
+    static struct drv_usart _RtUart2;
+#endif
+
 int rt_hw_uart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
@@ -196,7 +208,6 @@ int rt_hw_uart_init(void)
     config.bufsz = RT_SERIAL_RB_BUFSZ;
     _RtUart0.serial.ops = &_uart_ops;
     _RtUart0.serial.config = config;
-    // Ft_Uart0.config.instance_id = FUART0_ID;
 
     _RtUart0.handle = &Ft_Uart0;
     _RtUart0.config.uart_instance = FUART0_ID;
@@ -213,7 +224,6 @@ int rt_hw_uart_init(void)
     config.bufsz = RT_SERIAL_RB_BUFSZ;
     _RtUart1.serial.ops = &_uart_ops;
     _RtUart1.serial.config = config;
-    // Ft_Uart1.config.instance_id = FUART1_ID;
     _RtUart1.handle = &Ft_Uart1;
 
     _RtUart1.config.uart_instance = FUART1_ID;
@@ -226,6 +236,24 @@ int rt_hw_uart_init(void)
                           &_RtUart1);
 #endif
 
+
+#ifdef RT_USING_UART2
+    config.bufsz = RT_SERIAL_RB_BUFSZ;
+    _RtUart2.serial.ops = &_uart_ops;
+    _RtUart2.serial.config = config;
+    _RtUart2.handle = &Ft_Uart2;
+
+    _RtUart2.config.uart_instance = FUART2_ID;
+    _RtUart2.config.isr_priority = 0xd0;
+    _RtUart2.config.isr_event_mask = (RTOS_UART_ISR_OEIM_MASK | RTOS_UART_ISR_BEIM_MASK | RTOS_UART_ISR_PEIM_MASK | RTOS_UART_ISR_FEIM_MASK | RTOS_UART_ISR_RTIM_MASK | RTOS_UART_ISR_RXIM_MASK);
+    _RtUart2.config.uart_baudrate = 115200;
+
+    rt_hw_serial_register(&_RtUart2.serial, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          &_RtUart2);
+#endif
+
+
     return 0;
 }
 INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/phytium/libraries/drivers/drv_usart.h b/bsp/phytium/libraries/drivers/drv_usart.h
index f82b3dc4d3d..ed7e532c8cc 100644
--- a/bsp/phytium/libraries/drivers/drv_usart.h
+++ b/bsp/phytium/libraries/drivers/drv_usart.h
@@ -8,7 +8,7 @@
  * Change Logs:
  * Date        Author       Notes
  * 2022-10-26  huanghe      first commit
- *
+ * 2023-04-27  huanghe      support RT-Smart
  */
 
 #ifndef __DRV_USART_H__
diff --git a/bsp/phytium/libraries/drivers/drv_xmac.c b/bsp/phytium/libraries/drivers/drv_xmac.c
new file mode 100644
index 00000000000..61f5dbfb400
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_xmac.c
@@ -0,0 +1,22 @@
+/*
+ * @Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * @FilePath: drv_xmac.c
+ * @Date: 2023-04-19 15:19:29
+ * @LastEditTime: 2023-04-19 15:19:29
+ * @Description:  This file is for
+ *
+ * @Modify History:
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
diff --git a/bsp/phytium/libraries/drivers/drv_xmac.h b/bsp/phytium/libraries/drivers/drv_xmac.h
new file mode 100644
index 00000000000..c935747e241
--- /dev/null
+++ b/bsp/phytium/libraries/drivers/drv_xmac.h
@@ -0,0 +1,22 @@
+/*
+ * @Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * @FilePath: drv_xmac.h
+ * @Date: 2023-04-19 15:19:39
+ * @LastEditTime: 2023-04-19 15:19:40
+ * @Description:  This file is for
+ *
+ * @Modify History:
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
diff --git a/bsp/phytium/libraries/examples/spi_sfud_sample.c b/bsp/phytium/libraries/examples/spi_sfud_sample.c
new file mode 100644
index 00000000000..ed9d0423ac3
--- /dev/null
+++ b/bsp/phytium/libraries/examples/spi_sfud_sample.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Email: opensource_embedded@phytium.com.cn
+ *
+ * Change Logs:
+ * Date        Author       Notes
+ * 2022-11-20  liqiaozhong  first commit
+ * 2022-03-08  liqiaozhong  add format function and mount table
+ */
+#include <rtthread.h>
+#include <string.h>
+
+#if defined (RT_USING_SFUD) && defined(RT_USING_DFS)
+
+#include <dfs_fs.h>
+#include <dfs_file.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <sys/stat.h>
+#include <sys/statfs.h>
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+
+#include "fdebug.h"
+#include "fparameters_comm.h"
+
+#include "fspim.h"
+/************************** Variable Definitions *****************************/
+sfud_flash_t spim_flash = RT_NULL;
+const struct dfs_mount_tbl mount_table[] =
+{
+    { "flash2", "/", "elm", 0, RT_NULL },
+    {0},
+};
+/***************** Macros (Inline Fungoctions) Definitions *********************/
+#define FSPIM_DEBUG_TAG "SPIM"
+#define FSPIM_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_WARN(format, ...)   FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_INFO(format, ...)    FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSPIM_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/*******************************Api Functions*********************************/
+static int spi_flash_sfud_init(void)
+{
+    if (RT_NULL == rt_sfud_flash_probe("flash2", "spi02"))
+    {
+        rt_kprintf("rt_sfud_flash_probe failed\n");
+        return RT_ERROR;
+    }
+    spim_flash = rt_sfud_flash_find_by_dev_name("flash2");
+    if (RT_NULL == spim_flash)
+    {
+        rt_kprintf("Flash init failed -> can't find flash2 device!\n");
+        return RT_ERROR;
+    }
+    rt_kprintf("Spi flash device flash2 init\n");
+    rt_kprintf("Flash device: flash2 info\nmf_id: 0x%x\ntype_id: 0x%x\ncapacity_id: 0x%x\nerase granularity: %lu\n",
+    spim_flash->chip.mf_id,
+    spim_flash->chip.type_id,
+    spim_flash->chip.capacity_id,
+    spim_flash->chip.erase_gran);
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(spi_flash_sfud_init);
+
+/* format the flash with elm environment */
+static int flash_format_operation(void)
+{
+    int result = RT_EOK;
+    result = dfs_mkfs("elm", "flash2");
+    return result;
+}
+INIT_ENV_EXPORT(flash_format_operation);
+
+#endif /* RT_USING_SFUD || RT_USING_DFS */
diff --git a/bsp/phytium/libraries/standalone/README.md b/bsp/phytium/libraries/standalone/README.md
index a9dbcff01ab..8011132ab35 100644
--- a/bsp/phytium/libraries/standalone/README.md
+++ b/bsp/phytium/libraries/standalone/README.md
@@ -1,17 +1,23 @@
 # Phytium-Standalone-SDK
 
-**v0.3.1** [ReleaseNote](./doc/ChangeLog.md)
+**v1.0.0** [ReleaseNote](./doc/ChangeLog.md)
 
 ## 1. 项目概要
 
-### 1.1 基本介绍
+### 1.1 仓库介绍
+
+本项目代码仓库整体共分为两个分支：
+master 分支：开发分支，用于保存最新的协作开发代码以及bug修复后的代码。其只要求保障新功能基本正确并且能够满足基本的使用需求，并没有经过系统性和复杂条件下的测试。
+release 分支：发布分支，包含核心启动代码、芯片外设驱动、用户使用例程和构建的脚本工具。用于保存经过系统性测试的代码并对外发布版本，默认下载此分支的代码。
+
+### 1.2 基本介绍
 
 本项目发布了 Phytium 系列 CPU 的 嵌入式软件开发工具包，包括板级支持包、第三方开源中间件、交叉编译构建工具、及其 Baremetal 参考例程，在支持多平台裸机应用开发的基础上，能够为多种RTOS提供外设驱动和配置构建工具。
 
 ![LetterShell](./doc/fig/letter_shell.png)
 
 
-### 1.2 系统架构
+### 1.3 系统架构
 
 
 本项目的整体设计如下所示，自下而上可以分为平台层、组件层、框架层和应用层。
@@ -26,7 +32,7 @@
 
 - 应用层（Application）提供了应用开发模板和例程，帮助开发者迅速熟悉SDK的使用，进行不同类型的应用程序开发
 
-### 1.3. 源代码结构
+### 1.4 源代码结构
 
 ```
 .
@@ -105,9 +111,8 @@ FT-2000/4 是一款面向桌面应用的高性能通用 4 核处理器。每 2 
 - 集成 34 Lane PCIE3.0 接口：2 个 X16（每个可拆分成 2 个 X8），2 个 X1
 - 集成 2 个 GMAC，RGMII 接口，支持 10/100/1000 自适应
 - 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
-- 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
-- 集成 SM2、SM3、SM4 模块
-- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通 用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
+- 集成 加密计算单元
+- 集成 4 个 UART，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通 用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
 - 集成温度传感器
 
 ### 3.2 D2000
@@ -123,39 +128,55 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
 - 集成 1 个 SD 卡控制器，兼容 SD 2.0 规范
 - 集成 1 个 HDAudio，支持音频输出，可同时支持最多 4 个 Codec
 - 集成 SM2、SM3、SM4、SM9 模块
-- 集成 4 个 UART，1 个 LPC，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
+- 集成 4 个 UART，32 个 GPIO，4 个 I2C，1 个 QSPI，2 个通用 SPI，2 个 WDT，16 个外部中断（和 GPIO 共用 IO）
 - 集成 2 个温度传感器
 
+### 3.3 E2000Q
+
+- E2000Q 集成2个FTC664核和2个FTC310核。主要技术特征如下：
+
+- 兼容ARM v8 64 位指令系统，兼容32 位指令
+- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
+- 支持单精度、双精度浮点运算指令
+- 两个 FTC664 核各包含 1MB 私有 L2 Cache,由两个 FTC310 核组成的Cluster 内含 256KB 共享的 L2 Cache
+- 集成1个DDR4 通道
+- 集成6Lane PCIE3.0 接口（X4+2*X1 、X2+4*X2、6*X1）
+- 集成4个1000M以太网控制器，支持2路SGMII接口和2路SGMII/RGMII接口
+- 集成3路USB2.0(OTG)和2路USB3.0(兼容 2.0)
+- 集成2路SATA3.0模块
+- 2路 DisplayPort1.4 接口
+- 集成常用低速接口：WDT、QSPI、PWM、Nand、SD/SDIO/eMMC 、SPI_M、UART、I2C、I2S、MIO、CAN-FD、GPIO、LocalBus、Timer
 
-### 3.3 E2000D
+### 3.4 E2000D
 
-- E2000D 1个cluster有2个cpu，共两核。主要技术特征如下：
+- E2000D 集成 2 个 FTC310 核。主要技术特征如下：
 
 - 兼容ARM v8 64 位指令系统，兼容32 位指令
+- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
 - 支持单精度、双精度浮点运算指令
-- L1有32KB，L2有256KB
-- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
+- L2 Cache 有256KB
+- 集成1个DDR4 通道
 - 集成4 Lane PCIE3.0 接口（4X1）
-- 集成网络接口4x1000M SGMII，1路支持RGMII/RMII，支持1路TSN
-- 集成2个USB2.0(OTG)接口
-- 集成1个HDAudio，支持音频输出;2路DP显示接口
+- 集成4个1000M以太网控制器，支持 2 路 SGMII 接口和 2 路 SGMII/RGMII 接口
+- 集成3路USB2.0(OTG)和2路USB3.0(兼容 2.0)
 - 集成2路SATA3.0模块
-- 集成常用低速接口：WDT，DMAC，QSPI，PWM，Nand，SD/SDIO/eMMC ，SPI_M，UART，I2C，MIO，CAN， LPC_M_S，GPIO，LBC，Timer
+- 2路 DisplayPort1.4 接口
+- 集成常用低速接口：WDT，QSPI，PWM，Nand，SD/SDIO/eMMC ，SPI_M，UART，I2C，MIO，CAN-FD，GPIO，LocalBus，Timer
 
-### 3.4 E2000S
+### 3.5 E2000S
 
-- E2000S 1个cluster有1个cpu，单核结构。主要技术特征如下：
+- E2000S 集成 1 个 FTC310 核，单核结构。主要技术特征如下：
 
 - 兼容ARM v8 64 位指令系统，兼容32 位指令
+- 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA
 - 支持单精度、双精度浮点运算指令
-- L1有32KB，L2有256KB
-- 集成1个DDR4 通道，可对DDR 存储数据进行实时加密
+- L2 Cache 有256KB
+- 集成1个DDR4 通道
 - 集成2 Lane PCIE3.0 接口（2X1）
-- 集成网络接口2x1000M SGMII/RGMII/RMII，支持2路NCSI
-- 集成2个USB2.0(OTG)接口
-- 集成1个HDAudio，支持音频输出;2路DP显示接口
-- 集成JPEG Encoder模块
-- 集成常用低速接口：WDT，DMAC，PWM，QSPI，SD/SDIO/eMMC，SPI_M，UART，I2C，MIO，I3C，PMBUS， LPC_M_S，GPIO，oneWire，Timer
+- 集成3个1000M以太网控制器，支持1路SGMII接口和2路RGMII/RMII接口
+- 集成1路USB2.0(Device)和2路USB2.0(OTG)
+- 2路 DisplayPort1.4 接口
+- 集成常用低速接口：WDT、DMAC、PWM、QSPI、SD/SDIO/eMMC、SPI Master、UART、I2C、MIO、I3C、PMBUS、GPIO、SGPIO、One-Wire、Timer、One-Wire
 
 
 ## 4 外设驱动支持情况
@@ -200,6 +221,7 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
 | OpenAMP                        | FT2000/4<br>D2000<br>E2000 |                             | openamp                   |
 | LittleFS-2.4.2                 |                            | FT2000/4<br>E2000<br>D2000  | littlefs-2.4.2            |
 | SPIFFS-0.3.7                   | FT2000/4<br>D2000<br>E2000 |                             | spiffs-0.3.7              |
+| freemodbus-v1.6                | E2000                      |                             | protocols/fmodbus_test    |
 
 ---
 
@@ -241,6 +263,8 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个
 
 #### 5.1.17 [FSDIO](./doc/reference/driver/fsdio.md)
 
+#### 5.1.18 [FMEDIA](doc/reference/driver/fmedia.md)
+
 ### 5.2 MEMORY
 #### 5.2.1 [FMEMORY_POOL](./doc/reference/sdk/fmemory_pool.md)
 
@@ -266,6 +290,13 @@ wangxiaodong1030@phytium.com.cn
 
 liushengming1118@phytium.com.cn
 
+wangzongqiang1322@phytium.com.cn
+
+liqiaozhong1404@phytium.com.cn
+
+liuzhihong1235@phytium.com.cn
+
+zhangyan1491@phytium.com.cn
 
 ---
 
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/faarch32.h b/bsp/phytium/libraries/standalone/arch/armv8/aarch32/faarch32.h
deleted file mode 100644
index 0a7778fad21..00000000000
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/faarch32.h
+++ /dev/null
@@ -1,416 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: faarch32.h
- * Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:28:37
- * Description:  This files is for
- *
- * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
- * 1.0   Huanghe     2021/7/3     init
- * 1.1   Wangxiaodong  2021/9/24    modify sys_icc_bpr_set and sys_icc_bpr_get
- */
-
-#ifndef BSP_AARCH32_ASM_H
-#define BSP_AARCH32_ASM_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-#include "ftypes.h"
-
-#define __ASM __asm
-#define __STATIC_INLINE static inline
-#define __STRINGIFY(x) #x
-/* C语言实现MCR指令 */
-#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2)                                                                                                   \
-    __ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", "                                                                           \
-                                                                            "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
-                   :                                                                                                                                       \
-                   : "r"(src)                                                                                                                              \
-                   : "memory");
-
-/* C语言实现MRC指令 */
-#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2)                                                                                                                \
-    (                                                                                                                                                              \
-        {                                                                                                                                                          \
-            u32 __dst;                                                                                                                                             \
-            __ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", "                                                                           \
-                                                                                    "%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \
-                           : "=r"(__dst)::"memory");                                                                                                               \
-            __dst;                                                                                                                                                 \
-        })
-
-/* C语言实现MRRC指令 */
-#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) (                                              \
-    {                                                                                              \
-        __asm__ __volatile__(                                                                      \
-            "MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", "                         \
-                                                                      "%0,%1," __STRINGIFY(c##CRm) \
-            : "=r"(dst_1), "=r"(dst_2));                                                           \
-    })
-
-/**
- * @name: aarch32_cntp_ctl_get
- * @msg:  Read the register that holds the timer value for the EL1 physical timer.
- * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
- */
-__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void)
-{
-    /* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m)  1(opcode2) */
-    return __MRC(15, 0, 14, 2, 1);
-}
-
-/**
- * @name: aarch32_cntp_tlb_get
- * @msg:
- * @return {*}
- * @param {__STATIC_INLINE u32} aarch32_cntp_ctl_get
- */
-__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_tlb_get(void)
-{
-    return __MRC(15, 0, 0, 2, 0);
-}
-
-/**
- * @name: aarch32_cntp_ctl_set
- * @msg:  Read the register that holds the timer value for the EL1 physical timer.
- * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
- */
-__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal)
-{
-    /* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m)  1(opcode2) */
-    __MCR(15, 0, regVal, 14, 2, 1);
-}
-
-/**
- * @name: arm_aarch32_cntfrq_get
- * @msg:  This register is provided so that software can discover the frequency of the system counter.
- * @return {__STATIC_INLINEu32}:  frequency of the system counter
- */
-__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void)
-{
-    return __MRC(15, 0, 14, 0, 0);
-}
-
-/**
- * @name: aarch32_cntpct_get
- * @msg: get the 64-bit physical count value
- * @return {*}
- * @param {__STATIC_INLINE u64} aarch32_cntpct_get
- */
-__attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get()
-{
-    u64 cnt = 0;
-    u32 cnt_low = 0, cnt_high = 0;
-    __MRRC(15, 0, cnt_low, cnt_high, 14);
-    cnt = (u64)cnt_high << 32 | cnt_low;
-    return cnt;
-}
-
-/**
- * @name: aarch32_cntp_tval_set
- * @msg:  write the register that control register for the EL1 physical timer.
- * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
- */
-__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 2, 0);
-}
-
-/**
- * @name: aarch32_sctrl_get
- * @msg: read the register that control system
- */
-__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get()
-{
-    return __MRC(15, 0, 1, 0, 0);
-}
-
-/**
-     * @name: aarch32_sctrl_set
-     * @msg: read the register that control system
-     */
-#define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */
-__attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal)
-{
-    __MCR(15, 0, RegVal, 1, 0, 0);
-}
-
-/**********************************************/
-
-__attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void)
-{
-    return __MRC(15, 0, 12, 0, 0);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar)
-{
-    __MCR(15, 0, vbar, 12, 0, 0);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 6);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void)
-{
-    return __MRC(15, 0, 12, 12, 6);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 7);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void)
-{
-    return __MRC(15, 0, 12, 12, 7);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 4);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void)
-{
-    return __MRC(15, 0, 12, 12, 4);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void)
-{
-    return __MRC(15, 0, 12, 8, 2);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 3);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void)
-{
-    return __MRC(15, 0, 12, 12, 3);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void)
-{
-    return __MRC(15, 0, 12, 12, 2);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 8, 1);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 1);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value)
-{
-    __MCR(15, 0, value, 4, 6, 0);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void)
-{
-    return __MRC(15, 0, 4, 6, 0);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void)
-{
-    return __MRC(15, 0, 12, 12, 0);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value)
-{
-    __MCR(15, 0, value, 12, 12, 5);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void)
-{
-    return __MRC(15, 0, 12, 12, 5);
-}
-
-__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void)
-{
-    return __MRC(15, 0, 12, 11, 3);
-}
-
-/*   Generic Timer registers  */
-/**
-     * @name: arm_aarch32_cntfrq_get
-     * @msg:  This register is provided so that software can discover the frequency of the system counter.
-     * @return {__STATIC_INLINEu32}:  frequency of the system counter
-     */
-__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void)
-{
-    return __MRC(15, 0, 14, 0, 0);
-}
-
-/* arm_aarch32_cnttimer_set */
-__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 2, 2);
-}
-
-/**
-     * @name: arm_aarch32_cnthv_tval_get
-     * @msg:  Provides AArch32 access to the timer value for the EL2 virtual timer.
-     * @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt.
-     */
-__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void)
-{
-    return __MRC(15, 0, 14, 3, 0);
-}
-
-/**
-     * @name: arm_aarch32_cnthv_ctl_set
-     * @msg:  Provides AArch32 access to the control register for the EL2 virtual timer.
-     * @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
-     *                  IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit.   1 Timer interrupt is masked by the IMASK bit.
-     *                  ISTATUS, bit [2]:  0 Timer condition is not met. 1 Timer condition is met. rea-only
-     */
-__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 3, 1);
-}
-
-/**
-     * @name: arm_aarch32_cnthv_ctl_get
-     * @msg:  Provides AArch32 access to the control register for the EL2 virtual timer.
-     * @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled.
-     *                  IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit.   1 Timer interrupt is masked by the IMASK bit.
-     *                  ISTATUS, bit [2]:  0 Timer condition is not met. 1 Timer condition is met. read-only
-     */
-__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void)
-{
-    return __MRC(15, 0, 14, 3, 1);
-}
-
-/**
-     * @name: arm_aarch32_cnthv_tval_set
-     * @msg:  Provides AArch32 access to the timer value for the EL2 virtual timer.
-     * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer.
-     */
-__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 3, 0);
-}
-
-/**
-     * @name: arm_aarch32_cntvct_get
-     * @msg:  Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF.
-     * @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value.
-     */
-__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void)
-{
-    /* "r0" --- low,
-        "r1" --- hi
-      */
-    u32 low;
-    u32 hi;
-    __asm__ volatile(
-        ".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */
-        "mov %0, r0 \n"
-        "mov %1, r1 \n"
-        : "=&r"(low), "=&r"(hi));
-    return (((u64)hi) << 32) | low;
-}
-
-/* physical */
-
-/**
-     * @name: arm_aarch32_cntp_tval_get
-     * @msg:  Read the register that holds the timer value for the EL1 physical timer.
-     * @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
-     */
-__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void)
-{
-    return __MRC(15, 0, 14, 2, 0);
-}
-
-/**
-     * @name: arm_aarch32_cntp_tval_set
-     * @msg:  write the register that control register for the EL1 physical timer.
-     * @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer.
-     */
-__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 2, 0);
-}
-
-/**
-     * @name: arm_aarch32_cntp_ctl_set
-     * @msg:  write the register that control register for the EL1 physical timer.
-     * @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
-     */
-__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue)
-{
-    __MCR(15, 0, RegValue, 14, 2, 1);
-}
-
-/**
-     * @name: arm_aarch32_cntp_ctl_get
-     * @msg:  Read the register that control register for the EL1 physical timer.
-     * @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer.
-     */
-__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void)
-{
-    return __MRC(15, 0, 14, 2, 1);
-}
-
-/**
-     * @name: arm_aarch32_cntpct_get
-     * @msg:  Read the register that holds the 64-bit physical count value.
-     * @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value.
-     */
-__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void)
-{
-    /* "r0" --- low,
-        "r1" --- hi
-      */
-    u32 low;
-    u32 hi;
-    __asm__ volatile(
-
-        ".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */
-        "mov %0, r0 \n"
-        "mov %1, r1 \n"
-        : "=&r"(low), "=&r"(hi));
-    return (((u64)hi) << 32) | low;
-}
-
-#define INTERRUPT_DISABLE()         \
-    __asm volatile("CPSID i" ::     \
-                       : "memory"); \
-    __asm volatile("DSB");          \
-    __asm volatile("ISB");
-
-#define INTERRUPT_ENABLE()          \
-    __asm volatile("CPSIE i" ::     \
-                       : "memory"); \
-    __asm volatile("DSB");          \
-    __asm volatile("ISB");
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // !
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.c b/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.c
deleted file mode 100644
index 082a74eb4ea..00000000000
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
- * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
- * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: generic_timer.c
- * Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:30:07
- * Description:  This files is for
- *
- * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
- */
-
-
-#include "fparameters.h"
-#include "fgeneric_timer.h"
-#include "faarch32.h"
-#include "sdkconfig.h"
-
-#ifndef SDK_CONFIG_H__
-    #warning "Please include sdkconfig.h"
-#endif
-
-#ifdef CONFIG_USE_SYS_TICK
-    #include "fassert.h"
-    #include "finterrupt.h"
-
-    static volatile u32 genericTick;
-    static GenericTimerTickHandler usr_tick_handler = NULL;
-#endif
-
-#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0)
-#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1)
-
-void GenericTimerStart(void)
-{
-    u32 ctrl = aarch32_cntp_ctl_get();
-
-    if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
-    {
-        ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK;
-        aarch32_cntp_ctl_set(ctrl);
-    }
-}
-
-void GenericTimerStop(void)
-{
-    u32 ctrl = aarch32_cntp_ctl_get();
-    if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK))
-    {
-        ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK;
-        aarch32_cntp_ctl_set(ctrl);
-    }
-}
-
-void GenericTimerInterruptEnable(void)
-{
-    u32 ctrl = aarch32_cntp_ctl_get();
-    if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)
-    {
-        ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK;
-        aarch32_cntp_ctl_set(ctrl);
-    }
-}
-
-void GenericTimerInterruptDisable(void)
-{
-    u64 ctrl = aarch32_cntp_ctl_get();
-    if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK))
-    {
-        ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK;
-        aarch32_cntp_ctl_set(ctrl);
-    }
-}
-
-u32 GenericTimerFrequecy(void)
-{
-    u32 rate = aarch32_cntfrq_get();
-    return (rate != 0) ? rate : 1000000;
-}
-
-u64 GenericTimerRead(void)
-{
-    return aarch32_cntpct_get();
-}
-
-void GenericTimerCompare(u32 interval)
-{
-    aarch32_cntp_tval_set(interval);
-}
-
-#ifdef CONFIG_USE_SYS_TICK
-static void GenericTimerClearTickIntr(u32 tickRateHz)
-{
-    GenericTimerCompare(GenericTimerFrequecy() / tickRateHz);
-}
-
-static void GenericTimerTickIntrHandler(s32 vector, void *param)
-{
-    u32 tickRateHz = (u32)param;
-    (void)vector;
-    genericTick++;                         /* tick */
-    GenericTimerClearTickIntr(tickRateHz); /* clear tick intrrupt */
-
-    if (usr_tick_handler) /* execute user handler */
-        usr_tick_handler();
-}
-#endif
-
-void GenericTimerSetupSystick(u32 tickRateHz, GenericTimerTickHandler tickHandler, u32 intrPrority)
-{
-#ifdef CONFIG_USE_SYS_TICK
-    u32 cntFrq;
-
-    /* disable timer and get system frequency */
-    GenericTimerStop();
-    cntFrq = GenericTimerFrequecy();
-
-    /* set tick rate */
-    GenericTimerCompare(cntFrq / tickRateHz);
-    GenericTimerInterruptEnable();
-
-    /* set generic timer intrrupt */
-    InterruptSetPriority(GENERIC_TIMER_NS_IRQ_NUM, intrPrority);
-
-    /* install tick handler */
-    usr_tick_handler = tickHandler;
-    InterruptInstall(GENERIC_TIMER_NS_IRQ_NUM, GenericTimerTickIntrHandler,
-                     (void *)tickRateHz, "GenericTimerTick");
-
-    /* enable intrrupt */
-    InterruptUmask(GENERIC_TIMER_NS_IRQ_NUM);
-    GenericTimerStart();
-#endif
-}
-
-u32 GenericGetTick(void)
-{
-#ifdef CONFIG_USE_SYS_TICK
-    return genericTick;
-#else
-    return 0xffU;
-#endif
-}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/Kconfig b/bsp/phytium/libraries/standalone/board/Kconfig
index f0a7ec4b704..5169f3e1e23 100644
--- a/bsp/phytium/libraries/standalone/board/Kconfig
+++ b/bsp/phytium/libraries/standalone/board/Kconfig
@@ -11,19 +11,22 @@ menu "Board Configuration"
 
         config TARGET_D2000
             bool "D2000"
-
+            
         config TARGET_E2000Q
             bool "E2000Q"
             select TARGET_E2000
-
+        
         config TARGET_E2000D
             bool "E2000D"
             select TARGET_E2000
-
+        
         config TARGET_E2000S
             bool "E2000S"
             select TARGET_E2000
 
+#       config TARGET_TARDIGRADE
+#           bool "TARDIGRADE"
+                   
     endchoice # BUILD_TARGET_CHIP_TYPE
 
     # an invisible config to define common code of E2000 Q/D/S
@@ -43,7 +46,7 @@ menu "Board Configuration"
     config DEFAULT_DEBUG_PRINT_UART2
         bool "Use uart2"
     endchoice # DEBUG_PRINT_UART
-
+    
 
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/board/common/fcpu_asm.S b/bsp/phytium/libraries/standalone/board/common/fcpu_asm.S
index 530186fecfd..c536bef925b 100644
--- a/bsp/phytium/libraries/standalone/board/common/fcpu_asm.S
+++ b/bsp/phytium/libraries/standalone/board/common/fcpu_asm.S
@@ -14,7 +14,7 @@
  * FilePath: _cpu_asm.S
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-17 17:57:55
- * Description:  This files is for 
+ * Description:  This file is for 
  * 
  * Modify History: 
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/board/common/fcpu_info.c b/bsp/phytium/libraries/standalone/board/common/fcpu_info.c
index 7e711e20187..9b7c718acea 100644
--- a/bsp/phytium/libraries/standalone/board/common/fcpu_info.c
+++ b/bsp/phytium/libraries/standalone/board/common/fcpu_info.c
@@ -34,48 +34,48 @@ FError GetCpuId(u32 *cpu_id_p)
     switch (affinity & 0xfff)
     {
 #ifdef CORE0_AFF
-    case CORE0_AFF:
-        *cpu_id_p = 0 ;
-        break;
+        case CORE0_AFF:
+            *cpu_id_p = 0 ;
+            break;
 #endif
 #ifdef CORE1_AFF
-    case CORE1_AFF:
-        *cpu_id_p = 1 ;
-        break;
+        case CORE1_AFF:
+            *cpu_id_p = 1 ;
+            break;
 #endif
 #ifdef CORE2_AFF
-    case CORE2_AFF:
-        *cpu_id_p = 2;
-        break;
+        case CORE2_AFF:
+            *cpu_id_p = 2;
+            break;
 #endif
 #ifdef CORE3_AFF
-    case CORE3_AFF:
-        *cpu_id_p = 3 ;
-        break;
+        case CORE3_AFF:
+            *cpu_id_p = 3 ;
+            break;
 #endif
 #ifdef CORE4_AFF
-    case CORE4_AFF:
-        *cpu_id_p = 4 ;
-        break;
+        case CORE4_AFF:
+            *cpu_id_p = 4 ;
+            break;
 #endif
 #ifdef CORE5_AFF
-    case CORE5_AFF:
-        *cpu_id_p = 5 ;
-        break;
+        case CORE5_AFF:
+            *cpu_id_p = 5 ;
+            break;
 #endif
 #ifdef CORE6_AFF
-    case CORE6_AFF:
-        *cpu_id_p = 6 ;
-        break;
+        case CORE6_AFF:
+            *cpu_id_p = 6 ;
+            break;
 #endif
 #ifdef CORE7_AFF
-    case CORE7_AFF:
-        *cpu_id_p = 7 ;
-        break;
+        case CORE7_AFF:
+            *cpu_id_p = 7 ;
+            break;
 #endif
-    default:
-        ret = ERR_GENERAL ;
-        break;
+        default:
+            ret = ERR_GENERAL ;
+            break;
     }
     return ret;
 }
@@ -95,48 +95,48 @@ FError GetCpuAffinityByMask(u32 cpu_id_mask, u64 *affinity_level_p)
     switch (cpu_id_mask)
     {
 #ifdef CORE0_AFF
-    case (1<<0):
-        *affinity_level_p = CORE0_AFF;
-        break ;
+        case (1<<0):
+            *affinity_level_p = CORE0_AFF;
+            break ;
 #endif
 #ifdef CORE1_AFF
-    case (1<<1):
-        *affinity_level_p = CORE1_AFF;
-        break ;
+        case (1<<1):
+            *affinity_level_p = CORE1_AFF;
+            break ;
 #endif
 #ifdef CORE2_AFF
-    case (1<<2):
-        *affinity_level_p = CORE2_AFF;
-        break ;
+        case (1<<2):
+            *affinity_level_p = CORE2_AFF;
+            break ;
 #endif
 #ifdef CORE3_AFF
-    case (1<<3):
-        *affinity_level_p = CORE3_AFF;
-        break ;
+        case (1<<3):
+            *affinity_level_p = CORE3_AFF;
+            break ;
 #endif
 #ifdef CORE4_AFF
-    case (1<<4):
-        *affinity_level_p = CORE4_AFF;
-        break ;
+        case (1<<4):
+            *affinity_level_p = CORE4_AFF;
+            break ;
 #endif
 #ifdef CORE5_AFF
-    case (1<<5):
-        *affinity_level_p = CORE5_AFF;
-        break ;
+        case (1<<5):
+            *affinity_level_p = CORE5_AFF;
+            break ;
 #endif
 #ifdef CORE6_AFF
-    case (1<<6):
-        *affinity_level_p = CORE6_AFF;
-        break ;
+        case (1<<6):
+            *affinity_level_p = CORE6_AFF;
+            break ;
 #endif
 #ifdef CORE7_AFF
-    case (1<<7):
-        *affinity_level_p = CORE7_AFF;
-        break ;
+        case (1<<7):
+            *affinity_level_p = CORE7_AFF;
+            break ;
 #endif
-    default:
-        ret = ERR_GENERAL;
-        break;
+        default:
+            ret = ERR_GENERAL;
+            break;
     }
     return ret;
 }
@@ -157,48 +157,48 @@ FError GetCpuAffinity(u32 cpu_id, u64 *affinity_level_p)
     switch (cpu_id)
     {
 #ifdef CORE0_AFF
-    case (0):
-        *affinity_level_p = CORE0_AFF;
-        break ;
+        case (0):
+            *affinity_level_p = CORE0_AFF;
+            break ;
 #endif
 #ifdef CORE1_AFF
-    case (1):
-        *affinity_level_p = CORE1_AFF;
-        break ;
+        case (1):
+            *affinity_level_p = CORE1_AFF;
+            break ;
 #endif
 #ifdef CORE2_AFF
-    case (2):
-        *affinity_level_p = CORE2_AFF;
-        break ;
+        case (2):
+            *affinity_level_p = CORE2_AFF;
+            break ;
 #endif
 #ifdef CORE3_AFF
-    case (3):
-        *affinity_level_p = CORE3_AFF;
-        break ;
+        case (3):
+            *affinity_level_p = CORE3_AFF;
+            break ;
 #endif
 #ifdef CORE4_AFF
-    case (4):
-        *affinity_level_p = CORE4_AFF;
-        break ;
+        case (4):
+            *affinity_level_p = CORE4_AFF;
+            break ;
 #endif
 #ifdef CORE5_AFF
-    case (5):
-        *affinity_level_p = CORE5_AFF;
-        break ;
+        case (5):
+            *affinity_level_p = CORE5_AFF;
+            break ;
 #endif
 #ifdef CORE6_AFF
-    case (6):
-        *affinity_level_p = CORE6_AFF;
-        break ;
+        case (6):
+            *affinity_level_p = CORE6_AFF;
+            break ;
 #endif
 #ifdef CORE7_AFF
-    case (7):
-        *affinity_level_p = CORE7_AFF;
-        break ;
+        case (7):
+            *affinity_level_p = CORE7_AFF;
+            break ;
 #endif
-    default:
-        ret = ERR_GENERAL;
-        break;
+        default:
+            ret = ERR_GENERAL;
+            break;
     }
     return ret;
 }
@@ -217,48 +217,48 @@ FError UseAffinityGetCpuId(u64 affinity_level, u32 *cpu_id_p)
     switch (affinity_level)
     {
 #ifdef CORE0_AFF
-    case CORE0_AFF:
-        *cpu_id_p = 0;
-        break ;
+        case CORE0_AFF:
+            *cpu_id_p = 0;
+            break ;
 #endif
 #ifdef CORE1_AFF
-    case CORE1_AFF:
-        *cpu_id_p = 1;
-        break ;
+        case CORE1_AFF:
+            *cpu_id_p = 1;
+            break ;
 #endif
 #ifdef CORE2_AFF
-    case CORE2_AFF:
-        *cpu_id_p = 2;
-        break ;
+        case CORE2_AFF:
+            *cpu_id_p = 2;
+            break ;
 #endif
 #ifdef CORE3_AFF
-    case CORE3_AFF:
-        *cpu_id_p = 3;
-        break ;
+        case CORE3_AFF:
+            *cpu_id_p = 3;
+            break ;
 #endif
 #ifdef CORE4_AFF
-    case CORE4_AFF:
-        *cpu_id_p = 4;
-        break ;
+        case CORE4_AFF:
+            *cpu_id_p = 4;
+            break ;
 #endif
 #ifdef CORE5_AFF
-    case CORE5_AFF:
-        *cpu_id_p = 5;
-        break ;
+        case CORE5_AFF:
+            *cpu_id_p = 5;
+            break ;
 #endif
 #ifdef CORE6_AFF
-    case CORE6_AFF:
-        *cpu_id_p = 6;
-        break ;
+        case CORE6_AFF:
+            *cpu_id_p = 6;
+            break ;
 #endif
 #ifdef CORE7_AFF
-    case CORE7_AFF:
-        *cpu_id_p = 7;
-        break ;
+        case CORE7_AFF:
+            *cpu_id_p = 7;
+            break ;
 #endif
-    default:
-        ret = ERR_GENERAL;
-        break;
+        default:
+            ret = ERR_GENERAL;
+            break;
     }
     return ret;
 }
diff --git a/bsp/phytium/libraries/standalone/board/e2000/fearly_uart.c b/bsp/phytium/libraries/standalone/board/common/fearly_uart.c
similarity index 98%
rename from bsp/phytium/libraries/standalone/board/e2000/fearly_uart.c
rename to bsp/phytium/libraries/standalone/board/common/fearly_uart.c
index a330aa37b3a..7d114ceac91 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/fearly_uart.c
+++ b/bsp/phytium/libraries/standalone/board/common/fearly_uart.c
@@ -14,7 +14,7 @@
  * FilePath: early_uart.c
  * Date: 2022-02-11 13:33:28
  * LastEditTime: 2022-02-17 17:59:26
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/board/e2000/fearly_uart.h b/bsp/phytium/libraries/standalone/board/common/fearly_uart.h
similarity index 96%
rename from bsp/phytium/libraries/standalone/board/e2000/fearly_uart.h
rename to bsp/phytium/libraries/standalone/board/common/fearly_uart.h
index cbb47a898fc..d1568048671 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/fearly_uart.h
+++ b/bsp/phytium/libraries/standalone/board/common/fearly_uart.h
@@ -14,15 +14,15 @@
  * FilePath: fearly_uart.h
  * Date: 2022-02-11 13:33:28
  * LastEditTime: 2022-02-17 18:00:16
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
  * 1.0   rtos       2022/6/25    init commit
  */
-#ifndef  BOARD_E2000_EARLY_UART_H
-#define  BOARD_E2000_EARLY_UART_H
+#ifndef  BOARD_COMMON_EARLY_UART_H
+#define  BOARD_COMMON_EARLY_UART_H
 
 #ifdef __cplusplus
 extern "C"
diff --git a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c
new file mode 100644
index 00000000000..ae1ff0d3a2a
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fioctrl.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:29
+ * Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/2/22   init commit
+ */
+
+
+/***************************** Include Files *********************************/
+#include "fparameters.h"
+#include "fio.h"
+#include "fkernel.h"
+#include "fassert.h"
+#include "fdebug.h"
+
+#include "fioctrl.h"
+#include "fpinctrl.h"
+
+/************************** Constant Definitions *****************************/
+/* Bit[0] : 输入延迟功能使能  */
+#define FIOCTRL_DELAY_EN(delay_beg)                      BIT(delay_beg)
+#define FIOCTRL_INPUT_DELAY_OFF                          0
+
+/* Bit[3:1] : 输入延迟精调档位选择 */
+#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg)             GENMASK((delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg)     GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg)         SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
+
+/* Bit[6:4] : 输入延迟粗调档位选择 */
+#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg)               GENMASK((delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg)       GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg)           SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
+
+/* Bit[7] : 保留 */
+/* Bit[8] : 输出延迟功能使能 */
+
+/* Bit[11:9] : 输出延迟精调档位选择 */
+/* Bit [14:12] : 输出延迟粗调档位选择  */
+/* Bit [15] : 保留 */
+
+#define FIOCTRL_FUNC_BEG_OFF(reg_bit)   ((reg_bit) + 0)
+#define FIOCTRL_FUNC_END_OFF(reg_bit)   ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
+#define FIOCTRL_PULL_BEG_OFF(reg_bit)   ((reg_bit) + 2)
+#define FIOCTRL_PULL_END_OFF(reg_bit)   ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
+
+#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit)    ((reg_bit) + 0)
+#define FIOCTRL_DELAY_IN_END_OFF(reg_bit)    ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
+#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit)   ((reg_bit) + 8)
+#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit)   ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
+
+/* 芯片引脚控制寄存器的起止位置 */
+#define FIOCTRL_REG_OFFSET_MIN                           0x200
+#define FIOCTRL_REG_OFFSET_MAX                           0x22c
+
+/* 芯片引脚延时寄存器的起止位置 */
+#define FIOCTRL_DELAY_REG_OFFSET_MIN                     0x400
+#define FIOCTRL_DELAY_REG_OFFSET_MAX                     0x404
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOCTRL_DEBUG_TAG "FIOCTRL"
+#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_WARN(format, ...)  FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_INFO(format, ...)  FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
+#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
+#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
+
+#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
+#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+
+/**
+ * @name: FPinGetFunc
+ * @msg: 获取IO引脚当前的复用功能
+ * @return {FPinFunc} 当前的复用功能
+ * @param {FPinIndex} pin IO引脚索引
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+FPinFunc FPinGetFunc(const FPinIndex pin)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
+    FIOCTRL_ASSERT_FUNC(func);
+
+    return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
+}
+
+/**
+ * @name: FPinSetFunc
+ * @msg: 设置IO引脚复用功能
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} func IO复用功能
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+void FPinSetFunc(const FPinIndex pin, FPinFunc func)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+    FIOCTRL_ASSERT_FUNC(func);
+
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    reg_val &= ~GENMASK(func_end, func_beg);
+    reg_val |= SET_REG32_BITS(func, func_end, func_beg);
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinGetPull
+ * @msg: 获取IO引脚当前的上下拉设置
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+FPinPull FPinGetPull(const FPinIndex pin)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
+
+    FIOCTRL_ASSERT_PULL(pull);
+    return (FPinPull)pull;
+}
+
+/**
+ * @name: FPinSetPull
+ * @msg: 设置IO引脚当前的上下拉
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinPull} pull 上下拉设置
+ */
+void FPinSetPull(const FPinIndex pin, FPinPull pull)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+    FIOCTRL_ASSERT_PULL(pull);
+
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    reg_val &= ~GENMASK(pull_end, pull_beg);
+    reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinGetConfig
+ * @msg: 获取IO引脚的复用、上下拉和驱动能力设置
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} *func IO复用功能
+ * @param {FPinPull} *pull pull 上下拉设置
+ */
+void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    if (func)
+    {
+        *func = GET_REG32_BITS(reg_val, func_end, func_beg);
+    }
+
+    if (pull)
+    {
+        *pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
+    }
+
+    return;
+}
+
+/**
+ * @name: FPinSetConfig
+ * @msg: 设置IO引脚的复用、上下拉和驱动能力
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} func IO复用功能
+ * @param {FPinPull} pull pull 上下拉设置
+ */
+void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    reg_val &= ~GENMASK(func_end, func_beg);
+    reg_val |= SET_REG32_BITS(func, func_end, func_beg);
+
+    reg_val &= ~GENMASK(pull_end, pull_beg);
+    reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinGetDelay
+ * @msg: 获取IO引脚当前的延时设置
+ * @return {FPinDelay} 当前的延时设置
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {FPinDelayType} type 精调/粗调延时
+ */
+FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    u8 delay = 0;
+    const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FPIN_DELAY_FINE_TUNING == type)
+    {
+        delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
+    }
+    else if (FPIN_DELAY_COARSE_TUNING == type)
+    {
+        delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    FIOCTRL_ASSERT_DELAY(delay);
+    return (FPinDelay)delay;
+}
+
+
+/**
+ * @name: FPinGetDelayEn
+ * @msg: 获取IO引脚当前的延时使能标志位
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ */
+boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    boolean enabled = FALSE;
+    const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
+    {
+        enabled = TRUE;
+    }
+
+    return enabled;
+}
+
+/**
+ * @name: FPinSetDelay
+ * @msg: 设置IO引脚延时
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {FPinDelayType} type 精调/粗调延时
+ * @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
+ */
+void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    FIOCTRL_ASSERT_DELAY(delay);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FPIN_DELAY_FINE_TUNING == type)
+    {
+        reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
+        delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
+    }
+    else if (FPIN_DELAY_COARSE_TUNING == type)
+    {
+        reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
+        delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinSetDelayEn
+ * @msg: 使能/去使能IO引脚延时
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {boolean} enable TRUE: 使能, FALSE: 去使能
+ */
+void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
+    if (enable)
+    {
+        reg_val |= FIOCTRL_DELAY_EN(delay_beg);
+    }
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h
new file mode 100644
index 00000000000..9012e7d2abc
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fioctrl.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:35
+ * Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/2/22   init commit
+ */
+
+
+#ifndef  BOARD_D2000_FIOCTRL_H
+#define  BOARD_D2000_FIOCTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#include "ftypes.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOCTRL_INDEX(offset, func_beg) \
+    { \
+        /* reg_off */   (offset),  \
+        /* reg_bit */   (func_beg) \
+    }
+
+/************************** Variable Definitions *****************************/
+#define FIOCTRL_CRU_CLK_OBV_PAD           (FPinIndex)FIOCTRL_INDEX(0x200, 24)
+#define FIOCTRL_SPI0_CSN0_PAD             (FPinIndex)FIOCTRL_INDEX(0x208, 16)
+#define FIOCTRL_SPI0_SCK_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 12)
+#define FIOCTRL_SPI0_SO_PAD               (FPinIndex)FIOCTRL_INDEX(0x208, 8)
+#define FIOCTRL_SPI0_SI_PAD               (FPinIndex)FIOCTRL_INDEX(0x208, 4)
+
+#define FIOCTRL_TJTAG_TDI_PAD             (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
+#define FIOCTRL_SWDITMS_SWJ_PAD           (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
+
+#define FIOCTRL_NTRST_SWJ_PAD             (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
+#define FIOCTRL_SWDO_SWJ_PAD              (FPinIndex)FIOCTRL_INDEX(0x204, 8)  /* can1-rx: func 1 */
+
+#define FIOCTRL_I2C0_SCL_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
+#define FIOCTRL_I2C0_SDA_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
+#define FIOCTRL_ALL_PLL_LOCK_PAD          (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
+#define FIOCTRL_CRU_CLK_OBV_PAD           (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
+#define FIOCTRL_SWDO_SWJ_PAD              (FPinIndex)FIOCTRL_INDEX(0x204, 8)  /* i2c2-scl: func 2 */
+#define FIOCTRL_TDO_SWJ_IN_PAD            (FPinIndex)FIOCTRL_INDEX(0x204, 4)  /* i2c2-sda: func 2 */
+#define FIOCTRL_HDT_MB_DONE_STATE_PAD     (FPinIndex)FIOCTRL_INDEX(0x204, 0)  /* i2c3-scl: func 2 */
+#define FIOCTRL_HDT_MB_FAIL_STATE_PAD     (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
+
+#define FIOCTRL_UART_2_RXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x210, 0)  /* spi1_csn0: func 1 */
+#define FIOCTRL_UART_2_TXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
+#define FIOCTRL_UART_3_RXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
+#define FIOCTRL_UART_3_TXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
+#define FIOCTRL_QSPI_CSN2_PAD             (FPinIndex)FIOCTRL_INDEX(0x214, 8)  /* spi1_csn1: func 1 */
+#define FIOCTRL_QSPI_CSN3_PAD             (FPinIndex)FIOCTRL_INDEX(0x214, 4)  /* spi1_csn2: func 1 */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/board/d2000/fparameters.h b/bsp/phytium/libraries/standalone/board/d2000/fparameters.h
new file mode 100644
index 00000000000..e848dfa90d7
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/d2000/fparameters.h
@@ -0,0 +1,347 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fparameters.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-17 17:58:51
+ * Description:  This file is for
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef BSP_BOARD_D2000_PARAMETERS_H
+#define BSP_BOARD_D2000_PARAMETERS_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if !defined(__ASSEMBLER__)
+#include "ftypes.h"
+#endif
+
+#define CORE0_AFF 0x0
+#define CORE1_AFF 0x1
+#define CORE2_AFF 0x100
+#define CORE3_AFF 0x101
+#define CORE4_AFF 0x200
+#define CORE5_AFF 0x201
+#define CORE6_AFF 0x300
+#define CORE7_AFF 0x301
+
+/* cache */
+#define CACHE_LINE_ADDR_MASK 0x3F
+#define CACHE_LINE 64U
+
+/*  Device register address */
+#define FDEV_BASE_ADDR 0x28000000
+#define FDEV_END_ADDR 0x2FFFFFFF
+
+/* Generic Timer */
+#define GENERIC_TIMER_NS_IRQ_NUM 30
+
+/* PCI  */
+
+#define FPCIE_NUM 1
+#define FPCIE0_ID 0
+#define FPCIE0_MISC_IRQ_NUM 59
+
+#define FPCIE_CFG_MAX_NUM_OF_BUS 256
+#define FPCIE_CFG_MAX_NUM_OF_DEV 32
+#define FPCIE_CFG_MAX_NUM_OF_FUN 8
+
+#define FPCI_CONFIG_BASE_ADDR 0x40000000
+#define FPCI_CONFIG_REG_LENGTH 0x10000000
+
+#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
+#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
+
+#define FPCI_MEM32_BASE_ADDR   0x58000000
+#define FPCI_MEM32_REG_LENGTH 0x27ffffff
+
+#define FPCI_MEM64_BASE_ADDR 0x1000000000
+#define FPCI_MEM64_REG_LENGTH 0x1000000000
+
+#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29900000
+#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29910000
+#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29920000
+#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29930000
+#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29940000
+#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29950000
+
+#define FPCI_EU0_CONFIG_BASE_ADDR 0x29900000
+#define FPCI_EU1_CONFIG_BASE_ADDR 0x299A0000
+
+
+#define FPCI_INTA_IRQ_NUM     60
+#define FPCI_INTB_IRQ_NUM     61
+#define FPCI_INTC_IRQ_NUM     62
+#define FPCI_INTD_IRQ_NUM     63
+
+#define FPCI_NEED_SKIP        0
+
+#define FPCI_INTX_EOI
+#define FPCI_INTX_PEU0_STAT   0x29100000
+#define FPCI_INTX_PEU1_STAT   0x29101000
+
+#define FPCI_INTX_EU0_C0_CONTROL  0x29000184
+#define FPCI_INTX_EU0_C1_CONTROL  0x29010184
+#define FPCI_INTX_EU0_C2_CONTROL  0x29020184
+#define FPCI_INTX_EU1_C0_CONTROL  0x29030184
+#define FPCI_INTX_EU1_C1_CONTROL  0x29040184
+#define FPCI_INTX_EU1_C2_CONTROL  0x29050184
+
+#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
+#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
+
+/* platform ahci host */
+#define PLAT_AHCI_HOST_MAX_COUNT 5
+#define AHCI_BASE_0     0
+#define AHCI_BASE_1     0
+#define AHCI_BASE_2     0
+#define AHCI_BASE_3     0
+#define AHCI_BASE_4     0
+
+#define AHCI_IRQ_0      0
+#define AHCI_IRQ_1      0
+#define AHCI_IRQ_2      0
+#define AHCI_IRQ_3      0
+#define AHCI_IRQ_4      0
+
+/* UART */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FUART0_ID = 0,
+    FUART1_ID,
+    FUART2_ID,
+    FUART3_ID,
+
+    FUART_NUM
+};
+#endif
+
+#define FUART0_IRQ_NUM 38
+#define FUART0_BASE_ADDR 0x28000000
+#define FUART0_CLK_FREQ_HZ 48000000
+
+#define FUART1_IRQ_NUM 39
+#define FUART1_BASE_ADDR 0x28001000
+#define FUART1_CLK_FREQ_HZ 48000000
+
+#define FUART2_IRQ_NUM 40
+#define FUART2_BASE_ADDR 0x28002000
+#define FUART2_CLK_FREQ_HZ 48000000
+
+#define FUART3_IRQ_NUM 41
+#define FUART3_BASE_ADDR 0x28003000
+#define FUART3_CLK_FREQ_HZ 48000000
+
+#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR
+#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR
+
+/* QSPI */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FQSPI0_ID = 0,
+
+    FQSPI_NUM
+};
+
+/* FQSPI cs 0_3, chip number */
+enum
+{
+    FQSPI_CS_0 = 0,
+    FQSPI_CS_1 = 1,
+    FQSPI_CS_2 = 2,
+    FQSPI_CS_3 = 3,
+    FQSPI_CS_NUM
+};
+#endif
+
+#define FQSPI_BASE_ADDR 0x28014000
+#define FQSPI_MEM_START_ADDR 0x0
+#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
+
+/* GIC v3 */
+#define ARM_GIC_NR_IRQS 1024
+#define ARM_GIC_IRQ_START 0
+#define FGIC_NUM 1
+
+
+#define GICV3_BASE_ADDR 0x29a00000U
+#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
+#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U)
+#define GICV3_RD_OFFSET (2U << 16)
+#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define GICV3_MAX_INTR_PRIO_VAL 240U
+#define GICV3_INTR_PRIO_MASK 0x000000f0U
+
+#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count  */
+#define SGI_INT_MAX 16
+#define SPI_START_INT_NUM 32 /* SPI start at ID32        */
+#define PPI_START_INT_NUM 16 /* PPI start at ID16        */
+#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
+
+/* GPIO */
+#define FGPIO0_BASE_ADDR (0x28004000)
+#define FGPIO1_BASE_ADDR (0x28005000)
+
+#define FGPIO0_ID      0
+#define FGPIO1_ID      1
+#define FGPIO_NUM      2
+
+#define FGPIO0_IRQ_NUM (42) /* gpio0 irq number */
+#define FGPIO1_IRQ_NUM (43) /* gpio1 irq number */
+
+/* IOMUX */
+#define FIOCTRL_REG_BASE_ADDR  0x28180000
+
+/* SPI */
+#define FSPI0_BASE_ADDR 0x2800c000
+#define FSPI1_BASE_ADDR 0x28013000
+#define FSPI0_ID   0
+#define FSPI1_ID   1
+#define FSPI_CLK_FREQ_HZ 48000000
+#define FSPI_NUM 2
+#define FSPI0_IRQ_NUM 50
+#define FSPI1_IRQ_NUM 51
+
+/* I2C */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FI2C0_ID = 0,
+    FI2C1_ID = 1,
+    FI2C2_ID,
+    FI2C3_ID,
+
+    FI2C_NUM
+};
+#endif
+
+#define FI2C0_BASE_ADDR 0x28006000
+#define FI2C1_BASE_ADDR 0x28007000
+#define FI2C2_BASE_ADDR 0x28008000
+#define FI2C3_BASE_ADDR 0x28009000
+
+#define FI2C0_IRQ_NUM 44
+#define FI2C1_IRQ_NUM 45
+#define FI2C2_IRQ_NUM 46
+#define FI2C3_IRQ_NUM 47
+
+#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
+
+/* WDT */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FWDT0_ID = 0,
+    FWDT1_ID = 1,
+
+    FWDT_NUM
+};
+#endif
+
+#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
+#define FWDT1_REFRESH_BASE_ADDR 0x28016000
+
+#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
+
+#define FWDT0_IRQ_NUM 48
+#define FWDT1_IRQ_NUM 49
+
+#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
+
+/* SDCI */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FSDMMC0_ID = 0,
+
+    FSDMMC_NUM
+};
+#endif
+
+#define FSDMMC0_BASE_ADDR 0x28207C00
+
+#define FSDMMC0_DMA_IRQ_NUM 52
+#define FSDMMC0_CMD_IRQ_NUM 53
+#define FSDMMC0_ERR_IRQ_NUM 54
+
+#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
+
+/* GMAC */
+#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
+
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FGMAC0_ID = 0,
+    FGMAC1_ID,
+
+    FGMAC_NUM
+};
+#endif
+
+#define FGMAC0_BASE_ADDR 0x2820C000
+#define FGMAC1_BASE_ADDR 0x28210000
+
+#define FGMAC0_IRQ_NUM 81
+#define FGMAC1_IRQ_NUM 82
+
+#define FGMAC_DMA_MIN_ALIGN 128
+#define FGMAC_MAX_PACKET_SIZE 1600
+
+/* rtc base address */
+#define RTC_CONTROL_BASE 0x2800D000
+
+#define FT_CPUS_NR CORE_NUM
+
+
+
+/* can */
+#define FCAN_CLK_FREQ_HZ 600000000
+
+#define FCAN_REG_LENGTH 0x1000
+#define FCAN0_BASE_ADDR 0x28207000
+#define FCAN1_BASE_ADDR 0x28207400
+#define FCAN2_BASE_ADDR 0x28207800
+#define FCAN0_IRQ_NUM 119
+#define FCAN1_IRQ_NUM 123
+#define FCAN2_IRQNUM 124
+
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FCAN0_ID = 0,
+    FCAN1_ID = 1,
+    FCAN2_ID = 2,
+
+    FCAN_NUM
+};
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c
index b1faaa7dadf..2453c866e40 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c
+++ b/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c
@@ -14,7 +14,7 @@
  * FilePath: fiopad_config.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for io-pad function definition
+ * Description:  This file is for io-pad function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -70,33 +70,59 @@ void FIOPadSetSpimMux(u32 spim_id)
  */
 void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
 {
-    if (FGPIO_ID_3 == gpio_id)
+    if (FGPIO3_ID == gpio_id)
     {
         switch (pin_id)
         {
-        case 3: /* gpio 3-a-3 */
-            FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
-            break;
-        case 4: /* gpio 3-a-4 */
-            FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
-            break;
-        case 5: /* gpio 3-a-5 */
-            FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
-            break;
-        case 6: /* gpio 3-a-6 */
-            FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
-            break;
-        case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
-            FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
-            break;
-        case 8: /* gpio 3-a-8 */
-            FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
-            break;
-        case 9: /* gpio 3-a-9 */
-            FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
-            break;
-        default:
-            break;
+            case 3: /* gpio 3-a-3 */
+                FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
+                break;
+            case 4: /* gpio 3-a-4 */
+                FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
+                break;
+            case 5: /* gpio 3-a-5 */
+                FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
+                break;
+            case 6: /* gpio 3-a-6 */
+                FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
+                break;
+            case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
+                FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
+                break;
+            case 8: /* gpio 3-a-8 */
+                FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
+                break;
+            case 9: /* gpio 3-a-9 */
+                FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
+                break;
+            default:
+                break;
+        }
+    }
+    else if (FGPIO4_ID == gpio_id)
+    {
+        switch (pin_id)
+        {
+            case 5: /* gpio 4-a-5 */
+                FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
+                break;
+            case 9: /* gpio 4-a-9 */
+                FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
+                break;
+            case 10: /* gpio 4-a-10 */
+                FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
+                break;
+            case 11: /* gpio 4-a-11 */
+                FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
+                break;
+            case 12: /* gpio 4-a-12 */
+                FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
+                break;
+            case 13: /* gpio 4-a-13 */
+                FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
+                break;
+            default:
+                break;
         }
     }
 }
@@ -109,15 +135,15 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
  */
 void FIOPadSetCanMux(u32 can_id)
 {
-    if (can_id == FCAN_INSTANCE_0)
+    if (can_id == FCAN0_ID)
     {
-        /* mio0 */
+		/* can0 */
         FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */
         FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */
     }
-    else if (can_id == FCAN_INSTANCE_1)
+    else if (can_id == FCAN1_ID)
     {
-        /* mio1 */
+		/* can1 */
         FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */
         FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */
     }
@@ -137,7 +163,7 @@ void FIOPadSetCanMux(u32 can_id)
 void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
 {
 
-    if (qspi_id == FQSPI_INSTANCE_0)
+    if (qspi_id == FQSPI0_ID)
     {
         /* add sck, io0-io3 iopad multiplex */
     }
@@ -174,359 +200,326 @@ void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
  */
 void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
 {
-    FASSERT(pwm_id < FPWM_INSTANCE_NUM);
+    FASSERT(pwm_id < FPWM_NUM);
     FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
 
     switch (pwm_id)
     {
-    case FPWM_INSTANCE_0:
-        if (pwm_channel == 0)
+        case FPWM0_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
+            }
+            break;
+
+        case FPWM1_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
+            }
+            break;
+
+        case FPWM2_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
+            }
+            break;
+
+        case FPWM3_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
+            }
+            break;
+
+        case FPWM4_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
+            }
+            break;
+
+        case FPWM5_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
+            }
+            break;
+
+        case FPWM6_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
+            }
+            break;
+
+        case FPWM7_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
+            }
+            break;
+
+        default:
+            FIOPAD_ERROR("pwm id is error.\r\n");
+            break;
+    }
+}
+
+
+/**
+ * @name: FIOPadSetAdcMux
+ * @msg: set iopad mux for adc
+ * @return {*}
+ * @param {u32} adc_id, id of adc instance
+ * @param {u32} adc_channel, id of adc channel
+ */
+void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
+{
+
+    if (adc_id == FADC0_ID)
+    {
+        switch (adc_channel)
         {
-            FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
+            case FADC_CHANNEL_0:
+                FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
+                break;
+            case FADC_CHANNEL_1:
+                FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
+                break;
+            case FADC_CHANNEL_2:
+                FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
+                break;
+            case FADC_CHANNEL_3:
+                FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
+                break;
+            case FADC_CHANNEL_4:
+                FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
+                break;
+            case FADC_CHANNEL_5:
+                FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
+                break;
+            case FADC_CHANNEL_6:
+                FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
+                break;
+            case FADC_CHANNEL_7:
+                FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
+                break;
+            default:
+                FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+                break;
         }
-        if (pwm_channel == 1)
+    }
+    else
+    {
+        FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+    }
+}
+
+/**
+ * @name: FIOPadSetMioMux
+ * @msg: set iopad mux for mio
+ * @return {*}
+ * @param {u32} mio_id, instance id of i2c
+ */
+void FIOPadSetMioMux(u32 mio_id)
+{
+    switch (mio_id)
+    {
+        case FMIO0_ID:
         {
-            FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_1:
-        if (pwm_channel == 0)
+        case FMIO1_ID:
         {
-            FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO2_ID:
         {
-            FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_2:
-        if (pwm_channel == 0)
+        case FMIO3_ID:
         {
-            FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
+            FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO4_ID:
         {
-            FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
+            FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_3:
-        if (pwm_channel == 0)
+        case FMIO5_ID:
         {
-            FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
+            FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO6_ID:
         {
-            FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_4:
-        if (pwm_channel == 0)
+        case FMIO7_ID:
         {
-            FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
+            FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO8_ID:
         {
-            FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_5:
-        if (pwm_channel == 0)
+        case FMIO9_ID:
         {
-            FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO10_ID:
         {
-            FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
+            FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_6:
-        if (pwm_channel == 0)
+        case FMIO11_ID:
         {
-            FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
+            FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO12_ID:
         {
-            FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
+            FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_7:
-        if (pwm_channel == 0)
+        case FMIO13_ID:
         {
-            FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
+            FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO14_ID:
         {
-            FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
+            FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
         }
         break;
-
-    default:
-        FIOPAD_ERROR("pwm id is error.\r\n");
+        case FMIO15_ID:
+        {
+            FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
+        }
         break;
+        default:
+            break;
     }
 }
 
-
 /**
- * @name: FIOPadSetAdcMux
- * @msg: set iopad mux for adc
+ * @name: FIOPadSetTachoMux
+ * @msg: set iopad mux for pwm_in
  * @return {*}
- * @param {u32} adc_id, id of adc instance
- * @param {u32} adc_channel, id of adc channel
+ * @param {u32} pwm_in_id, instance id of tacho
  */
-void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
+void FIOPadSetTachoMux(u32 pwm_in_id)
 {
-
-    if (adc_id == FADC_INSTANCE_0)
+    switch (pwm_in_id)
     {
-        switch (adc_channel)
-        {
-        case FADC_CHANNEL_0:
-            FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
+        case FTACHO0_ID:
+            FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_1:
-            FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
+        case FTACHO1_ID:
+            FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_2:
-            FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
+        case FTACHO2_ID:
+            FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_3:
-            FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
+        case FTACHO3_ID:
+            FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_4:
-            FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
+        case FTACHO4_ID:
+            FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_5:
-            FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
+        case FTACHO5_ID:
+            FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_6:
-            FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
+        case FTACHO6_ID:
+            FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_7:
-            FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
+        case FTACHO7_ID:
+            FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
             break;
-        default:
-            FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+        case FTACHO8_ID:
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
             break;
-        }
-    }
-    else if (adc_id == FADC_INSTANCE_1)
-    {
-        switch (adc_channel)
-        {
-        case FADC_CHANNEL_0:
-            FPinSetFunc(FIOPAD_G43, FPIN_FUNC7); /* adc1-0: func 7 */
-            break;
-        case FADC_CHANNEL_1:
-            FPinSetFunc(FIOPAD_J43, FPIN_FUNC7); /* adc1-1: func 7 */
+        case FTACHO9_ID:
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_2:
-            FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc1-2: func 7 */
+        case FTACHO10_ID:
+            FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_3:
-            FPinSetFunc(FIOPAD_N45, FPIN_FUNC7); /* adc1-3: func 7 */
+        case FTACHO11_ID:
+            FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_4:
-            FPinSetFunc(FIOPAD_L47, FPIN_FUNC7); /* adc1-4: func 7 */
+        case FTACHO12_ID:
+            FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_5:
-            FPinSetFunc(FIOPAD_L45, FPIN_FUNC7); /* adc1-5: func 7 */
+        case FTACHO13_ID:
+            FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_6:
-            FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-6: func 7 */
+        case FTACHO14_ID:
+            FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_7:
-            FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-7: func 7 */
+        case FTACHO15_ID:
+            FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
             break;
         default:
-            FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
             break;
-        }
-    }
-    else
-    {
-        FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
-    }
-}
-
-/**
- * @name: FIOPadSetMioMux
- * @msg: set iopad mux for mio
- * @return {*}
- * @param {u32} mio_id, instance id of i2c
- */
-void FIOPadSetMioMux(u32 mio_id)
-{
-    switch (mio_id)
-    {
-    case MIO_INSTANCE_0:
-    {
-        FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_1:
-    {
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_2:
-    {
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_3:
-    {
-        FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_4:
-    {
-        FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_5:
-    {
-        FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_6:
-    {
-        FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_7:
-    {
-        FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_8:
-    {
-        FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_9:
-    {
-        FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_10:
-    {
-        FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_11:
-    {
-        FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_12:
-    {
-        FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_13:
-    {
-        FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_14:
-    {
-        FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_15:
-    {
-        FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
-    }
-    break;
-    default:
-        break;
-    }
-}
-
-/**
- * @name: FIOPadSetTachoMux
- * @msg: set iopad mux for pwm_in
- * @return {*}
- * @param {u32} pwm_in_id, instance id of tacho
- */
-void FIOPadSetTachoMux(u32 pwm_in_id)
-{
-    switch (pwm_in_id)
-    {
-    case TACHO_INSTANCE_0:
-        FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_1:
-        FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_2:
-        FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_3:
-        FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_4:
-        FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_5:
-        FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_6:
-        FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_7:
-        FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_8:
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_9:
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_10:
-        FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_11:
-        FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_12:
-        FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_13:
-        FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_14:
-        FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_15:
-        FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
-        break;
-    default:
-        break;
     }
 }
 
@@ -540,23 +533,23 @@ void FIOPadSetUartMux(u32 uart_id)
 {
     switch (uart_id)
     {
-    case FUART0_ID:
-        FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
-        FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
-        break;
-    case FUART1_ID:
-        FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
-        break;
-    case FUART2_ID:
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
-        break;
-    case FUART3_ID:
-        FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
-        FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
-        break;
-    default:
-        break;
+        case FUART0_ID:
+            FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
+            FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
+            break;
+        case FUART1_ID:
+            FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
+            break;
+        case FUART2_ID:
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
+            break;
+        case FUART3_ID:
+            FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
+            FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
+            break;
+        default:
+            break;
     }
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h
index 3703d3e78b5..7857ed48ce6 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h
+++ b/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h
@@ -14,7 +14,7 @@
  * FilePath: fparameters.h
  * Date: 2022-02-11 13:33:28
  * LastEditTime: 2022-02-17 18:00:50
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c
index e26cafcc8d7..3be376cce18 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c
+++ b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c
@@ -14,7 +14,7 @@
  * FilePath: fiopad_comm.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for io-pad function definition
+ * Description:  This file is for io-pad function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -202,7 +202,7 @@ void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDriv
 
     if (drive)
     {
-        *pull = FIOPAD_X_REG0_DRIVE_GET(reg_val);
+        *drive = FIOPAD_X_REG0_DRIVE_GET(reg_val);
     }
 
     return;
@@ -331,16 +331,24 @@ boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
     if (FPIN_OUTPUT_DELAY == dir)
     {
         if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val)
+        {
             enabled = TRUE;
+        }
         else
+        {
             enabled = FALSE;
+        }
     }
     else if (FPIN_INPUT_DELAY == dir)
     {
         if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val)
+        {
             enabled = TRUE;
+        }
         else
+        {
             enabled = FALSE;
+        }
     }
     else
     {
@@ -424,16 +432,24 @@ void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
     if (FPIN_OUTPUT_DELAY == dir)
     {
         if (enable)
+        {
             reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN;
+        }
         else
+        {
             reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN;
+        }
     }
     else if (FPIN_INPUT_DELAY == dir)
     {
         if (enable)
+        {
             reg_val |= FIOPAD_X_REG1_IN_DELAY_EN;
+        }
         else
+        {
             reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN;
+        }
     }
     else
     {
diff --git a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h
index 311fb6f0763..8251caee75e 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h
+++ b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h
@@ -17,10 +17,10 @@ extern "C"
 
 /***************** Macros (Inline Functions) Definitions *********************/
 #define FIOPAD_INDEX(offset) \
-   { \
+    { \
         /* reg_off */   (offset),  \
         /* reg_bit */   (0) \
-   }
+    }
 
 /*****************************************************************************/
 /* register offset of iopad function / pull / driver strength */
diff --git a/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h b/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h
index 5f807e78435..77076546548 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h
+++ b/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h
@@ -14,7 +14,7 @@
  * FilePath: fparameters_comm.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-17 18:01:11
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -44,55 +44,55 @@ extern "C"
 #define FT_DEV_END_ADDR 0x2FFFFFFFU
 
 /* PCI */
-#define FT_PCIE_NUM 1
-#define FT_PCIE0_ID 0
-#define FT_PCIE0_MISC_IRQ_NUM 40
+#define FPCIE_NUM 1
+#define FPCIE0_ID 0
+#define FPCIE0_MISC_IRQ_NUM 40
 
-#define FT_PCIE_CFG_MAX_NUM_OF_BUS 256
-#define FT_PCIE_CFG_MAX_NUM_OF_DEV 32
-#define FT_PCIE_CFG_MAX_NUM_OF_FUN 8
+#define FPCIE_CFG_MAX_NUM_OF_BUS 256
+#define FPCIE_CFG_MAX_NUM_OF_DEV 32
+#define FPCIE_CFG_MAX_NUM_OF_FUN 8
 
-#define FT_PCI_CONFIG_BASEADDR 0x40000000U
-#define FT_PCI_CONFIG_REG_LENGTH 0x10000000U
+#define FPCI_CONFIG_BASE_ADDR 0x40000000U
+#define FPCI_CONFIG_REG_LENGTH 0x10000000U
 
-#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000U
-#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000U
+#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000U
+#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000U
 
-#define FT_PCI_MEM32_BASEADDR 0x58000000U
-#define FT_PCI_MEM32_REG_LENGTH 0x27FFFFFFU
+#define FPCI_MEM32_BASE_ADDR 0x58000000U
+#define FPCI_MEM32_REG_LENGTH 0x27FFFFFFU
 
-#define FT_PCI_MEM64_BASEADDR 0x1000000000U
-#define FT_PCI_MEM64_REG_LENGTH 0x1000000000U
+#define FPCI_MEM64_BASE_ADDR 0x1000000000U
+#define FPCI_MEM64_REG_LENGTH 0x1000000000U
 
-#define FT_PCI_EU0_C0_CONTROL_BASEADDR 0x29000000U
-#define FT_PCI_EU0_C1_CONTROL_BASEADDR 0x29010000U
-#define FT_PCI_EU0_C2_CONTROL_BASEADDR 0x29020000U
-#define FT_PCI_EU1_C0_CONTROL_BASEADDR 0x29030000U
-#define FT_PCI_EU1_C1_CONTROL_BASEADDR 0x29040000U
-#define FT_PCI_EU1_C2_CONTROL_BASEADDR 0x29050000U
+#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000U
+#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000U
+#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000U
+#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000U
+#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000U
+#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000U
 
-#define FT_PCI_EU0_CONFIG_BASEADDR 0x29100000U
-#define FT_PCI_EU1_CONFIG_BASEADDR 0x29101000U
+#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000U
+#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000U
 
-#define FT_PCI_INTA_IRQ_NUM     36
-#define FT_PCI_INTB_IRQ_NUM     37
-#define FT_PCI_INTC_IRQ_NUM     38
-#define FT_PCI_INTD_IRQ_NUM     39
+#define FPCI_INTA_IRQ_NUM     36
+#define FPCI_INTB_IRQ_NUM     37
+#define FPCI_INTC_IRQ_NUM     38
+#define FPCI_INTD_IRQ_NUM     39
 
-#define FT_PCI_NEED_SKIP        0
+#define FPCI_NEED_SKIP        0
 
-#define FT_PCI_INTX_PEU0_STAT   0x29100000U
-#define FT_PCI_INTX_PEU1_STAT   0x29101000U
+#define FPCI_INTX_PEU0_STAT   0x29100000U
+#define FPCI_INTX_PEU1_STAT   0x29101000U
 
-#define FT_PCI_INTX_EU0_C0_CONTROL  0x29000184U
-#define FT_PCI_INTX_EU0_C1_CONTROL  0x29010184U
-#define FT_PCI_INTX_EU0_C2_CONTROL  0x29020184U
-#define FT_PCI_INTX_EU1_C0_CONTROL  0x29030184U
-#define FT_PCI_INTX_EU1_C1_CONTROL  0x29040184U
-#define FT_PCI_INTX_EU1_C2_CONTROL  0x29050184U
+#define FPCI_INTX_EU0_C0_CONTROL  0x29000184U
+#define FPCI_INTX_EU0_C1_CONTROL  0x29010184U
+#define FPCI_INTX_EU0_C2_CONTROL  0x29020184U
+#define FPCI_INTX_EU1_C0_CONTROL  0x29030184U
+#define FPCI_INTX_EU1_C1_CONTROL  0x29040184U
+#define FPCI_INTX_EU1_C2_CONTROL  0x29050184U
 
-#define FT_PCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
-#define FT_PCI_INTX_SATA_NUM 2 /* Total number of controllers */
+#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */
+#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */
 
 
 /* platform ahci host */
@@ -110,22 +110,37 @@ extern "C"
 #define AHCI_IRQ_4      0
 
 /* sata controller */
-#define FSATA0_BASEADDR 0x31A40000U
-#define FSATA1_BASEADDR 0x32014000U
+#define FSATA0_BASE_ADDR 0x31A40000U
+#define FSATA1_BASE_ADDR 0x32014000U
 
-#define FSATA0_IRQNUM   74
-#define FSATA1_IRQNUM   75
+#define FSATA0_IRQ_NUM   74
+#define FSATA1_IRQ_NUM   75
 
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    FSATA_INSTANCE_0 = 0,
-    FSATA_INSTANCE_1 = 1,
+    FSATA0_ID = 0,
+    FSATA1_ID = 1,
 
-    FSATA_INSTANCE_NUM
-} FSataInstance;
+    FSATA_NUM
+};
 #endif
 
+/* SCMI and MHU */
+#define FSCMI_MHU_BASE_ADDR 0x32a00000
+#define FSCMI_MHU_IRQ_NUM   (22U + 32U)
+#define FSCMI_SHR_MEM_ADDR  0x32a11400
+#define FSCMI_MEM_TX_OFSET  0x1400
+#define FSCMI_MEM_RX_OFSET  0x1000
+#define FSCMI_SHR_MEM_SIZE  0x400
+
+#define FSCMI_MSG_SIZE			128	
+#define FSCMI_MAX_STR_SIZE		16
+#define FSCMI_MAX_NUM_SENSOR	16
+#define FSCMI_MAX_PROTOCOLS_IMP	16
+#define FSCMI_MAX_PERF_DOMAINS  3
+#define FSCMI_MAX_OPPS		    4
+
 /* Generic Timer */
 #define GENERIC_TIMER_CLK_FREQ_MHZ 48U
 #define GENERIC_TIMER_NS_IRQ_NUM 30U
@@ -169,7 +184,7 @@ typedef enum
 #define GICV3_MAX_INTR_PRIO_VAL 240U
 #define GICV3_INTR_PRIO_MASK 0x000000f0U
 
-#define ARM_GIC_NR_IRQS 160U
+#define ARM_GIC_NR_IRQS 270U
 #define ARM_GIC_IRQ_START 0U
 #define FGIC_NUM 1U
 
@@ -179,28 +194,35 @@ typedef enum
 #define PPI_START_INT_NUM 16U /* PPI start at ID16        */
 #define GIC_INT_MAX_NUM 1020U /* GIC max interrupts count */
 
-#define GICV3_BASEADDRESS 0x30800000U
-#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0)
-#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U)
+#define GICV3_BASE_ADDR 0x30800000U
+#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
+#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U)
 #define GICV3_RD_OFFSET (2U << 16)
 #define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
 
 /* GPIO */
-#define FGPIO_ID_0                      0U
-#define FGPIO_ID_1                      1U
-#define FGPIO_ID_2                      2U
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FGPIO0_ID = 0,
+    FGPIO1_ID = 1,
+    FGPIO2_ID,
+    FGPIO3_ID,
+    FGPIO4_ID,
+    FGPIO5_ID,
+
+    FGPIO_NUM
+};
+#endif
+
 #define FGPIO_WITH_PIN_IRQ              2U /* max id of gpio assign irq for each pin */
-#define FGPIO_ID_3                      3U
-#define FGPIO_ID_4                      4U
-#define FGPIO_ID_5                      5U
-#define FGPIO_NUM                       6U
-
-#define FGPIO_0_BASE_ADDR               0x28034000U
-#define FGPIO_1_BASE_ADDR               0x28035000U
-#define FGPIO_2_BASE_ADDR               0x28036000U
-#define FGPIO_3_BASE_ADDR               0x28037000U
-#define FGPIO_4_BASE_ADDR               0x28038000U
-#define FGPIO_5_BASE_ADDR               0x28039000U
+
+#define FGPIO0_BASE_ADDR               0x28034000U
+#define FGPIO1_BASE_ADDR               0x28035000U
+#define FGPIO2_BASE_ADDR               0x28036000U
+#define FGPIO3_BASE_ADDR               0x28037000U
+#define FGPIO4_BASE_ADDR               0x28038000U
+#define FGPIO5_BASE_ADDR               0x28039000U
 
 #define FGPIO_CTRL_PIN_NUM              16U
 
@@ -214,8 +236,8 @@ typedef enum
 #define FGPIO_PIN_IRQ_TOTAL             51U
 
 /* SPI */
-#define FSPI0_BASE 0x2803A000U
-#define FSPI1_BASE 0x2803B000U
+#define FSPI0_BASE_ADDR 0x2803A000U
+#define FSPI1_BASE_ADDR 0x2803B000U
 #define FSPI2_BASE 0x2803C000U
 #define FSPI3_BASE 0x2803D000U
 #define FSPI0_ID   0U
@@ -228,90 +250,88 @@ typedef enum
 #define FSPI2_IRQ_NUM 193U
 #define FSPI3_IRQ_NUM 194U
 
-#define FSPI_FREQ 50000000U
-#define FSPI_DEVICE_NUM 4U
+#define FSPI_CLK_FREQ_HZ 50000000U
+#define FSPI_NUM 4U
 
 /* XMAC */
-#define FT_XMAC_NUM 4U
-
-#define FT_XMAC0_ID 0U
-#define FT_XMAC1_ID 1U
-#define FT_XMAC2_ID 2U
-#define FT_XMAC3_ID 3U
-
-#define FT_XMAC0_BASEADDRESS 0x3200C000U
-#define FT_XMAC1_BASEADDRESS 0x3200E000U
-#define FT_XMAC2_BASEADDRESS 0x32010000U
-#define FT_XMAC3_BASEADDRESS 0x32012000U
-
-#define FT_XMAC0_MODE_SEL_BASEADDRESS 0x3200DC00U
-#define FT_XMAC0_LOOPBACK_SEL_BASEADDRESS 0x3200DC04U
-#define FT_XMAC1_MODE_SEL_BASEADDRESS 0x3200FC00U
-#define FT_XMAC1_LOOPBACK_SEL_BASEADDRESS 0x3200FC04U
-#define FT_XMAC2_MODE_SEL_BASEADDRESS 0x32011C00U
-#define FT_XMAC2_LOOPBACK_SEL_BASEADDRESS 0x32011C04U
-#define FT_XMAC3_MODE_SEL_BASEADDRESS 0x32013C00U
-#define FT_XMAC3_LOOPBACK_SEL_BASEADDRESS 0x32013C04U
-
-#define FT_XMAC0_PCLK 50000000U
-#define FT_XMAC1_PCLK 50000000U
-#define FT_XMAC2_PCLK 50000000U
-#define FT_XMAC3_PCLK 50000000U
-#define FT_XMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
-#define FT_XMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
-#define FT_XMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
-#define FT_XMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
-
-#define FT_XMAC_QUEUE_MAX_NUM 16U
-
-#define FT_XMAC0_QUEUE0_IRQ_NUM (57U + 30U)
-#define FT_XMAC0_QUEUE1_IRQ_NUM (58U + 30U)
-#define FT_XMAC0_QUEUE2_IRQ_NUM (59U + 30U)
-#define FT_XMAC0_QUEUE3_IRQ_NUM (60U + 30U)
-#define FT_XMAC0_QUEUE4_IRQ_NUM (30U + 30U)
-#define FT_XMAC0_QUEUE5_IRQ_NUM (31U + 30U)
-#define FT_XMAC0_QUEUE6_IRQ_NUM (32U + 30U)
-#define FT_XMAC0_QUEUE7_IRQ_NUM (33U + 30U)
-
-#define FT_XMAC1_QUEUE0_IRQ_NUM (61U + 30U)
-#define FT_XMAC1_QUEUE1_IRQ_NUM (62U + 30U)
-#define FT_XMAC1_QUEUE2_IRQ_NUM (63U + 30U)
-#define FT_XMAC1_QUEUE3_IRQ_NUM (64U + 30U)
-
-#define FT_XMAC2_QUEUE0_IRQ_NUM (66U + 30U)
-#define FT_XMAC2_QUEUE1_IRQ_NUM (67U + 30U)
-#define FT_XMAC2_QUEUE2_IRQ_NUM (68U + 30U)
-#define FT_XMAC2_QUEUE3_IRQ_NUM (69U + 30U)
-
-#define FT_XMAC3_QUEUE0_IRQ_NUM (70U + 30U)
-#define FT_XMAC3_QUEUE1_IRQ_NUM (71U + 30U)
-#define FT_XMAC3_QUEUE2_IRQ_NUM (72U + 30U)
-#define FT_XMAC3_QUEUE3_IRQ_NUM (73U + 30U)
-
-#define FT_XMAC_PHY_MAX_NUM 32U
+#define FXMAC_NUM 4U
+
+#define FXMAC0_ID 0U
+#define FXMAC1_ID 1U
+#define FXMAC2_ID 2U
+#define FXMAC3_ID 3U
+
+#define FXMAC0_BASE_ADDR 0x3200C000U
+#define FXMAC1_BASE_ADDR 0x3200E000U
+#define FXMAC2_BASE_ADDR 0x32010000U
+#define FXMAC3_BASE_ADDR 0x32012000U
+
+#define FXMAC0_MODE_SEL_BASE_ADDR 0x3200DC00U
+#define FXMAC0_LOOPBACK_SEL_BASE_ADDR 0x3200DC04U
+#define FXMAC1_MODE_SEL_BASE_ADDR 0x3200FC00U
+#define FXMAC1_LOOPBACK_SEL_BASE_ADDR 0x3200FC04U
+#define FXMAC2_MODE_SEL_BASE_ADDR 0x32011C00U
+#define FXMAC2_LOOPBACK_SEL_BASE_ADDR 0x32011C04U
+#define FXMAC3_MODE_SEL_BASE_ADDR 0x32013C00U
+#define FXMAC3_LOOPBACK_SEL_BASE_ADDR 0x32013C04U
+
+#define FXMAC0_PCLK 50000000U
+#define FXMAC1_PCLK 50000000U
+#define FXMAC2_PCLK 50000000U
+#define FXMAC3_PCLK 50000000U
+#define FXMAC0_HOTPLUG_IRQ_NUM (53U + 30U)
+#define FXMAC1_HOTPLUG_IRQ_NUM (54U + 30U)
+#define FXMAC2_HOTPLUG_IRQ_NUM (55U + 30U)
+#define FXMAC3_HOTPLUG_IRQ_NUM (56U + 30U)
+
+#define FXMAC_QUEUE_MAX_NUM 16U
+
+#define FXMAC0_QUEUE0_IRQ_NUM (57U + 30U)
+#define FXMAC0_QUEUE1_IRQ_NUM (58U + 30U)
+#define FXMAC0_QUEUE2_IRQ_NUM (59U + 30U)
+#define FXMAC0_QUEUE3_IRQ_NUM (60U + 30U)
+#define FXMAC0_QUEUE4_IRQ_NUM (30U + 30U)
+#define FXMAC0_QUEUE5_IRQ_NUM (31U + 30U)
+#define FXMAC0_QUEUE6_IRQ_NUM (32U + 30U)
+#define FXMAC0_QUEUE7_IRQ_NUM (33U + 30U)
+
+#define FXMAC1_QUEUE0_IRQ_NUM (61U + 30U)
+#define FXMAC1_QUEUE1_IRQ_NUM (62U + 30U)
+#define FXMAC1_QUEUE2_IRQ_NUM (63U + 30U)
+#define FXMAC1_QUEUE3_IRQ_NUM (64U + 30U)
+
+#define FXMAC2_QUEUE0_IRQ_NUM (66U + 30U)
+#define FXMAC2_QUEUE1_IRQ_NUM (67U + 30U)
+#define FXMAC2_QUEUE2_IRQ_NUM (68U + 30U)
+#define FXMAC2_QUEUE3_IRQ_NUM (69U + 30U)
+
+#define FXMAC3_QUEUE0_IRQ_NUM (70U + 30U)
+#define FXMAC3_QUEUE1_IRQ_NUM (71U + 30U)
+#define FXMAC3_QUEUE2_IRQ_NUM (72U + 30U)
+#define FXMAC3_QUEUE3_IRQ_NUM (73U + 30U)
+
+#define FXMAC_PHY_MAX_NUM 32U
 
 /* QSPI */
-
-#define FQSPI_BASEADDR 0x028008000U
-
 #if !defined(__ASSEMBLER__)
-
-typedef enum
+enum
 {
-    FQSPI_INSTANCE_0 = 0,
+    FQSPI0_ID = 0,
+
+    FQSPI_NUM
+};
 
-    FQSPI_INSTANCE_NUM
-} FQspiInstance;
+#define FQSPI_BASE_ADDR 0x028008000U
 
 /* FQSPI cs 0_3, chip number */
-typedef enum
+enum
 {
     FQSPI_CS_0 = 0,
     FQSPI_CS_1 = 1,
     FQSPI_CS_2 = 2,
     FQSPI_CS_3 = 3,
     FQSPI_CS_NUM
-} FQspiChipCS;
+};
 
 #endif
 
@@ -321,113 +341,112 @@ typedef enum
 #define FQSPI_MEM_END_ADDR_64 0x17FFFFFFFU /* 2GB */
 
 /* TIMER and TACHO */
-#define TIMER_NUM 38U
-#define TACHO_NUM 16U
-#define TIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
-#define TIMER_TICK_PERIOD_NS 20U      /* 20ns */
-#define TIMER_TACHO_IRQ_ID(n) (226U + (n))
-#define TIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
+#define FTIMER_NUM 38U
+#define FTIMER_CLK_FREQ_HZ 50000000U /* 50MHz */
+#define FTIMER_TICK_PERIOD_NS 20U      /* 20ns */
+#define FTIMER_TACHO_IRQ_NUM(n) (226U + (n))
+#define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n))
 
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    TACHO_INSTANCE_0 = 0,
-    TACHO_INSTANCE_1 = 1,
-    TACHO_INSTANCE_2 = 2,
-    TACHO_INSTANCE_3 = 3,
-    TACHO_INSTANCE_4 = 4,
-    TACHO_INSTANCE_5 = 5,
-    TACHO_INSTANCE_6 = 6,
-    TACHO_INSTANCE_7 = 7,
-    TACHO_INSTANCE_8 = 8,
-    TACHO_INSTANCE_9 = 9,
-    TACHO_INSTANCE_10 = 10,
-    TACHO_INSTANCE_11 = 11,
-    TACHO_INSTANCE_12 = 12,
-    TACHO_INSTANCE_13 = 13,
-    TACHO_INSTANCE_14 = 14,
-    TACHO_INSTANCE_15 = 15,
-
-    TACHO_INSTANCE_NUM
-} TachoInstance;
+    FTACHO0_ID = 0,
+    FTACHO1_ID = 1,
+    FTACHO2_ID,
+    FTACHO3_ID,
+    FTACHO4_ID,
+    FTACHO5_ID,
+    FTACHO6_ID,
+    FTACHO7_ID,
+    FTACHO8_ID,
+    FTACHO9_ID,
+    FTACHO10_ID,
+    FTACHO11_ID,
+    FTACHO12_ID,
+    FTACHO13_ID,
+    FTACHO14_ID,
+    FTACHO15_ID,
+
+    FTACHO_NUM
+} ;
 #endif
 
 /* GDMA */
 #define FGDMA0_ID           0U
 #define FGDMA0_BASE_ADDR    0x32B34000U
-#define FGDMA0_IRQ_NUM      266U
-
+#define FGDMA0_CHANNEL0_IRQ_NUM      266U
+#define FGDMA_NUM_OF_CHAN   16
 #define FGDMA_INSTANCE_NUM  1U
+#define FGDMA0_CAPACITY (1U<<0) 
 
 /* CANFD */
-#define FCAN_REF_CLOCK 200000000U
+#define FCAN_CLK_FREQ_HZ 200000000U
 
-#define FCAN0_BASEADDR 0x2800A000U
-#define FCAN1_BASEADDR 0x2800B000U
+#define FCAN0_BASE_ADDR 0x2800A000U
+#define FCAN1_BASE_ADDR 0x2800B000U
 
-#define FCAN0_IRQNUM 113U
-#define FCAN1_IRQNUM 114U
+#define FCAN0_IRQ_NUM 113U
+#define FCAN1_IRQ_NUM 114U
 
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    FCAN_INSTANCE_0 = 0,
-    FCAN_INSTANCE_1 = 1,
+    FCAN0_ID = 0,
+    FCAN1_ID = 1,
 
-    FCAN_INSTANCE_NUM
-} FCanInstance;
+    FCAN_NUM
+};
 #endif
 
 /* WDT */
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    FWDT_INSTANCE_0 = 0,
-    FWDT_INSTANCE_1,
+    FWDT0_ID = 0,
+    FWDT1_ID,
 
-    FWDT_INSTANCE_NUM
-} FWdtInstance;
+    FWDT_NUM
+};
 #endif
 
-#define FWDT0_REFRESH_BASE 0x28040000U
-#define FWDT0_CONTROL_BASE 0x28041000U
-#define FWDT1_REFRESH_BASE 0x28042000U
-#define FWDT1_CONTROL_BASE 0x28043000U
+#define FWDT0_REFRESH_BASE_ADDR 0x28040000U
+#define FWDT1_REFRESH_BASE_ADDR 0x28042000U
 
-#define FWDT0_INTR_IRQ 196U
-#define FWDT1_INTR_IRQ 197U
+#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
 
-#define FWDT_CLK 48000000U /* 48MHz */
+#define FWDT0_IRQ_NUM 196U
+#define FWDT1_IRQ_NUM 197U
+
+#define FWDT_CLK_FREQ_HZ 48000000U /* 48MHz */
 
 /*MIO*/
-#define FMIO_NUM 16
 #define FMIO_BASE_ADDR(n) (0x28014000 + 0x2000 * (n))
 #define FMIO_CONF_ADDR(n) FMIO_BASE_ADDR(n)+0x1000
 #define FMIO_IRQ_NUM(n) (124+n)
-#define MIO_REF_CLK_HZ 50000000 /* 50MHz */
+#define FMIO_CLK_FREQ_HZ 50000000 /* 50MHz */
 
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    MIO_INSTANCE_0 = 0,
-    MIO_INSTANCE_1,
-    MIO_INSTANCE_2,
-    MIO_INSTANCE_3,
-    MIO_INSTANCE_4,
-    MIO_INSTANCE_5,
-    MIO_INSTANCE_6,
-    MIO_INSTANCE_7,
-    MIO_INSTANCE_8,
-    MIO_INSTANCE_9,
-    MIO_INSTANCE_10,
-    MIO_INSTANCE_11,
-    MIO_INSTANCE_12,
-    MIO_INSTANCE_13,
-    MIO_INSTANCE_14,
-    MIO_INSTANCE_15,
-
-    MIO_INSTANCE_NUM
-} MioInstance;
+    FMIO0_ID = 0,
+    FMIO1_ID = 1,
+    FMIO2_ID,
+    FMIO3_ID,
+    FMIO4_ID,
+    FMIO5_ID,
+    FMIO6_ID,
+    FMIO7_ID,
+    FMIO8_ID,
+    FMIO9_ID,
+    FMIO10_ID,
+    FMIO11_ID,
+    FMIO12_ID,
+    FMIO13_ID,
+    FMIO14_ID,
+    FMIO15_ID,
+
+    FMIO_NUM
+};
 #endif
 
 #if !defined(__ASSEMBLER__)
@@ -435,49 +454,49 @@ typedef enum
 * I2C1 -> PMBUS1
 * I2C2 -> SMBUS0
 */
-typedef enum
+enum
 {
-    I2C_INSTANCE_0 = 0,
-    I2C_INSTANCE_1,
-    I2C_INSTANCE_2,
+    FI2C0_ID = 0,
+    FI2C1_ID,
+    FI2C2_ID,
 
-    I2C_INSTANCE_NUM
-} I2cInstance;
+    FI2C_NUM
+};
 #endif
 
-#define I2C_0_BASEADDR 0x28011000
-#define I2C_1_BASEADDR 0x28012000
-#define I2C_2_BASEADDR 0x28013000
+#define FI2C0_BASE_ADDR 0x28011000
+#define FI2C1_BASE_ADDR 0x28012000
+#define FI2C2_BASE_ADDR 0x28013000
 
-#define I2C_0_INTR_IRQ 121
-#define I2C_1_INTR_IRQ 122
-#define I2C_2_INTR_IRQ 123
+#define FI2C0_IRQ_NUM 121
+#define FI2C1_IRQ_NUM 122
+#define FI2C2_IRQ_NUM 123
 
-#define I2C_REF_CLK_HZ 50000000 /* 50MHz */
+#define FI2C_CLK_FREQ_HZ 50000000 /* 50MHz */
 
 /* SDIO */
 #if !defined(__ASSEMBLER__)
 enum
 {
-    FSDIO_HOST_INSTANCE_0 = 0,
-    FSDIO_HOST_INSTANCE_1,
+    FSDIO0_ID = 0,
+    FSDIO1_ID = 1,
 
-    FSDIO_HOST_INSTANCE_NUM
+    FSDIO_NUM
 };
 #endif
 
-#define FSDIO_HOST_0_BASE_ADDR 0x28000000U
-#define FSDIO_HOST_1_BASE_ADDR 0x28001000U
+#define FSDIO0_BASE_ADDR 0x28000000U
+#define FSDIO1_BASE_ADDR 0x28001000U
 
-#define FSDIO_HOST_0_IRQ_NUM 104U
-#define FSDIO_HOST_1_IRQ_NUM 105U
+#define FSDIO0_IRQ_NUM 104U
+#define FSDIO1_IRQ_NUM 105U
 
-#define FSDIO_CLK_RATE_HZ (1200000000UL) /* 1.2GHz */
+#define FSDIO_CLK_FREQ_HZ (1200000000UL) /* 1.2GHz */
 
 /* NAND */
 #define FNAND_NUM 1U
 #define FNAND_INSTANCE0 0U
-#define FNAND_BASEADDRESS 0x28002000U
+#define FNAND_BASE_ADDR 0x28002000U
 #define FNAND_IRQ_NUM (106U)
 #define FNAND_CONNECT_MAX_NUM 1U
 
@@ -519,13 +538,12 @@ enum
 
 /* ADC */
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    FADC_INSTANCE_0 = 0,
-    FADC_INSTANCE_1,
+    FADC0_ID = 0,
 
-    FADC_INSTANCE_NUM
-} FAdcInstance;
+    FADC_NUM
+};
 
 typedef enum
 {
@@ -543,27 +561,25 @@ typedef enum
 
 #endif
 
-#define FADC0_CONTROL_BASE 0x2807B000U
-#define FADC1_CONTROL_BASE 0x2807C000U
+#define FADC0_BASE_ADDR 0x2807B000U
 
-#define FADC0_INTR_IRQ 264U
-#define FADC1_INTR_IRQ 265U
+#define FADC0_IRQ_NUM 264U
 
 /* PWM */
 #if !defined(__ASSEMBLER__)
-typedef enum
+enum
 {
-    FPWM_INSTANCE_0 = 0,
-    FPWM_INSTANCE_1,
-    FPWM_INSTANCE_2,
-    FPWM_INSTANCE_3,
-    FPWM_INSTANCE_4,
-    FPWM_INSTANCE_5,
-    FPWM_INSTANCE_6,
-    FPWM_INSTANCE_7,
-
-    FPWM_INSTANCE_NUM
-} FPwmInstance;
+    FPWM0_ID = 0,
+    FPWM1_ID = 1,
+    FPWM2_ID,
+    FPWM3_ID,
+    FPWM4_ID,
+    FPWM5_ID,
+    FPWM6_ID,
+    FPWM7_ID,
+
+    FPWM_NUM
+};
 
 typedef enum
 {
@@ -574,26 +590,26 @@ typedef enum
 } FPwmChannel;
 #endif
 
-#define FPWM_CONTROL_BASE 0x2804A000U
-
-#define FPWM_CLK 50000000U /* 50MHz */
-
-#define FPWM0_INTR_IRQ 205U
-#define FPWM1_INTR_IRQ 206U
-#define FPWM2_INTR_IRQ 207U
-#define FPWM3_INTR_IRQ 208U
-#define FPWM4_INTR_IRQ 209U
-#define FPWM5_INTR_IRQ 210U
-#define FPWM6_INTR_IRQ 211U
-#define FPWM7_INTR_IRQ 212U
-#define FPWM8_INTR_IRQ 213U
-#define FPWM9_INTR_IRQ 214U
-#define FPWM10_INTR_IRQ 215U
-#define FPWM11_INTR_IRQ 216U
-#define FPWM12_INTR_IRQ 217U
-#define FPWM13_INTR_IRQ 218U
-#define FPWM14_INTR_IRQ 219U
-#define FPWM15_INTR_IRQ 220U
+#define FPWM_BASE_ADDR 0x2804A000U
+
+#define FPWM_CLK_FREQ_HZ 50000000U /* 50MHz */
+
+#define FPWM0_IRQ_NUM 205U
+#define FPWM1_IRQ_NUM 206U
+#define FPWM2_IRQ_NUM 207U
+#define FPWM3_IRQ_NUM 208U
+#define FPWM4_IRQ_NUM 209U
+#define FPWM5_IRQ_NUM 210U
+#define FPWM6_IRQ_NUM 211U
+#define FPWM7_IRQ_NUM 212U
+#define FPWM8_IRQ_NUM 213U
+#define FPWM9_IRQ_NUM 214U
+#define FPWM10_IRQ_NUM 215U
+#define FPWM11_IRQ_NUM 216U
+#define FPWM12_IRQ_NUM 217U
+#define FPWM13_IRQ_NUM 218U
+#define FPWM14_IRQ_NUM 219U
+#define FPWM15_IRQ_NUM 220U
 
 /* Semaphore */
 #define FSEMA0_ID               0U
@@ -606,14 +622,41 @@ typedef enum
 #define FLSD_CK_STOP_CONFIG0_HADDR  0x10U
 
 /* USB3 */
-#define FUSB3_ID_0         0U
-#define FUSB3_ID_1         1U
-#define FUSB3_NUM          2U
-#define FUSB3_XHCI_OFFSET  0x8000U
-#define FUSB3_0_BASE_ADDR  0x31A00000U
-#define FUSB3_1_BASE_ADDR  0x31A20000U
-#define FUSB3_0_IRQ_NUM    48U
-#define FUSB3_1_IRQ_NUM    49U
+#define FUSB3_ID_0 0U
+#define FUSB3_ID_1 1U
+#define FUSB3_NUM 2U
+#define FUSB3_XHCI_OFFSET 0x8000U
+#define FUSB3_0_BASE_ADDR 0x31A00000U
+#define FUSB3_1_BASE_ADDR 0x31A20000U
+#define FUSB3_0_IRQ_NUM 48U
+#define FUSB3_1_IRQ_NUM 49U
+
+/* DcDp */
+#if !defined(__ASSEMBLER__)
+
+typedef enum
+{
+    FDCDP_ID0 = 0,
+    FDCDP_ID1,
+
+    FDCDP_INSTANCE_NUM
+} FDcDpNum;
+
+#endif
+
+#define FDC_CTRL_BASE_OFFSET 0x32000000U
+
+#define FDC0_CHANNEL_BASE_OFFSET 0x32001000U
+#define FDC1_CHANNEL_BASE_OFFSET (FDC0_CHANNEL_BASE_OFFSET + 0x1000U)
+
+#define FDP0_CHANNEL_BASE_OFFSET 0x32004000U
+#define FDP1_CHANNEL_BASE_OFFSET (FDP0_CHANNEL_BASE_OFFSET + 0x1000U)
+
+#define FDP0_PHY_BASE_OFFSET 0x32300000U
+#define FDP1_PHY_BASE_OFFSET (FDP0_PHY_BASE_OFFSET + 0x100000U)
+
+#define FDCDP_IRQ_NUM 76
+
 /*****************************************************************************/
 
 #ifdef __cplusplus
diff --git a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c
index b29a9e0a2b0..c60770ce712 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c
+++ b/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c
@@ -14,7 +14,7 @@
  * FilePath: fiopad_config.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for io-pad function definition
+ * Description:  This file is for io-pad function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -93,6 +93,17 @@ void FIOPadSetSpimMux(u32 spim_id)
     }
 }
 
+static void FIOPadDumpGpioPin(FPinIndex pin, u32 gpio_id, u32 pin_id)
+{
+    FPinFunc func = FPIN_FUNC0;
+    FPinPull pull = FPIN_PULL_NONE;
+    FPinDrive drive = FPIN_DRV0;
+
+    FPinGetConfig(pin, &func, &pull, &drive);
+    FIOPAD_DEBUG("GPIO-%d-%d: func: %d, pull: %d, drive: %d",
+                 gpio_id, pin_id, func, pull, drive);
+}
+
 /**
  * @name: FIOPadSetGpioMux
  * @msg: set iopad mux for gpio
@@ -102,59 +113,71 @@ void FIOPadSetSpimMux(u32 spim_id)
  */
 void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
 {
-    if (FGPIO_ID_2 == gpio_id)
+    if (FGPIO2_ID == gpio_id)
     {
         switch (pin_id)
         {
-        case 11: /* gpio 2-a-11 */
-            FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
-            break;
-        case 12: /* gpio 2-a-12 */
-            FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
-            break;
-        case 13: /* gpio 2-a-13 */
-            FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
-            break;
-        case 14: /* gpio 2-a-14 */
-            FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
-            break;
-        case 15: /* gpio 2-a-15 */
-            FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
-            break;
+            case 11: /* gpio 2-a-11 */
+                FPinSetFunc(FIOPAD_N49, FPIN_FUNC0);
+                break;
+            case 12: /* gpio 2-a-12 */
+                FPinSetFunc(FIOPAD_L51, FPIN_FUNC0);
+                break;
+            case 13: /* gpio 2-a-13 */
+                FPinSetFunc(FIOPAD_L49, FPIN_FUNC0);
+                break;
+            case 14: /* gpio 2-a-14 */
+                FPinSetFunc(FIOPAD_N53, FPIN_FUNC0);
+                break;
+            case 15: /* gpio 2-a-15 */
+                FPinSetFunc(FIOPAD_J53, FPIN_FUNC0);
+                break;
         }
     }
-    else if (FGPIO_ID_3 == gpio_id)
+    else if (FGPIO3_ID == gpio_id)
     {
         switch (pin_id)
         {
-        case 3: /* gpio 3-a-3 */
-            FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
-            break;
-        case 4: /* gpio 3-a-4 */
-            FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
-            break;
-        case 5: /* gpio 3-a-5 */
-            FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
-            break;
-        case 6: /* gpio 3-a-6 */
-            FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
-            break;
-        default:
-            break;
+            case 3: /* gpio 3-a-3 */
+                FPinSetFunc(FIOPAD_A33, FPIN_FUNC6);
+                break;
+            case 4: /* gpio 3-a-4 */
+                FPinSetFunc(FIOPAD_C33, FPIN_FUNC6);
+                break;
+            case 5: /* gpio 3-a-5 */
+                FPinSetFunc(FIOPAD_C31, FPIN_FUNC6);
+                break;
+            case 6: /* gpio 3-a-6 */
+                FPinSetFunc(FIOPAD_A31, FPIN_FUNC6);
+                break;
+            default:
+                break;
         }
     }
-    else if (FGPIO_ID_4 == gpio_id)
+    else if (FGPIO4_ID == gpio_id)
     {
         switch (pin_id)
         {
-        case 5: /* gpio 4-a-5 */
-            FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
-            break;
-        case 9: /* gpio 4-a-9 */
-            FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
-            break;
-        default:
-            break;
+            case 5: /* gpio 4-a-5 */
+                FPinSetFunc(FIOPAD_W51, FPIN_FUNC6);
+                break;
+            case 9: /* gpio 4-a-9 */
+                FPinSetFunc(FIOPAD_U53, FPIN_FUNC6);
+                break;
+            case 10: /* gpio 4-a-10 */
+                FPinSetFunc(FIOPAD_AE49, FPIN_FUNC6);
+                break;
+            case 11: /* gpio 4-a-11 */
+                FPinSetFunc(FIOPAD_AC49, FPIN_FUNC6);
+                break;
+            case 12: /* gpio 4-a-12 */
+                FPinSetFunc(FIOPAD_AE47, FPIN_FUNC6);
+                break;
+            case 13: /* gpio 4-a-13 */
+                FPinSetFunc(FIOPAD_AA47, FPIN_FUNC6);
+                break;
+            default:
+                break;
         }
     }
 }
@@ -168,15 +191,15 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
  */
 void FIOPadSetCanMux(u32 can_id)
 {
-    if (can_id == FCAN_INSTANCE_0)
+    if (can_id == FCAN0_ID)
     {
-        /* mio0 */
+		/* can0 */
         FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */
         FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */
     }
-    else if (can_id == FCAN_INSTANCE_1)
+    else if (can_id == FCAN1_ID)
     {
-        /* mio1 */
+		/* can1 */
         FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */
         FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */
     }
@@ -196,7 +219,7 @@ void FIOPadSetCanMux(u32 can_id)
 void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
 {
 
-    if (qspi_id == FQSPI_INSTANCE_0)
+    if (qspi_id == FQSPI0_ID)
     {
         /* add sck, io0-io3 iopad multiplex */
     }
@@ -232,358 +255,325 @@ void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
  */
 void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
 {
-    FASSERT(pwm_id < FPWM_INSTANCE_NUM);
+    FASSERT(pwm_id < FPWM_NUM);
     FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
 
     switch (pwm_id)
     {
-    case FPWM_INSTANCE_0:
-        if (pwm_channel == 0)
+        case FPWM0_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
+            }
+            break;
+
+        case FPWM1_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
+            }
+            break;
+
+        case FPWM2_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
+            }
+            break;
+
+        case FPWM3_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
+            }
+            break;
+
+        case FPWM4_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
+            }
+            break;
+
+        case FPWM5_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
+            }
+            break;
+
+        case FPWM6_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
+            }
+            break;
+
+        case FPWM7_ID:
+            if (pwm_channel == 0)
+            {
+                FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
+            }
+            if (pwm_channel == 1)
+            {
+                FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
+            }
+            break;
+
+        default:
+            FIOPAD_ERROR("pwm id is error.\r\n");
+            break;
+    }
+}
+
+
+/**
+ * @name: FIOPadSetAdcMux
+ * @msg: set iopad mux for adc
+ * @return {*}
+ * @param {u32} adc_id, id of adc instance
+ * @param {u32} adc_channel, id of adc channel
+ */
+void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
+{
+    if (adc_id == FADC0_ID)
+    {
+        switch (adc_channel)
         {
-            FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */
+            case FADC_CHANNEL_0:
+                FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
+                break;
+            case FADC_CHANNEL_1:
+                FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
+                break;
+            case FADC_CHANNEL_2:
+                FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
+                break;
+            case FADC_CHANNEL_3:
+                FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
+                break;
+            case FADC_CHANNEL_4:
+                FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
+                break;
+            case FADC_CHANNEL_5:
+                FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
+                break;
+            case FADC_CHANNEL_6:
+                FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
+                break;
+            case FADC_CHANNEL_7:
+                FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
+                break;
+            default:
+                FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+                break;
         }
-        if (pwm_channel == 1)
+    }
+    else
+    {
+        FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+    }
+}
+
+/**
+ * @name: FIOPadSetMioMux
+ * @msg: set iopad mux for mio
+ * @return {*}
+ * @param {u32} mio_id, instance id of i2c
+ */
+void FIOPadSetMioMux(u32 mio_id)
+{
+    switch (mio_id)
+    {
+        case FMIO0_ID:
         {
-            FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_1:
-        if (pwm_channel == 0)
+        case FMIO1_ID:
         {
-            FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO2_ID:
         {
-            FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */
+            FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_2:
-        if (pwm_channel == 0)
+        case FMIO3_ID:
         {
-            FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */
+            FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO4_ID:
         {
-            FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */
+            FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_3:
-        if (pwm_channel == 0)
+        case FMIO5_ID:
         {
-            FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */
+            FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO6_ID:
         {
-            FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_4:
-        if (pwm_channel == 0)
+        case FMIO7_ID:
         {
-            FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */
+            FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO8_ID:
         {
-            FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_5:
-        if (pwm_channel == 0)
+        case FMIO9_ID:
         {
-            FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */
+            FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO10_ID:
         {
-            FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */
+            FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_6:
-        if (pwm_channel == 0)
+        case FMIO11_ID:
         {
-            FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */
+            FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO12_ID:
         {
-            FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */
+            FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
         }
         break;
-
-    case FPWM_INSTANCE_7:
-        if (pwm_channel == 0)
+        case FMIO13_ID:
         {
-            FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */
+            FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
         }
-        if (pwm_channel == 1)
+        break;
+        case FMIO14_ID:
         {
-            FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */
+            FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
         }
         break;
-
-    default:
-        FIOPAD_ERROR("pwm id is error.\r\n");
+        case FMIO15_ID:
+        {
+            FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
+        }
         break;
+        default:
+            break;
     }
 }
 
-
 /**
- * @name: FIOPadSetAdcMux
- * @msg: set iopad mux for adc
+ * @name: FIOPadSetTachoMux
+ * @msg: set iopad mux for pwm_in
  * @return {*}
- * @param {u32} adc_id, id of adc instance
- * @param {u32} adc_channel, id of adc channel
+ * @param {u32} pwm_in_id, instance id of tacho
  */
-void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
+void FIOPadSetTachoMux(u32 pwm_in_id)
 {
-    if (adc_id == FADC_INSTANCE_0)
+    switch (pwm_in_id)
     {
-        switch (adc_channel)
-        {
-        case FADC_CHANNEL_0:
-            FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */
+        case FTACHO0_ID:
+            FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_1:
-            FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */
+        case FTACHO1_ID:
+            FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_2:
-            FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */
+        case FTACHO2_ID:
+            FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_3:
-            FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */
+        case FTACHO3_ID:
+            FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_4:
-            FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */
+        case FTACHO4_ID:
+            FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_5:
-            FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */
+        case FTACHO5_ID:
+            FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
             break;
-        case FADC_CHANNEL_6:
-            FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */
+        case FTACHO6_ID:
+            FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_7:
-            FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */
+        case FTACHO7_ID:
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
             break;
-        default:
-            FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
+        case FTACHO8_ID:
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
             break;
-        }
-    }
-    else if (adc_id == FADC_INSTANCE_1)
-    {
-        switch (adc_channel)
-        {
-        case FADC_CHANNEL_0:
-            FPinSetFunc(FIOPAD_G47, FPIN_FUNC7); /* adc1-0: func 7 */
+        case FTACHO9_ID:
+            FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_1:
-            FPinSetFunc(FIOPAD_J47, FPIN_FUNC7); /* adc1-1: func 7 */
+        case FTACHO10_ID:
+            FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_2:
-            FPinSetFunc(FIOPAD_J49, FPIN_FUNC7); /* adc1-2: func 7 */
+        case FTACHO11_ID:
+            FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_3:
-            FPinSetFunc(FIOPAD_N49, FPIN_FUNC7); /* adc1-3: func 7 */
+        case FTACHO12_ID:
+            FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_4:
-            FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc1-4: func 7 */
+        case FTACHO13_ID:
+            FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_5:
-            FPinSetFunc(FIOPAD_L49, FPIN_FUNC7); /* adc1-5: func 7 */
+        case FTACHO14_ID:
+            FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
             break;
-        case FADC_CHANNEL_6:
-            FPinSetFunc(FIOPAD_N53, FPIN_FUNC7); /* adc1-6: func 7 */
-            break;
-        case FADC_CHANNEL_7:
-            FPinSetFunc(FIOPAD_J53, FPIN_FUNC7); /* adc1-7: func 7 */
+        case FTACHO15_ID:
+            FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
             break;
         default:
-            FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
             break;
-        }
-    }
-    else
-    {
-        FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
-    }
-}
-
-/**
- * @name: FIOPadSetMioMux
- * @msg: set iopad mux for mio
- * @return {*}
- * @param {u32} mio_id, instance id of i2c
- */
-void FIOPadSetMioMux(u32 mio_id)
-{
-    switch (mio_id)
-    {
-    case MIO_INSTANCE_0:
-    {
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_1:
-    {
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_2:
-    {
-        FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_3:
-    {
-        FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_4:
-    {
-        FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_5:
-    {
-        FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_6:
-    {
-        FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_7:
-    {
-        FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_8:
-    {
-        FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_9:
-    {
-        FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_10:
-    {
-        FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_11:
-    {
-        FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_12:
-    {
-        FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_13:
-    {
-        FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_14:
-    {
-        FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_15:
-    {
-        FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */
-    }
-    break;
-    default:
-        break;
-    }
-}
-
-/**
- * @name: FIOPadSetTachoMux
- * @msg: set iopad mux for pwm_in
- * @return {*}
- * @param {u32} pwm_in_id, instance id of tacho
- */
-void FIOPadSetTachoMux(u32 pwm_in_id)
-{
-    switch (pwm_in_id)
-    {
-    case TACHO_INSTANCE_0:
-        FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_1:
-        FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_2:
-        FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_3:
-        FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_4:
-        FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_5:
-        FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_6:
-        FPinSetFunc(FIOPAD_C37, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_7:
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_8:
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_9:
-        FPinSetFunc(FIOPAD_A47, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_10:
-        FPinSetFunc(FIOPAD_C49, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_11:
-        FPinSetFunc(FIOPAD_A33, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_12:
-        FPinSetFunc(FIOPAD_C31, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_13:
-        FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_14:
-        FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2);
-        break;
-    case TACHO_INSTANCE_15:
-        FPinSetFunc(FIOPAD_G59, FPIN_FUNC2);
-        break;
-    default:
-        break;
     }
 }
 
@@ -597,23 +587,23 @@ void FIOPadSetUartMux(u32 uart_id)
 {
     switch (uart_id)
     {
-    case FUART0_ID:
-        FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
-        FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
-        break;
-    case FUART1_ID:
-        FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
-        break;
-    case FUART2_ID:
-        FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
-        break;
-    case FUART3_ID:
-        FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
-        FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
-        break;
-    default:
-        break;
+        case FUART0_ID:
+            FPinSetFunc(FIOPAD_J37, FPIN_FUNC4);
+            FPinSetFunc(FIOPAD_J39, FPIN_FUNC4);
+            break;
+        case FUART1_ID:
+            FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0);
+            break;
+        case FUART2_ID:
+            FPinSetFunc(FIOPAD_A47, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_A49, FPIN_FUNC0);
+            break;
+        case FUART3_ID:
+            FPinSetFunc(FIOPAD_L37, FPIN_FUNC2);
+            FPinSetFunc(FIOPAD_N35, FPIN_FUNC2);
+            break;
+        default:
+            break;
     }
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h
index 9d7a5691e8a..680ba76b2d1 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h
+++ b/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h
@@ -14,7 +14,7 @@
  * FilePath: fparameters.h
  * Date: 2022-02-11 13:33:28
  * LastEditTime: 2022-02-17 18:00:50
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c
index 8ab06f48375..ac4fb903af2 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c
+++ b/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c
@@ -14,7 +14,7 @@
  * FilePath: fiopad_config.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for io-pad function definition
+ * Description:  This file is for io-pad function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -63,24 +63,50 @@ void FIOPadSetSpimMux(u32 spim_id)
  */
 void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
 {
-    if (FGPIO_ID_3 == gpio_id)
+    if (FGPIO3_ID == gpio_id)
     {
         switch (pin_id)
         {
-        case 3: /* gpio 3-a-3 */
-            FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
-            break;
-        case 4: /* gpio 3-a-4 */
-            FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
-            break;
-        case 5: /* gpio 3-a-5 */
-            FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
-            break;
-        case 6: /* gpio 3-a-6 */
-            FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
-            break;
-        default:
-            break;
+            case 3: /* gpio 3-a-3 */
+                FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
+                break;
+            case 4: /* gpio 3-a-4 */
+                FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
+                break;
+            case 5: /* gpio 3-a-5 */
+                FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
+                break;
+            case 6: /* gpio 3-a-6 */
+                FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
+                break;
+            default:
+                break;
+        }
+    }
+    else if (FGPIO4_ID == gpio_id)
+    {
+        switch (pin_id)
+        {
+            case 5: /* gpio 4-a-5 */
+                FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
+                break;
+            case 9: /* gpio 4-a-9 */
+                FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
+                break;
+            case 10: /* gpio 4-a-10 */
+                FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
+                break;
+            case 11: /* gpio 4-a-11 */
+                FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
+                break;
+            case 12: /* gpio 4-a-12 */
+                FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
+                break;
+            case 13: /* gpio 4-a-13 */
+                FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
+                break;
+            default:
+                break;
         }
     }
 }
@@ -95,167 +121,167 @@ void FIOPadSetMioMux(u32 mio_id)
 {
     switch (mio_id)
     {
-    case MIO_INSTANCE_0:
-    {
-        FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_1:
-    {
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_2:
-    {
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_3:
-    {
-        FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_4:
-    {
-        FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_5:
-    {
-        FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_6:
-    {
-        FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_7:
-    {
-        FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_8:
-    {
-        FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_9:
-    {
-        FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
-        FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_10:
-    {
-        FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
-        FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_11:
-    {
-        FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_12:
-    {
-        FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
-        FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_13:
-    {
-        FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_14:
-    {
-        FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
-    }
-    break;
-    case MIO_INSTANCE_15:
-    {
-        FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
-        FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
-    }
-    break;
-    default:
-        break;
-    }
-}
-
-/**
- * @name: FIOPadSetTachoMux
- * @msg: set iopad mux for pwm_in
- * @return {*}
- * @param {u32} pwm_in_id, instance id of tacho
- */
-void FIOPadSetTachoMux(u32 pwm_in_id)
-{
-    switch (pwm_in_id)
-    {
-    case TACHO_INSTANCE_0:
-        FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
-        break;
-    case TACHO_INSTANCE_1:
-        FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
+        case FMIO0_ID:
+        {
+            FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_2:
-        FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
+        case FMIO1_ID:
+        {
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_3:
-        FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
+        case FMIO2_ID:
+        {
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_4:
-        FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
+        case FMIO3_ID:
+        {
+            FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_5:
-        FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
+        case FMIO4_ID:
+        {
+            FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_6:
-        FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
+        case FMIO5_ID:
+        {
+            FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_7:
-        FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
+        case FMIO6_ID:
+        {
+            FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_8:
-        FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
+        case FMIO7_ID:
+        {
+            FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_9:
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
+        case FMIO8_ID:
+        {
+            FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_10:
-        FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
+        case FMIO9_ID:
+        {
+            FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
+            FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_11:
-        FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
+        case FMIO10_ID:
+        {
+            FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
+            FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_12:
-        FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
+        case FMIO11_ID:
+        {
+            FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_13:
-        FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
+        case FMIO12_ID:
+        {
+            FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
+            FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_14:
-        FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
+        case FMIO13_ID:
+        {
+            FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
+        }
         break;
-    case TACHO_INSTANCE_15:
-        FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
+        case FMIO14_ID:
+        {
+            FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
+        }
         break;
-    default:
+        case FMIO15_ID:
+        {
+            FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
+            FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
+        }
         break;
+        default:
+            break;
+    }
+}
+
+/**
+ * @name: FIOPadSetTachoMux
+ * @msg: set iopad mux for pwm_in
+ * @return {*}
+ * @param {u32} pwm_in_id, instance id of tacho
+ */
+void FIOPadSetTachoMux(u32 pwm_in_id)
+{
+    switch (pwm_in_id)
+    {
+        case FTACHO0_ID:
+            FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
+            break;
+        case FTACHO1_ID:
+            FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
+            break;
+        case FTACHO2_ID:
+            FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
+            break;
+        case FTACHO3_ID:
+            FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
+            break;
+        case FTACHO4_ID:
+            FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
+            break;
+        case FTACHO5_ID:
+            FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
+            break;
+        case FTACHO6_ID:
+            FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
+            break;
+        case FTACHO7_ID:
+            FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
+            break;
+        case FTACHO8_ID:
+            FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
+            break;
+        case FTACHO9_ID:
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
+            break;
+        case FTACHO10_ID:
+            FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
+            break;
+        case FTACHO11_ID:
+            FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
+            break;
+        case FTACHO12_ID:
+            FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
+            break;
+        case FTACHO13_ID:
+            FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
+            break;
+        case FTACHO14_ID:
+            FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
+            break;
+        case FTACHO15_ID:
+            FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
+            break;
+        default:
+            break;
     }
 }
 
@@ -269,23 +295,23 @@ void FIOPadSetUartMux(u32 uart_id)
 {
     switch (uart_id)
     {
-    case FUART0_ID:
-        FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
-        FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
-        break;
-    case FUART1_ID:
-        FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
-        break;
-    case FUART2_ID:
-        FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
-        FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
-        break;
-    case FUART3_ID:
-        FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
-        FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
-        break;
-    default:
-        break;
+        case FUART0_ID:
+            FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
+            FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
+            break;
+        case FUART1_ID:
+            FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
+            break;
+        case FUART2_ID:
+            FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
+            FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
+            break;
+        case FUART3_ID:
+            FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
+            FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
+            break;
+        default:
+            break;
     }
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h
index 24b67ac1227..4948188f85e 100644
--- a/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h
+++ b/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h
@@ -14,7 +14,7 @@
  * FilePath: fparameters.h
  * Date: 2022-02-11 13:33:28
  * LastEditTime: 2022-02-17 18:00:50
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c
new file mode 100644
index 00000000000..7591b19fade
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fioctrl.c
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:29
+ * Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay)
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/2/22   init commit
+ */
+
+
+/***************************** Include Files *********************************/
+#include "fparameters.h"
+#include "fio.h"
+#include "fkernel.h"
+#include "fassert.h"
+#include "fdebug.h"
+
+#include "fioctrl.h"
+#include "fpinctrl.h"
+
+/************************** Constant Definitions *****************************/
+/* Bit[0] : 输入延迟功能使能  */
+#define FIOCTRL_DELAY_EN(delay_beg)                      BIT(delay_beg)
+#define FIOCTRL_INPUT_DELAY_OFF                          0
+
+/* Bit[3:1] : 输入延迟精调档位选择 */
+#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg)             GENMASK((delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg)     GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1))
+#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg)         SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1))
+
+/* Bit[6:4] : 输入延迟粗调档位选择 */
+#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg)               GENMASK((delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg)       GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4))
+#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg)           SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4))
+
+/* Bit[7] : 保留 */
+/* Bit[8] : 输出延迟功能使能 */
+
+/* Bit[11:9] : 输出延迟精调档位选择 */
+/* Bit [14:12] : 输出延迟粗调档位选择  */
+/* Bit [15] : 保留 */
+
+#define FIOCTRL_FUNC_BEG_OFF(reg_bit)   ((reg_bit) + 0)
+#define FIOCTRL_FUNC_END_OFF(reg_bit)   ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */
+#define FIOCTRL_PULL_BEG_OFF(reg_bit)   ((reg_bit) + 2)
+#define FIOCTRL_PULL_END_OFF(reg_bit)   ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */
+
+#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit)    ((reg_bit) + 0)
+#define FIOCTRL_DELAY_IN_END_OFF(reg_bit)    ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */
+#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit)   ((reg_bit) + 8)
+#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit)   ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */
+
+/* 芯片引脚控制寄存器的起止位置 */
+#define FIOCTRL_REG_OFFSET_MIN                           0x200
+#define FIOCTRL_REG_OFFSET_MAX                           0x22c
+
+/* 芯片引脚延时寄存器的起止位置 */
+#define FIOCTRL_DELAY_REG_OFFSET_MIN                     0x400
+#define FIOCTRL_DELAY_REG_OFFSET_MAX                     0x404
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOCTRL_DEBUG_TAG "FIOCTRL"
+#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_WARN(format, ...)  FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_INFO(format, ...)  FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off))
+#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func))
+#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull))
+
+#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off))
+#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay));
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+
+/**
+ * @name: FPinGetFunc
+ * @msg: 获取IO引脚当前的复用功能
+ * @return {FPinFunc} 当前的复用功能
+ * @param {FPinIndex} pin IO引脚索引
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+FPinFunc FPinGetFunc(const FPinIndex pin)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 func = GET_REG32_BITS(reg_val, func_end, func_beg);
+    FIOCTRL_ASSERT_FUNC(func);
+
+    return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg);
+}
+
+/**
+ * @name: FPinSetFunc
+ * @msg: 设置IO引脚复用功能
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinFunc} func IO复用功能
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+void FPinSetFunc(const FPinIndex pin, FPinFunc func)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+    FIOCTRL_ASSERT_FUNC(func);
+
+    u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit);
+    u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    reg_val &= ~GENMASK(func_end, func_beg);
+    reg_val |= SET_REG32_BITS(func, func_end, func_beg);
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinGetPull
+ * @msg: 获取IO引脚当前的上下拉设置
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值
+ */
+FPinPull FPinGetPull(const FPinIndex pin)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg);
+
+    FIOCTRL_ASSERT_PULL(pull);
+    return (FPinPull)pull;
+}
+
+/**
+ * @name: FPinSetPull
+ * @msg: 设置IO引脚当前的上下拉
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚索引
+ * @param {FPinPull} pull 上下拉设置
+ */
+void FPinSetPull(const FPinIndex pin, FPinPull pull)
+{
+    FIOCTRL_ASSERT_REG_OFF(pin);
+    FIOCTRL_ASSERT_PULL(pull);
+
+    u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit);
+    u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+
+    reg_val &= ~GENMASK(pull_end, pull_beg);
+    reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg);
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinGetDelay
+ * @msg: 获取IO引脚当前的延时设置
+ * @return {FPinDelay} 当前的延时设置
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {FPinDelayType} type 精调/粗调延时
+ */
+FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    u8 delay = 0;
+    const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FPIN_DELAY_FINE_TUNING == type)
+    {
+        delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); /* bit[3:1] delicate delay tune */
+    }
+    else if (FPIN_DELAY_COARSE_TUNING == type)
+    {
+        delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); /* bit[6:4] rough delay adjust */
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    FIOCTRL_ASSERT_DELAY(delay);
+    return (FPinDelay)delay;
+}
+
+
+/**
+ * @name: FPinGetDelayEn
+ * @msg: 获取IO引脚当前的延时使能标志位
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ */
+boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    boolean enabled = FALSE;
+    const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FIOCTRL_DELAY_EN(delay_beg) & reg_val)
+    {
+        enabled = TRUE;
+    }
+
+    return enabled;
+}
+
+/**
+ * @name: FPinSetDelay
+ * @msg: 设置IO引脚延时
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {FPinDelayType} type 精调/粗调延时
+ * @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用
+ */
+void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    FIOCTRL_ASSERT_DELAY(delay);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    if (FPIN_DELAY_FINE_TUNING == type)
+    {
+        reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg);
+        delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg);
+    }
+    else if (FPIN_DELAY_COARSE_TUNING == type)
+    {
+        reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg);
+        delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
+
+/**
+ * @name: FPinSetDelayEn
+ * @msg: 使能/去使能IO引脚延时
+ * @return {*}
+ * @param {FPinIndex} pin IO引脚延时设置索引
+ * @param {FPinDelayDir} dir 输入/输出延时
+ * @param {boolean} enable TRUE: 使能, FALSE: 去使能
+ */
+void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable)
+{
+    FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
+    u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off);
+    u32 delay_beg = 0, delay_end = 0;
+
+    if (FPIN_OUTPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off);
+    }
+    else if (FPIN_INPUT_DELAY == dir)
+    {
+        delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off);
+    }
+    else
+    {
+        FASSERT(0);
+    }
+
+    reg_val &= ~FIOCTRL_DELAY_EN(delay_beg);
+    if (enable)
+    {
+        reg_val |= FIOCTRL_DELAY_EN(delay_beg);
+    }
+
+    FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val);
+    return;
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h
new file mode 100644
index 00000000000..5d0caac525d
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fioctrl.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-18 08:25:35
+ * Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay)
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/2/22   init commit
+ */
+
+
+#ifndef  BOARD_D2000_FIOCTRL_H
+#define  BOARD_D2000_FIOCTRL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/***************************** Include Files *********************************/
+#include "ftypes.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define FIOCTRL_INDEX(offset, func_beg) \
+    { \
+        /* reg_off */   (offset),  \
+        /* reg_bit */   (func_beg) \
+    }
+
+/************************** Variable Definitions *****************************/
+#define FIOCTRL_CRU_CLK_OBV_PAD           (FPinIndex)FIOCTRL_INDEX(0x200, 24)
+#define FIOCTRL_SPI0_CSN0_PAD             (FPinIndex)FIOCTRL_INDEX(0x208, 16)
+#define FIOCTRL_SPI0_SCK_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 12)
+#define FIOCTRL_SPI0_SO_PAD               (FPinIndex)FIOCTRL_INDEX(0x208, 8)
+#define FIOCTRL_SPI0_SI_PAD               (FPinIndex)FIOCTRL_INDEX(0x208, 4)
+
+#define FIOCTRL_TJTAG_TDI_PAD             (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */
+#define FIOCTRL_SWDITMS_SWJ_PAD           (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */
+
+#define FIOCTRL_NTRST_SWJ_PAD             (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */
+#define FIOCTRL_SWDO_SWJ_PAD              (FPinIndex)FIOCTRL_INDEX(0x204, 8)  /* can1-rx: func 1 */
+
+#define FIOCTRL_I2C0_SCL_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */
+#define FIOCTRL_I2C0_SDA_PAD              (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */
+#define FIOCTRL_ALL_PLL_LOCK_PAD          (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */
+#define FIOCTRL_CRU_CLK_OBV_PAD           (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */
+#define FIOCTRL_SWDO_SWJ_PAD              (FPinIndex)FIOCTRL_INDEX(0x204, 8)  /* i2c2-scl: func 2 */
+#define FIOCTRL_TDO_SWJ_IN_PAD            (FPinIndex)FIOCTRL_INDEX(0x204, 4)  /* i2c2-sda: func 2 */
+#define FIOCTRL_HDT_MB_DONE_STATE_PAD     (FPinIndex)FIOCTRL_INDEX(0x204, 0)  /* i2c3-scl: func 2 */
+#define FIOCTRL_HDT_MB_FAIL_STATE_PAD     (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */
+
+#define FIOCTRL_UART_2_RXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x210, 0)  /* spi1_csn0: func 1 */
+#define FIOCTRL_UART_2_TXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */
+#define FIOCTRL_UART_3_RXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */
+#define FIOCTRL_UART_3_TXD_PAD            (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */
+#define FIOCTRL_QSPI_CSN2_PAD             (FPinIndex)FIOCTRL_INDEX(0x214, 8)  /* spi1_csn1: func 1 */
+#define FIOCTRL_QSPI_CSN3_PAD             (FPinIndex)FIOCTRL_INDEX(0x214, 4)  /* spi1_csn2: func 1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h b/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h
new file mode 100644
index 00000000000..61a1943a5b4
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fparameters.h
+ * Date: 2022-02-10 14:53:42
+ * LastEditTime: 2022-02-17 18:01:11
+ * Description:  This file is for
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ */
+
+#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H
+#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#if !defined(__ASSEMBLER__)
+#include "ftypes.h"
+#endif
+
+#define CORE0_AFF 0x0
+#define CORE1_AFF 0x1
+#define CORE2_AFF 0x100
+#define CORE3_AFF 0x101
+
+
+/* cache */
+#define CACHE_LINE_ADDR_MASK 0x3F
+#define CACHE_LINE 64U
+
+
+/*  Device register address */
+#define FDEV_BASE_ADDR 0x28000000
+#define FDEV_END_ADDR 0x2FFFFFFF
+
+/* PCI  */
+
+#define FPCIE_NUM 1
+#define FPCIE0_ID 0
+#define FPCIE0_MISC_IRQ_NUM 59
+
+#define FPCIE_CFG_MAX_NUM_OF_BUS 256
+#define FPCIE_CFG_MAX_NUM_OF_DEV 32
+#define FPCIE_CFG_MAX_NUM_OF_FUN 8
+
+#define FPCI_CONFIG_BASE_ADDR 0x40000000
+#define FPCI_CONFIG_REG_LENGTH 0x10000000
+
+#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000
+#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000
+
+#define FPCI_MEM32_BASE_ADDR 0x58000000
+#define FPCI_MEM32_REG_LENGTH 0x27ffffff
+
+#define FPCI_MEM64_BASE_ADDR 0x1000000000
+#define FPCI_MEM64_REG_LENGTH 0x1000000000
+
+#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000
+#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000
+#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000
+#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000
+#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000
+#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000
+
+#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000
+#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000
+
+#define FPCI_INTA_IRQ_NUM     60
+#define FPCI_INTB_IRQ_NUM     61
+#define FPCI_INTC_IRQ_NUM     62
+#define FPCI_INTD_IRQ_NUM     63
+
+#define FPCI_NEED_SKIP        1
+
+/* platform ahci host */
+#define PLAT_AHCI_HOST_MAX_COUNT 5
+#define AHCI_BASE_0     0
+#define AHCI_BASE_1     0
+#define AHCI_BASE_2     0
+#define AHCI_BASE_3     0
+#define AHCI_BASE_4     0
+
+#define AHCI_IRQ_0      0
+#define AHCI_IRQ_1      0
+#define AHCI_IRQ_2      0
+#define AHCI_IRQ_3      0
+#define AHCI_IRQ_4      0
+
+// timer
+#define GENERIC_TIMER_NS_IRQ_NUM 30
+#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ
+
+// UART
+
+#define FUART_NUM 4
+#define FUART_REG_LENGTH 0x18000
+
+#define FUART0_ID 0
+#define FUART0_IRQ_NUM 38
+#define FUART0_BASE_ADDR 0x28000000
+#define FUART0_CLK_FREQ_HZ 48000000
+
+#define FUART1_ID 1
+#define FUART1_IRQ_NUM 39
+#define FUART1_BASE_ADDR 0x28001000
+#define FUART1_CLK_FREQ_HZ 48000000
+
+#define FUART2_ID 2
+#define FUART2_IRQ_NUM 40
+#define FUART2_BASE_ADDR 0x28002000
+#define FUART2_CLK_FREQ_HZ 48000000
+
+#define FUART3_BASE_ADDR 0x28003000
+#define FUART3_ID 3
+#define FUART3_IRQ_NUM 41
+#define FUART3_CLK_FREQ_HZ 48000000
+
+#define FT_STDOUT_BASE_ADDRESS FUART1_BASE_ADDR
+#define FT_STDIN_BASE_ADDRESS FUART1_BASE_ADDR
+
+/****** GIC v3  *****/
+#define FT_GICV3_INSTANCES_NUM 1U
+#define GICV3_REG_LENGTH 0x00009000
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define GICV3_MAX_INTR_PRIO_VAL 240U
+#define GICV3_INTR_PRIO_MASK 0x000000f0U
+#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count         */
+#define SGI_INT_MAX 16
+#define SPI_START_INT_NUM 32 /* SPI start at ID32        */
+#define PPI_START_INT_NUM 16 /* PPI start at ID16        */
+#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */
+#define GICV3_BASE_ADDR 0x29900000U
+#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0)
+#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U)
+#define GICV3_RD_OFFSET (2U << 16)
+#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM
+
+/* GPIO */
+#define FGPIO0_BASE_ADDR  0x28004000
+#define FGPIO1_BASE_ADDR  0x28005000
+
+#define FGPIO0_ID      0
+#define FGPIO1_ID      1
+#define FGPIO_NUM      2
+
+#define FGPIO0_IRQ_NUM 42 /* gpio0 irq number */
+#define FGPIO1_IRQ_NUM 43 /* gpio1 irq number */
+
+/* SPI */
+#define FSPI0_BASE_ADDR 0x2800c000
+#define FSPI1_BASE_ADDR 0x28013000
+#define FSPI0_ID   0
+#define FSPI1_ID   1
+#define FSPI_CLK_FREQ_HZ 48000000
+#define FSPI_NUM 2
+#define FSPI0_IRQ_NUM 50
+#define FSPI1_IRQ_NUM 51
+
+/* QSPI */
+/* QSPI */
+#if !defined(__ASSEMBLER__)
+typedef enum
+{
+    FQSPI0_ID = 0,
+
+    FQSPI_NUM
+} FQspiInstance;
+
+/* FQSPI cs 0_3, chip number */
+enum
+{
+    FQSPI_CS_0 = 0,
+    FQSPI_CS_1 = 1,
+    FQSPI_CS_2 = 2,
+    FQSPI_CS_3 = 3,
+    FQSPI_CS_NUM
+};
+#endif
+
+#define FQSPI_BASE_ADDR 0x28014000
+#define FQSPI_MEM_START_ADDR 0x0
+#define FQSPI_MEM_END_ADDR 0x1FFFFFFF
+
+/* IOCTRL */
+#define FIOCTRL_REG_BASE_ADDR  0x28180000
+
+// Gic
+#define ARM_GIC_NR_IRQS 1024
+#define ARM_GIC_IRQ_START 0
+#define FGIC_NUM 1
+
+/* can */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FCAN0_ID = 0,
+    FCAN1_ID = 1,
+    FCAN2_ID = 2,
+
+    FCAN_NUM
+};
+#endif
+
+#define FCAN_CLK_FREQ_HZ 600000000
+
+#define FCAN0_BASE_ADDR 0x28207000
+#define FCAN1_BASE_ADDR 0x28207400
+#define FCAN2_BASE_ADDR 0x28207800
+#define FCAN0_IRQ_NUM 119
+#define FCAN1_IRQ_NUM 123
+#define FCAN2_IRQNUM 124
+
+/* I2C */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FI2C0_ID = 0,
+    FI2C1_ID = 1,
+    FI2C2_ID,
+    FI2C3_ID,
+
+    FI2C_NUM
+};
+#endif
+
+#define FI2C0_BASE_ADDR 0x28006000
+#define FI2C1_BASE_ADDR 0x28007000
+#define FI2C2_BASE_ADDR 0x28008000
+#define FI2C3_BASE_ADDR 0x28009000
+
+#define FI2C0_IRQ_NUM 44
+#define FI2C1_IRQ_NUM 45
+#define FI2C2_IRQ_NUM 46
+#define FI2C3_IRQ_NUM 47
+
+#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */
+
+/* WDT */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FWDT0_ID = 0,
+    FWDT1_ID = 1,
+
+    FWDT_NUM
+} ;
+#endif
+
+#define FWDT0_REFRESH_BASE_ADDR 0x2800a000
+#define FWDT1_REFRESH_BASE_ADDR 0x28016000
+
+#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000)
+
+#define FWDT0_IRQ_NUM 48
+#define FWDT1_IRQ_NUM 49
+
+#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */
+
+/* SDCI */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FSDMMC0_ID = 0,
+    FSDMMC_NUM
+};
+#endif
+
+#define FSDMMC0_BASE_ADDR 0x28207C00
+
+#define FSDMMC0_DMA_IRQ_NUM 52
+#define FSDMMC0_CMD_IRQ_NUM 53
+#define FSDMMC0_ERR_IRQ_NUM 54
+
+#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */
+#define SDCI_SEN_DEBNCE 10000000     /* 10 MHz */
+#define SDCI_CMD_TIMEOUT 10000000    /* 1s */
+#define SDCI_DATA_TIMEOUT 40000000   /* 4S */
+
+/* GMAC */
+#if !defined(__ASSEMBLER__)
+enum
+{
+    FGMAC0_ID = 0,
+    FGMAC1_ID,
+
+    FGMAC_NUM
+};
+#endif
+#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */
+
+#define FGMAC0_BASE_ADDR 0x2820C000
+#define FGMAC1_BASE_ADDR 0x28210000
+
+#define FGMAC0_IRQ_NUM 81
+#define FGMAC1_IRQ_NUM 82
+
+#define FGMAC_DMA_MIN_ALIGN 128
+#define FGMAC_MAX_PACKET_SIZE 1600
+
+/*RTC*/
+#define RTC_CONTROL_BASE 0x2800D000
+
+#define FT_CPUS_NR CORE_NUM
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/common/Kconfig b/bsp/phytium/libraries/standalone/common/Kconfig
index aa2fd1c471c..221bbbaca2f 100644
--- a/bsp/phytium/libraries/standalone/common/Kconfig
+++ b/bsp/phytium/libraries/standalone/common/Kconfig
@@ -1,6 +1,5 @@
 
 
-
 choice DEBUG_LOG_LEVEL
     prompt "Debug Log Level"
     default LOG_ERROR
@@ -31,7 +30,7 @@ config USE_DEFAULT_INTERRUPT_CONFIG
     bool
     prompt "Use default interrupt configuration"
     default y
-    help
+    help 
         "If this option is not selected, core0 is used as the main core by default and all interrupt driver modules are initialized. Non-0 core initializes only the necessary interrupt driver modules.  If this option is selected, the developer needs to initiate each module independently  "
     if USE_DEFAULT_INTERRUPT_CONFIG
         choice INTERRUPT_ROLE_SELECT
@@ -41,8 +40,8 @@ config USE_DEFAULT_INTERRUPT_CONFIG
             "Select Interrupt role"
 
         config INTERRUPT_ROLE_MASTER
-            bool "use master role"
-
+            bool "use master role"    
+        
         config INTERRUPT_ROLE_SLAVE
             bool "use slave role"
 
@@ -55,10 +54,16 @@ config LOG_EXTRA_INFO
     help
         Print debug information with source file name and source code line num.
 
+config LOG_DISPALY_CORE_NUM
+    bool "Debug Display with Core"
+    default n
+    help
+        To display CPU core information during debugging
+
 config BOOTUP_DEBUG_PRINTS
     bool
     prompt "Bootup debug"
     default n
     help
         Enable Bootup debug printing
-
+	
diff --git a/bsp/phytium/libraries/standalone/common/fassert.c b/bsp/phytium/libraries/standalone/common/fassert.c
index ec1ade974ba..ad23aeee268 100644
--- a/bsp/phytium/libraries/standalone/common/fassert.c
+++ b/bsp/phytium/libraries/standalone/common/fassert.c
@@ -11,16 +11,16 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: ft_assert.c
+ * FilePath: fassert.c
  * Date: 2021-04-07 09:53:07
  * LastEditTime: 2022-02-17 18:04:28
- * Description:  This files is for assertion implmentation
+ * Description:  This file is for assertion implmentation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021.4       init commit
- * 1.1   zhugengyu  2022.3       re-define assert macro
+ * 1.0   huanghe    2021/4/5       init commit
+ * 1.1   zhugengyu  2022/3/7       re-define assert macro
  */
 
 /***************************** Include Files *********************************/
@@ -92,7 +92,9 @@ static void FAssertCallback(const char *file, s32 line, int ret)
 void FAssertSetCB(FAssertCB cb)
 {
     if (NULL != cb)
+    {
         assert_info.cb = cb;
+    }
 }
 
 /**
diff --git a/bsp/phytium/libraries/standalone/common/fassert.h b/bsp/phytium/libraries/standalone/common/fassert.h
index 9bb44362ff2..47e3a44147e 100644
--- a/bsp/phytium/libraries/standalone/common/fassert.h
+++ b/bsp/phytium/libraries/standalone/common/fassert.h
@@ -14,29 +14,27 @@
  * FilePath: fassert.h
  * Date: 2021-04-07 09:53:07
  * LastEditTime: 2022-02-17 18:04:35
- * Description:  This files is for assertion defintion
+ * Description:  This file is for assertion defintion.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021.4       init commit
- * 1.1   zhugengyu  2022.3       re-define assert macro
+ * 1.0   huanghe    2021/4/5       init commit
+ * 1.1   zhugengyu  2022/3/7       re-define assert macro
  */
 
-#ifndef FT_ASSERT_H
-#define FT_ASSERT_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FASSERT_H
+#define FASSERT_H
 
 /***************************** Include Files *********************************/
 #include "fprintk.h"
 #include "ferror_code.h"
 #include "ftypes.h"
 
-/************************** Constant Definitions *****************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 /**************************** Type Definitions *******************************/
 typedef enum
diff --git a/bsp/phytium/libraries/standalone/common/fdebug.c b/bsp/phytium/libraries/standalone/common/fdebug.c
index 2a6d906e592..60a5f70e778 100644
--- a/bsp/phytium/libraries/standalone/common/fdebug.c
+++ b/bsp/phytium/libraries/standalone/common/fdebug.c
@@ -11,18 +11,19 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: ft_debug.c
+ * FilePath: fdebug.c
  * Date: 2021-04-25 16:44:23
  * LastEditTime: 2022-02-17 18:04:50
- * Description:  This files is for
+ * Description:  This file is for providing debug functions.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ *  1.0  zhugengyu  2022/10/27   rename file name
  */
 
 #include "fdebug.h"
-#include "fprintf.h"
+#include "fprintk.h"
 #include "stdio.h"
 
 #define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
@@ -33,19 +34,25 @@ void FtDumpHexByte(const u8 *ptr, u32 buflen)
 
     for (i = 0; i < buflen; i += 16)
     {
-        printf("%p: ", ptr + i);
+        f_printk("%p: ", ptr + i);
 
         for (j = 0; j < 16; j++)
             if (i + j < buflen)
-                printf("%02X ", buf[i + j]);
+            {
+                f_printk("%02X ", buf[i + j]);
+            }
             else
-                printf("   ");
-        printf(" ");
+            {
+                f_printk("   ");
+            }
+        f_printk(" ");
 
         for (j = 0; j < 16; j++)
             if (i + j < buflen)
-                printf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
-        printf("\r\n");
+            {
+                f_printk("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
+            }
+        f_printk("\r\n");
     }
 }
 
@@ -56,19 +63,25 @@ void FtDumpHexByteDebug(const u8 *ptr, u32 buflen)
 
     for (i = 0; i < buflen; i += 16)
     {
-        f_printf("%x: ", ptr + i);
+        f_printk("%x: ", ptr + i);
 
         for (j = 0; j < 16; j++)
             if (i + j < buflen)
-                f_printf("%x ", buf[i + j]);
+            {
+                f_printk("%x ", buf[i + j]);
+            }
             else
-                f_printf("   ");
-        f_printf(" ");
+            {
+                f_printk("   ");
+            }
+        f_printk(" ");
 
         for (j = 0; j < 16; j++)
             if (i + j < buflen)
-                f_printf("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
-        f_printf("\r\n");
+            {
+                f_printk("%c", (char)(__is_print(buf[i + j]) ? buf[i + j] : '.'));
+            }
+        f_printk("\r\n");
     }
 }
 
@@ -81,26 +94,28 @@ void FtDumpHexWord(const u32 *ptr, u32 buflen)
     buflen = buflen / 4;
     for (i = 0; i < buflen; i += 4)
     {
-        printf("%p: ", ptr + i);
+        f_printk("%p: ", ptr + i);
 
         for (j = 0; j < 4; j++)
         {
             if (i + j < buflen)
             {
-                printf("%lx ", buf[i + j]);
+                f_printk("%lx ", buf[i + j]);
             }
             else
             {
-                printf("   ");
+                f_printk("   ");
             }
         }
 
-        printf(" ");
+        f_printk(" ");
 
         for (j = 0; j < 16; j++)
             if (i + j < buflen)
-                printf("%c", (char)(__is_print(char_data[i + j]) ? char_data[i + j] : '.'));
+            {
+                f_printk("%c", (char)(__is_print(char_data[i + j]) ? char_data[i + j] : '.'));
+            }
 
-        printf("\r\n");
+        f_printk("\r\n");
     }
 }
diff --git a/bsp/phytium/libraries/standalone/common/fdebug.h b/bsp/phytium/libraries/standalone/common/fdebug.h
index 84f283b75e9..63d8a218fc7 100644
--- a/bsp/phytium/libraries/standalone/common/fdebug.h
+++ b/bsp/phytium/libraries/standalone/common/fdebug.h
@@ -14,18 +14,34 @@
  * FilePath: fdebug.h
  * Date: 2021-04-07 09:53:07
  * LastEditTime: 2022-02-17 18:04:58
- * Description:  This files is for debug functions
+ * Description:  This file is for showing debug api.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu  2022/10/27   rename file name
  */
 
-#ifndef BSP_COMMON_FT_DEBUG_H
-#define BSP_COMMON_FT_DEBUG_H
+#ifndef FDEBUG_H
+#define FDEBUG_H
+
 #include <stdio.h>
 #include "sdkconfig.h"
 #include "ftypes.h"
+#include "fprintk.h"
+#ifdef CONFIG_USE_AMP
+#include "fsmp.h"
+#endif
+
+#if defined(CONFIG_USE_AMP)
+#include "fcpu_info.h"
+#endif
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 typedef enum
 {
@@ -76,7 +92,26 @@ typedef enum
 
 #define LOG_FORMAT(letter, format) LOG_COLOR_##letter " %s: " format LOG_RESET_COLOR "\r\n"
 
-#define PORT_KPRINTF printf
+#define PORT_KPRINTF f_printk
+
+#if defined(CONFIG_LOG_DISPALY_CORE_NUM)    
+    #define DISPALY_CORE_NUM() \
+        do {u32 cpu_id;                                                           \
+        GetCpuId(&cpu_id);                                                    \
+        PORT_KPRINTF("cpu%d:", cpu_id);                                      } while(0)
+#else
+#define DISPALY_CORE_NUM()
+#endif
+
+
+#ifdef CONFIG_USE_AMP
+#define LOG_SPIN_LOCK() SpinLock();
+#define LOG_SPIN_UNLOCK() SpinUnlock() ;
+#else
+#define LOG_SPIN_LOCK()
+#define LOG_SPIN_UNLOCK()
+#endif
+
 
 #ifndef CONFIG_LOG_EXTRA_INFO
 #define LOG_EARLY_IMPL(tag, format, log_level, log_tag_letter, ...)           \
@@ -84,7 +119,10 @@ typedef enum
     {                                                                         \
         if (LOG_LOCAL_LEVEL < log_level)                                      \
             break;                                                            \
+        LOG_SPIN_LOCK();                                                      \
+        DISPALY_CORE_NUM();                                                   \
         PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format), tag, ##__VA_ARGS__); \
+        LOG_SPIN_UNLOCK();                                                    \
     } while (0)
 #else
 #include <string.h>
@@ -95,6 +133,7 @@ typedef enum
     {                                                                         \
         if (LOG_LOCAL_LEVEL < log_level)                                      \
             break;                                                            \
+        DISPALY_CORE_NUM()  \
         PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format" @%s:%d"), tag, ##__VA_ARGS__, __FILENAME__, __LINE__); \
     } while (0)
 #endif
@@ -124,4 +163,9 @@ typedef enum
 
 void FtDumpHexWord(const u32 *ptr, u32 buflen);
 void FtDumpHexByte(const u8 *ptr, u32 buflen);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif // !
diff --git a/bsp/phytium/libraries/standalone/common/felf.c b/bsp/phytium/libraries/standalone/common/felf.c
new file mode 100644
index 00000000000..93b423c4258
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/common/felf.c
@@ -0,0 +1,987 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: felf.c
+ * Date: 2021-08-31 11:16:59
+ * LastEditTime: 2022-02-17 18:05:16
+ * Description:  This file is for providing elf functions.
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu  2022/10/27   rename file name
+ */
+
+#include <string.h>
+#include "fkernel.h"
+#include "felf.h"
+#include "fcache.h"
+#include "fdebug.h"
+#include "fprintk.h"
+/* This version doesn't work for 64-bit ABIs - Erik */
+
+/* These typedefs need to be handled better */
+typedef u32 Elf32_Addr;  /* Unsigned program address */
+typedef u32 Elf32_Off;   /* Unsigned file offset */
+typedef s32 Elf32_Sword; /* Signed large integer */
+typedef u32 Elf32_Word;  /* Unsigned large integer */
+typedef u16 Elf32_Half;  /* Unsigned medium integer */
+
+/* 64-bit ELF base types */
+typedef u64 Elf64_Addr;
+typedef u16 Elf64_Half;
+typedef s16 Elf64_SHalf;
+typedef u64 Elf64_Off;
+typedef s32 Elf64_Sword;
+typedef u32 Elf64_Word;
+typedef u64 Elf64_Xword;
+typedef s64 Elf64_Sxword;
+
+/* e_ident[] identification indexes */
+#define EI_MAG0 0       /* file ID */
+#define EI_MAG1 1       /* file ID */
+#define EI_MAG2 2       /* file ID */
+#define EI_MAG3 3       /* file ID */
+#define EI_CLASS 4      /* file class */
+#define EI_DATA 5       /* data encoding */
+#define EI_VERSION 6    /* ELF header version */
+#define EI_OSABI 7      /* OS/ABI specific ELF extensions */
+#define EI_ABIVERSION 8 /* ABI target version */
+#define EI_PAD 9        /* start of pad bytes */
+#define EI_NIDENT 16    /* Size of e_ident[] */
+
+/* ELF Header */
+typedef struct
+{
+    unsigned char e_ident[EI_NIDENT]; /* ELF Identification */
+    Elf32_Half e_type;                /* object file type */
+    Elf32_Half e_machine;             /* machine */
+    Elf32_Word e_version;             /* object file version */
+    Elf32_Addr e_entry;               /* virtual entry point */
+    Elf32_Off e_phoff;                /* program header table offset */
+    Elf32_Off e_shoff;                /* section header table offset */
+    Elf32_Word e_flags;               /* processor-specific flags */
+    Elf32_Half e_ehsize;              /* ELF header size */
+    Elf32_Half e_phentsize;           /* program header entry size */
+    Elf32_Half e_phnum;               /* number of program header entries */
+    Elf32_Half e_shentsize;           /* section header entry size */
+    Elf32_Half e_shnum;               /* number of section header entries */
+    Elf32_Half e_shstrndx;            /* section header table's "section
+                       header string table" entry offset */
+} Elf32_Ehdr;
+
+typedef struct
+{
+    unsigned char e_ident[EI_NIDENT]; /* ELF Identification */
+    Elf64_Half e_type;                /* object file type */
+    Elf64_Half e_machine;             /* machine */
+    Elf64_Word e_version;             /* object file version */
+    Elf64_Addr e_entry;               /* virtual entry point */
+    Elf64_Off e_phoff;                /* program header table offset */
+    Elf64_Off e_shoff;                /* section header table offset */
+    Elf64_Word e_flags;               /* processor-specific flags */
+    Elf64_Half e_ehsize;              /* ELF header size */
+    Elf64_Half e_phentsize;           /* program header entry size */
+    Elf64_Half e_phnum;               /* number of program header entries */
+    Elf64_Half e_shentsize;           /* section header entry size */
+    Elf64_Half e_shnum;               /* number of section header entries */
+    Elf64_Half e_shstrndx;            /* section header table's "section
+                       header string table" entry offset */
+} Elf64_Ehdr;
+
+/* Section Header */
+typedef struct
+{
+    Elf32_Word sh_name;      /* name - index into section header
+                       string table section */
+    Elf32_Word sh_type;      /* type */
+    Elf32_Word sh_flags;     /* flags */
+    Elf32_Addr sh_addr;      /* address */
+    Elf32_Off sh_offset;     /* file offset */
+    Elf32_Word sh_size;      /* section size */
+    Elf32_Word sh_link;      /* section header table index link */
+    Elf32_Word sh_info;      /* extra information */
+    Elf32_Word sh_addralign; /* address alignment */
+    Elf32_Word sh_entsize;   /* section entry size */
+} Elf32_Shdr;
+
+typedef struct
+{
+    Elf64_Word sh_name;       /* name - index into section header
+                       string table section */
+    Elf64_Word sh_type;       /* type */
+    Elf64_Xword sh_flags;     /* flags */
+    Elf64_Addr sh_addr;       /* address */
+    Elf64_Off sh_offset;      /* file offset */
+    Elf64_Xword sh_size;      /* section size */
+    Elf64_Word sh_link;       /* section header table index link */
+    Elf64_Word sh_info;       /* extra information */
+    Elf64_Xword sh_addralign; /* address alignment */
+    Elf64_Xword sh_entsize;   /* section entry size */
+} Elf64_Shdr;
+
+/* Symbol Table Entry */
+typedef struct
+{
+    Elf32_Word st_name;     /* name - index into string table */
+    Elf32_Addr st_value;    /* symbol value */
+    Elf32_Word st_size;     /* symbol size */
+    unsigned char st_info;  /* type and binding */
+    unsigned char st_other; /* 0 - no defined meaning */
+    Elf32_Half st_shndx;    /* section header index */
+} Elf32_Sym;
+
+/* Relocation entry with implicit addend */
+typedef struct
+{
+    Elf32_Addr r_offset; /* offset of relocation */
+    Elf32_Word r_info;   /* symbol table index and type */
+} Elf32_Rel;
+
+/* Relocation entry with explicit addend */
+typedef struct
+{
+    Elf32_Addr r_offset; /* offset of relocation */
+    Elf32_Word r_info;   /* symbol table index and type */
+    Elf32_Sword r_addend;
+} Elf32_Rela;
+
+typedef struct
+{
+    Elf64_Addr r_offset; /* Location at which to apply the action */
+    Elf64_Xword r_info;  /* index and type of relocation */
+} Elf64_Rel;
+
+typedef struct
+{
+    Elf64_Addr r_offset;   /* Location at which to apply the action */
+    Elf64_Xword r_info;    /* index and type of relocation */
+    Elf64_Sxword r_addend; /* Constant addend used to compute value */
+} Elf64_Rela;
+
+/* Program Header */
+typedef struct
+{
+    Elf32_Word p_type;   /* segment type */
+    Elf32_Off p_offset;  /* segment offset */
+    Elf32_Addr p_vaddr;  /* virtual address of segment */
+    Elf32_Addr p_paddr;  /* physical address of segment */
+    Elf32_Word p_filesz; /* number of bytes in file for seg */
+    Elf32_Word p_memsz;  /* number of bytes in mem. for seg */
+    Elf32_Word p_flags;  /* flags */
+    Elf32_Word p_align;  /* memory alignment */
+} Elf32_Phdr;
+
+typedef struct
+{
+    Elf64_Word p_type;    /* segment type */
+    Elf64_Word p_flags;   /* flags */
+    Elf64_Off p_offset;   /* segment offset */
+    Elf64_Addr p_vaddr;   /* virtual address of segment */
+    Elf64_Addr p_paddr;   /* physical address of segment */
+    Elf64_Xword p_filesz; /* number of bytes in file for seg */
+    Elf64_Xword p_memsz;  /* number of bytes in mem. for seg */
+    Elf64_Xword p_align;  /* memory alignment */
+} Elf64_Phdr;
+
+/* Dynamic structure */
+typedef struct
+{
+    Elf32_Sword d_tag; /* controls meaning of d_val */
+    union
+    {
+        Elf32_Word d_val; /* Multiple meanings - see d_tag */
+        Elf32_Addr d_ptr; /* program virtual address */
+    } d_un;
+} Elf32_Dyn;
+
+extern Elf32_Dyn _DYNAMIC[];
+
+typedef struct
+{
+    Elf64_Sxword d_tag; /* entry tag value */
+    union
+    {
+        Elf64_Xword d_val;
+        Elf64_Addr d_ptr;
+    } d_un;
+} Elf64_Dyn;
+
+/* e_ident[] magic number */
+#define ELFMAG0 0x7f     /* e_ident[EI_MAG0] */
+#define ELFMAG1 'E'      /* e_ident[EI_MAG1] */
+#define ELFMAG2 'L'      /* e_ident[EI_MAG2] */
+#define ELFMAG3 'F'      /* e_ident[EI_MAG3] */
+#define ELFMAG "\177ELF" /* magic */
+#define SELFMAG 4        /* size of magic */
+
+/* e_ident[] file class */
+#define ELFCLASSNONE 0 /* invalid */
+#define ELFCLASS32 1   /* 32-bit objs */
+#define ELFCLASS64 2   /* 64-bit objs */
+#define ELFCLASSNUM 3  /* number of classes */
+
+/* e_ident[] data encoding */
+#define ELFDATANONE 0 /* invalid */
+#define ELFDATA2LSB 1 /* Little-Endian */
+#define ELFDATA2MSB 2 /* Big-Endian */
+#define ELFDATANUM 3  /* number of data encode defines */
+
+/* e_ident[] OS/ABI specific ELF extensions */
+#define ELFOSABI_NONE 0     /* No extension specified */
+#define ELFOSABI_HPUX 1     /* Hewlett-Packard HP-UX */
+#define ELFOSABI_NETBSD 2   /* NetBSD */
+#define ELFOSABI_LINUX 3    /* Linux */
+#define ELFOSABI_SOLARIS 6  /* Sun Solaris */
+#define ELFOSABI_AIX 7      /* AIX */
+#define ELFOSABI_IRIX 8     /* IRIX */
+#define ELFOSABI_FREEBSD 9  /* FreeBSD */
+#define ELFOSABI_TRU64 10   /* Compaq TRU64 UNIX */
+#define ELFOSABI_MODESTO 11 /* Novell Modesto */
+#define ELFOSABI_OPENBSD 12 /* OpenBSD */
+/* 64-255 Architecture-specific value range */
+
+/* e_ident[] ABI Version */
+#define ELFABIVERSION 0
+
+/* e_ident */
+#define IS_ELF(ehdr) ((ehdr).e_ident[EI_MAG0] == ELFMAG0 && \
+                      (ehdr).e_ident[EI_MAG1] == ELFMAG1 && \
+                      (ehdr).e_ident[EI_MAG2] == ELFMAG2 && \
+                      (ehdr).e_ident[EI_MAG3] == ELFMAG3)
+
+/* e_type */
+#define ET_NONE 0        /* No file type */
+#define ET_REL 1         /* relocatable file */
+#define ET_EXEC 2        /* executable file */
+#define ET_DYN 3         /* shared object file */
+#define ET_CORE 4        /* core file */
+#define ET_NUM 5         /* number of types */
+#define ET_LOOS 0xfe00   /* reserved range for operating */
+#define ET_HIOS 0xfeff   /* system specific e_type */
+#define ET_LOPROC 0xff00 /* reserved range for processor */
+#define ET_HIPROC 0xffff /* specific e_type */
+
+/* e_machine */
+#define EM_NONE 0  /* No Machine */
+#define EM_M32 1   /* AT&T WE 32100 */
+#define EM_SPARC 2 /* SPARC */
+#define EM_386 3   /* Intel 80386 */
+#define EM_68K 4   /* Motorola 68000 */
+#define EM_88K 5   /* Motorola 88000 */
+#if 0
+    #define EM_486 6 /* RESERVED - was Intel 80486 */
+#endif
+#define EM_860 7          /* Intel 80860 */
+#define EM_MIPS 8         /* MIPS R3000 Big-Endian only */
+#define EM_S370 9         /* IBM System/370 Processor */
+#define EM_MIPS_RS4_BE 10 /* MIPS R4000 Big-Endian */
+#if 0
+#define EM_SPARC64 11 /* RESERVED - was SPARC v9 \
+64-bit unoffical */
+#endif
+/* RESERVED 11-14 for future use */
+#define EM_PARISC 15 /* HPPA */
+/* RESERVED 16 for future use */
+#define EM_VPP500 17      /* Fujitsu VPP500 */
+#define EM_SPARC32PLUS 18 /* Enhanced instruction set SPARC */
+#define EM_960 19         /* Intel 80960 */
+#define EM_PPC 20         /* PowerPC */
+#define EM_PPC64 21       /* 64-bit PowerPC */
+#define EM_S390 22        /* IBM System/390 Processor */
+/* RESERVED 23-35 for future use */
+#define EM_V800 36     /* NEC V800 */
+#define EM_FR20 37     /* Fujitsu FR20 */
+#define EM_RH32 38     /* TRW RH-32 */
+#define EM_RCE 39      /* Motorola RCE */
+#define EM_ARM 40      /* Advanced Risc Machines ARM */
+#define EM_ALPHA 41    /* Digital Alpha */
+#define EM_SH 42       /* Hitachi SH */
+#define EM_SPARCV9 43  /* SPARC Version 9 */
+#define EM_TRICORE 44  /* Siemens TriCore embedded processor */
+#define EM_ARC 45      /* Argonaut RISC Core */
+#define EM_H8_300 46   /* Hitachi H8/300 */
+#define EM_H8_300H 47  /* Hitachi H8/300H */
+#define EM_H8S 48      /* Hitachi H8S */
+#define EM_H8_500 49   /* Hitachi H8/500 */
+#define EM_IA_64 50    /* Intel Merced */
+#define EM_MIPS_X 51   /* Stanford MIPS-X */
+#define EM_COLDFIRE 52 /* Motorola Coldfire */
+#define EM_68HC12 53   /* Motorola M68HC12 */
+#define EM_MMA 54      /* Fujitsu MMA Multimedia Accelerator*/
+#define EM_PCP 55      /* Siemens PCP */
+#define EM_NCPU 56     /* Sony nCPU embeeded RISC */
+#define EM_NDR1 57     /* Denso NDR1 microprocessor */
+#define EM_STARCORE 58 /* Motorola Start*Core processor */
+#define EM_ME16 59     /* Toyota ME16 processor */
+#define EM_ST100 60    /* STMicroelectronic ST100 processor */
+#define EM_TINYJ 61    /* Advanced Logic Corp. Tinyj emb.fam*/
+#define EM_X86_64 62   /* AMD x86-64 */
+#define EM_PDSP 63     /* Sony DSP Processor */
+/* RESERVED 64,65 for future use */
+#define EM_FX66 66     /* Siemens FX66 microcontroller */
+#define EM_ST9PLUS 67  /* STMicroelectronics ST9+ 8/16 mc */
+#define EM_ST7 68      /* STmicroelectronics ST7 8 bit mc */
+#define EM_68HC16 69   /* Motorola MC68HC16 microcontroller */
+#define EM_68HC11 70   /* Motorola MC68HC11 microcontroller */
+#define EM_68HC08 71   /* Motorola MC68HC08 microcontroller */
+#define EM_68HC05 72   /* Motorola MC68HC05 microcontroller */
+#define EM_SVX 73      /* Silicon Graphics SVx */
+#define EM_ST19 74     /* STMicroelectronics ST19 8 bit mc */
+#define EM_VAX 75      /* Digital VAX */
+#define EM_CHRIS 76    /* Axis Communications embedded proc. */
+#define EM_JAVELIN 77  /* Infineon Technologies emb. proc. */
+#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */
+#define EM_ZSP 79      /* LSI Logic 16-bit DSP Processor */
+#define EM_MMIX 80     /* Donald Knuth's edu 64-bit proc. */
+#define EM_HUANY 81    /* Harvard University mach-indep objs */
+#define EM_PRISM 82    /* SiTera Prism */
+#define EM_AVR 83      /* Atmel AVR 8-bit microcontroller */
+#define EM_FR30 84     /* Fujitsu FR30 */
+#define EM_D10V 85     /* Mitsubishi DV10V */
+#define EM_D30V 86     /* Mitsubishi DV30V */
+#define EM_V850 87     /* NEC v850 */
+#define EM_M32R 88     /* Mitsubishi M32R */
+#define EM_MN10300 89  /* Matsushita MN10200 */
+#define EM_MN10200 90  /* Matsushita MN10200 */
+#define EM_PJ 91       /* picoJava */
+#define EM_NUM 92      /* number of machine types */
+
+/* Version */
+#define EV_NONE 0    /* Invalid */
+#define EV_CURRENT 1 /* Current */
+#define EV_NUM 2     /* number of versions */
+
+/* Special Section Indexes */
+#define SHN_UNDEF 0          /* undefined */
+#define SHN_LORESERVE 0xff00 /* lower bounds of reserved indexes */
+#define SHN_LOPROC 0xff00    /* reserved range for processor */
+#define SHN_HIPROC 0xff1f    /* specific section indexes */
+#define SHN_LOOS 0xff20      /* reserved range for operating */
+#define SHN_HIOS 0xff3f      /* specific semantics */
+#define SHN_ABS 0xfff1       /* absolute value */
+#define SHN_COMMON 0xfff2    /* common symbol */
+#define SHN_XINDEX 0xffff    /* Index is an extra table */
+#define SHN_HIRESERVE 0xffff /* upper bounds of reserved indexes */
+
+/* sh_type */
+#define SHT_NULL 0            /* inactive */
+#define SHT_PROGBITS 1        /* program defined information */
+#define SHT_SYMTAB 2          /* symbol table section */
+#define SHT_STRTAB 3          /* string table section */
+#define SHT_RELA 4            /* relocation section with addends*/
+#define SHT_HASH 5            /* symbol hash table section */
+#define SHT_DYNAMIC 6         /* dynamic section */
+#define SHT_NOTE 7            /* note section */
+#define SHT_NOBITS 8          /* no space section */
+#define SHT_REL 9             /* relation section without addends */
+#define SHT_SHLIB 10          /* reserved - purpose unknown */
+#define SHT_DYNSYM 11         /* dynamic symbol table section */
+#define SHT_INIT_ARRAY 14     /* Array of constructors */
+#define SHT_FINI_ARRAY 15     /* Array of destructors */
+#define SHT_PREINIT_ARRAY 16  /* Array of pre-constructors */
+#define SHT_GROUP 17          /* Section group */
+#define SHT_SYMTAB_SHNDX 18   /* Extended section indeces */
+#define SHT_NUM 19            /* number of section types */
+#define SHT_LOOS 0x60000000   /* Start OS-specific */
+#define SHT_HIOS 0x6fffffff   /* End OS-specific */
+#define SHT_LOPROC 0x70000000 /* reserved range for processor */
+#define SHT_HIPROC 0x7fffffff /* specific section header types */
+#define SHT_LOUSER 0x80000000 /* reserved range for application */
+#define SHT_HIUSER 0xffffffff /* specific indexes */
+
+/* Section names */
+#define ELF_BSS ".bss"                     /* uninitialized data */
+#define ELF_COMMENT ".comment"             /* version control information */
+#define ELF_DATA ".data"                   /* initialized data */
+#define ELF_DATA1 ".data1"                 /* initialized data */
+#define ELF_DEBUG ".debug"                 /* debug */
+#define ELF_DYNAMIC ".dynamic"             /* dynamic linking information */
+#define ELF_DYNSTR ".dynstr"               /* dynamic string table */
+#define ELF_DYNSYM ".dynsym"               /* dynamic symbol table */
+#define ELF_FINI ".fini"                   /* termination code */
+#define ELF_FINI_ARRAY ".fini_array"       /* Array of destructors */
+#define ELF_GOT ".got"                     /* global offset table */
+#define ELF_HASH ".hash"                   /* symbol hash table */
+#define ELF_INIT ".init"                   /* initialization code */
+#define ELF_INIT_ARRAY ".init_array"       /* Array of constuctors */
+#define ELF_INTERP ".interp"               /* Pathname of program interpreter */
+#define ELF_LINE ".line"                   /* Symbolic line numnber information */
+#define ELF_NOTE ".note"                   /* Contains note section */
+#define ELF_PLT ".plt"                     /* Procedure linkage table */
+#define ELF_PREINIT_ARRAY ".preinit_array" /* Array of pre-constructors */
+#define ELF_REL_DATA ".rel.data"           /* relocation data */
+#define ELF_REL_FINI ".rel.fini"           /* relocation termination code */
+#define ELF_REL_INIT ".rel.init"           /* relocation initialization code */
+#define ELF_REL_DYN ".rel.dyn"             /* relocaltion dynamic link info */
+#define ELF_REL_RODATA ".rel.rodata"       /* relocation read-only data */
+#define ELF_REL_TEXT ".rel.text"           /* relocation code */
+#define ELF_RODATA ".rodata"               /* read-only data */
+#define ELF_RODATA1 ".rodata1"             /* read-only data */
+#define ELF_SHSTRTAB ".shstrtab"           /* section header string table */
+#define ELF_STRTAB ".strtab"               /* string table */
+#define ELF_SYMTAB ".symtab"               /* symbol table */
+#define ELF_SYMTAB_SHNDX ".symtab_shndx"   /* symbol table section index */
+#define ELF_TBSS ".tbss"                   /* thread local uninit data */
+#define ELF_TDATA ".tdata"                 /* thread local init data */
+#define ELF_TDATA1 ".tdata1"               /* thread local init data */
+#define ELF_TEXT ".text"                   /* code */
+
+/* Section Attribute Flags - sh_flags */
+#define SHF_WRITE 0x1              /* Writable */
+#define SHF_ALLOC 0x2              /* occupies memory */
+#define SHF_EXECINSTR 0x4          /* executable */
+#define SHF_MERGE 0x10             /* Might be merged */
+#define SHF_STRINGS 0x20           /* Contains NULL terminated strings */
+#define SHF_INFO_LINK 0x40         /* sh_info contains SHT index */
+#define SHF_LINK_ORDER 0x80        /* Preserve order after combining*/
+#define SHF_OS_NONCONFORMING 0x100 /* Non-standard OS specific handling */
+#define SHF_GROUP 0x200            /* Member of section group */
+#define SHF_TLS 0x400              /* Thread local storage */
+#define SHF_MASKOS 0x0ff00000      /* OS specific */
+#define SHF_MASKPROC 0xf0000000    /* reserved bits for processor */
+/* specific section attributes */
+
+/* Section Group Flags */
+#define GRP_COMDAT 0x1          /* COMDAT group */
+#define GRP_MASKOS 0x0ff00000   /* Mask OS specific flags */
+#define GRP_MASKPROC 0xf0000000 /* Mask processor specific flags */
+
+/* Symbol table index */
+#define STN_UNDEF 0 /* undefined */
+
+/* Extract symbol info - st_info */
+#define ELF32_ST_BIND(x) ((x) >> 4)
+#define ELF32_ST_TYPE(x) (((unsigned int)x) & 0xf)
+#define ELF32_ST_INFO(b, t) (((b) << 4) + ((t)&0xf))
+#define ELF32_ST_VISIBILITY(x) ((x)&0x3)
+
+/* Symbol Binding - ELF32_ST_BIND - st_info */
+#define STB_LOCAL 0   /* Local symbol */
+#define STB_GLOBAL 1  /* Global symbol */
+#define STB_WEAK 2    /* like global - lower precedence */
+#define STB_NUM 3     /* number of symbol bindings */
+#define STB_LOOS 10   /* reserved range for operating */
+#define STB_HIOS 12   /* system specific symbol bindings */
+#define STB_LOPROC 13 /* reserved range for processor */
+#define STB_HIPROC 15 /* specific symbol bindings */
+
+/* Symbol type - ELF32_ST_TYPE - st_info */
+#define STT_NOTYPE 0  /* not specified */
+#define STT_OBJECT 1  /* data object */
+#define STT_FUNC 2    /* function */
+#define STT_SECTION 3 /* section */
+#define STT_FILE 4    /* file */
+#define STT_NUM 5     /* number of symbol types */
+#define STT_TLS 6     /* Thread local storage symbol */
+#define STT_LOOS 10   /* reserved range for operating */
+#define STT_HIOS 12   /* system specific symbol types */
+#define STT_LOPROC 13 /* reserved range for processor */
+#define STT_HIPROC 15 /* specific symbol types */
+
+/* Symbol visibility - ELF32_ST_VISIBILITY - st_other */
+#define STV_DEFAULT 0   /* Normal visibility rules */
+#define STV_INTERNAL 1  /* Processor specific hidden class */
+#define STV_HIDDEN 2    /* Symbol unavailable in other mods */
+#define STV_PROTECTED 3 /* Not preemptible, not exported */
+
+/* Extract relocation info - r_info */
+#define ELF32_R_SYM(i) ((i) >> 8)
+#define ELF32_R_TYPE(i) ((unsigned char)(i))
+#define ELF32_R_INFO(s, t) (((s) << 8) + (unsigned char)(t))
+
+/* Segment types - p_type */
+#define PT_NULL 0            /* unused */
+#define PT_LOAD 1            /* loadable segment */
+#define PT_DYNAMIC 2         /* dynamic linking section */
+#define PT_INTERP 3          /* the RTLD */
+#define PT_NOTE 4            /* auxiliary information */
+#define PT_SHLIB 5           /* reserved - purpose undefined */
+#define PT_PHDR 6            /* program header */
+#define PT_TLS 7             /* Thread local storage template */
+#define PT_NUM 8             /* Number of segment types */
+#define PT_LOOS 0x60000000   /* reserved range for operating */
+#define PT_HIOS 0x6fffffff   /* system specific segment types */
+#define PT_LOPROC 0x70000000 /* reserved range for processor */
+#define PT_HIPROC 0x7fffffff /* specific segment types */
+
+/* Segment flags - p_flags */
+#define PF_X 0x1               /* Executable */
+#define PF_W 0x2               /* Writable */
+#define PF_R 0x4               /* Readable */
+#define PF_MASKOS 0x0ff00000   /* OS specific segment flags */
+#define PF_MASKPROC 0xf0000000 /* reserved bits for processor */
+/* specific segment flags */
+
+#define ELF64_R_SYM(i) ((i) >> 32)
+#define ELF64_R_TYPE(i) ((i)&0xffffffff)
+
+/* Dynamic Array Tags - d_tag */
+#define DT_NULL 0             /* marks end of _DYNAMIC array */
+#define DT_NEEDED 1           /* string table offset of needed lib */
+#define DT_PLTRELSZ 2         /* size of relocation entries in PLT */
+#define DT_PLTGOT 3           /* address PLT/GOT */
+#define DT_HASH 4             /* address of symbol hash table */
+#define DT_STRTAB 5           /* address of string table */
+#define DT_SYMTAB 6           /* address of symbol table */
+#define DT_RELA 7             /* address of relocation table */
+#define DT_RELASZ 8           /* size of relocation table */
+#define DT_RELAENT 9          /* size of relocation entry */
+#define DT_STRSZ 10           /* size of string table */
+#define DT_SYMENT 11          /* size of symbol table entry */
+#define DT_INIT 12            /* address of initialization func */
+#define DT_FINI 13            /* address of termination function */
+#define DT_SONAME 14          /* string table offset of shared obj */
+#define DT_RPATH 15           /* string table offset of library \
+search path */
+#define DT_SYMBOLIC 16        /* start sym search in shared obj */
+#define DT_REL 17             /* address of rel. tbl. w addends */
+#define DT_RELSZ 18           /* size of DT_REL relocation table */
+#define DT_RELENT 19          /* size of DT_REL relocation entry */
+#define DT_PLTREL 20          /* PLT referenced relocation entry */
+#define DT_DEBUG 21           /* bugger */
+#define DT_TEXTREL 22         /* Allow rel. mod. to unwritable seg */
+#define DT_JMPREL 23          /* add. of PLT's relocation entries */
+#define DT_BIND_NOW 24        /* Process relocations of object */
+#define DT_INIT_ARRAY 25      /* Array with addresses of init fct */
+#define DT_FINI_ARRAY 26      /* Array with addresses of fini fct */
+#define DT_INIT_ARRAYSZ 27    /* Size in bytes of DT_INIT_ARRAY */
+#define DT_FINI_ARRAYSZ 28    /* Size in bytes of DT_FINI_ARRAY */
+#define DT_RUNPATH 29         /* Library search path */
+#define DT_FLAGS 30           /* Flags for the object being loaded */
+#define DT_ENCODING 32        /* Start of encoded range */
+#define DT_PREINIT_ARRAY 32   /* Array with addresses of preinit fct*/
+#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */
+#define DT_NUM 34             /* Number used */
+#define DT_LOOS 0x60000000    /* reserved range for OS */
+#define DT_HIOS 0x6fffffff    /* specific dynamic array tags */
+#define DT_LOPROC 0x70000000  /* reserved range for processor */
+#define DT_HIPROC 0x7fffffff  /* specific dynamic array tags */
+
+/* Dynamic Tag Flags - d_un.d_val */
+#define DF_ORIGIN 0x01     /* Object may use DF_ORIGIN */
+#define DF_SYMBOLIC 0x02   /* Symbol resolutions starts here */
+#define DF_TEXTREL 0x04    /* Object contains text relocations */
+#define DF_BIND_NOW 0x08   /* No lazy binding for this object */
+#define DF_STATIC_TLS 0x10 /* Static thread local storage */
+
+/* Standard ELF hashing function */
+unsigned long elf_hash(const unsigned char *name);
+
+#define ELF_TARG_VER 1 /* The ver for which this code is intended */
+
+/* ELF register definitions */
+#define R_386_NONE 0
+#define R_386_32 1
+#define R_386_PC32 2
+#define R_386_GOT32 3
+#define R_386_PLT32 4
+#define R_386_COPY 5
+#define R_386_GLOB_DAT 6
+#define R_386_JMP_SLOT 7
+#define R_386_RELATIVE 8
+#define R_386_GOTOFF 9
+#define R_386_GOTPC 10
+#define R_386_NUM 11
+
+/* x86-64 relocation types */
+#define R_X86_64_NONE 0      /* No reloc */
+#define R_X86_64_64 1        /* Direct 64 bit  */
+#define R_X86_64_PC32 2      /* PC relative 32 bit signed */
+#define R_X86_64_GOT32 3     /* 32 bit GOT entry */
+#define R_X86_64_PLT32 4     /* 32 bit PLT address */
+#define R_X86_64_COPY 5      /* Copy symbol at runtime */
+#define R_X86_64_GLOB_DAT 6  /* Create GOT entry */
+#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
+#define R_X86_64_RELATIVE 8  /* Adjust by program base */
+/* 32 bit signed pc relative offset to GOT */
+#define R_X86_64_GOTPCREL 9
+#define R_X86_64_32 10   /* Direct 32 bit zero extended */
+#define R_X86_64_32S 11  /* Direct 32 bit sign extended */
+#define R_X86_64_16 12   /* Direct 16 bit zero extended */
+#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */
+#define R_X86_64_8 14    /* Direct 8 bit sign extended  */
+#define R_X86_64_PC8 15  /* 8 bit sign extended pc relative */
+
+#define R_X86_64_NUM 16
+
+/*
+ * XXX - PowerPC defines really don't belong in here,
+ * but we'll put them in for simplicity.
+ */
+
+/* Values for Elf32/64_Ehdr.e_flags */
+#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */
+
+#define EF_PPC64_ELFV1_ABI 0x00000001
+#define EF_PPC64_ELFV2_ABI 0x00000002
+
+/* Cygnus local bits below */
+#define EF_PPC_RELOCATABLE 0x00010000     /* PowerPC -mrelocatable flag*/
+#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib \
+flag */
+
+/* PowerPC relocations defined by the ABIs */
+#define R_PPC_NONE 0
+#define R_PPC_ADDR32 1    /* 32bit absolute address */
+#define R_PPC_ADDR24 2    /* 26bit address, 2 bits ignored */
+#define R_PPC_ADDR16 3    /* 16bit absolute address */
+#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
+#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
+#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
+#define R_PPC_ADDR14 7    /* 16bit address, 2 bits ignored */
+#define R_PPC_ADDR14_BRTAKEN 8
+#define R_PPC_ADDR14_BRNTAKEN 9
+#define R_PPC_REL24 10 /* PC relative 26 bit */
+#define R_PPC_REL14 11 /* PC relative 16 bit */
+#define R_PPC_REL14_BRTAKEN 12
+#define R_PPC_REL14_BRNTAKEN 13
+#define R_PPC_GOT16 14
+#define R_PPC_GOT16_LO 15
+#define R_PPC_GOT16_HI 16
+#define R_PPC_GOT16_HA 17
+#define R_PPC_PLTREL24 18
+#define R_PPC_COPY 19
+#define R_PPC_GLOB_DAT 20
+#define R_PPC_JMP_SLOT 21
+#define R_PPC_RELATIVE 22
+#define R_PPC_LOCAL24PC 23
+#define R_PPC_UADDR32 24
+#define R_PPC_UADDR16 25
+#define R_PPC_REL32 26
+#define R_PPC_PLT32 27
+#define R_PPC_PLTREL32 28
+#define R_PPC_PLT16_LO 29
+#define R_PPC_PLT16_HI 30
+#define R_PPC_PLT16_HA 31
+#define R_PPC_SDAREL16 32
+#define R_PPC_SECTOFF 33
+#define R_PPC_SECTOFF_LO 34
+#define R_PPC_SECTOFF_HI 35
+#define R_PPC_SECTOFF_HA 36
+/* Keep this the last entry */
+#define R_PPC_NUM 37
+
+/*
+ * The remaining relocs are from the Embedded ELF ABI, and are not
+ * in the SVR4 ELF ABI.
+ */
+#define R_PPC_EMB_NADDR32 101
+#define R_PPC_EMB_NADDR16 102
+#define R_PPC_EMB_NADDR16_LO 103
+#define R_PPC_EMB_NADDR16_HI 104
+#define R_PPC_EMB_NADDR16_HA 105
+#define R_PPC_EMB_SDAI16 106
+#define R_PPC_EMB_SDA2I16 107
+#define R_PPC_EMB_SDA2REL 108
+#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */
+#define R_PPC_EMB_MRKREF 110
+#define R_PPC_EMB_RELSEC16 111
+#define R_PPC_EMB_RELST_LO 112
+#define R_PPC_EMB_RELST_HI 113
+#define R_PPC_EMB_RELST_HA 114
+#define R_PPC_EMB_BIT_FLD 115
+#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */
+
+/* Diab tool relocations */
+#define R_PPC_DIAB_SDA21_LO 180  /* like EMB_SDA21, but lower 16 bit */
+#define R_PPC_DIAB_SDA21_HI 181  /* like EMB_SDA21, but high 16 bit */
+#define R_PPC_DIAB_SDA21_HA 182  /* like EMB_SDA21, adjusted high 16 */
+#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */
+#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */
+#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */
+
+/*
+ * This is a phony reloc to handle any old fashioned TOC16 references
+ * that may still be in object files.
+ */
+#define R_PPC_TOC16 255
+
+/* ARM relocs */
+#define R_ARM_NONE 0      /* No reloc */
+#define R_ARM_RELATIVE 23 /* Adjust by program base */
+
+/* AArch64 relocs */
+#define R_AARCH64_NONE 0        /* No relocation */
+#define R_AARCH64_RELATIVE 1027 /* Adjust by program base */
+
+/* RISC-V relocations */
+#define R_RISCV_32 1
+#define R_RISCV_64 2
+#define R_RISCV_RELATIVE 3
+
+/*
+ * A very simple ELF64 loader, assumes the image is valid, returns the
+ * entry point address.
+ *
+ * Note if U-Boot is 32-bit, the loader assumes the to segment's
+ * physical address and size is within the lower 32-bit address space.
+ */
+static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr)
+{
+    Elf64_Ehdr *ehdr; /* Elf header structure pointer */
+    Elf64_Phdr *phdr; /* Program header structure pointer */
+    int i;
+
+    ehdr = (Elf64_Ehdr *)addr;
+    phdr = (Elf64_Phdr *)(addr + (unsigned long)ehdr->e_phoff);
+
+    /* Load each program header */
+    for (i = 0; i < ehdr->e_phnum; ++i)
+    {
+        void *dst = (void *)(unsigned long)phdr->p_paddr;
+        void *src = (void *)addr + phdr->p_offset;
+
+        f_printk("Loading phdr %i to 0x%p (%lu bytes)",
+                      i, dst, (unsigned long)phdr->p_filesz);
+        if (phdr->p_filesz)
+        {
+            memcpy(dst, src, phdr->p_filesz);
+        }
+
+        if (phdr->p_filesz != phdr->p_memsz)
+        {
+            memset(dst + phdr->p_filesz, 0x00,
+                   phdr->p_memsz - phdr->p_filesz);
+        }
+
+        FCacheDCacheFlushRange((uintptr)dst, phdr->p_memsz);
+        ++phdr;
+    }
+
+    if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags & EF_PPC64_ELFV1_ABI))
+    {
+        /*
+         * For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
+         * descriptor pointer with the first double word being the
+         * address of the entry point of the function.
+         */
+        uintptr_t addr = ehdr->e_entry;
+
+        return *(Elf64_Addr *)addr;
+    }
+
+    return ehdr->e_entry;
+}
+
+static unsigned long ElfLoadElf64ImageShdr(unsigned long addr)
+{
+    Elf64_Ehdr *ehdr;          /* Elf header structure pointer */
+    Elf64_Shdr *shdr;          /* Section header structure pointer */
+    unsigned char *strtab = 0; /* String table pointer */
+    unsigned char *image;      /* Binary image pointer */
+    int i;                     /* Loop counter */
+
+    ehdr = (Elf64_Ehdr *)addr;
+
+    /* Find the section header string table for output info */
+    shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff +
+                          (ehdr->e_shstrndx * sizeof(Elf64_Shdr)));
+
+    if (shdr->sh_type == SHT_STRTAB)
+    {
+        strtab = (unsigned char *)(addr + (unsigned long)shdr->sh_offset);
+    }
+
+    /* Load each appropriate section */
+    for (i = 0; i < ehdr->e_shnum; ++i)
+    {
+        shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff +
+                              (i * sizeof(Elf64_Shdr)));
+
+        if (!(shdr->sh_flags & SHF_ALLOC) ||
+            shdr->sh_addr == 0 || shdr->sh_size == 0)
+        {
+            continue;
+        }
+
+        if (strtab)
+        {
+            f_printk("%sing %s @ 0x%08lx (%ld bytes)",
+                          (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+                          &strtab[shdr->sh_name],
+                          (unsigned long)shdr->sh_addr,
+                          (long)shdr->sh_size);
+        }
+
+        if (shdr->sh_type == SHT_NOBITS)
+        {
+            memset((void *)(uintptr)shdr->sh_addr, 0,
+                   shdr->sh_size);
+        }
+        else
+        {
+            image = (unsigned char *)addr + (unsigned long)shdr->sh_offset;
+            memcpy((void *)(uintptr)shdr->sh_addr,
+                   (const void *)image, shdr->sh_size);
+        }
+        FCacheDCacheFlushRange((uintptr)shdr->sh_addr, shdr->sh_size);
+    }
+
+    if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
+                                        EF_PPC64_ELFV1_ABI))
+    {
+        /*
+         * For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
+         * descriptor pointer with the first double word being the
+         * address of the entry point of the function.
+         */
+        uintptr addr = ehdr->e_entry;
+
+        return *(Elf64_Addr *)addr;
+    }
+
+    return ehdr->e_entry;
+}
+
+unsigned long ElfLoadElfImagePhdr(unsigned long addr)
+{
+    Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+    Elf32_Phdr *phdr; /* Program header structure pointer */
+    int i;
+
+    ehdr = (Elf32_Ehdr *)addr;
+    if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+    {
+        return ElfLoadElf64ImagePhdr(addr);
+    }
+
+    phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff);
+
+    /* Load each program header */
+    for (i = 0; i < ehdr->e_phnum; ++i)
+    {
+        void *dst = (void *)(uintptr)phdr->p_paddr;
+        void *src = (void *)addr + phdr->p_offset;
+
+        f_printk("Loading phdr %i to 0x%p (%i bytes)",
+                      i, dst, phdr->p_filesz);
+        if (phdr->p_filesz)
+        {
+            memcpy(dst, src, phdr->p_filesz);
+        }
+        if (phdr->p_filesz != phdr->p_memsz)
+        {
+            memset(dst + phdr->p_filesz, 0x00,
+                   phdr->p_memsz - phdr->p_filesz);
+        }
+
+        FCacheDCacheFlushRange((uintptr)dst, phdr->p_memsz);
+        ++phdr;
+    }
+
+    return ehdr->e_entry;
+}
+
+unsigned long ElfLoadElfImageShdr(unsigned long addr)
+{
+    Elf32_Ehdr *ehdr;          /* Elf header structure pointer */
+    Elf32_Shdr *shdr;          /* Section header structure pointer */
+    unsigned char *strtab = 0; /* String table pointer */
+    unsigned char *image;      /* Binary image pointer */
+    int i;                     /* Loop counter */
+
+    ehdr = (Elf32_Ehdr *)addr;
+    if (ehdr->e_ident[EI_CLASS] == ELFCLASS64)
+    {
+        return ElfLoadElf64ImageShdr(addr);
+    }
+
+    /* Find the section header string table for output info */
+    shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+                          (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
+
+    if (shdr->sh_type == SHT_STRTAB)
+    {
+        strtab = (unsigned char *)(addr + shdr->sh_offset);
+    }
+
+    /* Load each appropriate section */
+    for (i = 0; i < ehdr->e_shnum; ++i)
+    {
+        shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff +
+                              (i * sizeof(Elf32_Shdr)));
+
+        if (!(shdr->sh_flags & SHF_ALLOC) ||
+            shdr->sh_addr == 0 || shdr->sh_size == 0)
+        {
+            continue;
+        }
+
+        if (strtab)
+        {
+            f_printk("%sing %s @ 0x%08lx (%ld bytes)",
+                          (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
+                          &strtab[shdr->sh_name],
+                          (unsigned long)shdr->sh_addr,
+                          (long)shdr->sh_size);
+        }
+
+        if (shdr->sh_type == SHT_NOBITS)
+        {
+            memset((void *)(uintptr)shdr->sh_addr, 0,
+                   shdr->sh_size);
+        }
+        else
+        {
+            image = (unsigned char *)addr + shdr->sh_offset;
+            memcpy((void *)(uintptr)shdr->sh_addr,
+                   (const void *)image, shdr->sh_size);
+        }
+
+        FCacheDCacheFlushRange((uintptr)shdr->sh_addr, shdr->sh_size);
+    }
+
+    return ehdr->e_entry;
+}
+
+/*
+ * Determine if a valid ELF image exists at the given memory location.
+ * First look at the ELF header magic field, then make sure that it is
+ * executable.
+ */
+int ElfIsImageValid(unsigned long addr)
+{
+    Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+
+    ehdr = (Elf32_Ehdr *)addr;
+
+    if (!IS_ELF(*ehdr))
+    {
+        f_printk("## No elf image at address 0x%08lx.", addr);
+        return 0;
+    }
+
+    if (ehdr->e_type != ET_EXEC)
+    {
+        f_printk("## Not a 32-bit elf image at address 0x%08lx.", addr);
+        return 0;
+    }
+
+    return 1;
+}
+
+/* Allow ports to override the default behavior */
+unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]),
+                             int argc, char *const argv[])
+{
+    unsigned long ret;
+
+    /*
+     * pass address parameter as argv[0] (aka command name),
+     * and all remaining args
+     */
+    ret = entry(argc, argv);
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fsmc.h b/bsp/phytium/libraries/standalone/common/felf.h
similarity index 62%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch32/fsmc.h
rename to bsp/phytium/libraries/standalone/common/felf.h
index 8fc2005940c..bc485787430 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fsmc.h
+++ b/bsp/phytium/libraries/standalone/common/felf.h
@@ -11,43 +11,35 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: fsmc.h
- * Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:30:49
- * Description:  This files is for
+ * FilePath: felf.h
+ * Date: 2021-08-31 11:16:49
+ * LastEditTime: 2022-02-17 18:05:22
+ * Description:  This file is for showing elf api.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu  2022/10/27   rename file name
  */
 
+#ifndef FELF_H
+#define FELF_H
 
-#ifndef BSP_ARCH_ARMV8_AARCH32_SMC_H
-#define BSP_ARCH_ARMV8_AARCH32_SMC_H
+#include "ftypes.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
-#include "ftypes.h"
-
-typedef struct
-{
-    /* data */
-    u32 function_identifier;
-    u32 a1;
-    u32 a2;
-    u32 a3;
-    u32 a4;
-    u32 a5;
-    u32 a6;
-
-} FSmc_Data_t;
 
-void FSmcCall(FSmc_Data_t *Input, FSmc_Data_t *Output);
+unsigned long ElfLoadElfImagePhdr(unsigned long addr);
+unsigned long ElfLoadElfImageShdr(unsigned long addr);
+int ElfIsImageValid(unsigned long addr);
+unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]),
+                             int argc, char *const argv[]);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // !FT_SMC_H
+#endif // !
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/common/ferror_code.h b/bsp/phytium/libraries/standalone/common/ferror_code.h
index f00bcba0010..98ca6ea870c 100644
--- a/bsp/phytium/libraries/standalone/common/ferror_code.h
+++ b/bsp/phytium/libraries/standalone/common/ferror_code.h
@@ -14,17 +14,22 @@
  * FilePath: ferror_code.h
  * Date: 2021-04-07 09:53:30
  * LastEditTime: 2022-02-17 18:05:27
- * Description:  This files is for error code functions
+ * Description:  This file is for error code functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
  */
-#ifndef _FT_ERROR_CODE_H
-#define _FT_ERROR_CODE_H
+#ifndef FERROR_CODE_H
+#define FERROR_CODE_H
 
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 typedef u32 FError;
 
 #define FT_SUCCESS 0
@@ -54,6 +59,7 @@ typedef enum
 {
     ErrBspGeneral = 0,
     ErrBspClk,
+    ErrBspScmi,
     ErrBspRtc,
     ErrBspTimer,
     ErrBspUart,
@@ -78,7 +84,9 @@ typedef enum
     ErrBspAdc,
     ErrBspPwm,
     ErrSema,
-
+    ErrBspMEDIA,
+    ErrBspMhu,
+	
     ErrBspModMaxMask = 255
 } FtErrCodeBspMask;
 
@@ -103,4 +111,8 @@ typedef enum
 #define ERR_SUCCESS FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 0) /* 成功 */
 #define ERR_GENERAL FT_MAKE_ERRCODE(ErrorModGeneral, ErrBspGeneral, 1) /* 一般错误 */
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/bsp/phytium/libraries/standalone/common/fio.h b/bsp/phytium/libraries/standalone/common/fio.h
index 1f1d8331cf7..66f60940aeb 100644
--- a/bsp/phytium/libraries/standalone/common/fio.h
+++ b/bsp/phytium/libraries/standalone/common/fio.h
@@ -14,15 +14,17 @@
  * FilePath: fio.h
  * Date: 2021-04-07 09:53:07
  * LastEditTime: 2022-02-18 08:24:01
- * Description:  This files is for general reigster io functions
+ * Description:  This file is for general reigster io functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu   2021/04/07  init
+ * 1.1  zhugengyu   2022/02/18  add Phytium Public License 1.0
  */
 
-#ifndef FT_IO_H
-#define FT_IO_H
+#ifndef FIO_H
+#define FIO_H
 
 #ifdef __cplusplus
 extern "C"
diff --git a/bsp/phytium/libraries/standalone/arch/common/fkernel.h b/bsp/phytium/libraries/standalone/common/fkernel.h
similarity index 59%
rename from bsp/phytium/libraries/standalone/arch/common/fkernel.h
rename to bsp/phytium/libraries/standalone/common/fkernel.h
index 60efa30bb4e..b193920185d 100644
--- a/bsp/phytium/libraries/standalone/arch/common/fkernel.h
+++ b/bsp/phytium/libraries/standalone/common/fkernel.h
@@ -11,19 +11,26 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: kernel.h
+ * FilePath: fkernel.h
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:35:07
- * Description:  This files is for
+ * Description:  This file is for kernel definition functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/10/20       first release
+ * 1.1   zhugengyu  2022/2/17        add extra functionality
  */
 
 
-#ifndef KERNEL_H
-#define KERNEL_H
+#ifndef FKERNEL_H
+#define FKERNEL_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 #ifdef __ASSEMBLY__
     #define _AC(X, Y) X
@@ -44,24 +51,27 @@
 #define ULL(x) (_ULL(x))
 
 #define min(x, y) (                    \
-    {                                  \
-        typeof(x) _min1 = (x);         \
-        typeof(y) _min2 = (y);         \
-        (void)(&_min1 == &_min2);      \
-        _min1 < _min2 ? _min1 : _min2; \
-    })
+{                                  \
+    typeof(x) _min1 = (x);         \
+    typeof(y) _min2 = (y);         \
+    (void)(&_min1 == &_min2);      \
+    _min1 < _min2 ? _min1 : _min2; \
+})
 
 #define max(x, y) (                    \
-    {                                  \
-        typeof(x) _max1 = (x);         \
-        typeof(y) _max2 = (y);         \
-        (void)(&_max1 == &_max2);      \
-        _max1 > _max2 ? _max1 : _max2; \
-    })
+{                                  \
+    typeof(x) _max1 = (x);         \
+    typeof(y) _max2 = (y);         \
+    (void)(&_max1 == &_max2);      \
+    _max1 > _max2 ? _max1 : _max2; \
+})
 
 #define min3(x, y, z) min((typeof(x))min(x, y), z)
 #define max3(x, y, z) max((typeof(x))max(x, y), z)
 
+#define min_t(type, a, b) min(((type) a), ((type) b))
+#define max_t(type, a, b) max(((type) a), ((type) b))
+
 /**
  * clamp - return a value clamped to a given range with strict typechecking
  * @val: current value
@@ -88,25 +98,25 @@
  * beware of side effects!
  */
 #define do_div(n, base) (                 \
-    {                                     \
-        uint32_t __base = (base);         \
-        uint32_t __rem;                   \
-        __rem = ((uint64_t)(n)) % __base; \
-        (n) = ((uint64_t)(n)) / __base;   \
-        __rem;                            \
-    })
+{                                     \
+    uint32_t __base = (base);         \
+    uint32_t __rem;                   \
+    __rem = ((uint64_t)(n)) % __base; \
+    (n) = ((uint64_t)(n)) / __base;   \
+    __rem;                            \
+})
 
 /* The `const' in roundup() prevents gcc-3.3 from calling __divdi3 */
 #define roundup(x, y) (                  \
-    {                                    \
-        const typeof(y) __y = y;         \
-        ((x + (__y - 1)) / __y) * __y; \
-    })
+{                                    \
+    const typeof(y) __y = y;         \
+    ((x + (__y - 1)) / __y) * __y; \
+})
 #define rounddown(x, y) (    \
-    {                        \
-        typeof(x) __x = (x); \
-        __x - (__x % (y));   \
-    })
+{                        \
+    typeof(x) __x = (x); \
+    __x - (__x % (y));   \
+})
 
 #define DIV_ROUND_UP(n, d) (((n) + (d)-1) / (d))
 
@@ -234,4 +244,101 @@
 #define PALIGN_DOWN(x,align)    (x & ~(align-1))
 /* Integer alignment up */
 #define PALIGN_UP(x,align)      ((x + (align-1)) & ~(align-1))
+
+#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
+
+#define __BUILD_BUG_ON_NOT_POWER_OF_2(n)	\
+	BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n)			\
+	BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
+
+/**
+ * COMILETIME_ASSERT - break build and emit msg if condition is false
+ * @condition: a compile-time constant condition to check
+ * @msg:       a message to emit if condition is false
+ *
+ * In tradition of POSIX assert, this macro will break the build if the
+ * supplied condition is *false*, emitting the supplied error message if the
+ * compiler has support to do so.
+ */
+# define COMILETIME_ASSERT(condition, msg, prefix, suffix)		\
+	do {								\
+		extern void prefix ## suffix(void) __attribute__((error(msg))); \
+		if (!(condition))					\
+			prefix ## suffix();				\
+	} while (0)
+ 
+/**
+ * BUILD_BUG_ON_MSG - break compile if a condition is true & emit supplied
+ *		      error message.
+ * @condition: the condition which the compiler should know is false.
+ *
+ * See BUILD_BUG_ON for description.
+ */
+#define BUILD_BUG_ON_MSG(cond, msg) COMILETIME_ASSERT(!(cond), msg, __compiletime_assert_, __COUNTER__)
+
+/*
+ * Bitfield access macros
+ *
+ * FIELD_{GET,PREP} macros take as first parameter shifted mask
+ * from which they extract the base mask and shift amount.
+ * Mask must be a compilation time constant.
+ *
+ * Example:
+ *
+ *  #define REG_FIELD_A  GENMASK(6, 0)
+ *  #define REG_FIELD_B  BIT(7)
+ *  #define REG_FIELD_C  GENMASK(15, 8)
+ *  #define REG_FIELD_D  GENMASK(31, 16)
+ *
+ * Get:
+ *  a = FIELD_GET(REG_FIELD_A, reg);
+ *  b = FIELD_GET(REG_FIELD_B, reg);
+ *
+ * Set:
+ *  reg = FIELD_PREP(REG_FIELD_A, 1) |
+ *	  FIELD_PREP(REG_FIELD_B, 0) |
+ *	  FIELD_PREP(REG_FIELD_C, c) |
+ *	  FIELD_PREP(REG_FIELD_D, 0x40);
+ *
+ * Modify:
+ *  reg &= ~REG_FIELD_C;
+ *  reg |= FIELD_PREP(REG_FIELD_C, c);
+ */
+
+#define BF_SHF(x) (__builtin_ffsll(x) - 1)
+
+#define BF_FIELD_CHECK(mask, reg, val, pfx)			\
+	({								\
+		BUILD_BUG_ON_MSG(!__builtin_constant_p(mask),		\
+				 pfx "mask is not constant");		\
+		BUILD_BUG_ON_MSG((mask) == 0, pfx "mask is zero");	\
+		BUILD_BUG_ON_MSG(__builtin_constant_p(val) ?		\
+				 ~((mask) >> BF_SHF(mask)) & (val) : 0, \
+				 pfx "value too large for the field"); \
+		BUILD_BUG_ON_MSG((mask) > (typeof(reg))~0ull,		\
+				 pfx "type of reg too small for mask"); \
+		__BUILD_BUG_ON_NOT_POWER_OF_2((mask) +			\
+					      (1ULL << BF_SHF(mask))); \
+	})
+
+
+/**
+ * FIELD_PREP() - prepare a bitfield element
+ * @mask: shifted mask defining the field's length and position
+ * @val:  value to put in the field
+ *
+ * FIELD_PREP() masks and shifts up the value.  The result should
+ * be combined with other fields of the bitfield using logical OR.
+ */
+#define FIELD_PREP(mask, val)						\
+	({								\
+		BF_FIELD_CHECK(mask, 0ULL, val, "FIELD_PREP: ");	\
+		((typeof(mask))(val) << BF_SHF(mask)) & (mask);	\
+	})
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/common/fpinctrl.h b/bsp/phytium/libraries/standalone/common/fpinctrl.h
index 891e8f74de7..113a4db7231 100644
--- a/bsp/phytium/libraries/standalone/common/fpinctrl.h
+++ b/bsp/phytium/libraries/standalone/common/fpinctrl.h
@@ -14,15 +14,15 @@
  * FilePath: fpinctrl.h
  * Date: 2022-03-28 14:16:09
  * LastEditTime: 2022-03-28 14:16:10
- * Description:  This files is for IO pin ctrl API definition
+ * Description:  This file is for IO pin ctrl API definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
  * 1.0   zhugengyu   2022/3/28   init commit
  */
-#ifndef  COMMON_FPINCTRL_H
-#define  COMMON_FPINCTRL_H
+#ifndef  FPINCTRL_H
+#define  FPINCTRL_H
 
 #ifdef __cplusplus
 extern "C"
@@ -39,7 +39,7 @@ extern "C"
 #endif
 #endif
 
-#if defined(CONFIG_TARGET_E2000)
+#if defined(CONFIG_TARGET_E2000) || defined(CONFIG_TARGET_TARDIGRADE)
 #ifndef FPIN_IO_PAD
 #define FPIN_IO_PAD
 #endif
diff --git a/bsp/phytium/libraries/standalone/common/fprintf.c b/bsp/phytium/libraries/standalone/common/fprintf.c
index a37c4d3e2ab..5f6bb43935a 100644
--- a/bsp/phytium/libraries/standalone/common/fprintf.c
+++ b/bsp/phytium/libraries/standalone/common/fprintf.c
@@ -11,14 +11,15 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: f_printf.c
+ * FilePath: fprintf.c
  * Date: 2021-08-23 16:24:02
  * LastEditTime: 2022-02-17 18:01:19
- * Description:  This files is for
+ * Description:  This file is for creating custom print interface for standlone sdk.
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0    huanghe      2022/7/23            first release
  */
 
 
@@ -37,7 +38,9 @@ static void printchar(char **str, int c)
         ++(*str);
     }
     else
+    {
         (void)putchar((const char)c);
+    }
 }
 
 static int prints(char **out, const char *string, int width, int pad)
@@ -49,13 +52,21 @@ static int prints(char **out, const char *string, int width, int pad)
         register int len = 0;
         register const char *ptr;
         for (ptr = string; *ptr; ++ptr)
+        {
             ++len;
+        }
         if (len >= width)
+        {
             width = 0;
+        }
         else
+        {
             width -= len;
+        }
         if (pad & PAD_ZERO)
+        {
             padchar = '0';
+        }
     }
     if (!(pad & PAD_RIGHT))
     {
@@ -109,7 +120,9 @@ static int printi(char **out, int i, int b, int sg, int width, int pad, int letb
     {
         t = u % b;
         if (t >= 10)
+        {
             t += letbase - '0' - 10;
+        }
         *--s = t + '0';
         u /= b;
     }
@@ -144,9 +157,13 @@ static int print(char **out, const char *format, va_list args)
             ++format;
             width = pad = 0;
             if (*format == '\0')
+            {
                 break;
+            }
             if (*format == '%')
+            {
                 goto out;
+            }
             if (*format == '-')
             {
                 ++format;
@@ -206,7 +223,9 @@ static int print(char **out, const char *format, va_list args)
         }
     }
     if (out)
+    {
         **out = '\0';
+    }
     va_end(args);
     return pc;
 }
diff --git a/bsp/phytium/libraries/standalone/common/fprintf.h b/bsp/phytium/libraries/standalone/common/fprintf.h
index 4877234b825..4659b768163 100644
--- a/bsp/phytium/libraries/standalone/common/fprintf.h
+++ b/bsp/phytium/libraries/standalone/common/fprintf.h
@@ -14,15 +14,16 @@
  * FilePath: fprintf.h
  * Date: 2021-08-23 16:24:02
  * LastEditTime: 2022-02-17 18:01:24
- * Description:  This files is for
+ * Description:  This file is for creating custom print interface for standlone sdk.
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0    huanghe      2022/7/23            first release
  */
 
-#ifndef COMMON_F_PRINTF_H
-#define COMMON_F_PRINTF_H
+#ifndef FPRINTF_H
+#define FPRINTF_H
 
 #ifdef __cplusplus
 extern "C"
diff --git a/bsp/phytium/libraries/standalone/common/fprintk.c b/bsp/phytium/libraries/standalone/common/fprintk.c
index d07f6b994a3..eb83ae74e8c 100644
--- a/bsp/phytium/libraries/standalone/common/fprintk.c
+++ b/bsp/phytium/libraries/standalone/common/fprintk.c
@@ -11,14 +11,15 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: f_printk.c
+ * FilePath: fprintk.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-17 18:01:29
- * Description:  This files is for
+ * Description:  This file is for creating custom print interface for standlone sdk.
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0    huanghe      2022/7/23            first release
  */
 
 
@@ -140,228 +141,228 @@ int cbvprintf(cbprintf_cb out, void *ctx, const char *fmt, va_list ap)
     {
         switch (*fmt)
         {
-        case 0:
-            return count;
-
-        case '%':
-            OUTC('%');
-            goto start;
+            case 0:
+                return count;
 
-        case '-':
-            padding_mode = PAD_TAIL;
-            continue;
+            case '%':
+                OUTC('%');
+                goto start;
 
-        case '.':
-            precision = 0;
-            padding_mode &= (char)~PAD_ZERO;
-            continue;
+            case '-':
+                padding_mode = PAD_TAIL;
+                continue;
 
-        case '0':
-            if (min_width < 0 && precision < 0 && !padding_mode)
-            {
-                padding_mode = PAD_ZERO;
+            case '.':
+                precision = 0;
+                padding_mode &= (char)~PAD_ZERO;
                 continue;
-            }
-            __fallthrough;
-
-        case '1':
-        case '2':
-        case '3':
-        case '4':
-        case '5':
-        case '6':
-        case '7':
-        case '8':
-        case '9':
-            if (precision >= 0)
-            {
-                precision = 10 * precision + *fmt - '0';
-            }
-            else
-            {
-                if (min_width < 0)
+
+            case '0':
+                if (min_width < 0 && precision < 0 && !padding_mode)
                 {
-                    min_width = 0;
+                    padding_mode = PAD_ZERO;
+                    continue;
                 }
-                min_width = 10 * min_width + *fmt - '0';
-            }
-            continue;
+                __fallthrough;
+
+            case '1':
+            case '2':
+            case '3':
+            case '4':
+            case '5':
+            case '6':
+            case '7':
+            case '8':
+            case '9':
+                if (precision >= 0)
+                {
+                    precision = 10 * precision + *fmt - '0';
+                }
+                else
+                {
+                    if (min_width < 0)
+                    {
+                        min_width = 0;
+                    }
+                    min_width = 10 * min_width + *fmt - '0';
+                }
+                continue;
 
-        case '*':
-            if (precision >= 0)
-            {
-                precision = va_arg(ap, int);
-            }
-            else
-            {
-                min_width = va_arg(ap, int);
-                if (min_width < 0)
+            case '*':
+                if (precision >= 0)
                 {
-                    min_width = -min_width;
-                    padding_mode = PAD_TAIL;
+                    precision = va_arg(ap, int);
                 }
-            }
-            continue;
-
-        case '+':
-        case ' ':
-        case '#':
-            special = *fmt;
-            continue;
-
-        case 'h':
-        case 'l':
-        case 'z':
-            if (*fmt == 'h' && length_mod == 'h')
-            {
-                length_mod = 'H';
-            }
-            else if (*fmt == 'l' && length_mod == 'l')
-            {
-                length_mod = 'L';
-            }
-            else if (length_mod == '\0')
-            {
-                length_mod = *fmt;
-            }
-            else
-            {
-                OUTC('%');
-                OUTC(*fmt);
-                goto start;
-            }
-            continue;
+                else
+                {
+                    min_width = va_arg(ap, int);
+                    if (min_width < 0)
+                    {
+                        min_width = -min_width;
+                        padding_mode = PAD_TAIL;
+                    }
+                }
+                continue;
 
-        case 'd':
-        case 'i':
-        case 'u':
-        {
-            uint_value_type d;
+            case '+':
+            case ' ':
+            case '#':
+                special = *fmt;
+                continue;
 
-            if (length_mod == 'z')
-            {
-                d = va_arg(ap, ssize_t);
-            }
-            else if (length_mod == 'l')
-            {
-                d = va_arg(ap, long);
-            }
-            else if (length_mod == 'L')
+            case 'h':
+            case 'l':
+            case 'z':
+                if (*fmt == 'h' && length_mod == 'h')
+                {
+                    length_mod = 'H';
+                }
+                else if (*fmt == 'l' && length_mod == 'l')
+                {
+                    length_mod = 'L';
+                }
+                else if (length_mod == '\0')
+                {
+                    length_mod = *fmt;
+                }
+                else
+                {
+                    OUTC('%');
+                    OUTC(*fmt);
+                    goto start;
+                }
+                continue;
+
+            case 'd':
+            case 'i':
+            case 'u':
             {
-                long long lld = va_arg(ap, long long);
+                uint_value_type d;
+
+                if (length_mod == 'z')
+                {
+                    d = va_arg(ap, ssize_t);
+                }
+                else if (length_mod == 'l')
+                {
+                    d = va_arg(ap, long);
+                }
+                else if (length_mod == 'L')
+                {
+                    long long lld = va_arg(ap, long long);
 
-                if (sizeof(int_value_type) < 8U &&
+                    if (sizeof(int_value_type) < 8U &&
                         lld != (int_value_type)lld)
+                    {
+                        data = "ERR";
+                        data_len = 3;
+                        precision = 0;
+                        break;
+                    }
+                    d = (uint_value_type)lld;
+                }
+                else if (*fmt == 'u')
                 {
-                    data = "ERR";
-                    data_len = 3;
-                    precision = 0;
-                    break;
+                    d = va_arg(ap, unsigned int);
+                }
+                else
+                {
+                    d = va_arg(ap, int);
                 }
-                d = (uint_value_type)lld;
-            }
-            else if (*fmt == 'u')
-            {
-                d = va_arg(ap, unsigned int);
-            }
-            else
-            {
-                d = va_arg(ap, int);
-            }
 
-            if (*fmt != 'u' && (int_value_type)d < 0)
-            {
-                d = -d;
-                prefix = "-";
-                min_width--;
-            }
-            else if (special == ' ')
-            {
-                prefix = " ";
-                min_width--;
-            }
-            else if (special == '+')
-            {
-                prefix = "+";
-                min_width--;
-            }
-            else
-            {
-                ;
+                if (*fmt != 'u' && (int_value_type)d < 0)
+                {
+                    d = -d;
+                    prefix = "-";
+                    min_width--;
+                }
+                else if (special == ' ')
+                {
+                    prefix = " ";
+                    min_width--;
+                }
+                else if (special == '+')
+                {
+                    prefix = "+";
+                    min_width--;
+                }
+                else
+                {
+                    ;
+                }
+                data_len = convert_value(d, 10, 0, buf + sizeof(buf));
+                data = buf + sizeof(buf) - data_len;
+                break;
             }
-            data_len = convert_value(d, 10, 0, buf + sizeof(buf));
-            data = buf + sizeof(buf) - data_len;
-            break;
-        }
 
-        case 'p':
-        case 'x':
-        case 'X':
-        {
-            uint_value_type x;
-
-            if (*fmt == 'p')
+            case 'p':
+            case 'x':
+            case 'X':
             {
-                x = (uintptr_t)va_arg(ap, void *);
-                if (x == (uint_value_type)0)
+                uint_value_type x;
+
+                if (*fmt == 'p')
                 {
-                    data = "(nil)";
-                    data_len = 5;
-                    precision = 0;
-                    break;
+                    x = (uintptr_t)va_arg(ap, void *);
+                    if (x == (uint_value_type)0)
+                    {
+                        data = "(nil)";
+                        data_len = 5;
+                        precision = 0;
+                        break;
+                    }
+                    special = '#';
                 }
-                special = '#';
-            }
-            else if (length_mod == 'l')
-            {
-                x = va_arg(ap, unsigned long);
-            }
-            else if (length_mod == 'L')
-            {
-                x = va_arg(ap, unsigned long long);
-            }
-            else
-            {
-                x = va_arg(ap, unsigned int);
-            }
-            if (special == '#')
-            {
-                prefix = (*fmt & 0x20) ? "0x" : "0x";
-                min_width -= 2;
+                else if (length_mod == 'l')
+                {
+                    x = va_arg(ap, unsigned long);
+                }
+                else if (length_mod == 'L')
+                {
+                    x = va_arg(ap, unsigned long long);
+                }
+                else
+                {
+                    x = va_arg(ap, unsigned int);
+                }
+                if (special == '#')
+                {
+                    prefix = (*fmt & 0x20) ? "0x" : "0x";
+                    min_width -= 2;
+                }
+                data_len = convert_value(x, 16, ALPHA(*fmt),
+                                         buf + sizeof(buf));
+                data = buf + sizeof(buf) - data_len;
+                break;
             }
-            data_len = convert_value(x, 16, ALPHA(*fmt),
-                                     buf + sizeof(buf));
-            data = buf + sizeof(buf) - data_len;
-            break;
-        }
 
-        case 's':
-        {
-            data = va_arg(ap, char *);
-            data_len = strlen(data);
-            if (precision >= 0 && data_len > precision)
+            case 's':
             {
-                data_len = precision;
+                data = va_arg(ap, char *);
+                data_len = strlen(data);
+                if (precision >= 0 && data_len > precision)
+                {
+                    data_len = precision;
+                }
+                precision = 0;
+                break;
             }
-            precision = 0;
-            break;
-        }
 
-        case 'c':
-        {
-            int c = va_arg(ap, int);
+            case 'c':
+            {
+                int c = va_arg(ap, int);
 
-            buf[0] = c;
-            data = buf;
-            data_len = 1;
-            precision = 0;
-            break;
-        }
+                buf[0] = c;
+                data = buf;
+                data_len = 1;
+                precision = 0;
+                break;
+            }
 
-        default:
-            OUTC('%');
-            OUTC(*fmt);
-            goto start;
+            default:
+                OUTC('%');
+                OUTC(*fmt);
+                goto start;
         }
 
         if (precision < 0 && (padding_mode & PAD_ZERO))
@@ -403,7 +404,7 @@ int cbvprintf(cbprintf_cb out, void *ctx, const char *fmt, va_list ap)
     }
 }
 
-static int f_vprintf(const char *restrict format, va_list vargs)
+static void f_vprintf(const char *restrict format, va_list vargs)
 {
     struct str_context ctx = {0};
     cbvprintf(char_out, &ctx, format, vargs);
diff --git a/bsp/phytium/libraries/standalone/common/fprintk.h b/bsp/phytium/libraries/standalone/common/fprintk.h
index 907b841ca79..2e271b37e51 100644
--- a/bsp/phytium/libraries/standalone/common/fprintk.h
+++ b/bsp/phytium/libraries/standalone/common/fprintk.h
@@ -14,22 +14,23 @@
  * FilePath: fprintk.h
  * Date: 2021-08-23 16:24:02
  * LastEditTime: 2022-02-17 18:01:35
- * Description:  This files is for
+ * Description:  This file is for creating custom print interface for standlone sdk.
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0    huanghe      2022/7/23            first release
  */
 
-#ifndef COMMON_F_PRINTK_H
-#define COMMON_F_PRINTK_H
+#ifndef FPRINTK_H
+#define FPRINTK_H
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-int f_printk(const char *format, ...) ;
+void f_printk(const char *format, ...) ;
 
 #ifdef __cplusplus
 }
diff --git a/bsp/phytium/libraries/standalone/common/fswap.h b/bsp/phytium/libraries/standalone/common/fswap.h
new file mode 100644
index 00000000000..51d16593d92
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/common/fswap.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fswap.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:35:24
+ * Description:  This files is for endian conversion.
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu  2021/06/15        first release
+ */
+
+#ifndef FSWAP_H
+#define FSWAP_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define __swab16(x) (uint16_t)__builtin_bswap16((uint16_t)(x))
+#define __swab32(x) (uint32_t)__builtin_bswap32((uint32_t)(x))
+#define __swab64(x) (uint64_t)__builtin_bswap64((uint64_t)(x))
+
+#define cpu_to_le64(x) ((__u64)(x))
+#define le64_to_cpu(x) ((__le64)(x))
+#define cpu_to_le32(x) ((__u32)(x))
+#define le32_to_cpu(x) ((__le32)(x))
+#define cpu_to_le16(x) ((__u16)(x))
+#define le16_to_cpu(x) ((__le16)(x))
+#define cpu_to_be64(x) __swab64((x))
+#define be64_to_cpu(x) __swab64((x))
+#define cpu_to_be32(x) __swab32((x))
+#define be32_to_cpu(x) __swab32((x))
+#define cpu_to_be16(x) __swab16((x))
+#define be16_to_cpu(x) __swab16((x))
+
+#define ___htonl(x) cpu_to_be32(x)
+#define ___htons(x) cpu_to_be16(x)
+#define ___ntohl(x) be32_to_cpu(x)
+#define ___ntohs(x) be16_to_cpu(x)
+
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/common/ftypes.h b/bsp/phytium/libraries/standalone/common/ftypes.h
index aa097b3aded..1ec12c05a3d 100644
--- a/bsp/phytium/libraries/standalone/common/ftypes.h
+++ b/bsp/phytium/libraries/standalone/common/ftypes.h
@@ -14,25 +14,27 @@
  * FilePath: ftypes.h
  * Date: 2021-05-27 13:30:03
  * LastEditTime: 2022-02-18 08:24:15
- * Description:  This files is for
+ * Description:  This file is for variable type definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu   2021/05/27  init
+ * 1.1  zhugengyu   2022/02/18  add some typedef
  */
 
 
-#ifndef _BSP_COMMON_FT_TYPE_H
-#define _BSP_COMMON_FT_TYPE_H
+#ifndef FTYPES_H
+#define FTYPES_H
+
+#include <stdint.h>
+#include <stddef.h>
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include <stdint.h>
-#include <stddef.h>
-
 #define FT_COMPONENT_IS_READY 0x11111111U
 #define FT_COMPONENT_IS_STARTED 0x22222222U
 
diff --git a/bsp/phytium/libraries/standalone/doc/ChangeLog.md b/bsp/phytium/libraries/standalone/doc/ChangeLog.md
index 376e459c685..4e4f95863fc 100644
--- a/bsp/phytium/libraries/standalone/doc/ChangeLog.md
+++ b/bsp/phytium/libraries/standalone/doc/ChangeLog.md
@@ -1,3 +1,553 @@
+# Phytium Standalone SDK 2023-3-2 ChangeLog
+
+Change Log since 2023-03-01
+
+- modify for drvier and arch de-couple
+
+## aarch && common
+
+- move felf, finterrupt and fsleep from common to arch, which are arch related
+- move fkernel, fswap from arch to common, which are not arch related
+- fix issue that f_printk have different reture type in implmentation and declaration, which is considered a warning for compiler
+
+## make
+
+- add drviver.mk, board.mk, arch.mk and lib.mk, to seprate src and inc to groups
+- remove un-used packsource.mk
+- support compiling with makefile depends
+- support compiling drviver only without arch support 
+
+## drivers
+
+- remove un-used reference to finterrupt.h
+- add port folder to implment stub function of arch
+
+## tools
+
+- add tool export-sdk, demo the usage in export rt-thread bsp
+- remove un-used export_rtt_bsp.py
+
+# Phytium Standalone SDK 2023-3-2 ChangeLog
+
+Change Log since 2023-03-01
+
+## baremetal
+
+- add multi-display test example 
+
+## driver
+
+- add multi-display driver and change the config
+
+## third-party
+
+- change the lvgl/port config and adapt to the multi-display config
+
+# Phytium Standalone SDK 2023-3-1 ChangeLog
+
+Change Log since 2023-02-20
+
+## aarch
+
+- Modify AARCH32 and AARCH32 interrupt handler function
+
+## driver
+
+- fix bug of can id handler
+
+## example
+
+- add system/nested_interrupt test example
+- adapt gic sgi test example
+
+# Phytium Standalone SDK 2023-02-27 ChangeLog
+
+Change Log since 2023-02-22
+
+## example
+
+- Adapt the OpenAMP routine to e2000q/d and fix some errors
+
+## third party
+
+* Fixed a flag bit error in non-IPi mode
+
+# Phytium Standalone SDK 2023-02-24 ChangeLog
+
+Change Log since 2023-02-22
+
+## aarch
+
+- move BOOT_WITH_FLUSH_CACHE code into CONFIG_USE_AARCH64_L1_TO_AARCH32
+
+## make
+
+- add E2000/D2000 board config loader/saver
+
+## tools
+
+- rename 'make boot' as 'make deploy' and move to console.mk
+- add config of pre-upload image name and folder
+
+## example
+
+- reduce dupliace 'make boot' and unused makefile target
+
+# Phytium Standalone SDK 2023-02-22 ChangeLog
+
+Change Log since 2023-02-21
+
+## aarch
+
+- add config BOOT_WITH_FLUSH_CACHE and support flush dcache before boot image
+
+# Phytium Standalone SDK 2023-02-21 ChangeLog
+
+Change Log since 2023-02-21
+
+## example
+
+- modified uart fifo test display
+
+# Phytium Standalone SDK 2023-02-21 ChangeLog
+
+Change Log since 2023-02-16
+
+## third party
+
+- modify sfud
+
+# Phytium Standalone SDK 2023-02-16 ChangeLog
+
+Change Log since 2023-02-15
+
+## example
+
+- add uart FIFO test example
+- refresh picture of uart test example
+
+## driver
+
+- fix bug of uart tx_send
+
+# Phytium Standalone SDK 2023-02-15 ChangeLog
+
+Change Log since 2023-02-13
+
+## example
+
+- add sfud_test example
+
+## third party
+
+- modify sfud
+
+# Phytium Standalone SDK 2023-02-09 ChangeLog
+
+Change Log since 2023-02-07
+
+## board
+
+- add E2000 MHU module define
+
+## example
+
+- add scmi example project
+
+## driver
+
+- add scmi base protocol support
+- add mhu of E2000 support
+- add scmi sensor protocol support
+- add scmi performance protocol support
+- add scmi communication to SCP
+
+## doc
+
+- add fscmi_mhu.md file that introduce how to use scmi_mhu drivers
+
+# Phytium Standalone SDK 2023-02-07 ChangeLog
+
+## example
+
+- remove build_all in example
+- set CONFIG_OUTPUT_BINARY as defaut ON
+- modify USR_SRC_DIR in raw_api example to absolute path
+
+## make
+
+- remove build_all.mk
+- add default_load.mk
+- modify compiling output style
+- add make flash_serial to support ymodem image flash
+
+## script
+
+- add script to support ymodem flash and serial access
+
+# Phytium Standalone SDK 2023-01-30 ChangeLog
+
+Change Log since 2023-01-10
+
+## example
+
+- Adapt to tardigrade
+
+## driver
+
+- Adapt to tardigrade
+
+# Phytium Standalone SDK 2023-01-18 v1.0.0 ChangeLog
+
+Change Log since 2023-01-12
+
+## README
+
+- add developer infomation
+- install.py update including version infomation modified
+
+## example
+
+- all example xxxx_eg_configs update
+- all example sdkconfig sdkconfig.h update
+- get-start/hello_world readme update
+- peripheral/dma/fgdma_async_memcpy/README.md update
+- peripheral/gic/fgic_test/README.md update
+- peripheral/ipc/fsemaphore_test/README.md update
+- storage/spi_sfud/README.md update
+- peripheral/media/lvgl_test/README.md update
+- peripheral/media/media_test/README.md update
+- system/exception_debug/main.c add stdio.h,delete fprintk.h
+- peripheral/qspi/qspi_nor_flash add flash type info
+- peripheral/qspi/qspi_nor_flash cmd qspi auto related codes modified
+
+# Phytium Standalone SDK 2023-01-16 ChangeLog
+
+Change Log since 2023-01-11
+
+## example
+
+- e2000q adds nand test configuration
+
+# Phytium Standalone SDK 2023-01-11 ChangeLog
+
+Change Log since 2023-01-11
+
+## example
+
+- add header for some .c .h files in example folder of media.
+
+## driver
+
+- add header for some .c .h files in driver folder of media
+
+## third-party
+
+- change folder of lvgl name to lvgl-8.3
+- add header for some .c .h files in driver folder of third-party/lvgl-8.3/port
+
+# Phytium Standalone SDK 2023-01-11 ChangeLog
+
+Change Log since 2023-01-09
+
+## example
+
+- add header for some .c .h files in example folder.
+
+## driver
+
+- add header for some .c .h files in driver folder.
+
+# Phytium Standalone SDK 2023-01-09 ChangeLog
+
+Change Log since 2022-12-30
+
+## drivers
+
+- eth/nand/mmc module to add comments
+
+## third-party
+
+- libmetal/backtrace/openamp module to add comments
+
+## example
+
+- nand/amp module to add comments
+
+## common
+
+- finterrupt module to add comments
+
+# Phytium Standalone SDK 2023-01-09 ChangeLog
+
+Change Log since 2023-01-09
+
+## example
+
+- network/lwip_startup add func sys_now
+- The data type of timer_base_cnt is unified from u64 to u32.
+- LwipTestLoop func modified. add  LinkDetectLoop(netif).
+
+# Phytium Standalone SDK 2023-01-04 ChangeLog
+
+Change Log since 2023-01-03
+
+## example
+
+- add header for all .c .h files in example/network
+
+## common
+
+- add header for files (fsleep fprintf fpritk) .c  .h in common/
+
+## third-party
+
+- modify lwip-2.1.2/ports/kconfig
+- modify lwip-2.1.2/kconfig
+- add header for all .c .h files in lwip-2.1.2/ports
+
+# Phytium Standalone SDK 2022-12-30 ChangeLog
+
+Change Log since 2022-12-27
+
+## drivers
+
+- update format for eth, usb, pcie, sdmmc
+
+# Phytium Standalone SDK 2022-12-30 ChangeLog
+
+Change Log since 2022-12-23
+
+## drivers
+
+- modify format issues in gic/i2c/ipc/pin/sata/timer/watchdog
+
+## third-party
+
+- add sata fatfs_0.1.4 port
+- delete fatfs_0.1.3 content
+- delete storage/sata_fatfs content
+
+# Phytium Standalone SDK 2022-12-30 ChangeLog
+
+Change Log since 2022-12-22
+
+## example
+
+- modify peripheral/  adc nand serial
+
+## drivers
+
+- modify adc nand serial
+
+## common
+
+- Modify the header file name to be consistent with the header macro definition
+- Print interface range adjustment
+
+# Phytium Standalone SDK 2022-12-27 ChangeLog
+
+Change Log since 2022-12-21
+
+## example
+
+- update print info for gic example
+
+## drivers
+
+- update format for can/gic/rtc
+- add file declare for pin/spi/usb
+
+## third-party
+
+- update fatfs/littlefs/lwip/sdmmc file declare
+
+# Phytium Standalone SDK 2022-12-21 ChangeLog
+
+Change Log since 2022-12-20
+
+## drivers
+
+- modify format issues in spi
+- modify format issues in pwm
+
+## third-party
+
+- modify format issues in sfud
+- modify format issues in littlefs
+
+# Phytium Standalone SDK 2022-12-20 ChangeLog
+
+Change Log since 2022-12-14
+
+## driver
+
+- modify format issues in dma
+
+## example
+
+- Modify format issues in dma example
+
+# Phytium Standalone SDK 2022-12-14 ChangeLog
+
+Change Log since 2022-12-08
+
+## aarch64
+
+- modify FilePath name
+- adjust macro definit and c++ support
+
+## arch/common
+
+- modify FilePath name
+- adjust  macro definit and c++ support
+
+## example
+
+- adjust "printf" and remove "FT_DEBUG_PRINT_*"
+- modify baremetal/example/storage/qspi_sfud/inc/qspi_sfud_example.h macro definit
+
+## common
+
+- modify FilePath name
+- adjust macro definit and c++ support
+- adjust Print interface that will be use f_printk
+
+## README.md
+
+- modify chip description
+
+# Phytium Standalone SDK 2022-12-14 ChangeLog
+
+Change Log since 2022-12-08
+
+## third-party
+
+- freemodbus-v16/port/port.h ,modify the #include "fcp15.h" ,only used in _aarch32_
+- freemodbus-v16/port/porttimer.c,change the TIMER_CLK_FREQ_HZ as FTIMER_CLK_FREQ_HZ
+- freemodbus-v16/port/porttimer.c,change the TIMER_TACHO_IRQ_ID as FTIMER_TACHO_IRQ_NUM
+
+# Phytium Standalone SDK 2022-12-08 ChangeLog
+
+Change Log since 2022-12-05
+
+## example
+
+- add LSuserShellNoWaitLoop api.This api can enables the NIC to receive data without blocking.
+- modify file format  all file adopt lf format.
+- add network/lwip_startup
+- add network/raw_api/tcp_client
+- add network/raw_api/tcp_server
+- add network/raw_api/udp_client
+- add network/raw_api/udp_server
+- delete lwip_tftpclient
+- delete lwip_echo
+
+## third-party
+
+- add lwip_port.c && lwip_port.h
+- Restructuring the directory lwip-2.1.2/ports
+
+# Phytium Standalone SDK 2022-12-06 ChangeLog
+
+Change Log since 2022-12-06
+
+## drivers
+
+- Add media drivers ,including the dc & dp
+
+## example
+
+- Add media test to light the screen
+- Add LVGL demo to test the benchmark
+
+## third-party
+
+- Add LVGL library
+
+## README
+
+- Add media config
+
+# Phytium Standalone SDK 2022-12-06 ChangeLog
+
+Change Log since 2022-12-02
+
+## example
+
+- merge fatfs tests (usb/sdmmc/sdio)
+- merge sdmmc tests (fsdmmc/fsdio)
+
+## driver
+
+- fix fsdio multi-block issue
+- add data barrier to avoid optim issue (fsdio/fsdmmc)
+
+## third-party
+
+- add fatfs 0.1.4 and related configs
+- port multi storage type with glue, therefore multi storage can be used at one binary image
+
+# Phytium Standalone SDK 2022-12-02 ChangeLog
+
+Change Log since 2022-12-01
+
+## example
+
+- add freemodbus test example
+- add readme file and E2000Q and E2000D configs
+
+## third-party
+
+- add freemodbus V1.6
+- modified protocol port file of serial
+- add Kconfig to select peripheral and chip
+- modified third-party.mk to add complie freemodbus files
+
+# Phytium Standalone SDK 2022-12-1 ChangeLog
+
+Change Log sinc 2022-11-28
+
+## board
+
+- Unified parameter format in fparameters.h
+- Move fearly_uart module  to common folder
+
+# Phytium Standalone SDK 2022-11-04 v0.4.0 ChangeLog
+
+Change Log since 2022-11-01
+
+## README
+
+- add gitee branch description
+
+## example
+
+- add E2000D/Q default config
+- add test picture
+- modified example description
+- adjust example cmd
+- update get-start\hello_world readme
+- add  get-start\hello_world fig indicating test result
+- update qspi/rtc/wdt_test/sdmmc_cmd/qspi_sfud config for d2000 board
+- update letter_shell readme
+- update adc/pcie/qspi example for E2000 Demo board
+- update lwip_echo/exception_debug/letter_shell_test/memory_pool_test/newlibc_test readme
+- update exception_debug/letter_shell_test/memory_pool_test/newlibc_test examples for E2000 Q Demo board
+
+# Phytium Standalone SDK 2022-11-01 ChangeLog
+
+Change Log since 2022-10-26
+
+## drivers
+
+- fix bug in get pin pull mode
+- fix bug in gpio 4/5, irq num mistype
+
+## example
+
+- update spi/sdio/gpio/usb example for E2000 Q Demo board
+
 # Phytium Standalone SDK 2022-10-26 ChangeLog
 
 Change Log sinc 2022-10-21
@@ -118,7 +668,6 @@ Change Log since 2022-08-24
 
 - Modify adc test example, add auto test
 
-
 # Phytium Standalone SDK 2022-8-18 ChangeLog
 
 Change Log since 2022-08-16
@@ -174,12 +723,12 @@ Change Log since 2022-08-11
 - Modify rtc rtc_ds1339 example to support e2000q,add e2000q default configs
 - Modify timer timer_tacho example to support e2000q,add e2000q default configs
 
-
 # Phytium Standalone SDK 2022-8-11 v0.3.1 ChangeLog
 
 Change Log since v0.3.0
 
 ## README
+
 - add E2000D/S description
 
 # Phytium Standalone SDK 2022-8-5 v0.3.0 ChangeLog
@@ -197,7 +746,7 @@ Change Log since 2022-08-04
 
 ## third-party
 
-- Restruct adapter e2000 
+- Restruct adapter e2000
 
 # Phytium Standalone SDK 2022-08-04 ChangeLog
 
@@ -277,6 +826,7 @@ Change Log since 2022-7-29
 ## example
 
 - Modify the lwip_echo example
+
 # Phytium Standalone SDK 2022-07-29 ChangeLog
 
 Change Log since 2022-07-18
@@ -294,6 +844,7 @@ Change Log since 2022-07-18
 # third-party
 
 - fix sfud, spiffs, fatfs modules
+
 # Phytium Standalone SDK 2022-07-27 ChangeLog
 
 Change Log since 2022-07-14
@@ -336,7 +887,7 @@ Change Log since 2022-6-20
 - modify e2000 iomux set function
 - modify some parameters
 
-# driver 
+# driver
 
 - modify qspi read and write driver for E2000, add register port read and write data
 - modify sata controller and pcie-sata read and write driver for E2000
@@ -377,11 +928,11 @@ Change Log since 2022-6-30
 
 - modify e2000 fparameters_comm.h and add set mio function
 
-# driver 
+# driver
 
 - add fi2c configs and init things
 - create Mio driver for E2000
-- modify uart configs to support E2000 
+- modify uart configs to support E2000
 
 # example
 
@@ -406,7 +957,7 @@ Change Log since 2022-6-28
 
 # third-party
 
-- modify sfud fspim port to support cs-set 
+- modify sfud fspim port to support cs-set
 
 # example
 
@@ -429,10 +980,10 @@ Change Log since 2022-6-20
 
 - update fgpio for E2000
 
-
 # Phytium Standalone SDK 2022-06-20 ChangeLog
 
 Change Log since 2022-6-16
+
 ## arch
 
 - fix aarch32 Bss clear bug
@@ -512,7 +1063,7 @@ Change Log since 2022-6-10
 
 ## README
 
-- remove Linux arm aarch64 development environment 
+- remove Linux arm aarch64 development environment
 
 # Phytium Standalone SDK 2022-6-10 ChangeLog
 
@@ -575,7 +1126,6 @@ Change Log since 2022-5-7
 
 # Phytium Standalone SDK 2022-5-13 ChangeLog
 
-
 Change Log since 2022-5-5
 
 ## drivers
@@ -610,12 +1160,13 @@ Change Log since 2022-4-15
 ## example
 
 - Change the command interface
-- Add virtual eeprom 
+- Add virtual eeprom
 - Simulate master-slave communication at D2000
 
 # Phytium Standalone SDK 2022-4-22 ChangeLog
 
 Change Log since 2022-4-15
+
 ## drivers
 
 - Restruct I2C driver
@@ -647,6 +1198,7 @@ Change Log since 2022-4-11
 
 - Add mac lwip port layer to support gmac and xmac
 - Restruct gmac and xmac lwip interface
+
 # Phytium Standalone SDK 2022-4-15 ChangeLog
 
 Change Log since 2022-4-8
@@ -681,7 +1233,7 @@ Change Log since 2022-4-8
 
 ## third-party
 
-- add spiffs 
+- add spiffs
 - add littlefs, support littlefs dry-run
 
 ## common
@@ -719,7 +1271,6 @@ Change Log since 2022-2-18
 
 - re-organize example of qspi test, broken down into peripheral and storage
 
-
 # Phytium Standalone SDK 2022-3-25 ChangeLog
 
 Chang Log since 2022-3-18
@@ -767,7 +1318,7 @@ Chang Log since 2022-2-18
 
 Change Log since 2022-2-18
 
-## arch 
+## arch
 
 - Modified some parameters in the MMU and added FSetTlbAttributes interfaces
 
@@ -810,15 +1361,14 @@ Change Log since 2021-02-7
 
 ## common
 
-- Modify the function interface in the _cpu.c document to change the core content not to respond when the work core does not support it  
-
-- Fixing interrupt.c initialization problems  
+- Modify the function interface in the _cpu.c document to change the core content not to respond when the work core does not support it
+- Fixing interrupt.c initialization problems
 
 ## gicv3
 
-- Modifying cpu interface processing of multi-core interfaces in gicv3 
+- Modifying cpu interface processing of multi-core interfaces in gicv3
 
-##  example
+## example
 
 - Modifying the handling of multi-core function interfaces in Libmetal
 
@@ -907,31 +1457,30 @@ Change Log since 2021-11-25
 
 ## arch
 
-1. Add stack initialization  
+1. Add stack initialization
 2. Locate the final mode in SVC mode
-3. Initialize the BSS and SBSS segments  
-4. Copy data to the RAM  
-5. Enable the FPU function  
-6. Fpu is pushed when irq is abnormal  
-7. Other exceptions are treated as error exceptions  
+3. Initialize the BSS and SBSS segments
+4. Copy data to the RAM
+5. Enable the FPU function
+6. Fpu is pushed when irq is abnormal
+7. Other exceptions are treated as error exceptions
 
 ## ld
 
-1. Add stack parameter Settings for different exceptions  
-2. Rename variables in different sections  
+1. Add stack parameter Settings for different exceptions
+2. Rename variables in different sections
 
 ## example
 
 1. Letter_shell test modifies the makefile
 
-
 # Phytium Standalone SDK 2021-11-25 ChangeLog
 
 Change Log since v0.1.14
 
 ## third-party
 
-- add sfud qspi test 
+- add sfud qspi test
 - restruct sfud_port.c, add spi and qspi probe
 
 ## drivers
@@ -1011,7 +1560,7 @@ Change Log since v0.1.11, 2021.11.15
 
 Change Log since v0.1.10, 2021.11.9
 
-## example 
+## example
 
 - add fspi nor flash example
 
@@ -1067,7 +1616,7 @@ Change Log since v0.1.8, 2021.11.1
 
 - add L3 cache disable
 - modify the savefloatRegister location
-- add 
+- add
 
 # Phytium Standalone SDK v0.1.8 ChangeLog
 
@@ -1094,7 +1643,7 @@ Change Log since v0.1.7, 2021.11.1
 
 ## doc
 
-- add i2c driver api refernce 
+- add i2c driver api refernce
 - add i2c slave & i2c eeprom readme
 - add driver template
 - add more design figure *.dio
@@ -1123,7 +1672,7 @@ Change Log since v0.1.5, 2021.10.19
 - install cross tool to `PHYTIUM_DEV_PATH`
 - update GNU CC version to 10.3.1-2021.07
 - modify CC libc.a for printf issue
-- merge newlib to CC tool 
+- merge newlib to CC tool
 
 # Phytium Standalone SDK v0.1.5 ChangeLog
 
@@ -1146,7 +1695,7 @@ Change Log since v0.1.3, 2021.10.13
 
 ## driver
 
-- add iomux for E2000 
+- add iomux for E2000
 - add nandflash driver for E2000
 
 ## third-party
@@ -1231,6 +1780,7 @@ Change Log since v0.0.11
 - support linkscript config with sdkconfig.h
 
 # Phytium Standalone SDK v0.0.11 ChangeLog
+
 Change Log since v0.0.10
 
 ## drivers
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.c b/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.c
index 75fb7437599..3020d9173e9 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.c
@@ -14,7 +14,7 @@
  * FilePath: foox_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:47
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.h b/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.h
index 47bbfb4a1f2..13748650f7a 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.h
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/foox_hw.h
@@ -14,7 +14,7 @@
  * FilePath: foox_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:52
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/foox_options.c b/bsp/phytium/libraries/standalone/doc/driver_template/foox_options.c
index cd0ae66d342..6e132fe9a83 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/foox_options.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/foox_options.c
@@ -14,7 +14,7 @@
  * FilePath: foox_options.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:58
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/foox_role.c b/bsp/phytium/libraries/standalone/doc/driver_template/foox_role.c
index 90960fc4f1c..b3ed3ab919c 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/foox_role.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/foox_role.c
@@ -14,7 +14,7 @@
  * FilePath: foox_role.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:03
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.c b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.c
index 539688f2460..5efc3ab35be 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.c
@@ -14,7 +14,7 @@
  * FilePath: fooxx.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.h b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.h
index ad27bbaf05e..023bbfbe315 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.h
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx.h
@@ -14,7 +14,7 @@
  * FilePath: fooxx.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:35
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_g.c b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_g.c
index f3a10eec57b..a5ce6f65aea 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_g.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_g.c
@@ -14,7 +14,7 @@
  * FilePath: fooxx_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:09
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_sinit.c b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_sinit.c
index fa31af0ae9d..2fbe421f642 100644
--- a/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_sinit.c
+++ b/bsp/phytium/libraries/standalone/doc/driver_template/fooxx_sinit.c
@@ -14,7 +14,7 @@
  * FilePath: fooxx_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:15
- * Description:  This files is for
+ * Description:  This file is for
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/doc/fig/disk_manager.png b/bsp/phytium/libraries/standalone/doc/fig/disk_manager.png
new file mode 100644
index 00000000000..cfc5173175d
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diff --git a/bsp/phytium/libraries/standalone/doc/fig/sd_image.png b/bsp/phytium/libraries/standalone/doc/fig/sd_image.png
new file mode 100644
index 00000000000..cdbbf234754
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diff --git a/bsp/phytium/libraries/standalone/doc/fig/sd_insert.png b/bsp/phytium/libraries/standalone/doc/fig/sd_insert.png
new file mode 100644
index 00000000000..9d9623cbc81
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/sd_insert.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/fig/sd_partinfo.png b/bsp/phytium/libraries/standalone/doc/fig/sd_partinfo.png
new file mode 100644
index 00000000000..cb186a2aafa
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/sd_partinfo.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/fig/sd_segement.png b/bsp/phytium/libraries/standalone/doc/fig/sd_segement.png
new file mode 100644
index 00000000000..b32d0a58f53
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/sd_segement.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/fig/usb_disk.png b/bsp/phytium/libraries/standalone/doc/fig/usb_disk.png
new file mode 100644
index 00000000000..63a0fa9459d
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/usb_disk.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/fig/usb_image.png b/bsp/phytium/libraries/standalone/doc/fig/usb_image.png
new file mode 100644
index 00000000000..a92593a6fa4
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/usb_image.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/fig/usb_insert.png b/bsp/phytium/libraries/standalone/doc/fig/usb_insert.png
new file mode 100644
index 00000000000..a0e70a90504
Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/usb_insert.png differ
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fadc.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fadc.md
index eaee72661cd..47f22ea096d 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fadc.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fadc.md
@@ -139,7 +139,7 @@ typedef enum
 - 获取fadc控制器默认配置
 
 ```c
-const FAdcConfig *FAdcLookupConfig(FAdcInstance instance_id);
+const FAdcConfig *FAdcLookupConfig(u32 instance_id);
 ```
 
 Note:
@@ -148,7 +148,7 @@ Note:
 
 Input:
 
-- {FAdcInstance} instance_id，adc控制器id号
+- {u32} instance_id，adc控制器id号
 
 Return:
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fcan.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fcan.md
index 449d9c89938..53e2c190386 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fcan.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fcan.md
@@ -115,7 +115,7 @@ typedef enum
 - 获取Fata控制器默认配置
 
 ```c
-const FCanConfig *FCanLookupConfig(FCanInstance instance_id);
+const FCanConfig *FCanLookupConfig(u32 instance_id);
 ```
 
 Note:
@@ -124,7 +124,7 @@ Note:
 
 Input:
 
-- {FCanInstance} instance_id，控制器id号
+- {u32} instance_id，控制器id号
 
 Return:
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md
index 4305d062bee..7cac74a8201 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md
@@ -45,12 +45,13 @@ fgdma
 typedef struct
 {
     u32 instance_id;               /* GDMA控制器ID */
-    u32 irq_num;                   /* GDMA控制器中断号 */
+    u32 irq_num[FGDMA_NUM_OF_CHAN];   /* GDMA控制器中断号 */
     u32 irq_prority;               /* GDMA控制器中断优先级 */
     volatile uintptr_t base_addr;  /* GDMA控制器基地址 */
     FGdmaOperPriority rd_qos;      /* 读操作优先级 */
     FGdmaOperPriority wr_qos;      /* 写操作优先级 */
-} FGdmaConfig;
+    u32 caps;                       /* driver capacity */
+} FGdmaConfig; /* GDMA控制器配置 */
 ```
 
 #### FGdmaChanConfig
@@ -126,6 +127,16 @@ typedef struct
 } __attribute__((__packed__)) FGdmaBdlDesc; /* BDL描述符 */
 ```
 
+```c
+/* gdma capacity mask  */
+
+#define FGDMA_IRQ1_MASK BIT(0)   /* All Gdma channel share a single interrupt */
+#define FGDMA_IRQ2_MASK BIT(1)   /* Each gdma channel owns an independent interrupt */
+#define FGDMA_TRANS_NEED_RESET_MASK BIT(2) /* Gdma needs to be reset before transmission */
+
+```
+
+
 ### 5.2  错误码定义
 
 #define FGDMA_SUCCESS           : 成功      
@@ -338,7 +349,26 @@ void FGdmaIrqHandler(s32 vector, void *args)
 
 Note:
 
-- GDMA中断处理函数
+- 当 FGdmaConfig.caps 为FGDMA_IRQ1_MASK 特性时，各通道统一上报至一个中断，选择使用此函数作为中断处理函数
+
+Input:
+
+- {s32} vector, 中断号
+- {void} *args, 中断参数
+
+Return:
+
+- 无
+
+
+#### FGdmaIrqHandlerPrivateChannel
+```c
+void FGdmaIrqHandlerPrivateChannel(s32 vector, void *args)
+```
+
+Note:
+
+- 当 FGdmaConfig.caps 为FGDMA_IRQ2_MASK 特性时，各通道独立上报中断，选择使用此函数作为中断处理函数
 
 Input:
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fi2c.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fi2c.md
index 5321e1a7c9b..0da1beb61a8 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fi2c.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fi2c.md
@@ -7,7 +7,7 @@
 
 - I2C 具有简单且制造成本低廉等优点，主要用于低速外围设备的短距离通信（一英尺以内）。
 
-- I2C 驱动支持的平台包括 FT2000/4、D2000。
+- I2C 驱动支持的平台包括 FT2000/4、D2000、E2000。
 
 
 ## 2. 驱动功能
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md
new file mode 100644
index 00000000000..20c8943ecf0
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md
@@ -0,0 +1,369 @@
+<!--
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmedia.md
+ * Date: 2022-12-07 19:57:17
+ * LastEditTime: 2022-12-07 19:57:18
+ * Description:  This file is for 
+ * 
+ * Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+-->
+
+# 驱动概述
+
+- DC 是一个显示控制器，主要完成将 CPU/GPU/VPU 处理后的图像数据，按照 Display 协议处理后送给 DP PHY 接入显示器。E2000 下 DC 主要有以下特性
+
+1. 支持两路Display,两路Display相互独立
+2. 支持的 size 有 640×480、800×600、1024×768、1152×864、1280×720、1280×960、1366×768、1440×900、1600×90、1920×1080，最大帧率为 2.7G/(size*32)
+3. 支持AHB配置寄存器
+4. 支持Hsync,Vsync配置
+5. 输出支持像素格式：RGB2101010，RGB888，RGB666，RGB555
+6. 输入图像格式：ARGB2101010，A/XRGB8888，A/XRGB1555，A/XRGB4444，RGB565；YUV422(YUY2，UYVY，NV16)；YUV420(YUY2(P010)YV12，NV12，NV21)
+
+当前Media 驱动控制器主要为用户提供了以下功能接口
+
+1. DC,DP 控制器状态初始化函数
+2. 中断接口
+3. 热插拔检测处理接口
+4. 多屏模式处理接口
+
+
+##  驱动功能
+
+驱动组成由以下所示 :
+
+.
+├── fdc.c
+├── fdc.h
+├── fdc_static.c
+├── fdc_hw.c
+├── fdc_hw.h
+├── fdc_g.c
+├── fdc_common_hw.c
+├── fdc_common_hw.c
+├── fdp.c
+├── fdp.h
+├── fdp_static.c
+├── fdp_phy.c
+├── fdp_phy.h
+├── fdp_hq.c
+├── fdp_hw.h
+├── fdp_g.c
+├── fdp_aux.c
+├── fdp_aux.h
+├── fdcdp.c
+├── fdcdp.h
+├── fdcdp_param.c
+├── fdcdp_intr.c
+├── fdcdp_multi_display.c
+├── fdcdp_multi_display.h
+
+
+其中fdcdp.h 为用户开发者主要使用接口，提供了以下功能:
+1. DC,DP 控制器控制器初始化接口
+2. DC,DP 控制器相关状态位的回调函数注册
+3. DC,DP 控制器中断处理函数
+4. DP热插拔检测处理函数
+
+
+## 数据结构
+```c
+typedef struct
+{
+    /* fdc instace object */
+    FDcCtrl dc_instance_p[FDCDP_INSTANCE_NUM];
+    /* fdp instace object */
+    FDpCtrl dp_instance_p[FDCDP_INSTANCE_NUM];
+    /* user config */
+    /* resolution */
+    /* color depth */
+    FDcDpDisplaySetting display_setting[FDCDP_DISPLAY_ID_MAX_NUM];
+    /* gamma parameter */
+    /* .... */
+    /* uintptr fb_p[FDCDP_INSTANCE_NUM];*/
+    u32 is_ready; /* Device is ininitialized and ready*/
+    FMediaIntrConfig intr_event[FDCDP_INTR_MAX_NUM];
+    
+    void *args;
+    u32 connect_flg[FDCDP_INSTANCE_NUM];
+    u32 connect_changed_flg[FDCDP_INSTANCE_NUM];
+} FDcDp;
+其中FdcPrivateParams结构体为dc模块相关变量，包含有时序，frambuffer，pannel,gamma,dither,cursor等等；FdpPrivateParams结构体为dp模块相关变量，包括有时序，传输参数，phy等等。
+
+```c
+dc 相关结构体定义
+typedef struct
+{
+  FDcDtdTable dtd_table;
+  FDcDisplayVHTimmingConfig timming_config;
+  FDcDisplayFramebuffer framebuffer;
+  FDcDisplayPanel panel;
+  FDcDisplayGamma gamma;
+  FDcDisplayDither dither;
+  FDcDisplayDpMode dp_mode;
+  FDcDisplayVideoMode video_mode;
+  FDcDisplayCursor cursor;
+} FDcCurrentConfig;
+
+typedef struct
+{
+  u32 instance_id;         /* dc id */
+  uintptr dcch_baseaddr;   /* DC channel register address*/
+  uintptr dcctrl_baseaddr; /* DC control register address */
+  u32 irq_num;             /* Device intrrupt id */
+
+} FDcConfig;
+
+typedef struct
+{
+  FDcCurrentConfig fdc_currentconfig;
+  FDcConfig config;
+  u32 multimode; /* The display mode of the device , including clone, horizontal and vertical display*/
+
+} FDcCtrl;
+
+dp 相关结构体
+
+typedef struct
+{
+  /* 设置参数 */
+  FDpSyncParameter sync_parameter[DP_GOP_MAX_MODENUM];
+
+  FDpTransmissionConfig transmission_config;
+
+  /* 当前状态 */
+  FDpStatus status;
+
+  u8 down_spread_enable;
+#define dtd_list_max 4
+  /* edid 缓冲数据 */
+  FDpDtdTable dtd_table[dtd_list_max]; /* the max dtd num is 4 */
+
+} FDpCurrentConfig;
+
+typedef struct
+{
+  u32 instance_id;
+  uintptr dp_channe_base_addr;
+  uintptr dp_phy_base_addr;
+  u32 irq_num;
+} FDpConfig;
+
+typedef struct
+{
+  FDpCurrentConfig fdp_current_config;
+  FDpConfig config;
+} FDpCtrl;
+
+中断 相关结构体
+
+typedef enum
+{
+    FDCDP_HPD_IRQ_CONNECTED = 0, /* hpd 中断 */
+    FDCDP_HPD_IRQ_DISCONNECTED,
+    FDCDP_AUX_REPLY_TIMEOUT,
+    FDCDP_AUX_REPLY_ERROR,
+
+    FDCDP_INTR_MAX_NUM
+} FDcDpIntrEventType;
+
+typedef void (*FDcDpIntrHandler )(void *param, u32 index);
+
+typedef struct 
+{
+  FMediaIntrConfigtype;  /* data */
+  FDcDpIntrHandler   handler;
+  void *param;
+} FMediaIntrConfig;
+```
+
+## 错误码定义
+``
+FMEDIA_DEFAULT_PARAM_ERR					/*获取默认参数失败 */
+FMEDIA_ERR_PIXEL							/* 时钟设置错误 */
+FMEDIA_ERR_EDID						/* EDID参数获取错误*/
+FMEDIA_AUX_CONNECT_FAILED						/* AUX连接失败 */
+FMEDIA_TRAIN_TIME_ERR						/* dp train次数超过5次还未能连接 */
+FMEDIA_REACH_MAX_VOLTAGE			/*已经达到最大电压设置 */
+
+``
+## 关键配置参数介绍
+
+当您在使用显示驱动时，有必要将显示系统中的关键参数为您介绍：
+
+- resolution 分辨率
+
+显示器能够呈现的最基本的单元是像素，显示器的显示区域正是被像素点所填充，显示器的分辨率就代表了显示器所能呈现的最大像素点，通常使用较多的是1024*768，1920*1080几种，在本驱动中，已将板卡支持分辨率统一至dpSyncTable，dcSyncTable中
+
+- color depth 色深
+
+色彩深度是用「n位元颜色」(n-bit colour)来作为单位的。若色彩深度是n位元,即有2的n次方种颜色选择,而储存每像素所用的位数目就是n，通常您见到最多的一般是16bit或32bit
+
+- fresh rate 刷新率
+
+显示器每秒刷新画面的次数；单位是Hz；例如60Hz,120Hz
+
+- pixel clock 像素时钟
+
+像素时钟 = 实际的水平像素*垂直像素*刷新率（像素数包括消隐数据）
+
+比如 {800 , 525 , 1 , 1 , 96 , 2 , 640 , 480 , 144 , 35 , 0 , 0 } 640*480@60Hz
+
+像素时钟 = 800*525*60 = 25.2 Mhz Vesa标准采用25.175
+
+## 应用例程
+``
+- baremetal/example/peripheral/media/media_test
+- baremetal/example/peripheral/media/lvgl
+
+ 其中第一个例程只是点亮屏幕；第二个例程可与lvgl库进行连接，测试
+
+## API 介绍
+
+### 1. FDcConfig && FDpConfig
+
+```
+FDcConfig *FDcLookupConfig(u32 instance_id)
+FDpConfig *FDpLookupConfig(u32 instance_id)
+```
+#### 介绍
+
+- 获取当前FDC驱动默认配置
+
+- 获取当前FDP驱动默认配置
+#### 参数
+- u32 instance_id :当前media驱动中对应的ID
+
+#### 返回
+FDcConfig * :dc静态默认配置
+FDpConfig * :dp静态默认配置
+
+
+### 2. FDcDpSetBasicParam
+
+```
+FError FDcDpSetBasicParam(FDcDp *instance_p, u32 channel_num, u32 mode_id);
+```
+#### 介绍
+- 根据传入配置，初始化MEDIA驱动实例，设置基本参数
+
+#### 参数
+- FDcDp *instance_p  FDcDp 控制器实例的指针
+- u32 channel_num DP通道号
+- u32 mode_id sync时序模式
+
+#### 返回
+- FError :FMEDIA_DP_SUCCESS 为初始成功
+
+### 3. FDcDpInitial
+
+```
+FError FDcDpInitial(FDcDp *instance_p, u32 channel_num, u32 mode_id, u32 multi_mode);
+```
+#### 介绍
+- 初始化DC,DP，设置参数，包括dc,dp的初始化和连接
+
+#### 参数
+- FDcDp *instance_p  FDcDp 控制器实例的指针
+- u32 channel_num DP通道号
+- u32 mode_id sync时序模式
+- u32 multi_mode 单屏/多屏
+
+#### 返回
+- FError :FMEDIA_DP_SUCCESS 为初始成功
+
+
+### 4. FDcDpRegisterHandler
+
+```
+void FDcDpRegisterHandler(FDcDp *instance_p, FMediaIntrConfig *intr_event_p)
+
+```
+#### 介绍
+
+- 中断注册函数
+
+#### 参数
+- FDcDp *instance_p  FDcDp 控制器实例的指针
+- FMediaIntrConfig event_p 中断事件参数
+
+### 5. FDcDpInterruptHandler
+
+```
+void FDcDpInterruptHandler(s32 vector, void *args);
+```
+
+#### 介绍
+-中断handle处理函数
+
+#### 参数
+```
+s32 vector 中断返回值
+void *irq_args 回调结构体指针
+```
+#### 返回
+- NULL
+
+### 6. FDcDpIrqEnable
+
+```
+void FDcDpIrqEnable(FDcDp *instance_p, FMediaIntrConfigintr_event_p);
+```
+
+#### 介绍
+-中断使能函数
+
+#### 参数
+```
+FDcDp *instance_p dcdp驱动实例
+FMediaIntrConfig intr_event_p 中断类型
+```
+#### 返回
+- NULL
+
+### 7. FDcDpMultiDisplayFrameBufferSet
+
+```
+FError FDcDpMultiDisplayFrameBufferSet(FDcDp *instance_p, u32 channel_num, u32 multi_mode);
+```
+
+#### 介绍
+-设置多屏模式下framebuffer参数
+
+#### 参数
+```
+FDcDp *instance_p dcdp驱动实例
+u32   channel_num 通道号
+u32   multi_mode 单屏/多屏
+```
+#### 返回
+- FMEDIA_DP_SUCCESS
+
+### 8. FDcDpGetFramebuffer
+
+```
+FDcDpFrameBuffer *FDcDpGetFramebuffer(FDcDp *instance_p);
+```
+
+#### 介绍
+-提供framebuffer信息对外接口
+
+#### 参数
+```
+FDcDp *instance_p dcdp驱动实例
+```
+#### 返回
+- &framebuffer_config  
+frambuffer信息
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fpwm.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fpwm.md
index c39a9c29a4a..90bced080ea 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fpwm.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fpwm.md
@@ -150,7 +150,7 @@ typedef enum
 - 获取Fata控制器默认配置
 
 ```c
-const FPwmConfig *FPwmLookupConfig(FPwmInstance instance_id);
+const FPwmConfig *FPwmLookupConfig(u32 instance_id);
 ```
 
 Note:
@@ -159,7 +159,7 @@ Note:
 
 Input:
 
-- {FPwmInstance} instance_id，pwm控制器id号
+- {u32} instance_id，pwm控制器id号
 
 Return:
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fscmi_mhu.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fscmi_mhu.md
new file mode 100644
index 00000000000..f29254fadc7
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fscmi_mhu.md
@@ -0,0 +1,282 @@
+# SCMI_MHU 驱动程序
+
+## 1. 概述
+
+- SCMI_MHU(System Control and Management Interface)(Message Handling Unit)SCMI是用于系统管理的一组独立于操作系统的软件接口,MHU模块是SCP(System Control Processor)子系统的一个模块因为存在安全访问与非安全访问的区分所以采用APB4接口与SCP子系统和CPU核相连。
+
+- AP与SCP之间的通信通过MHU与Shared memory实现。
+
+- MHU模块主要实现CPU核与MCU通信通道的定义，分为物理通道和虚拟通道以及二者消息传递的控制功能，可实现双向通信。
+
+```
+ ______________________         ___________________________         __________________________
+|Application processor |       |Message Handling Unit(MHU) |       |System Control Processor  |
+|        (AP)          | <---> |       Shared  Memory      | <---> |        (SCP)             |
+ ——————————————————————         ———————————————————————————         ——————————————————————————
+```
+
+## 2. 功能
+
+SCMI_MHU 驱动程序主要完成SCMI协议和MHU模块的初始化、MHU模块的收发置位、协议的组包和内存读写解析函数，该驱动程序具备以下功能：
+
+- 模块初始化
+- 模块的设置
+- 协议的组包
+- 共享内存的解析
+
+相关源文件为：
+
+```
+fscmi_mhu
+    ├── fmhu_g.c
+    ├── fnhu_hw.h
+    ├── fmhu_intr.c(暂未实现)
+    ├── fmhu.c
+    ├── fmhu.h
+    ├── fscmi_base.c
+    ├── fscmi_base.h
+	├── fscmi_perf.c
+    ├── fscmi_perf.h
+    ├── fscmi_sensors.c
+    ├── fscmi_sensors.h
+    ├── fscmi.c
+    └── fscmi.h
+```
+
+## 3. 配置方法
+
+以下部分将指导您完成 SCMI_MHU 驱动的软件配置:
+
+- 配置驱动程序，新建应用工程，make menuconfig使能SCMI_MHU驱动模块
+- 设置配置参数，使用虚拟通道1，poll模式。（后续增加中断模式）
+- 获取默认配置，设置使用MHU和shared memory地址
+- 调用API函数，获取或者设置SCP参数
+
+## 4. 应用示例
+
+
+### [scmi_mhu](../../../baremetal/example/system/scmi_mhu/README.md)
+
+
+## 5. API参考
+
+
+### 5.1. 用户数据结构
+
+- drivers/scmi/fscmi_mhu/fscmi.h
+
+- scmi_mhu实例配置
+
+```c
+typedef struct
+{
+    u32 is_ready; /* Device is ininitialized and ready*/
+    struct FScmiConfig config;
+    struct FScmiRevisionInfo revision;
+	struct FScmiSensorsInfo sensors;
+	struct FScmiPerfInfo perf;
+	struct FScmiTransferInfo info[FSCMI_SUPPORT_PROTOCOL_NUM];
+	u8 protocols_imp[FSCMI_MAX_PROTOCOLS_IMP];/* List of protocols implemented, currently maximum of FSCMI_MAX_PROTOCOLS_IMP elements allocated by the base protocol */
+	FScmiMhu scmi_mhu;
+} FScmi;
+```
+
+```c
+struct FScmiConfig
+{
+	uintptr share_mem;	/* Chan transport protocol shared memory */
+	u32 mbox_type;      /* select mbox driver */
+};
+```
+
+- 协议消息结构类型
+
+```c
+struct FScmiMsgHdr 
+{
+	u8 id;              /* message id   */
+	u8 protocol_id;     /* protocol id */
+	u16 seq;            /* message token */ 
+	u32 status;         /* protocal status */
+};
+
+struct FScmiMsg
+{
+	u8 buf[FSCMI_MSG_SIZE];          /* buffer in normal memory */
+	fsize_t len;        /* buffer length */
+};
+
+struct FScmiTransferInfo 
+{
+    struct FScmiMsgHdr hdr ; /* Message(Tx/Rx) header */
+    struct FScmiMsg tx ;
+    struct FScmiMsg rx ;
+    boolean poll_completion;
+};
+```
+
+- 传感器信息结构
+
+```c
+struct FScmiSensorsInfo {
+	u32 version;
+	u16 major_ver;
+    u16 minor_ver;
+	u32 num_sensors;
+	u32 max_requests;
+	u64 reg_addr;
+	u32 reg_size;
+	struct FScmiSensorInfo sensor_info[FSCMI_MAX_NUM_SENSOR];/* TS0 TS1 */
+};
+```
+
+```c
+struct FScmiSensorInfo {
+	u32 id;
+	u8 type;
+	char name[FSCMI_MAX_STR_SIZE];
+};
+```
+
+- Performance domain protocol
+
+```c
+struct FScmiOpp {
+	u32 perf;
+	u32 power;
+	u32 trans_latency_us;
+};
+
+struct FPerfDomInfo {
+	boolean set_limits;
+	boolean set_perf;
+	boolean perf_limit_notify;
+	boolean perf_level_notify;
+	u32 opp_count;
+	u32 sustained_freq_khz;
+	u32 sustained_perf_level;
+	u32 mult_factor;
+	char name[FSCMI_MAX_STR_SIZE];
+	struct FScmiOpp opp[FSCMI_MAX_OPPS];
+};
+
+struct FScmiPerfInfo {
+	u32 version;
+    u16 major_ver;
+    u16 minor_ver;
+	u32 num_domains;
+	boolean power_scale_mw;
+	u64 stats_addr;
+	u32 stats_size;
+	struct FPerfDomInfo dom_info[FSCMI_MAX_PERF_DOMAINS];
+};
+```
+
+- 基础协议信息结构
+
+```c
+struct FScmiRevisionInfo /* base protocol */
+{
+    u32 version;
+    u16 major_ver;
+    u16 minor_ver;
+	u8 num_protocols;
+	u8 num_agents;
+	u32 impl_ver;
+	char vendor_id[FSCMI_MAX_STR_SIZE];
+	char sub_vendor_id[FSCMI_MAX_STR_SIZE];
+};
+```
+
+### 5.2  错误码定义
+
+- FSCMI_ERROR_TYPE : 使用错误的驱动类型
+- FSCMI_ERROR_RANGE : 超出设定值范围
+- FSCMI_ERROR_NOT_FOUND : 没有找的对应的协议类型
+- FSCMI_ERROR_NULL_POINTER : 空指针
+- FSCMI_ERROR_WAIT_MBOX_TIMEOUT : mailbox超时
+- FSCMI_ERROR_WAIT_MEM_TIMEOUT : 共享内存访问超时
+- FSCMI_ERROR_FETCH_RESPONSE : 回复错误
+- FSCMI_ERROR_REQUEST :	错误请求
+- FSCMI_ERROR_VERSION : 版本号错误
+- FSCMI_ERROR_INIT : 初始化错误
+
+### 5.3. 用户API接口
+
+- 配置scmi初始化参数
+
+```c
+FError FScmiCfgInitialize(FScmi *instance_p, const struct FScmiConfig *config);
+```
+
+- 获取传感器的信息
+
+```c
+FError FScmiSensorGetInfo(FScmi *instance_p);
+```
+
+- scmi协议消息的初始化
+
+```c
+FError FScmiMessageInit(FScmi *instance_p, u8 msg_id, u8 pro_id, u32 tx_size, u32 rx_size, u8 *tx_buffer);
+```
+
+- scmi协议发送准备，将初始化完成消息协议写入共享内存
+
+```c
+FError FScmiProtocolTxPrepare(FScmi *instance_p, u8 pro_id);
+```
+
+- 等待共享内存的协议完成
+
+```c
+FError FScmiProtocolPollDone(FScmi *instance_p, u8 pro_id);
+```
+
+- 获取共享内存SCP的回复数据
+
+```c
+FError FScmiFetchResponse(FScmi *instance_p, u8 pro_id);
+```
+
+- 获取对应协议的消息表指针
+
+```c
+struct FScmiTransferInfo *FScmiGetInfo(FScmi *instance_p, u8 pro_id);
+```
+
+- 进行传输
+
+```c
+FError FScmiDoTransport(FScmi *instance_p, struct FScmiTransferInfo *info, u32 protocol_index);
+```
+
+- 传感器初始化
+
+```c
+FError FScmiSensorInit(FScmi *instance_p);
+```
+
+- 传感器温度的获取，需要初始化成功
+
+```c
+FError FScmiSensorGetTemp(FScmi *instance_p, u32 sensor_id,s64 *temp);
+```
+
+- 性能域的初始化
+
+```c
+FError FScmiPerfInit(FScmi *instance_p);
+```
+
+- 设置域性能
+
+```c
+FError FScmiDvfsFreqSet(FScmi *instance_p, u32 domain, u64 freq, boolean poll);
+```
+
+- 获取域性能
+
+```c
+FError FScmiDvfsFreqGet(FScmi *instance_p, u32 domain, u64 *freq, boolean poll);
+```
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fsdio.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fsdio.md
index ec8029e973d..606c7154c7e 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fsdio.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fsdio.md
@@ -55,6 +55,8 @@ typedef struct _FSdio
     FSdioIDmaDescList   desc_list;   /* DMA descriptor list, valid in DMA trans mode */
     FSdioEvtHandler     evt_handlers[FSDIO_NUM_OF_EVT]; /* call-backs for interrupt event */
     void                *evt_args[FSDIO_NUM_OF_EVT]; /* arguments for event call-backs */
+    FSdioRelaxHandler   relax_handler;
+    u32                 prev_cmd; /* record previous command code */
 } FSdio; /* SDIO intance */
 ```
 
@@ -71,6 +73,8 @@ typedef struct
     FSdioTransMode trans_mode;  /* Trans mode, PIO/DMA */
     FSdioSpeedType speed;       /* Trans speed type */
     FSdioVoltageType voltage;   /* Card voltage type */
+    boolean        non_removable; /* No removeable media, e.g eMMC */
+    boolean        filp_resp_byte_order; /* Some SD protocol implmentation may not do byte-order filp */
 } FSdioConfig; /* SDIO intance configuration */
 ```
 #### FSdioCmdData
@@ -237,6 +241,26 @@ Return:
 
 - {None}
 
+#### FSdioGetClkFreq
+
+```c
+u32 FSdioGetClkFreq(FSdio *const instance_p)
+```
+
+Note:
+
+- Get the Card clock freqency
+
+Input:
+
+- {FSdio} *instance_p, SDIO controller instance
+
+Return:
+
+- {u32} real clock in Hz
+
+
+
 #### FSdioDMATransfer
 
 ```c
@@ -259,7 +283,7 @@ Return:
 #### FSdioPollWaitDMAEnd
 
 ```c
-FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax)
+FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 ```
 
 Note:
@@ -270,7 +294,6 @@ Input:
 
 - {FSdio} *instance_p, SDIO controller instance
 - {FSdioCmdData} *cmd_data_p, contents of transfer command and data
-- {FSdioRelaxHandler} relax, handler of relax when wait busy
 
 Return:
 
@@ -381,7 +404,7 @@ Return:
 #### FSdioPollWaitPIOEnd
 
 ```c
-FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
 ```
 
 Note:
@@ -392,7 +415,6 @@ Input:
 
 - {FSdio} *instance_p, SDIO controller instance
 - {FSdioCmdData} *cmd_data_p, contents of transfer command and data
-- {FSdioRelaxHandler} relax, handler of relax when wait busy
 
 Return:
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fsdmmc.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fsdmmc.md
index e4805188bfd..5994269b455 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fsdmmc.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fsdmmc.md
@@ -58,6 +58,7 @@ typedef struct
     FSdmmcConfig config;      /* Current active configs */
     u32          is_ready;    /* Device is initialized and ready */
     FSdmmcEventHandler evt_handler[FSDMMC_EVT_NUM];
+    void         *evt_args[FSDMMC_EVT_NUM];
 } FSdmmc; /* Device instance */
 ```
 
@@ -364,7 +365,7 @@ Return:
 - 注册中断事件响应函数
 
 ```c
-void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler);
+void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler, void *args);
 ```
 
 Note:
@@ -380,4 +381,4 @@ Input:
 
 Return:
 
-- 无
\ No newline at end of file
+- 无
diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md
index d3d6fe56fe4..4ce27297f61 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md
@@ -102,12 +102,12 @@ XMAC 驱动程序的源文件包括，
         u32 auto_neg; /* Enable auto-negotiation - when set active high, autonegotiation operation is enabled. */
         u32 pclk_hz;
         u32 max_queue_num; /* Number of Xmac Controller Queues  */
-        u32 tx_queue_id;   /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
-        u32 rx_queue_id;   /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
+        u32 tx_queue_id;   /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
+        u32 rx_queue_id;   /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
         u32 hotplug_irq_num;
         u32 dma_brust_length; /*  burst length */
         u32 network_default_config; /* mac 控制器默认配置 */
-        u32 queue_irq_num[FT_XMAC_QUEUE_MAX_NUM]; /* mac0 8个 ，其他的 4个 */
+        u32 queue_irq_num[FXMAC_QUEUE_MAX_NUM]; /* mac0 8个 ，其他的 4个 */
     } FXmacConfig;
 ```
 
diff --git a/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md b/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md
new file mode 100644
index 00000000000..0c109e62c19
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md
@@ -0,0 +1,182 @@
+
+# Lwip Port
+
+## 1. 概述
+
+Lwip Port为开发者提供了一系列接口，驱动开发者在完成GMAC/XMAC 驱动之后，只需根据lwip要求的接口，将驱动内容填入，即可完成lwip port适配层功能。lwip port 会在初始化阶段，初始化协议栈，并且会根据用户传入的配置参数，并初始化netif参数。
+
+## 2. 功能
+
+1. 为开发者提供lwip功能与mac控制驱动耦合的相关接口
+2. 统一后续mac控制器接入lwip 协议栈的方式
+3. 简化mac 控制器适配lwip 的难度
+4. 统一不同mac 控制器下应用程序
+5. 提供上层用户配置mac 控制器的统一接口
+6. 管理mac 控制器的状态（phy link status）
+7. 管理lwip 中link up/down 状态
+8. 提供多网卡检索功能
+
+相关源文件为：
+```
+lwip_port
+    ├── lwip_port.c
+    └── lwip_port.h
+```
+
+
+## 3. 配置方法
+
+默认配置已经保存在config中，用户可根据实际需要自行扩展，该部分操作参考readme即可
+
+## 4. 应用示例
+
+### [lwip port](../../../baremetal/example/network/lwip_startup/)
+
+## 5. API参考
+
+### 5.1. 用户数据结构
+
+- lwip_port.h
+
+```c
+typedef struct
+{
+	u32 magic_code;		/* LWIP_PORT_CONFIG_MAGIC_CODE */
+	char name[2];		/* Used to name netif */
+	u32 driver_type;	/* driver type */
+	u32 mac_instance;	/* mac controler id */
+	u32 mii_interface;  /* LWIP_PORT_INTERFACE_XXX */
+    u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */
+    u32 phy_speed;  /* LWIP_PORT_SPEED_XXX */
+    u32 phy_duplex; /* 1 is LWIP_PORT_FULL_DUPLEX,0 is LWIP_PORT_HALF_DUPLE*/
+} UserConfig; /*用户初始化配置数据 */
+
+typedef struct
+{
+	void (*eth_input)(struct netif *netif);
+	enum lwip_port_link_status (*eth_detect)(struct netif *netif);
+	void (*eth_deinit)(struct netif *netif);
+	void (*eth_start)(struct netif *netif);
+} LwipPortOps; /*  lwip port 网卡注册函数*/
+
+struct LwipPort {
+	void *state; /* mac controler */
+	LwipPortOps ops;
+}; /*lwip port控制数据 */
+```
+
+### 5.2  错误码定义
+无
+### 5.3. 用户API接口
+
+#### LwipPortAdd
+- 作为 lwip 的netif_add 的一个封装，开发者可以通过此接口对不同mac 控制器进行初始化
+
+```c
+struct netif * LwipPortAdd(struct netif *netif,
+ip_addr_t *ipaddr, ip_addr_t *netmask, ip_addr_t *gw,
+unsigned char *mac_ethernet_address,
+UserConfig *user_config, u32 dhcp_en);
+```
+
+Note:
+
+- begin_addr end_addr 指向为内存池指定的缓冲区的起止地址
+
+Input:
+
+- {struct netif } *netif, 需要初始化的网卡对象
+- {ip_addr_t} *ipaddr, 分配给网卡的IP初始地址
+- {ip_addr_t} *netmask, 分配给掩码的IP初始地址
+- {ip_addr_t} *gw, 分配给网关的IP初始地址
+- {unsigned char } *mac_ethernet_address, 分配给网卡的mac初始地址
+- {UserConfig} *user_config, 网卡初始化所需要的用户配置数据
+- {u32} dhcp_en, 网卡是否使用dhcp服务控制数据
+Return:
+
+- {struct netif *} 返回初始化成功的netif网卡对象，返回NULL表示初始化失败
+
+#### LwipPortInput
+
+-  lwip协议栈获取驱动数据包的接口，客户可以使用此接口在裸跑中运行lwip 协议栈
+
+```c
+void LwipPortInput(struct netif *netif)
+```
+
+Note:
+
+- 需要初始化后才能调用，调用此函数后，lwip会获取网卡收到的数据包并进行处理
+
+Input:
+
+- {struct netif } *netif 已经实例化的网卡netif  
+
+Return:
+
+- 无
+
+#### LwipPortStop
+
+- 使用此接口可以达到两个目标：
+1. 关闭当前mac 控制器工作状态
+2. 将netif 移除lwip 协议栈
+
+
+```c
+void LwipPortStop(struct netif *netif);
+```
+
+Note:
+
+- 需要初始化后才能调用，调用该函数后，网卡将停止功能，若想继续工作需要重新进行网卡初始化
+
+Input:
+
+- {struct netif } *netif 已经实例化的网卡netif  
+
+Return:
+
+- 无
+#### LwipPortGetByName
+
+- 通过netif名字找到netif对象
+
+```c
+struct netif* LwipPortGetByName(const char *name);
+```
+
+Note:
+
+- 需要初始化后才能调用，调用该函数将在已经初始化的netif链表中寻找name字段相对应的netif，并返回该netif
+
+Input:
+
+- {const char} *name 网卡名字
+
+Return:
+
+- {struct netif*} 寻找到的netif对象，如果未找到返回NULL
+
+#### LwipPortDhcpSet
+
+- 网卡dhcp控制
+
+```c
+void LwipPortDhcpSet(struct netif *netif, boolean is_enabled);
+```
+
+Note:
+
+- 需要初始化后才能调用，调用该函数可以打开或关闭网卡的dhcp服务
+
+Input:
+
+- {struct netif} *netif 网卡对象
+- {boolean} is_enabled DHCP使能控制参数
+
+
+Return:
+
+- 无
+
diff --git a/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md b/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md
index 2e03a76df13..d461ec01611 100644
--- a/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md
+++ b/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md
@@ -170,6 +170,134 @@ tftp> q
 - 将镜像文件放置在上图所示的`%PHYTIUM_IDE_PATH%\tftp`目录下，开发板即可通过`tftpboot`加载镜像
 
 > 在`template_mingw64`工程中，通过定义`USR_BOOT_DIR`可以将编译的镜像自动拷贝带tftp目录下 -->
+
+
+### 1.2.3 设置板载FLASH自动启动，避免人工干预
+
+- 此项设置是把bin镜像保存到和UBOOT相同的NOR FLASH芯片里。此芯片一般8MB。目前uboot里的flash读写命令，最大支持16MB
+- uboot固件一般4MB左右。以下命令例子，把前6MB给uboot，从6MB到7MB的空间给bin镜像使用，操作命令如下，
+
+- 通过串口或者网络下载到内存
+```
+loadx 0x90100000
+tftpboot 0x90100000 baremetal.elf
+```
+
+- 将下载的镜像写入 QSPI NOR-Flash，位置为 0x600000，镜像大小为 0x100000
+> 如果下载的 bin/elf 镜像大小超过 0x100000 字节，需要随镜像大小进行调整
+```
+flashe 0x600000   0x100000
+flashw 0x90100000 0x600000 0x100000 
+cmp.b  0x600000   0x90100000 0x100000 
+cp.b   0x600000   0x90100000 0x100000
+```
+
+- 然后就可以下电、上电启动，自动从 QSPI NOR-Flash 引导系统
+> 使用 saveenv 前，需要找 FAE 确认 u-boot 版本是否支持
+```
+csetenv bootcmd "cp.b  0x600000  0x90100000 0xa00000; bootvx32 0x90100000"
+saveenv
+```
+
+- 如果用baremetal.bin文件，则把0x90100000改成0x80100000即可
+
+### 1.2.4 将镜像放置在 SD 卡文件系统中，进行启动
+
+- 以 Windows 10为例, 首先利用读卡器或者 SD 卡套将 SD 插入 Windows10 电脑接口，找到 SD 卡对应的磁盘
+
+![](../../fig/disk_manager.png)
+
+- 在 SD 卡磁盘上创建一个分区，格式为 FAT，由于 FAT 格式限制，分区不能超过太大，我们这里创建 256 MB 分区就可以了
+
+![](../../fig/sd_segement.png)
+
+- 将编译生成的 bin 文件或者 elf 文件放置在刚刚创建的 FAT 格式分区中
+
+![](../../fig/sd_image.png)
+
+- 将 SD 卡从 Windows10 电脑中正常弹出，将 SD 卡插入开发板卡槽
+
+![](../../fig/sd_insert.png)
+
+- 启动开发板，进入 u-boot 控制台，输入下列命令找到 bin/elf 镜像文件
+> 以 E2000-Demo 板为例，SD 卡槽连接的是 SD-1 控制器，
+
+```
+mmc dev 1
+mmc info
+fatls mmc 1:1
+```
+
+![](../../fig/sd_partinfo.png)
+
+- 输入下列命令加载 elf 镜像，开始启动
+
+```
+fatload mmc 1:1 0xa0100000 baremetal.elf
+bootelf -p 0xa0100000
+```
+
+- 使用 bin 镜像启动前，需要确保刷新过 cache 
+```
+fatload mmc 1:1 0x80100000 baremetal.bin
+dcache flush
+go 0x80100000
+```
+
+- 输入下列命令，可以下电、上电启动，自动从 SD 卡介质中引导系统
+> 使用 saveenv 前，需要找 FAE 确认 u-boot 版本是否支持
+```
+setenv bootcmd "mmc dev 1; fatload mmc 1:1 0x90100000 baremetal.elf; bootelf -p 0x90100000"
+saveenv
+```
+
+
+### 1.2.5 将镜像放置在 U盘文件系统中，进行启动
+
+- 以 Windows 10为例, 首先将 U 盘插入 Windows10 电脑接口，找到 SD 卡对应的磁盘
+- 在 U 盘上创建一个分区，格式为 FAT，由于 FAT 格式限制，分区不能超过太大，我们这里创建 128 MB 分区就可以了
+
+![](../../fig/usb_disk.png)
+
+- 将编译生成的 bin 文件或者 elf 文件放置在刚刚创建的 FAT 格式分区中
+
+- 将 U 盘从 Windows10 电脑中正常弹出，将 U 盘插入开发板USB插槽
+
+![](../../fig/usb_insert.png)
+
+- 启动 USB 控制器，找到 U 盘中的
+
+```
+usb start
+usb storage
+fatls usb 0
+```
+
+![](../../fig/usb_image.png)
+
+
+- 输入下列命令加载 elf 镜像，开始启动
+
+```
+fatload usb 0 0xa0100000 baremetal.elf
+bootelf -p 0xa0100000
+```
+
+- 使用 bin 镜像启动前，需要确保刷新过 cache 
+
+```
+ffatload usb 0 0x80100000 baremetal.bin
+dcache flush
+go 0x80100000
+```
+
+- 输入下列命令，可以下电、上电启动，自动从 U盘引导系统
+> 使用 saveenv 前，需要找 FAE 确认 u-boot 版本是否支持
+```
+setenv bootcmd "usb start; fatload usb 0 0x90100000 baremetal.elf; bootelf -p 0x90100000"
+saveenv
+```
+
 ## 1.3 新建一个baremetal应用工程
 如果您希望自己建立一个应用工程，可以参考下面的流程
 ### 1.3.1 选择工程模板
diff --git a/bsp/phytium/libraries/standalone/drivers/Kconfig b/bsp/phytium/libraries/standalone/drivers/Kconfig
index 27388c475cc..d1b05305006 100644
--- a/bsp/phytium/libraries/standalone/drivers/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/Kconfig
@@ -27,7 +27,7 @@ config USE_GIC
     default y
     help
         Include Generic Interrupt Controllor
-
+    
     if USE_GIC
         source "$STANDALONE_DIR/drivers/gic/Kconfig"
     endif
@@ -38,7 +38,7 @@ config USE_SERIAL
     default n
     help
         Include serial modules and enable serial
-
+    
     if USE_SERIAL
         source "$STANDALONE_DIR/drivers/serial/Kconfig"
     endif
@@ -150,18 +150,18 @@ config USE_DMA
     prompt "Use DMA"
     default n
     help
-        Include DMA
+        Include DMA 
 
     if USE_DMA
         source "$STANDALONE_DIR/drivers/dma/Kconfig"
     endif
-
+    
 config USE_NAND
     bool
     prompt "Use NAND"
     help
         Include NAND
-
+    
     if USE_NAND
         source "$STANDALONE_DIR/drivers/nand/Kconfig"
     endif
@@ -187,7 +187,7 @@ config USE_SATA
     if USE_SATA
         source "$STANDALONE_DIR/drivers/sata/Kconfig"
     endif
-
+       
 config USE_USB
     bool
     prompt "Use USB"
@@ -197,8 +197,8 @@ config USE_USB
 
     if USE_USB
         source "$STANDALONE_DIR/drivers/usb/Kconfig"
-    endif
-
+    endif   
+    
 config USE_ADC
     bool
     prompt "Use ADC"
@@ -209,7 +209,7 @@ config USE_ADC
     if USE_ADC
         source "$STANDALONE_DIR/drivers/adc/Kconfig"
     endif
-
+    
 config USE_PWM
     bool
     prompt "Use PWM"
@@ -233,5 +233,27 @@ config USE_IPC
     endif
 
 
+config USE_MEDIA
+    bool
+    prompt "USE MEDIA"
+    default n
+    help
+        Include media drivers
+    
+    if USE_MEDIA
+        source "$STANDALONE_DIR/drivers/media/Kconfig"
+    endif
+
+config USE_SCMI_MHU
+    bool
+    prompt "USE SCMI_MHU"
+    default n
+    help
+        Include scmi_mhu drivers
+    
+    if USE_SCMI_MHU
+        source "$STANDALONE_DIR/drivers/scmi/Kconfig"
+    endif
+
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/Kconfig b/bsp/phytium/libraries/standalone/drivers/adc/Kconfig
index 15ffeaa8fe9..58f7dd8a6f7 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/adc/Kconfig
@@ -4,7 +4,7 @@ menu "ADC Configuration"
         bool
         prompt "Use FADC"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.c b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.c
index 83247b60e61..2cd42b15380 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.c
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.c
@@ -14,12 +14,14 @@
  * FilePath: fadc.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:45
- * Description:  This files is for
+ * Description: This file is for the minimum required function implementations for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/8/15   init commit
  */
+
 #include <string.h>
 #include "fgeneric_timer.h"
 #include "fkernel.h"
@@ -178,7 +180,7 @@ FError FAdcConvertSet(FAdcCtrl *pctrl, FAdcConvertConfig *convert_config)
     FASSERT(clk_div < FADC_MAX_CLOCK_PRESC);
     if (clk_div % 2 == 1)
     {
-        FADC_ERROR("clk_div is not even.");
+        FADC_ERROR("Clk_div is not even.");
         return FADC_ERR_INVAL_PARM;
     }
     reg_val &= (~FADC_CTRL_REG_CLK_DIV_MASK);
@@ -236,24 +238,24 @@ FError FAdcInterruptEnable(FAdcCtrl *pctrl, FAdcChannel channel, FAdcIntrEventTy
     reg_val = FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET);
     switch (event_type)
     {
-    case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
-        reg_val &= ~(FADC_INTRMASK_REG_COVFIN_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
+            reg_val &= ~(FADC_INTRMASK_REG_COVFIN_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_DLIMIT:
-        reg_val &= ~(FADC_INTRMASK_REG_DLIMIT_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_DLIMIT:
+            reg_val &= ~(FADC_INTRMASK_REG_DLIMIT_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_ULIMIT:
-        reg_val &= ~(FADC_INTRMASK_REG_ULIMIT_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_ULIMIT:
+            reg_val &= ~(FADC_INTRMASK_REG_ULIMIT_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_ERROR:
-        reg_val &= ~(FADC_INTRMASK_REG_ERR_MASK);
-        break;
+        case FADC_INTR_EVENT_ERROR:
+            reg_val &= ~(FADC_INTRMASK_REG_ERR_MASK);
+            break;
 
-    default:
-        break;
+        default:
+            break;
     }
 
     FADC_WRITE_REG32(base_addr, FADC_INTRMASK_REG_OFFSET, reg_val);
@@ -281,24 +283,24 @@ FError FAdcInterruptDisable(FAdcCtrl *pctrl, FAdcChannel channel, FAdcIntrEventT
     reg_val = FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET);
     switch (event_type)
     {
-    case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
-        reg_val |= (FADC_INTRMASK_REG_COVFIN_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_COVFIN: /* enable channel convert complete irq */
+            reg_val |= (FADC_INTRMASK_REG_COVFIN_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_DLIMIT:
-        reg_val |= (FADC_INTRMASK_REG_DLIMIT_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_DLIMIT:
+            reg_val |= (FADC_INTRMASK_REG_DLIMIT_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_ULIMIT:
-        reg_val |= (FADC_INTRMASK_REG_ULIMIT_MASK(channel));
-        break;
+        case FADC_INTR_EVENT_ULIMIT:
+            reg_val |= (FADC_INTRMASK_REG_ULIMIT_MASK(channel));
+            break;
 
-    case FADC_INTR_EVENT_ERROR:
-        reg_val |= (FADC_INTRMASK_REG_ERR_MASK);
-        break;
+        case FADC_INTR_EVENT_ERROR:
+            reg_val |= (FADC_INTRMASK_REG_ERR_MASK);
+            break;
 
-    default:
-        break;
+        default:
+            break;
     }
 
     FADC_WRITE_REG32(base_addr, FADC_INTRMASK_REG_OFFSET, reg_val);
@@ -430,7 +432,7 @@ FError FAdcReadConvertResult(FAdcCtrl *pctrl, FAdcChannel channel, u16 *val)
 
     if (0 >= timeout)
     {
-        FADC_ERROR("timeout when read adc data, convert is not completed.");
+        FADC_ERROR("Timeout when reading adc-data, the conversion is not finished.");
         *val = 0;
         return FADC_ERR_TIMEOUT;
     }
@@ -521,7 +523,7 @@ FError FAdcCfgInitialize(FAdcCtrl *pctrl, const FAdcConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == pctrl->is_ready)
     {
-        FADC_WARN("device is already initialized!!!");
+        FADC_WARN("The device was already initialized!");
     }
 
     /*Set default values and configuration data */
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.h b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.h
index a7c96131f9c..118ba1294c0 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.h
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc.h
@@ -14,20 +14,16 @@
  * FilePath: fadc.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:29:10
- * Description:  This files is for
+ * Description: This file is for detailed description of the device configuration and driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
-#ifndef FT_ADC_H
-#define FT_ADC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FADC_H
+#define FADC_H
 
 #include "ftypes.h"
 #include "fdebug.h"
@@ -36,6 +32,12 @@ extern "C"
 #include "fparameters.h"
 
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
 #define FADC_SUCCESS                FT_SUCCESS
 #define FADC_ERR_INVAL_PARM         FT_MAKE_ERRCODE(ErrModBsp, ErrBspAdc, 1)
 #define FADC_ERR_NOT_READY          FT_MAKE_ERRCODE(ErrModBsp, ErrBspAdc, 2)
@@ -125,7 +127,7 @@ typedef struct
 } FAdcCtrl;
 
 /* get default configuration of specific adc id */
-const FAdcConfig *FAdcLookupConfig(FAdcInstance instance_id);
+const FAdcConfig *FAdcLookupConfig(u32 instance_id);
 
 /* DeInitialization function for the device instance */
 void FAdcDeInitialize(FAdcCtrl *pctrl);
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_g.c b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_g.c
index aae6f24981d..925692589ab 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_g.c
@@ -14,32 +14,25 @@
  * FilePath: fadc_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:45
- * Description:  This files is for
+ * Description: This file is for adc static configuration implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/16   init commit
  */
+
 #include "fparameters.h"
 #include "fadc.h"
 
-/* default configs of wdt ctrl */
-const FAdcConfig FAdcConfigTbl[FADC_INSTANCE_NUM] =
+/* default configs of adc ctrl */
+const FAdcConfig FAdcConfigTbl[FADC_NUM] =
 {
     {
-        .instance_id = FADC_INSTANCE_0,
-        .base_addr = FADC0_CONTROL_BASE,
-        .irq_num = FADC0_INTR_IRQ,
+        .instance_id = FADC0_ID,
+        .base_addr = FADC0_BASE_ADDR,
+        .irq_num = FADC0_IRQ_NUM,
         .irq_prority = 0,
         .instance_name = "ADC-0"
-
-    },
-
-    {
-        .instance_id = FADC_INSTANCE_1,
-        .base_addr = FADC1_CONTROL_BASE,
-        .irq_num = FADC1_INTR_IRQ,
-        .irq_prority = 0,
-        .instance_name = "ADC-1"
     }
 };
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.c b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.c
index c1e5cc63f75..9695f562cdf 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.c
@@ -14,17 +14,24 @@
  * FilePath: fadc_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * Description: This file is for adc register implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
 #include "fparameters.h"
 #include "fadc_hw.h"
 #include "stdio.h"
 
+#define FADC_DEBUG_TAG "FT_ADC_HW"
+#define FADC_DEBUG(format, ...)     FT_DEBUG_PRINT_D(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FADC_INFO(format, ...)      FT_DEBUG_PRINT_I(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FADC_WARN(format, ...)      FT_DEBUG_PRINT_W(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FADC_ERROR(format, ...)     FT_DEBUG_PRINT_E(FADC_DEBUG_TAG, format, ##__VA_ARGS__)
+
 /**
  * @name: FAdcDump
  * @msg: debug register value for adc channel.
@@ -34,15 +41,15 @@
  */
 void FAdcDump(uintptr base_addr, u8 channel)
 {
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_CTRL_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_INTER_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTER_REG_OFFSET));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_STATE_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_STATE_REG_OFFSET));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_INTRMASK_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_INTR_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTR_REG_OFFSET));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_COV_RESULT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_COV_RESULT_REG_OFFSET(channel)));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_FINISH_CNT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_FINISH_CNT_REG_OFFSET(channel)));
-    printf("Off[0x%02x]: = 0x%08x\r\n", FADC_HIS_LIMIT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_HIS_LIMIT_REG_OFFSET(channel)));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_CTRL_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_CTRL_REG_OFFSET));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_INTER_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTER_REG_OFFSET));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_STATE_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_STATE_REG_OFFSET));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_INTRMASK_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTRMASK_REG_OFFSET));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_INTR_REG_OFFSET, FADC_READ_REG32(base_addr, FADC_INTR_REG_OFFSET));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_COV_RESULT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_COV_RESULT_REG_OFFSET(channel)));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_FINISH_CNT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_FINISH_CNT_REG_OFFSET(channel)));
+    FADC_INFO("Off[0x%02x]: = 0x%08x", FADC_HIS_LIMIT_REG_OFFSET(channel), FADC_READ_REG32(base_addr, FADC_HIS_LIMIT_REG_OFFSET(channel)));
 
-    printf("\r\n");
+    FADC_INFO("");
 
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.h b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.h
index e9abff56b25..0796906dd9d 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_hw.h
@@ -14,23 +14,26 @@
  * FilePath: fadc_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:45
- * Description:  This files is for
+ * Description: This file is for adc register definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
-#ifndef BSP_DRIVERS_ADC_HW_H
-#define BSP_DRIVERS_ADC_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FADC_HW_H
+#define FADC_HW_H
 
 #include "fkernel.h"
 #include "ftypes.h"
 #include "fio.h"
+#include "fdebug.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 /* Generic ADC register definitions */
 
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_intr.c b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_intr.c
index 6a6ac7ba60f..f161eb64c4f 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_intr.c
@@ -14,15 +14,16 @@
  * FilePath: fadc_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:45
- * Description:  This files is for
+ * Description:  This file is for adc interrupt handler implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
+
 #include "fparameters.h"
 #include "fassert.h"
-#include "finterrupt.h"
 #include "fadc.h"
 #include "fadc_hw.h"
 
@@ -68,7 +69,6 @@ void FAdcIntrHandler(s32 vector, void *args)
     FAdcCtrl *pctrl = (FAdcCtrl *)args;
     u32 status = 0;
     u32 intrmask = 0;
-    u32 cfg = 0;
     u32 channel = 0;
     uintptr base_addr = pctrl->config.base_addr;
 
diff --git a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_sinit.c b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_sinit.c
index b6f415db2ab..1335e3bd0c9 100644
--- a/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/adc/fadc/fadc_sinit.c
@@ -14,11 +14,12 @@
  * FilePath: fadc_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * Description: This file is for adc static variables implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
 
 
@@ -29,7 +30,7 @@
 #include "fadc.h"
 #include "fassert.h"
 
-extern FAdcConfig FAdcConfigTbl[FADC_INSTANCE_NUM];
+extern FAdcConfig FAdcConfigTbl[FADC_NUM];
 
 /************************** Constant Definitions *****************************/
 
@@ -44,17 +45,17 @@ extern FAdcConfig FAdcConfigTbl[FADC_INSTANCE_NUM];
 /**
  * @name: FAdcLookupConfig
  * @msg:  get default configuration of specific adc id.
- * @param {FAdcInstance} instance_id, instance id of FADC controller
+ * @param {u32} instance_id, instance id of FADC controller
  * @return {FAdcConfig*} Default configuration parameters of FADC
  */
-const FAdcConfig *FAdcLookupConfig(FAdcInstance instance_id)
+const FAdcConfig *FAdcLookupConfig(u32 instance_id)
 {
     const FAdcConfig *pconfig = NULL;
-    FASSERT(instance_id < FADC_INSTANCE_NUM);
+    FASSERT(instance_id < FADC_NUM);
 
     u32 index = 0;
 
-    for (index = 0; index < (u32)FADC_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FADC_NUM; index++)
     {
         if (FAdcConfigTbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/can/Kconfig b/bsp/phytium/libraries/standalone/drivers/can/Kconfig
index c3e16b4834a..33dfe2855fb 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/can/Kconfig
@@ -6,13 +6,13 @@ menu "CAN Configuration"
         default n
     if  USE_FCAN
         config FCAN_USE_CANFD
-        depends on TARGET_E2000
+        depends on TARGET_E2000 || TARGET_TARDIGRADE
         bool
         prompt "Use CanFD"
         default n
         help
             use canfd protocol
     endif
-
+        
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.c
index 9de3f128f4c..83058453b1e 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.c
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.c
@@ -14,11 +14,14 @@
  * FilePath: fcan.c
  * Date: 2021-04-29 10:21:53
  * LastEditTime: 2022-02-18 08:29:20
- * Description:  This files is for
+ * Description:  This files is for the can functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
+ * 1.1   wangxiaodong  2022/9/23  improve functions
+ * 1.2   zhangyan      2022/12/7  improve functions
  */
 
 #include "string.h"
@@ -113,7 +116,9 @@ static s32 FCanUpdateSamplePoint(const FCanBittimingConst *btc,
     }
 
     if (sample_point_error_ptr)
+    {
         *sample_point_error_ptr = best_sample_point_error;
+    }
 
     return best_sample_point;
 }
@@ -162,40 +167,62 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
     }
     else
     {
-        if (target_baudrate > 1000000)
+        if (target_baudrate > 4000000)
+        {
             sample_point_nominal = 650;
+        }
+        else if (target_baudrate > 2000000)
+        {
+            sample_point_nominal = 680;
+        }
+        else if (target_baudrate > 1000000)
+        {
+            sample_point_nominal = 725;
+        }
         else if (target_baudrate > 800000)
+        {
             sample_point_nominal = 750;
+        }
         else if (target_baudrate > 500000)
+        {
             sample_point_nominal = 800;
+        }
         else
+        {
             sample_point_nominal = 875;
+        }
     }
 
     for (tseg = (btc->tseg1_max + btc->tseg2_max) * 2 + 1;
-            tseg >= (btc->tseg1_min + btc->tseg2_min) * 2; tseg--)
+         tseg >= (btc->tseg1_min + btc->tseg2_min) * 2; tseg--)
     {
         tsegall = CAN_CALC_SYNC_SEG + tseg / 2;
 
         /* Compute all possible tseg choices (tseg=tseg1+tseg2) */
-        brp = FCAN_REF_CLOCK / (tsegall * target_baudrate) + tseg % 2;
+        brp = FCAN_CLK_FREQ_HZ / (tsegall * target_baudrate) + tseg % 2;
 
         /* choose brp step which is possible in system */
         brp = (brp / btc->brp_inc) * btc->brp_inc;
 
         if ((brp < btc->brp_min) || (brp > btc->brp_max))
+        {
             continue;
+        }
 
-        baudrate = FCAN_REF_CLOCK / (brp * tsegall);
+        baudrate = FCAN_CLK_FREQ_HZ / (brp * tsegall);
         baudrate_error = abs(target_baudrate - baudrate);
 
         /* tseg brp biterror */
         if (baudrate_error > best_baudrate_error)
+        {
             continue;
+        }
 
         /* reset sample point error if we have a better baudrate */
         if (baudrate_error < best_baudrate_error)
+        {
             best_sample_point_error = UINT_MAX;
+        }
 
         FCanUpdateSamplePoint(btc, sample_point_nominal, tseg / 2, &tseg1, &tseg2, &sample_point_error);
 
@@ -216,7 +243,9 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
         FCAN_DEBUG("reg_val=%#x\n", reg_val);
 
         if (sample_point_error > best_sample_point_error)
+        {
             continue;
+        }
 
         best_sample_point_error = sample_point_error;
         best_baudrate_error = baudrate_error;
@@ -224,7 +253,9 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
         best_brp = brp;
 
         if (baudrate_error == 0 && sample_point_error == 0)
+        {
             break;
+        }
     }
 
     if (best_baudrate_error)
@@ -235,7 +266,7 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
         baudrate_error = (u32)v64;
         if (baudrate_error > CAN_CALC_MAX_ERROR)
         {
-            FCAN_ERROR("baudrate error");
+            FCAN_ERROR("Baudrate error.");
             return FCAN_FAILURE;
         }
     }
@@ -258,18 +289,22 @@ static FError FCanCalcBittiming(FCanBaudrateConfig *bt_p, u32 target_baudrate, u
     {
         /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */
         if (bt->sjw > btc->sjw_max)
+        {
             bt->sjw = btc->sjw_max;
+        }
         /* bt->sjw must not be higher than tseg2 */
         if (tseg2 < bt->sjw)
+        {
             bt->sjw = tseg2;
+        }
     }
 
     bt->brp = best_brp;
 
     /* real baudrate */
-    if (target_baudrate != FCAN_REF_CLOCK / (bt->brp * (CAN_CALC_SYNC_SEG + tseg1 + tseg2)))
+    if (target_baudrate != FCAN_CLK_FREQ_HZ / (bt->brp * (CAN_CALC_SYNC_SEG + tseg1 + tseg2)))
     {
-        FCAN_ERROR("target baudrate calculate timing failed");
+        FCAN_ERROR("Target baudrate calculate timing failed.");
         return FCAN_FAILURE;
     }
 
@@ -289,54 +324,54 @@ static u32 FCanGetDlcLen(u32 dlc)
 
     switch (dlc)
     {
-    case 1:
-        dlc_len = 1;
-        break;
-    case 2:
-        dlc_len = 2;
-        break;
-    case 3:
-        dlc_len = 3;
-        break;
-    case 4:
-        dlc_len = 4;
-        break;
-    case 5:
-        dlc_len = 5;
-        break;
-    case 6:
-        dlc_len = 6;
-        break;
-    case 7:
-        dlc_len = 7;
-        break;
-    case 8:
-        dlc_len = 8;
-        break;
-    case 9:
-        dlc_len = 12;
-        break;
-    case 10:
-        dlc_len = 16;
-        break;
-    case 11:
-        dlc_len = 20;
-        break;
-    case 12:
-        dlc_len = 24;
-        break;
-    case 13:
-        dlc_len = 32;
-        break;
-    case 14:
-        dlc_len = 48;
-        break;
-    case 15:
-        dlc_len = 64;
-        break;
-    default :
-        dlc_len = 0;
-        break;
+        case 1:
+            dlc_len = 1;
+            break;
+        case 2:
+            dlc_len = 2;
+            break;
+        case 3:
+            dlc_len = 3;
+            break;
+        case 4:
+            dlc_len = 4;
+            break;
+        case 5:
+            dlc_len = 5;
+            break;
+        case 6:
+            dlc_len = 6;
+            break;
+        case 7:
+            dlc_len = 7;
+            break;
+        case 8:
+            dlc_len = 8;
+            break;
+        case 9:
+            dlc_len = 12;
+            break;
+        case 10:
+            dlc_len = 16;
+            break;
+        case 11:
+            dlc_len = 20;
+            break;
+        case 12:
+            dlc_len = 24;
+            break;
+        case 13:
+            dlc_len = 32;
+            break;
+        case 14:
+            dlc_len = 48;
+            break;
+        case 15:
+            dlc_len = 64;
+            break;
+        default :
+            dlc_len = 0;
+            break;
     }
 
     return dlc_len;
@@ -401,7 +436,7 @@ void FCanReset(FCanCtrl *instance_p)
     reg_value = FCAN_READ_REG32(config_p->base_address, FCAN_CTRL_OFFSET);
     if (reg_value & FCAN_CTRL_XFER_MASK)
     {
-        FCAN_ERROR("FT can is not in configration mode\n");
+        FCAN_ERROR("Can is not in configration mode.");
         return;
     }
 
@@ -444,7 +479,7 @@ FError FCanCfgInitialize(FCanCtrl *instance_p, const FCanConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FCAN_WARN("device is already initialized!!!");
+        FCAN_WARN("Device is already initialized.");
     }
 
     /*Set default values and configuration data */
@@ -628,8 +663,8 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
     if (frame_p->canid & CAN_EFF_FLAG)
     {
         /* Extended CAN id format */
-        id = FCAN_IDR_ID2_GET(frame_p->canid & CAN_EFF_MASK);
-        id |= FCAN_IDR_ID1_GET((frame_p->canid & CAN_EFF_MASK) >>
+        id = FCAN_IDR_ID2_SET(frame_p->canid & CAN_EFF_MASK);
+        id |= FCAN_IDR_ID1_SET((frame_p->canid & CAN_EFF_MASK) >>
                                (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS));
 
         /* The substibute remote TX request bit should be "1"
@@ -672,10 +707,12 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
     else
     {
         /* Standard CAN id format */
-        id = FCAN_IDR_ID1_GET(frame_p->canid & CAN_SFF_MASK);
+        id = FCAN_IDR_ID1_SET(frame_p->canid & CAN_SFF_MASK);
 
         if (frame_p->canid & CAN_RTR_FLAG)
+        {
             id |= FCAN_IDR_SRR_MASK;
+        }
 
         FCAN_DEBUG("instance_p->use_canfd = %d, can_send_dlc = %d \n",
                    instance_p->use_canfd, can_send_dlc);
@@ -705,7 +742,7 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
         }
 
         id |= dlc;
-        FCAN_DEBUG("can_send id = %#x\n", id);
+        FCAN_DEBUG("FCanSend id = %#x\n", id);
         FCAN_WRITE_REG32(base_address, FCAN_TX_FIFO_OFFSET, be32_to_cpu(id));
 
     }
@@ -728,10 +765,18 @@ FError FCanSend(FCanCtrl *instance_p, FCanFrame *frame_p)
     }
 
     /* triggers tranmission */
-    FCAN_CLEARBIT(base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
-    FCAN_SETBIT(base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK | FCAN_CTRL_XFER_MASK);
+    if (FCAN_READ_REG32(base_address, FCAN_CTRL_OFFSET) & FCAN_CTRL_TXREQ_MASK)
+    {
+        FCAN_CLEARBIT(base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
+        FCAN_SETBIT(base_address, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK | FCAN_CTRL_XFER_MASK);
+        return FCAN_SUCCESS;
+    }
+    else
+    {
+        FCAN_WARN("Monitoring mode cannot send message!!!");
+        return FCAN_FAILURE;
+    }
 
-    return FCAN_SUCCESS;
 }
 
 /**
@@ -777,9 +822,13 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
     if (reg_val)
     {
         if (target_segment == FCAN_DATA_SEGMENT)
+        {
             FCAN_WRITE_REG32(base_address, FCAN_DAT_RATE_CTRL_OFFSET, reg_val);
+        }
         else
+        {
             FCAN_WRITE_REG32(base_address, FCAN_ARB_RATE_CTRL_OFFSET, reg_val);
+        }
     }
     else
     {
@@ -805,7 +854,7 @@ static FError FCanSetTiming(FCanCtrl *instance_p, FCanBaudrateConfig *bittiming_
  * @note this function is to set arb and data segment baudrate, according to the prop_seg,
  * phase_seg1, phase_seg2 ,brp and sjw parameters, users can use this function to set can baudrate.
  * A formula to calculate baudrate is:
- * baudrate = FCAN_REF_CLOCK/(brp*(sjw+prop_seg+phase_seg1++phase_seg2))
+ * baudrate = FCAN_CLK_FREQ_HZ/(brp*(sjw+prop_seg+phase_seg1++phase_seg2))
  * sample point = (sjw+prop_seg+phase_seg1)/(sjw+prop_seg+phase_seg1++phase_seg2)
  * Recommended sample point :
  * 75.0% : baudrate > 800000
@@ -833,7 +882,7 @@ FError FCanBaudrateSet(FCanCtrl *instance_p, FCanBaudrateConfig *baudrate_p)
             FCAN_ERROR("FCanBaudrateSet FCAN_DATA_SEGMENT baudrate = %d invalid", baudrate);
             return FCAN_INVAL_PARAM;
         }
-#elif defined(CONFIG_TARGET_E2000)
+#elif defined(CONFIG_TARGET_E2000) || defined(TARDIGRADE)
         if ((segment == FCAN_ARB_SEGMENT) && ((baudrate > FCAN_BAUDRATE_1000K) || (baudrate < FCAN_BAUDRATE_10K)))
         {
             FCAN_ERROR("FCanBaudrateSet FCAN_ARB_SEGMENT baudrate = %d invalid", baudrate);
@@ -894,7 +943,6 @@ FError FCanEnable(FCanCtrl *instance_p, boolean enable)
     FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
 
     uintptr base_addr = instance_p->config.base_address;
-
     if (enable == TRUE)
     {
         FCAN_SETBIT(base_addr, FCAN_CTRL_OFFSET, FCAN_CTRL_XFER_MASK);
@@ -930,24 +978,24 @@ FError FCanIdMaskFilterSet(FCanCtrl *instance_p, FCanIdMaskConfig *id_mask_p)
 
     switch (filter_index)
     {
-    case 0:
-        id_reg_offset = FCAN_ACC_ID0_OFFSET;
-        mask_reg_offset = FCAN_ACC_ID0_MASK_OFFSET;
-        break;
-    case 1:
-        id_reg_offset = FCAN_ACC_ID1_OFFSET;
-        mask_reg_offset = FCAN_ACC_ID1_MASK_OFFSET;
-        break;
-    case 2:
-        id_reg_offset = FCAN_ACC_ID2_OFFSET;
-        mask_reg_offset = FCAN_ACC_ID2_MASK_OFFSET;
-        break;
-    case 3:
-        id_reg_offset = FCAN_ACC_ID3_OFFSET;
-        mask_reg_offset = FCAN_ACC_ID3_MASK_OFFSET;
-        break;
-    default:
-        return FCAN_FAILURE;
+        case 0:
+            id_reg_offset = FCAN_ACC_ID0_OFFSET;
+            mask_reg_offset = FCAN_ACC_ID0_MASK_OFFSET;
+            break;
+        case 1:
+            id_reg_offset = FCAN_ACC_ID1_OFFSET;
+            mask_reg_offset = FCAN_ACC_ID1_MASK_OFFSET;
+            break;
+        case 2:
+            id_reg_offset = FCAN_ACC_ID2_OFFSET;
+            mask_reg_offset = FCAN_ACC_ID2_MASK_OFFSET;
+            break;
+        case 3:
+            id_reg_offset = FCAN_ACC_ID3_OFFSET;
+            mask_reg_offset = FCAN_ACC_ID3_MASK_OFFSET;
+            break;
+        default:
+            return FCAN_FAILURE;
     }
 
     if (id_mask_p->type == FCAN_STANDARD_FRAME)
@@ -1010,20 +1058,39 @@ FError FCanInterruptEnable(FCanCtrl *instance_p, FCanIntrEventType event_type)
 
     switch (event_type)
     {
-    case FCAN_INTR_EVENT_SEND:
-        reg_val |= FCAN_INTR_TEIE_MASK;
-        break;
+        case FCAN_INTR_EVENT_SEND:
+            reg_val |= FCAN_INTR_TEIE_MASK;
+            break;
+
+        case FCAN_INTR_EVENT_RECV:
+            reg_val |= FCAN_INTR_REIE_MASK;
+            break;
+
+        case FCAN_INTR_EVENT_ERROR:
+            reg_val |= FCAN_INTR_EIE_MASK;
+            break;
 
-    case FCAN_INTR_EVENT_RECV:
-        reg_val |= FCAN_INTR_REIE_MASK;
-        break;
+        case FCAN_INTR_EVENT_BUSOFF:
+            reg_val |= FCAN_INTR_BOIE_MASK;
+            break;
 
-    case FCAN_INTR_EVENT_ERROR:
-        reg_val |= FCAN_INTR_EIE_MASK;
-        break;
+        case FCAN_INTR_EVENT_PERROE:
+            reg_val |= FCAN_INTR_PEIE_MASK;
+            break;
 
-    default:
-        break;
+        case FCAN_INTR_EVENT_PWARN:
+            reg_val |= FCAN_INTR_PWIE_MASK;
+            break;
+
+        case FCAN_INTR_EVENT_FIFOFULL:
+            reg_val |= FCAN_INTR_RFIE_MASK;
+            break;
+
+        case FCAN_INTR_EVENT_FIFOEMPTY:
+            reg_val |= FCAN_INTR_TFIE_MASK;
+            break;
+        default:
+            break;
     }
 
     FCAN_WRITE_REG32(base_addr, FCAN_INTR_OFFSET, reg_val);
@@ -1057,4 +1124,30 @@ FError FCanFdEnable(FCanCtrl *instance_p, boolean enable)
     }
 
     return FCAN_SUCCESS;
-}
\ No newline at end of file
+}
+
+/**
+ * @name: FCanSetMode
+ * @msg:  Set the transmit mode, Monitor or Normal
+ * @param {FCanCtrl} *instance_p, instance of FCanCtrl controller
+ * @param {u32} tran_mode,parameters of target mode,0 Monitor mode,1 Normal mode
+ * @return err code information, FCAN_SUCCESS indicates success，others indicates failed
+ */
+FError FCanSetMode(FCanCtrl *instance_p, u32 tran_mode)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(FT_COMPONENT_IS_READY == instance_p->is_ready);
+    uintptr base_addr = instance_p->config.base_address;
+
+    if (tran_mode == FCAN_PROBE_MONITOR_MODE)
+    {
+        FCAN_CLEARBIT(base_addr, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK);
+    }
+    if (tran_mode == FCAN_PROBE_NORMAL_MODE)
+    {
+        FCAN_SETBIT(base_addr, FCAN_CTRL_OFFSET, FCAN_CTRL_TXREQ_MASK);
+    }
+
+    return FCAN_SUCCESS;
+}
+
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.h b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.h
index d35076fd746..b036f435d0e 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.h
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan.h
@@ -14,16 +14,19 @@
  * FilePath: fcan.h
  * Date: 2021-04-27 15:08:44
  * LastEditTime: 2022-02-18 08:29:25
- * Description:  This files is for
+ * Description:  This files is for the can function related definitions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
+ * 1.1   wangxiaodong  2022/9/23  improve functions
+ * 1.2   zhangyan      2022/12/7  improve functions
  */
 
 
-#ifndef FT_CAN_H
-#define FT_CAN_H
+#ifndef FCAN_H
+#define FCAN_H
 
 #include "ftypes.h"
 #include "ferror_code.h"
@@ -31,11 +34,21 @@
 #include "fkernel.h"
 #include "fcan_hw.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 typedef enum
 {
-    FCAN_INTR_EVENT_SEND = 0,    /* Handler type for frame sending interrupt */
-    FCAN_INTR_EVENT_RECV = 1,    /* Handler type for frame reception interrupt */
-    FCAN_INTR_EVENT_ERROR,       /* Handler type for error interrupt */
+    FCAN_INTR_EVENT_SEND = 0,     /* Handler type for frame sending interrupt */
+    FCAN_INTR_EVENT_RECV = 1,     /* Handler type for frame reception interrupt */
+    FCAN_INTR_EVENT_ERROR = 2,    /* Handler type for error interrupt */
+    FCAN_INTR_EVENT_BUSOFF = 3,   /* Handler type for bus off interrupt */
+    FCAN_INTR_EVENT_PERROE = 4,   /* Handler type for passion error interrupt */
+    FCAN_INTR_EVENT_PWARN = 5,    /* Handler type for passion warn interrupt */
+    FCAN_INTR_EVENT_FIFOFULL = 6, /* Handler type for rx fifo register full */
+    FCAN_INTR_EVENT_FIFOEMPTY = 7,/* Handler type for tx fifo register empty */
     FCAN_INTR_EVENT_NUM
 } FCanIntrEventType;
 
@@ -75,6 +88,10 @@ typedef enum
 #define CAN_CALC_MAX_ERROR  50 /* in one-tenth of a percent */
 #define CAN_CALC_SYNC_SEG   1
 
+/*Transmit mode*/
+#define FCAN_PROBE_MONITOR_MODE 0 /* Monitor mode */
+#define FCAN_PROBE_NORMAL_MODE  1 /* Normal mode */
+
 /* can segment type */
 typedef enum
 {
@@ -199,7 +216,7 @@ typedef struct
 } FCanCtrl;
 
 /* get default configuration of specific can id */
-const FCanConfig *FCanLookupConfig(FCanInstance instance_id);
+const FCanConfig *FCanLookupConfig(u32 instance_id);
 
 /* reset a specific can instance */
 void FCanReset(FCanCtrl *instance_p);
@@ -246,4 +263,11 @@ FError FCanInterruptEnable(FCanCtrl *instance_p, FCanIntrEventType event_type);
 /* Enable or disable can fd */
 FError FCanFdEnable(FCanCtrl *instance_p, boolean enable);
 
+/* Set the transmit mode  */
+FError FCanSetMode(FCanCtrl *instance_p, u32 tran_mode);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif // !FT_CAN_H
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_g.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_g.c
index 62d126a5709..b1a59bf2bd1 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_g.c
@@ -14,33 +14,34 @@
  * FilePath: fcan_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:45
- * Description:  This files is for
+ * Description:  This files is for the can default configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
  */
 
-
+#include "sdkconfig.h"
 #include "fcan.h"
 #include "fparameters.h"
 
-const FCanConfig FCanConfigTbl[FCAN_INSTANCE_NUM] =
+const FCanConfig FCanConfigTbl[FCAN_NUM] =
 {
     {
-        .instance_id = FCAN_INSTANCE_0, /* Id of device */
-        .base_address = FCAN0_BASEADDR,  /* Can base Address */
-        .irq_num = FCAN0_IRQNUM,
+        .instance_id = FCAN0_ID, /* Id of device */
+        .base_address = FCAN0_BASE_ADDR,  /* Can base Address */
+        .irq_num = FCAN0_IRQ_NUM,
     },
     {
-        .instance_id = FCAN_INSTANCE_1, /* Id of device */
-        .base_address = FCAN1_BASEADDR,  /* Can base Address */
-        .irq_num = FCAN1_IRQNUM,
+        .instance_id = FCAN1_ID, /* Id of device */
+        .base_address = FCAN1_BASE_ADDR,  /* Can base Address */
+        .irq_num = FCAN1_IRQ_NUM,
     },
 #if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
     {
-        .instance_id = FCAN_INSTANCE_2,  /* Id of device */
-        .base_address = FCAN2_BASEADDR, /* Can base Address */
+        .instance_id = FCAN2_ID,  /* Id of device */
+        .base_address = FCAN2_BASE_ADDR, /* Can base Address */
         .irq_num = FCAN2_IRQNUM,
     }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.c
index dedaa330778..b06da31ebcc 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.c
@@ -14,11 +14,12 @@
  * FilePath: fcan_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:28:50
- * Description:  This files is for
+ * Description:  This files is for the can register related functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
  */
 
 
@@ -37,31 +38,31 @@
 void FCanDump(uintptr base_addr)
 {
 
-    printf("Off[0x%x]: FCAN_CTRL_OFFSET  = 0x%08x\r\n", base_addr + FCAN_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_CTRL_OFFSET));
-    printf("Off[0x%x]: FCAN_INTR_OFFSET   = 0x%08x\r\n", base_addr + FCAN_INTR_OFFSET, FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
-    printf("Off[0x%x]: FCAN_ARB_RATE_CTRL_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ARB_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ARB_RATE_CTRL_OFFSET));
-    printf("Off[0x%x]: FCAN_DAT_RATE_CTRL_OFFSET   = 0x%08x\r\n", base_addr + FCAN_DAT_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DAT_RATE_CTRL_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID0_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID0_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID1_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID1_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID2_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID2_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID3_OFFSET  = 0x%08x\r\n", base_addr + FCAN_ACC_ID3_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID0_MASK_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID0_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_MASK_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID1_MASK_OFFSET   = 0x%08x\r\n", base_addr + FCAN_ACC_ID1_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_MASK_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID2_MASK_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID2_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_MASK_OFFSET));
-    printf("Off[0x%x]: FCAN_ACC_ID3_MASK_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID3_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_MASK_OFFSET));
-    printf("Off[0x%x]: FCAN_XFER_STS_OFFSET = 0x%08x\r\n", base_addr + FCAN_XFER_STS_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_STS_OFFSET));
-    printf("Off[0x%x]: FCAN_ERR_CNT_OFFSET  = 0x%08x\r\n", base_addr + FCAN_ERR_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_CTRL_OFFSET  = 0x%08x\r\n", base_addr + FCAN_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_CTRL_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_INTR_OFFSET   = 0x%08x\r\n", base_addr + FCAN_INTR_OFFSET, FCAN_READ_REG32(base_addr, FCAN_INTR_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ARB_RATE_CTRL_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ARB_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ARB_RATE_CTRL_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_DAT_RATE_CTRL_OFFSET   = 0x%08x\r\n", base_addr + FCAN_DAT_RATE_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DAT_RATE_CTRL_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID0_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID0_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID1_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID1_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID2_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID2_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID3_OFFSET  = 0x%08x\r\n", base_addr + FCAN_ACC_ID3_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID0_MASK_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID0_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID0_MASK_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID1_MASK_OFFSET   = 0x%08x\r\n", base_addr + FCAN_ACC_ID1_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID1_MASK_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID2_MASK_OFFSET    = 0x%08x\r\n", base_addr + FCAN_ACC_ID2_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID2_MASK_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ACC_ID3_MASK_OFFSET = 0x%08x\r\n", base_addr + FCAN_ACC_ID3_MASK_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ACC_ID3_MASK_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_XFER_STS_OFFSET = 0x%08x\r\n", base_addr + FCAN_XFER_STS_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_STS_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_ERR_CNT_OFFSET  = 0x%08x\r\n", base_addr + FCAN_ERR_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_ERR_CNT_OFFSET));
 
-    printf("Off[0x%x]: FCAN_FIFO_CNT_OFFSET = 0x%08x\r\n", base_addr + FCAN_FIFO_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FIFO_CNT_OFFSET));
-    printf("Off[0x%x]: FCAN_DMA_CTRL_OFFSET = 0x%08x\r\n", base_addr + FCAN_DMA_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DMA_CTRL_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_FIFO_CNT_OFFSET = 0x%08x\r\n", base_addr + FCAN_FIFO_CNT_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FIFO_CNT_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_DMA_CTRL_OFFSET = 0x%08x\r\n", base_addr + FCAN_DMA_CTRL_OFFSET, FCAN_READ_REG32(base_addr, FCAN_DMA_CTRL_OFFSET));
 
-    printf("Off[0x%x]: FCAN_XFER_EN_OFFSET = 0x%08x\r\n", base_addr + FCAN_XFER_EN_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_EN_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_XFER_EN_OFFSET = 0x%08x\r\n", base_addr + FCAN_XFER_EN_OFFSET, FCAN_READ_REG32(base_addr, FCAN_XFER_EN_OFFSET));
 
-    printf("Off[0x%x]: FCAN_FRM_INFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_FRM_INFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FRM_INFO_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_FRM_INFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_FRM_INFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_FRM_INFO_OFFSET));
 
-    printf("Off[0x%x]: FCAN_TX_FIFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_TX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_TX_FIFO_OFFSET));
-    printf("Off[0x%x]: FCAN_RX_FIFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_RX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_RX_FIFO_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_TX_FIFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_TX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_TX_FIFO_OFFSET));
+    FCAN_DEBUG("Off[0x%x]: FCAN_RX_FIFO_OFFSET  = 0x%08x\r\n", base_addr + FCAN_RX_FIFO_OFFSET, FCAN_READ_REG32(base_addr, FCAN_RX_FIFO_OFFSET));
 
-    printf("\r\n");
+    FCAN_DEBUG("\r\n");
 
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.h b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.h
index 1117d962bcb..0f59b3f2bea 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_hw.h
@@ -14,21 +14,29 @@
  * FilePath: fcan_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:29:05
- * Description:  This files is for
+ * Description:  This files is for the can register related definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
+ * 1.1   zhangyan      2022/12/7  improve functions
  */
 
 
-#ifndef FT_CAN_HW_H
-#define FT_CAN_HW_H
+#ifndef FCAN_HW_H
+#define FCAN_HW_H
 
+#include "fparameters.h"
 #include "ftypes.h"
 #include "fio.h"
 #include "sdkconfig.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /***ft CAN REGISTER offset*/
 #define FCAN_CTRL_OFFSET            0x00 /* Global control register */
 #define FCAN_INTR_OFFSET            0x04 /* Interrupt register */
@@ -89,7 +97,7 @@
 #define FCAN_INTR_TFIC_MASK     BIT(20) /* TX FIFO empty interrupt clear*/
 #define FCAN_INTR_REIC_MASK     BIT(21) /* RX frame end interrupt clear*/
 #define FCAN_INTR_TEIC_MASK     BIT(22) /* TX frame end interrupt clear*/
-#define FCAN_INTR_EIC_MASK      BIT(23)  /* Error interrupt clear*/
+#define FCAN_INTR_EIC_MASK      BIT(23) /* Error interrupt clear*/
 #define FCAN_INTR_BORIS_MASK    BIT(24)
 #define FCAN_INTR_PWRIS_MASK    BIT(25)
 #define FCAN_INTR_PERIS_MASK    BIT(26)
@@ -131,7 +139,7 @@
 #define FCAN_FIFO_CNT_TFN_GET(x)     GET_REG32_BITS((x), 22, 16)
 #define FCAN_FIFO_CNT_TFN_SET(x)     SET_REG32_BITS((x), 22, 16)
 
-#define FCAN_IDR_ID1_SHIFT          21 /* Standard Messg Identifier */
+#define FCAN_IDR_ID1_SHIFT          21 /* Standard Message Identifier */
 #define FCAN_IDR_SDLC_SHIFT         14
 #define FCANFD_IDR_EDLC_SHIFT       24
 #define FCAN_IDR_EDLC_SHIFT         26
@@ -186,7 +194,7 @@
     #define FCAN_DATA_BRP_MAX   512
     #define FCAN_DATA_BRP_INC   1
 
-#elif defined(CONFIG_TARGET_E2000)
+#elif defined(CONFIG_TARGET_E2000) || defined(TARDIGRADE)
 
     #define FCAN_ARB_TSEG1_MIN  1
     #define FCAN_ARB_TSEG1_MAX  16
@@ -235,7 +243,6 @@
 
 #define FCAN_CLEARBIT(base_addr, reg_offset, data)     FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
 
-
 #define FCAN_TX_FIFO_FULL(instance_p) (FCAN_FIFO_DEPTH == FCAN_FIFO_CNT_TFN_GET(FCAN_READ_REG32(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET)))
 
 #define FCAN_RX_FIFO_EMPTY(instance_p) (0 == FCAN_FIFO_CNT_RFN_GET(FCAN_READ_REG32(instance_p->config.base_address, FCAN_FIFO_CNT_OFFSET)))
@@ -243,4 +250,8 @@
 
 void FCanDump(uintptr base_addr);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif // !
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c
index a792448e73e..2f5c40c5464 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c
@@ -14,14 +14,15 @@
  * FilePath: fcan_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:29:10
- * Description:  This files is for
+ * Description:  This files is for the can interrupt functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first release
+ * 1.1   zhangyan      2022/12/7  improve functions
  */
 
-#include "finterrupt.h"
 #include "fcan.h"
 #include "fcan_hw.h"
 #include "fassert.h"
@@ -80,7 +81,7 @@ void FCanIntrHandler(s32 vector, void *args)
         return;
     }
 
-    /* Check for the type of error interrupt and Processing it */
+    /* Check for the type of interrupt and Processing it */
     if (irq_status & FCAN_INTR_TEIS_MASK)
     {
         irq_status &= ~FCAN_INTR_REIS_MASK;
@@ -93,36 +94,62 @@ void FCanIntrHandler(s32 vector, void *args)
         FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_SEND);
     }
 
-    if (irq_status & (FCAN_INTR_EIS_MASK | FCAN_INTR_RFIS_MASK | FCAN_INTR_TFIS_MASK |
+    if (irq_status & (FCAN_INTR_EIS_MASK  | FCAN_INTR_RFIS_MASK | FCAN_INTR_TFIS_MASK |
                       FCAN_INTR_BOIS_MASK | FCAN_INTR_PEIS_MASK | FCAN_INTR_PWIS_MASK))
     {
-        FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_ERROR);
-
         FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET,
-                    (FCAN_INTR_EIC_MASK | FCAN_INTR_RFIC_MASK | FCAN_INTR_BOIC_MASK |
-                     FCAN_INTR_PEIC_MASK | FCAN_INTR_PWIC_MASK));
+                    (FCAN_INTR_EIC_MASK  | FCAN_INTR_RFIC_MASK | FCAN_INTR_BOIC_MASK |
+                     FCAN_INTR_PEIC_MASK | FCAN_INTR_PWIC_MASK | FCAN_INTR_TFIC_MASK));
 
         /* Check for rx fifo full interrupt and output error information */
         if (irq_status & FCAN_INTR_RFIS_MASK)
         {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_FIFOFULL);
             FCAN_ERROR("rx_fifo is full!!!");
             /* disable rx fifo full interrupt */
             FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_RFIE_MASK);
         }
-
         if (irq_status & FCAN_INTR_TFIS_MASK)
         {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_FIFOEMPTY);
             FCAN_ERROR("tx_fifo is empty!!!");
             /* disable tx fifo empty interrupt */
             FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_TFIE_MASK);
         }
+        if (irq_status & FCAN_INTR_EIS_MASK)
+        {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_ERROR);
+            FCAN_ERROR("Error occurred!!!");
+            /* disable error interrupt */
+            FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_EIE_MASK);
+        }
+        if (irq_status & FCAN_INTR_BOIS_MASK)
+        {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_BUSOFF);
+            FCAN_ERROR("Bus off!!!");
+            /* disable busoff interrupt */
+            FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_BOIE_MASK);
+        }
+        if (irq_status & FCAN_INTR_PEIS_MASK)
+        {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_PERROE);
+            FCAN_ERROR("Passive error occurred!!!");
+            /* disable passive error interrupt */
+            FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_PEIE_MASK);
+        }
+        if (irq_status & FCAN_INTR_PWIS_MASK)
+        {
+            FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_PWARN);
+            FCAN_ERROR("Passive warning!!!");
+            /* disable passive warning interrupt */
+            FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_PWIE_MASK);
+        }
     }
 
     if (irq_status & FCAN_INTR_REIS_MASK)
     {
         FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
         FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIC_MASK);
-        FCAN_SETBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_REIE_MASK);
         FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_RECV);
     }
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_sinit.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_sinit.c
index 15dbb27ba0c..0b01226ee4a 100644
--- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_sinit.c
@@ -14,11 +14,12 @@
  * FilePath: fcan_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:29:15
- * Description:  This files is for
+ * Description:  This files is for getting default configuration of specific can instance_id
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/5/26  first releases
  */
 
 
@@ -26,21 +27,21 @@
 #include "fparameters.h"
 #include "fassert.h"
 
-extern const FCanConfig FCanConfigTbl[FCAN_INSTANCE_NUM];
+extern const FCanConfig FCanConfigTbl[FCAN_NUM];
 
 /**
  * @name: FCanLookupConfig
  * @msg:  get default configuration of specific can instance_id.
- * @param {FCanInstance} instance_id, instance id of Can controller
+ * @param {u32} instance_id, instance id of Can controller
  * @return {FCanConfig*} Default configuration parameters of Can
  */
-const FCanConfig *FCanLookupConfig(FCanInstance instance_id)
+const FCanConfig *FCanLookupConfig(u32 instance_id)
 {
-    FASSERT(instance_id < FCAN_INSTANCE_NUM);
+    FASSERT(instance_id < FCAN_NUM);
     const FCanConfig *pconfig = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FCAN_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FCAN_NUM; index++)
     {
         if (FCanConfigTbl[index].instance_id == instance_id)
         {
@@ -48,5 +49,5 @@ const FCanConfig *FCanLookupConfig(FCanInstance instance_id)
             break;
         }
     }
-    return (FCanConfig *)pconfig;
+    return (const FCanConfig *)pconfig;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/Kconfig b/bsp/phytium/libraries/standalone/drivers/dma/Kconfig
index 16336f66e16..9ed7f948482 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/dma/Kconfig
@@ -2,9 +2,9 @@
 config ENABLE_FGDMA
     bool
     prompt "Use FGDMA"
-    default n
+    default n    
 
 config ENABLE_FDDMA
     bool
     prompt "Use FDDMA"
-    default n
+    default n
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c
index 494af32fdeb..31fc660b65f 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c
@@ -14,12 +14,12 @@
  * FilePath: fddma.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:47
- * Description:  This files is for ddma interface implementation
+ * Description:  This file is for ddma interface implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
@@ -65,7 +65,7 @@ FError FDdmaCfgInitialization(FDdma *const instance, const FDdmaConfig *input_co
 
     if (FT_COMPONENT_IS_READY == instance->is_ready)
     {
-        FDDMA_WARN("device is already initialized!!!");
+        FDDMA_WARN("The device has been initialized !!!");
     }
 
     FDdmaDeInitialization(instance);
@@ -75,7 +75,7 @@ FError FDdmaCfgInitialization(FDdma *const instance, const FDdmaConfig *input_co
     if (FDDMA_SUCCESS == ret)
     {
         instance->is_ready = FT_COMPONENT_IS_READY;
-        FDDMA_INFO("ddma@0x%x init success !!!", base_addr);
+        FDDMA_INFO("ddma@0x%x initialized successfully !!!", base_addr);
     }
 
     return ret;
@@ -95,7 +95,7 @@ FError FDdmaStart(FDdma *const instance)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
@@ -118,7 +118,7 @@ FError FDdmaStop(FDdma *const instance)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
@@ -142,7 +142,7 @@ void FDdmaDeInitialization(FDdma *const instance)
     {
         if (instance->bind_status & BIT(chan))
         {
-            FDDMA_WARN("channel %d has not been unbind", chan);
+            FDDMA_WARN("Channel %d is not yet unbound", chan);
         }
     }
 
@@ -168,34 +168,34 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
     if ((TRUE == dma_chan->is_used) || (BIT(chan_idx) & instance->bind_status))
     {
-        FDDMA_ERROR("chan-%d is already is use !!!", chan_idx);
+        FDDMA_ERROR("Channel -%d has already been used !!!", chan_idx);
         return FDDMA_ERR_CHAN_BINDED;
     }
 
     if (FDdmaIsChanRunning(base_addr, chan_idx))
     {
-        FDDMA_ERROR("chan-%d is already running !!!", chan_idx);
+        FDDMA_ERROR("Channel -%d is running !!!", chan_idx);
         return FDDMA_ERR_CHAN_BINDED;
     }
 
     if (dma_chan_config->ddr_addr % FDDMA_DDR_ADDR_ALIGMENT)
     {
-        FDDMA_ERROR("ddr addr 0x%x must align with %d bytes",
+        FDDMA_ERROR("DDR addr 0x%x must be aligned with %d bytes",
                     dma_chan_config->ddr_addr, FDDMA_DDR_ADDR_ALIGMENT);
         return FDDMA_ERR_INVALID_DDR_ADDR;
     }
 
     if ((FDDMA_MAX_TRANSFER_LEN < dma_chan_config->trans_len) ||
-            (FDDMA_MIN_TRANSFER_LEN > dma_chan_config->trans_len) ||
-            (0 != dma_chan_config->trans_len % FDDMA_MIN_TRANSFER_LEN))
+        (FDDMA_MIN_TRANSFER_LEN > dma_chan_config->trans_len) ||
+        (0 != dma_chan_config->trans_len % FDDMA_MIN_TRANSFER_LEN))
     {
-        FDDMA_ERROR("invalid transfer size %d Bytes !!!", dma_chan_config->trans_len);
+        FDDMA_ERROR("Invalid transfer size %d bytes !!!", dma_chan_config->trans_len);
         return FDDMA_ERR_INVALID_TRANS_SIZE;
     }
 
@@ -203,13 +203,15 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const
     instance->chan[chan_idx] = dma_chan;
 
     if (&(dma_chan->config) != dma_chan_config)
+    {
         dma_chan->config = *dma_chan_config;
+    }
 
     FDdmaStop(instance); /* disable irq */
 
     if (FDDMA_SUCCESS != FDdmaDisableChan(base_addr, chan_idx))
     {
-        FDDMA_ERROR("disable DDMA@0x%x channel %d failed !!!", base_addr, chan_idx);
+        FDDMA_ERROR("Failed to disable DDMA@0x%x channel %d !!!", base_addr, chan_idx);
         return FDDMA_ERR_WAIT_TIMEOUT;
     }
 
@@ -235,10 +237,10 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const
     FDdmaSetChanDirection(base_addr, chan_idx,
                           (FDDMA_CHAN_REQ_RX == dma_chan->config.req_mode) ? TRUE : FALSE);
 
-    FDDMA_INFO("chan-%d ddr @0x%x", chan_idx, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan_idx));
+    FDDMA_INFO("channel-%d ddr @0x%x", chan_idx, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan_idx));
     FDDMA_INFO("ddr addr: 0x%x", FDdmaReadReg(base_addr, FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan_idx)));
     FDDMA_INFO("dev addr: 0x%x", FDdmaReadReg(base_addr, FDDMA_CHAN_DEV_ADDR_OFFSET(chan_idx)));
-    FDDMA_INFO("trans len: %d", FDdmaReadReg(base_addr, FDDMA_CHAN_TS_OFFSET(chan_idx)));
+    FDDMA_INFO("transfer len: %d", FDdmaReadReg(base_addr, FDDMA_CHAN_TS_OFFSET(chan_idx)));
 
     FDdmaSetChanTimeout(base_addr, chan_idx, 0xffff);
     FDdmaEnableChanIrq(base_addr, chan_idx);
@@ -247,7 +249,7 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const
     {
         instance->bind_status |= BIT(chan_idx);
         dma_chan->is_used = TRUE;
-        FDDMA_INFO("allocate channel %d", chan_idx);
+        FDDMA_INFO("Allocate channel %d", chan_idx);
     }
 
     return ret;
@@ -269,13 +271,13 @@ FError FDdmaDellocateChan(FDdmaChan *const dma_chan)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
     if (FDDMA_SUCCESS != FDdmaDisableChan(base_addr, chan_idx))
     {
-        FDDMA_ERROR("disable DDMA@0x%x channel %d failed !!!", base_addr, chan_idx);
+        FDDMA_ERROR("Failed to disable DDMA@0x%x channel %d !!!", base_addr, chan_idx);
         return FDDMA_ERR_WAIT_TIMEOUT;
     }
 
@@ -285,7 +287,7 @@ FError FDdmaDellocateChan(FDdmaChan *const dma_chan)
     ret = FDdmaDisableChan(base_addr, chan_idx);
     if (FDDMA_SUCCESS != ret) /* disable channel */
     {
-        FDDMA_ERROR("disable ddma@%p channel %d failed !!!", base_addr, chan_idx);
+        FDDMA_ERROR("Failure to disable ddma@%p channel %d !!!", base_addr, chan_idx);
         return ret;
     }
 
@@ -294,7 +296,7 @@ FError FDdmaDellocateChan(FDdmaChan *const dma_chan)
     instance->bind_status &= ~BIT(chan_idx); /* set bind status */
     instance->chan[chan_idx] = NULL;
 
-    FDDMA_INFO("deallocate channel %d", chan_idx);
+    FDDMA_INFO("DeAllocate channels %d", chan_idx);
     memset(dma_chan, 0, sizeof(*dma_chan));
 
     return ret;
@@ -315,7 +317,7 @@ FError FDdmaActiveChan(FDdmaChan *const dma_chan)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
@@ -332,7 +334,7 @@ FError FDdmaDeactiveChan(FDdmaChan *const dma_chan)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FDDMA_ERROR("dma instance not init !!!");
+        FDDMA_ERROR("The Dma instance is not initialized !!!");
         return FDDMA_ERR_NOT_INIT;
     }
 
@@ -355,7 +357,7 @@ static FError FDdmaReset(FDdma *const instance)
 
     if (0 != instance->bind_status)
     {
-        FDDMA_WARN("some channel not yet un-bind !!!");
+        FDDMA_WARN("Some channels are not yet unbound !!!");
     }
 
     FDdmaDisable(base_addr); /* disable ddma  */
@@ -369,7 +371,7 @@ static FError FDdmaReset(FDdma *const instance)
         ret = FDdmaDisableChan(base_addr, chan);
         if (FDDMA_SUCCESS != ret)
         {
-            FDDMA_ERROR("disable ddma@%p channel %d failed !!!", base_addr, chan);
+            FDDMA_ERROR("Failure to disable ddma@%p channel %d !!!", base_addr, chan);
             break;
         }
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h
index 486876a698e..5529a0c1e12 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h
@@ -14,16 +14,19 @@
  * FilePath: fddma.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:52
- * Description:  This files is for ddma interface definition
+ * Description:  This file is for ddma interface definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
-#ifndef  DRIVER_FDDMA_H
-#define  DRIVER_FDDMA_H
+#ifndef  FDDMA_H
+#define  FDDMA_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -31,9 +34,6 @@ extern "C"
 #endif
 /***************************** Include Files *********************************/
 
-#include "ftypes.h"
-#include "ferror_code.h"
-
 /************************** Constant Definitions *****************************/
 typedef enum
 {
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_g.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_g.c
index 4204d9d23e7..6bcce37b1fa 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_g.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.c
index dfbe76576e8..f66ca8aaf5d 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
@@ -91,14 +91,14 @@ void FDdmaSoftwareReset(uintptr base_addr)
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CTL_OFFSET);
     reg_val |= FDDMA_CTL_SRST;
     FDdmaWriteReg(base_addr, FDDMA_CTL_OFFSET, reg_val);
-    FDDMA_DEBUG("ddma @%p software reset start : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_CTL_OFFSET));
+    FDDMA_DEBUG("ddma @%p soft reset start : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_CTL_OFFSET));
 
     while (--delay > 0) /* wait a while to do reset */
         ;
 
     reg_val &= ~FDDMA_CTL_SRST;
     FDdmaWriteReg(base_addr, FDDMA_CTL_OFFSET, reg_val); /* exit from software reset */
-    FDDMA_DEBUG("ddma @%p software reset end : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_CTL_OFFSET));
+    FDDMA_DEBUG("ddma @%p soft reset end : 0x%x", base_addr, FDdmaReadReg(base_addr, FDDMA_CTL_OFFSET));
     return;
 }
 
@@ -139,7 +139,7 @@ void FDdmaEnableGlobalIrq(uintptr base_addr)
  */
 void FDdmaDisableChanIrq(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
     reg_val |= FDDMA_MASK_EN_CHAN_INTR(chan);
     FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
@@ -155,7 +155,7 @@ void FDdmaDisableChanIrq(uintptr base_addr, u32 chan)
  */
 void FDdmaEnableChanIrq(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val  = FDdmaReadReg(base_addr, FDDMA_MASK_INTR_OFFSET);
     reg_val &= ~FDDMA_MASK_EN_CHAN_INTR(chan); /* write 0 and enable  */
     FDdmaWriteReg(base_addr, FDDMA_MASK_INTR_OFFSET, reg_val);
@@ -171,7 +171,7 @@ void FDdmaEnableChanIrq(uintptr base_addr, u32 chan)
  */
 FError FDdmaDisableChan(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     int delay = 1000;
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
     reg_val &= ~FDDMA_CHAN_CTL_EN;
@@ -182,11 +182,13 @@ FError FDdmaDisableChan(uintptr base_addr, u32 chan)
     {
         reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
         if (delay-- <= 0)
+        {
             break;
+        }
     }
     while (reg_val & FDDMA_CHAN_CTL_EN);
 
-    FDDMA_DEBUG("ddma @%p chan %d disabled : 0x%x", base_addr, chan, FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan)));
+    FDDMA_DEBUG("ddma@ %p channel %d is disabled : 0x%x", base_addr, chan, FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan)));
     return (delay > 0) ? FDDMA_SUCCESS : FDDMA_ERR_WAIT_TIMEOUT;
 }
 
@@ -199,7 +201,7 @@ FError FDdmaDisableChan(uintptr base_addr, u32 chan)
  */
 void FDdmaEnableChan(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
     reg_val |= FDDMA_CHAN_CTL_EN;
     FDdmaWriteReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan), reg_val);
@@ -216,7 +218,7 @@ void FDdmaEnableChan(uintptr base_addr, u32 chan)
  */
 void FDdmaClearChanIrq(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     /* write 1 to clear irq status of channel */
     FDdmaWriteReg(base_addr, FDDMA_STA_OFFSET, FDDMA_STA_CHAN_REQ_DONE(chan));
 }
@@ -230,12 +232,14 @@ void FDdmaClearChanIrq(uintptr base_addr, u32 chan)
  */
 void FDdmaResetChan(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     int delay = 1000;
     u32 reg_val;
 
     if (FDdmaIsChanRunning(base_addr, chan)) /* disable channel if running */
+    {
         (void)FDdmaDisableChan(base_addr, chan);
+    }
 
     reg_val  = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
     reg_val |= FDDMA_CHAN_CTL_SRST;
@@ -246,7 +250,7 @@ void FDdmaResetChan(uintptr base_addr, u32 chan)
 
     reg_val &= ~FDDMA_CHAN_CTL_SRST;
     FDdmaWriteReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan), reg_val);
-    FDDMA_DEBUG("chan reset done, ctrl: 0x%x", FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan)));
+    FDDMA_DEBUG("Channel reset done, ctrl: 0x%x", FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan)));
     return;
 }
 
@@ -259,7 +263,7 @@ void FDdmaResetChan(uintptr base_addr, u32 chan)
  */
 boolean FDdmaIsChanRunning(uintptr base_addr, u32 chan)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
     return (FDDMA_CHAN_CTL_EN & reg_val) ? TRUE : FALSE;
 }
@@ -274,8 +278,8 @@ boolean FDdmaIsChanRunning(uintptr base_addr, u32 chan)
  */
 void FDdmaSetChanSelection(uintptr base_addr, u32 chan, u32 slave_id)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
-    FASSERT_MSG((FDDMA_MAX_SLAVE_ID >= slave_id), "invalid slave id %d", slave_id);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
+    FASSERT_MSG((FDDMA_MAX_SLAVE_ID >= slave_id), "Invalid slave id %d", slave_id);
     u32 reg_val;
 
     if (FDDMA_CHAN_4 > chan)
@@ -285,7 +289,7 @@ void FDdmaSetChanSelection(uintptr base_addr, u32 chan, u32 slave_id)
         reg_val |= FDDMA_CHAN_0_3_SEL(chan, slave_id);
         reg_val |= FDDMA_CHAN_0_3_SEL_EN(chan);
         FDdmaWriteReg(base_addr, FDDMA_CHAN_0_3_CFG_OFFSET, reg_val);
-        FDDMA_DEBUG("ddma@%p set chan-%d slave id-%d, 0x%x", base_addr, chan, slave_id, FDdmaReadReg(base_addr, FDDMA_CHAN_0_3_CFG_OFFSET));
+        FDDMA_DEBUG("ddma%p sets the slaveid of chan-%d to %d, 0x%x", base_addr, chan, slave_id, FDdmaReadReg(base_addr, FDDMA_CHAN_0_3_CFG_OFFSET));
     }
     else
     {
@@ -294,7 +298,7 @@ void FDdmaSetChanSelection(uintptr base_addr, u32 chan, u32 slave_id)
         reg_val |= FDDMA_CHAN_4_7_SEL(chan, slave_id);
         reg_val |= FDDMA_CHAN_4_7_SEL_EN(chan);
         FDdmaWriteReg(base_addr, FDDMA_CHAN_4_7_CFG_OFFSET, reg_val);
-        FDDMA_DEBUG("ddma@%p set chan-%d slave id-%d, 0x%x", base_addr, chan, slave_id, FDdmaReadReg(base_addr, FDDMA_CHAN_4_7_CFG_OFFSET));
+        FDDMA_DEBUG("ddma%p sets the slaveid of chan-%d to %d, 0x%x", base_addr, chan, slave_id, FDdmaReadReg(base_addr, FDDMA_CHAN_4_7_CFG_OFFSET));
     }
 
     return;
@@ -310,13 +314,17 @@ void FDdmaSetChanSelection(uintptr base_addr, u32 chan, u32 slave_id)
  */
 void FDdmaSetChanBind(uintptr base_addr, u32 chan, boolean bind)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_BIND_OFFSET);
 
     if (bind)
+    {
         reg_val |= BIT(chan);
+    }
     else
+    {
         reg_val &= ~BIT(chan);
+    }
 
     FDDMA_DEBUG("ddma@%p %s chan-%d, 0x%x", base_addr, bind ? "bind" : "unbind", chan, FDdmaReadReg(base_addr, FDDMA_CHAN_BIND_OFFSET));
     FDdmaWriteReg(base_addr, FDDMA_CHAN_BIND_OFFSET, reg_val);
@@ -333,12 +341,16 @@ void FDdmaSetChanBind(uintptr base_addr, u32 chan, boolean bind)
  */
 void FDdmaSetChanDirection(uintptr base_addr, u32 chan, boolean is_rx)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan));
     if (is_rx)
-        reg_val |= FDDMA_CHAN_CTL_RX_MODE; /* device to memory */
+    {
+        reg_val |= FDDMA_CHAN_CTL_RX_MODE;    /* device to memory */
+    }
     else
-        reg_val &= ~FDDMA_CHAN_CTL_RX_MODE; /* memory to device */
+    {
+        reg_val &= ~FDDMA_CHAN_CTL_RX_MODE;    /* memory to device */
+    }
     FDdmaWriteReg(base_addr, FDDMA_CHAN_CTL_OFFSET(chan), reg_val);
     return;
 }
@@ -353,7 +365,7 @@ void FDdmaSetChanDirection(uintptr base_addr, u32 chan, boolean is_rx)
  */
 void FDdmaSetChanTimeout(uintptr base_addr, u32 chan, u32 timeout)
 {
-    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "chan %d not support", chan);
+    FASSERT_MSG((FDDMA_NUM_OF_CHAN > chan), "Channel %d is not supported", chan);
     u32 reg_val = FDdmaReadReg(base_addr, FDDMA_CHAN_TIMEOUT_CNT_OFFSET(chan));
 
     if (0 < timeout)
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.h b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.h
index 2334abd1840..e84e6c6fd99 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_hw.h
@@ -19,16 +19,12 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
-#ifndef  DRIVERS_FDDMA_HW_H
-#define  DRIVERS_FDDMA_HW_H
+#ifndef  FDDMA_HW_H
+#define  FDDMA_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 /***************************** Include Files *********************************/
 
 #include "fassert.h"
@@ -36,6 +32,12 @@ extern "C"
 #include "fio.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
 /************************** Constant Definitions *****************************/
 /** @name Register Map
  *
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_intr.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_intr.c
index c71ba37018e..76cfdecb80f 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_intr.c
@@ -14,12 +14,12 @@
  * FilePath: fddma_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:47
- * Description:  This files is for ddma interrupt implementation
+ * Description:  This file is for ddma interrupt implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
@@ -112,7 +112,9 @@ void FDdmaIrqHandler(s32 vector, void *args)
     for (chan = FDDMA_CHAN_0; chan < FDDMA_NUM_OF_CHAN; chan++)
     {
         if (0 == (FDDMA_STA_CHAN_REQ_DONE(chan) & status))
+        {
             continue;
+        }
 
         FDDMA_INFO("handle chan %d", chan);
         FDdmaClearChanIrq(base_addr, chan);  /* clear interrupt status */
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_selftest.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_selftest.c
index dfe9dea6a52..5f1bd6557e0 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_selftest.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_selftest.c
@@ -14,12 +14,12 @@
  * FilePath: fddma_selftest.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:47
- * Description:  This files is for ddma self test
+ * Description:  This file is for ddma self test
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_sinit.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_sinit.c
index 0a7ad7f4302..ac5bdd5be18 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma_sinit.c
@@ -14,12 +14,12 @@
  * FilePath: fddma_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:47
- * Description:  This files is for static initialization
+ * Description:  This file is for static initialization
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/5/13    init commit
+ * 1.0   zhugengyu  2022/5/13    init commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c
index f43a56bd275..e5d256db219 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c
@@ -14,13 +14,13 @@
  * FilePath: fgdma.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for
+ * Description:  This file is for gdma user function implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- *  1.0   huanghe    2021-11-5    init commit
- *  1.1   zhugengyu  2022-5-16    support chan alloc. and qos setting
+ *  1.0   huanghe    2021/11/5    init commit
+ *  1.1   zhugengyu  2022/5/16    support chan alloc. and qos setting
  */
 
 
@@ -65,15 +65,17 @@ FError FGdmaCfgInitialize(FGdma *const instance_p, const FGdmaConfig *input_conf
 
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FGDMA_WARN("device is already initialized!!!");
+        FGDMA_WARN("The device has been initialized!!");
     }
 
     FGdmaDeInitialize(instance_p);
 
     if (&instance_p->config != input_config)
+    {
         instance_p->config = *input_config;
+    }
 
-    FASSERT_MSG((0 != base_addr), "invalid device base address");
+    FASSERT_MSG((0 != base_addr), "Invalid device base address");
     FGdmaReset(instance_p);
 
     if (FGDMA_SUCCESS == ret)
@@ -95,11 +97,11 @@ void FGdmaDeInitialize(FGdma *const instance_p)
     FASSERT(instance_p);
     u32 chan;
 
-    for (chan = FGDMA_CHAN0_INDEX; chan < FGDMA_NUM_OF_CHAN; chan++)
+    for (chan = 0; chan < FGDMA_NUM_OF_CHAN; chan++)
     {
         if (NULL != instance_p->chans[chan])
         {
-            FGDMA_WARN("chan-%d might be in use !!!", chan);
+            FGDMA_WARN("chans-% d may be used!!!", chan);
         }
     }
 
@@ -166,18 +168,26 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan,
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
 
+    if(chan_idx >= FGDMA_NUM_OF_CHAN)
+    {
+        FGDMA_ERROR("Channel %d is in use !!!", chan_idx);
+        return FGDMA_ERR_CHAN_IN_USE;
+    }
+
     if (NULL != instance_p->chans[chan_idx])
     {
-        FGDMA_ERROR("chan %d is in use !!!", chan_idx);
+        FGDMA_ERROR("Channel %d is in use !!!", chan_idx);
         return FGDMA_ERR_CHAN_IN_USE;
     }
 
     if (&dma_chan->config != dma_chan_config)
+    {
         dma_chan->config = *dma_chan_config;
+    }
 
     /* disable and reset chan */
     FGdmaChanDisable(base_addr, chan_idx);
@@ -190,7 +200,7 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan,
     reg_val = FGDMA_READREG(base_addr, FGDMA_CHX_MODE_OFFSET(chan_idx));
     if (FGDMA_OPER_BDL == dma_chan->config.trans_mode)
     {
-        FGDMA_INFO("set as BDL mode");
+        FGDMA_INFO("Set to BDL mode");
         reg_val |= FGDMA_CHX_MODE_BDL_EN;
 
         if (dma_chan->config.roll_back)
@@ -204,7 +214,7 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan,
     }
     else
     {
-        FGDMA_INFO("set as Direct mode");
+        FGDMA_INFO("Set to Direct mode");
         reg_val &= ~FGDMA_CHX_MODE_BDL_EN;
         reg_val &= ~FGDMA_CHX_MODE_BDL_ROLL_EN;
     }
@@ -249,7 +259,7 @@ FError FGdmaDellocateChan(FGdmaChan *const dma_chan)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
 
@@ -291,12 +301,12 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
 
     if ((src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)) ||
-            (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)))
+        (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)))
     {
         FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
                     src_addr, dst_addr, FGDMA_ADDR_ALIGMENT);
@@ -365,27 +375,27 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds
 FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr dst_addr, fsize_t data_len)
 {
     FASSERT(chan_p);
-    FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "BDL descriptor list not yet assign !!!");
+    FASSERT_MSG((chan_p->config.descs) && (chan_p->config.total_desc_num > 0), "The list of BDL descriptors has not yet been assigned !!!");
     u32 desc_idx = chan_p->config.valid_desc_num;
     FGdmaBdlDesc *desc_entry = &(chan_p->config.descs[desc_idx]);
 
     if (chan_p->config.valid_desc_num >= chan_p->config.total_desc_num)
     {
-        FGDMA_ERROR("total BDL descriptor num is %d, already used up", chan_p->config.total_desc_num);
+        FGDMA_ERROR("The total BDL descriptor num is %d and has been used up", chan_p->config.total_desc_num);
         return FGDMA_ERR_BDL_NOT_ENOUGH;
     }
 
     if ((0U != (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align))) ||
-            (0U != (src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align))))
+        (0U != (src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align))))
     {
-        FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes",
+        FGDMA_ERROR("SRC addr 0x%x or DST addr 0x%x are not aligned with the %d transfer size",
                     src_addr, dst_addr, FGDMA_GET_BURST_SIZE(chan_p->config.wr_align));
         return FGDMA_ERR_INVALID_ADDR;
     }
 
     if (0U != (data_len % chan_p->config.wr_align))
     {
-        FGDMA_ERROR("data length %d must be N times of burst size %d !!!",
+        FGDMA_ERROR("The data length %d must be N times the burst size %d !!!",
                     data_len, chan_p->config.wr_align);
         return FGDMA_ERR_INVALID_SIZE;
     }
@@ -438,13 +448,13 @@ FError FGdmaBDLTransfer(FGdmaChan *const chan_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
 
     if (0 == chan_p->config.valid_desc_num)
     {
-        FGDMA_WARN("need to assign BDL entry fisrt !!!");
+        FGDMA_WARN("First, the BDL entries need to be allocated !!!");
         return FGDMA_SUCCESS;
     }
 
@@ -499,13 +509,16 @@ FError FGdmaStart(FGdma *const instance_p)
     FASSERT(instance_p);
     uintptr base_addr = instance_p->config.base_addr;
     u32 reg_val;
-
+    
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
-
+    if(FGDMA_TRANS_NEED_RESET_MASK & instance_p->config.caps)
+    {
+        FGdmaSoftwareReset(base_addr);
+    }
     FGdmaIrqEnable(base_addr);
 
     reg_val = FGDMA_READREG(base_addr, FGDMA_CTL_OFFSET);
@@ -513,6 +526,8 @@ FError FGdmaStart(FGdma *const instance_p)
     reg_val |= FGDMA_CTL_OT_SET(FGDMA_OUTSTANDING); /* 设置传输outstanding数 */
     reg_val |= FGDMA_CTL_ENABLE; /* 使能DMA传输 */
     FGDMA_WRITEREG(base_addr, FGDMA_CTL_OFFSET, reg_val);
+    
+
 
     return FGDMA_SUCCESS; // 放到初始化
 }
@@ -533,20 +548,22 @@ FError FGdmaStop(FGdma *const instance_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGDMA_ERROR("dma instance not init !!!");
+        FGDMA_ERROR("The dma instance is not initialized !!!");
         return FGDMA_ERR_NOT_INIT;
     }
 
     /* Abort 流程 */
-    for (chan_id = FGDMA_CHAN0_INDEX; chan_id < FGDMA_NUM_OF_CHAN; chan_id++)
+    for (chan_id = 0; chan_id < FGDMA_NUM_OF_CHAN; chan_id++)
     {
         if (NULL == instance_p->chans[chan_id])
-            continue; /* skip un-allocate channel */
+        {
+            continue;    /* skip un-allocate channel */
+        }
 
         chan_status = FGdmaReadChanStatus(base_addr, chan_id);
         if (FGDMA_CHX_INT_STATE_BUSY & chan_status)
         {
-            FGDMA_WARN("chan-%d has abort unfinished request !!!", chan_id);
+            FGDMA_WARN("chan-%d was forcibly closed !!!", chan_id);
             FGdmaChanDisable(base_addr, chan_id); /* 关闭通道 */
             FGdmaChanReset(base_addr, chan_id); /* 需要进行软复位，否则再次使能通道时，仍然会执行之前的请求 */
         }
@@ -559,7 +576,7 @@ FError FGdmaStop(FGdma *const instance_p)
     }
 
     FGdmaDisable(base_addr);
-
+    
     return FGDMA_SUCCESS;
 }
 
@@ -631,22 +648,22 @@ static void FGdmaReset(FGdma *const instance_p)
     u32 chan;
     u32 reg_val;
 
-    FGDMA_INFO("reset ctrl @0x%x ...", base_addr);
+    FGDMA_INFO("Controller base address is %p ...", base_addr);
 
     FGdmaDisable(base_addr);
     FGdmaSoftwareReset(base_addr);
 
     FGdmaSetQos(instance_p);
 
-    FGDMA_INFO("reset chan ...");
+    FGDMA_INFO("Reset channel");
 
-    for (chan = FGDMA_CHAN0_INDEX; chan < FGDMA_NUM_OF_CHAN; chan++)
+    for (chan = 0; chan < FGDMA_NUM_OF_CHAN; chan++)
     {
         FGdmaChanDisable(base_addr, chan);
         FGdmaChanIrqDisable(base_addr, chan);
         FGdmaChanReset(base_addr, chan);
         FGdmaSetChanClock(base_addr, chan, FALSE);
     }
-
+    
     return;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h
index 0319af36188..8474ba88823 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h
@@ -14,17 +14,22 @@
  * FilePath: fgdma.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:35
- * Description:  This files is for gdma user api implementation
+ * Description:  This file is for gdma user api implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 
-#ifndef DRIVERS_FGDMA_H
-#define DRIVERS_FGDMA_H
+#ifndef FGDMA_H
+#define FGDMA_H
+
+#include "ftypes.h"
+#include "fassert.h"
+#include "ferror_code.h"
+#include "fkernel.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -33,33 +38,15 @@ extern "C"
 
 /***************************** Include Files *********************************/
 
-#include "ftypes.h"
-#include "fassert.h"
-#include "ferror_code.h"
-#include "fkernel.h"
+
 
 /************************** Constant Definitions *****************************/
-typedef enum
-{
-    FGDMA_CHAN0_INDEX = 0,
-    FGDMA_CHAN1_INDEX = 1,
-    FGDMA_CHAN2_INDEX = 2,
-    FGDMA_CHAN3_INDEX = 3,
-    FGDMA_CHAN4_INDEX = 4,
-    FGDMA_CHAN5_INDEX = 5,
-    FGDMA_CHAN6_INDEX = 6,
-    FGDMA_CHAN7_INDEX = 7,
-    FGDMA_CHAN8_INDEX = 8,
-    FGDMA_CHAN9_INDEX = 9,
-    FGDMA_CHAN10_INDEX = 10,
-    FGDMA_CHAN11_INDEX = 11,
-    FGDMA_CHAN12_INDEX = 12,
-    FGDMA_CHAN13_INDEX = 13,
-    FGDMA_CHAN14_INDEX = 14,
-    FGDMA_CHAN15_INDEX = 15,
-
-    FGDMA_NUM_OF_CHAN
-} FGdmaChanIndex; /* 16个独立通道, 0 ~ 15 */
+
+/* gdma capacity mask  */
+
+#define FGDMA_IRQ1_MASK BIT(0)   /* All Gdma channel share a single interrupt */
+#define FGDMA_IRQ2_MASK BIT(1)   /* Each gdma channel owns an independent interrupt */
+#define FGDMA_TRANS_NEED_RESET_MASK BIT(2) /* Gdma needs to be reset before transmission */
 
 typedef enum
 {
@@ -127,11 +114,12 @@ typedef struct _FGdmaChan FGdmaChan;
 typedef struct
 {
     u32 instance_id;               /* GDMA控制器ID */
-    u32 irq_num;                   /* GDMA控制器中断号 */
+    u32 irq_num[FGDMA_NUM_OF_CHAN];   /* GDMA控制器中断号 */
     u32 irq_prority;               /* GDMA控制器中断优先级 */
     volatile uintptr_t base_addr;  /* GDMA控制器基地址 */
     FGdmaOperPriority rd_qos;      /* 读操作优先级 */
     FGdmaOperPriority wr_qos;      /* 写操作优先级 */
+    u32 caps;                       /* driver capacity */
 } FGdmaConfig; /* GDMA控制器配置 */
 
 typedef struct
@@ -154,6 +142,8 @@ typedef struct
 
 FASSERT_STATIC(0x20U == sizeof(FGdmaBdlDesc));
 
+typedef u32 FGdmaChanIndex;
+
 typedef struct
 {
     FGdmaChanIndex      chan_id; /* DMA通道ID */
@@ -172,10 +162,11 @@ typedef struct
 
 typedef void (*FGdmaChanEvtHandler)(FGdmaChan *const chan, void *args);
 
+
 typedef struct _FGdmaChan
 {
     FGdmaChanConfig config;     /* DMA通道配置 */
-    FGdma *gdma;                /* DMA控制器实例 */
+    FGdma *gdma;                                              /* DMA控制器实例 */
     FGdmaChanEvtHandler evt_handlers[FGDMA_CHAN_NUM_OF_EVT];  /* DMA通道事件回调函数 */
     void *evt_handler_args[FGDMA_CHAN_NUM_OF_EVT];            /* DMA通道事件回调函数入参 */
 } FGdmaChan; /* GDMA通道实例 */
@@ -192,29 +183,29 @@ typedef struct _FGdma
 /***************** Macros (Inline Functions) Definitions *********************/
 /* 获取默认的通道配置 */
 #define FGDMA_DEFAULT_DIRECT_CHAN_CONFIG(_chan_id)\
-(FGdmaChanConfig){ \
-    .chan_id = (_chan_id),\
-    .rd_align = FGDMA_BURST_SIZE_4_BYTE,\
-    .wr_align = FGDMA_BURST_SIZE_4_BYTE,\
-    .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
-    .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
-    .trans_mode = FGDMA_OPER_DIRECT,\
-    .roll_back = FALSE\
-}
+    (FGdmaChanConfig){ \
+        .chan_id = (_chan_id),\
+        .rd_align = FGDMA_BURST_SIZE_4_BYTE,\
+        .wr_align = FGDMA_BURST_SIZE_4_BYTE,\
+        .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+        .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+        .trans_mode = FGDMA_OPER_DIRECT,\
+        .roll_back = FALSE\
+    }
 
 #define FGDMA_DEFAULT_BDL_CHAN_CONFIG(_chan_id, _bdl_descs, _bdl_desc_num)\
-(FGdmaChanConfig){ \
-    .chan_id = (_chan_id),\
-    .rd_align = FGDMA_BURST_SIZE_4_BYTE,\
-    .wr_align = FGDMA_BURST_SIZE_4_BYTE,\
-    .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
-    .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
-    .trans_mode = FGDMA_OPER_BDL,\
-    .roll_back = FALSE,\
-    .descs = _bdl_descs,\
-    .total_desc_num = _bdl_desc_num,\
-    .valid_desc_num = 0U\
-}
+    (FGdmaChanConfig){ \
+        .chan_id = (_chan_id),\
+        .rd_align = FGDMA_BURST_SIZE_4_BYTE,\
+        .wr_align = FGDMA_BURST_SIZE_4_BYTE,\
+        .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+        .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\
+        .trans_mode = FGDMA_OPER_BDL,\
+        .roll_back = FALSE,\
+        .descs = _bdl_descs,\
+        .total_desc_num = _bdl_desc_num,\
+        .valid_desc_num = 0U\
+    }
 
 /************************** Function Prototypes ******************************/
 /* 获取GDMA控制器默认配置 */
@@ -250,6 +241,7 @@ FError FGdmaStop(FGdma *const instance_p);
 
 /* GDMA中断处理函数 */
 void FGdmaIrqHandler(s32 vector, void *args);
+void FGdmaIrqHandlerPrivateChannel(s32 vector, void *args);
 
 /* 注册GDMA通道事件回调函数 */
 void FGdmaChanRegisterEvtHandler(FGdmaChan *const chan_p, FGdmaChanEvtType evt,
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c
index 8cb1ba77f84..fcd0dbc7f13 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c
@@ -14,13 +14,13 @@
  * FilePath: fgdma_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:09
- * Description:  This files is for static variables definition
+ * Description:  This file is for static variables definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 
 /***************************** Include Files *********************************/
@@ -47,10 +47,31 @@ const FGdmaConfig fgdma_cfg_tbl[FGDMA_INSTANCE_NUM] =
     {
         .instance_id = FGDMA0_ID,
         .base_addr = FGDMA0_BASE_ADDR,
-        .irq_num = FGDMA0_IRQ_NUM,
+        .irq_num ={
+                    FGDMA0_CHANNEL0_IRQ_NUM,
+                    #if defined(FGDMA0_CHANNEL1_IRQ_NUM)
+                    FGDMA0_CHANNEL1_IRQ_NUM,
+                    #endif
+                    #if defined(FGDMA0_CHANNEL2_IRQ_NUM)
+                    FGDMA0_CHANNEL2_IRQ_NUM,
+                    #endif
+                    #if defined(FGDMA0_CHANNEL3_IRQ_NUM)
+                    FGDMA0_CHANNEL3_IRQ_NUM,
+                    #endif
+                    #if defined(FGDMA0_CHANNEL4_IRQ_NUM)
+                    FGDMA0_CHANNEL4_IRQ_NUM,
+                    #endif
+                    #if defined(FGDMA0_CHANNEL5_IRQ_NUM)
+                    FGDMA0_CHANNEL5_IRQ_NUM,
+                    #endif
+                    #if defined(FGDMA0_CHANNEL6_IRQ_NUM)
+                    FGDMA0_CHANNEL6_IRQ_NUM,
+                    #endif
+                } , 
         .irq_prority = 0,
         .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,
-        .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL
+        .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,
+        .caps = FGDMA0_CAPACITY
     }
 };
 
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h
index 14e45c451e0..6ab2ffc9faf 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h
@@ -14,17 +14,21 @@
  * FilePath: fgdma_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:52
- * Description:  This files is for
+ * Description:  This file is for gdma register related defintion
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 
-#ifndef DRIVERS_FGDMA_HW_H
-#define DRIVERS_FGDMA_HW_H
+#ifndef FGDMA_HW_H
+#define FGDMA_HW_H
+
+#include "fparameters.h"
+#include "fio.h"
+#include "fkernel.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -32,10 +36,6 @@ extern "C"
 #endif
 /***************************** Include Files *********************************/
 
-#include "fparameters.h"
-#include "fio.h"
-#include "fkernel.h"
-
 /************************** Constant Definitions *****************************/
 
 /** @name Register Map
@@ -429,9 +429,13 @@ static inline void FGdmaSetChanClock(uintptr base_addr, u32 chan, boolean enable
 {
     u32 reg_val = FGDMA_READREG(base_addr, FGDMA_LP_OFFSET);
     if (enable)
-        reg_val &= ~FGDMA_CHX_LP_CTL(chan); /* 写0开启通道时钟 */
+    {
+        reg_val &= ~FGDMA_CHX_LP_CTL(chan);    /* 写0开启通道时钟 */
+    }
     else
-        reg_val |= FGDMA_CHX_LP_CTL(chan); /* 写1关断通道时钟 */
+    {
+        reg_val |= FGDMA_CHX_LP_CTL(chan);    /* 写1关断通道时钟 */
+    }
     FGDMA_WRITEREG(base_addr, FGDMA_LP_OFFSET, reg_val);
 
     return;
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_intr.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_intr.c
index 80ba4ea4d46..a00ac2d51fe 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_intr.c
@@ -14,13 +14,13 @@
  * FilePath: fgdma_intr.c
  * Date: 2022-05-16 17:01:48
  * LastEditTime: 2022-05-16 17:01:49
- * Description:  This files is for interrupt api implmentation
+ * Description:  This file is for interrupt api implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 
 /***************************** Include Files *********************************/
@@ -103,7 +103,7 @@ static void FGdmaChanIrqHandler(FGdmaChan *const chan_p)
 
 /**
  * @name: FGdmaIrqHandler
- * @msg: GDMA中断处理函数
+ * @msg: 当instance_p->config.caps 具有FGDMA_IRQ1_MASK特性时,此函数作为GDMA中断处理函数
  * @return {void} 无
  * @param {s32} vector, 中断号
  * @param {void} *args, 中断参数
@@ -113,6 +113,7 @@ void FGdmaIrqHandler(s32 vector, void *args)
     FASSERT(args);
     FGdma *const instance_p = (FGdma * const)args;
     FASSERT(FT_COMPONENT_IS_READY == instance_p->is_ready);
+    FASSERT(FGDMA_IRQ1_MASK & instance_p->config.caps);
     uintptr base_addr = instance_p->config.base_addr;
     u32 chan_id;
 
@@ -120,20 +121,58 @@ void FGdmaIrqHandler(s32 vector, void *args)
     FGDMA_INFO("status: 0x%x", status);
 
     FGdmaIrqDisable(base_addr);
-    for (chan_id = FGDMA_CHAN0_INDEX; chan_id < FGDMA_NUM_OF_CHAN; chan_id++)
+    for (chan_id = 0; chan_id < FGDMA_NUM_OF_CHAN; chan_id++)
     {
-        if (!(FGDMA_CHX_INTR_STATE(chan_id) & status))
+        if (!(FGDMA_CHX_INTR_STATE(chan_id) & status)) 
+        {
             continue;
+        }
 
         /* channel interrupt happens */
         FASSERT_MSG((NULL != instance_p->chans[chan_id]), "invalid chan interrupt event !!!");
         FGdmaChanIrqHandler(instance_p->chans[chan_id]);
     }
     FGdmaIrqEnable(base_addr);
+    status = FGdmaReadStatus(base_addr);
+    FGDMA_INFO("after status: 0x%x", status);
+    return;
+}
 
+/**
+ * @name: FGdmaIrqHandlerPrivateChannel
+ * @msg: 当instance_p->config.caps 具有FGDMA_IRQ2_MASK特性时,此函数作为GDMA中断处理函数
+ * @return {void} 无
+ * @param {s32} vector, 中断号
+ * @param {void} *args, 中断参数
+ */
+void FGdmaIrqHandlerPrivateChannel(s32 vector, void *args)
+{
+    FASSERT(args);
+    FGdmaChan *gdma_chan = (FGdmaChan *)args;
+    FASSERT(gdma_chan);
+    FGdma *const instance_p = (FGdma *const)gdma_chan->gdma;
+    FASSERT(FT_COMPONENT_IS_READY == instance_p->is_ready);
+    FASSERT(FGDMA_IRQ2_MASK & instance_p->config.caps);
+    uintptr base_addr = instance_p->config.base_addr;
+    u32 chan_id;
+    FGDMA_INFO("FGdmaIrqHandlerPrivateChannel is here %d \r\n",vector);
+    chan_id = gdma_chan->config.chan_id ;
+    FASSERT(chan_id <= FGDMA_NUM_OF_CHAN);
+    u32 status = FGdmaReadStatus(base_addr);
+    FGDMA_INFO("status: 0x%x", status);
+    if(!(FGDMA_CHX_INTR_STATE(chan_id) & status))
+    {
+        FGDMA_WARN("The interrupt state does not match the interrupt chan_id ,chan_id is %d, interrupt state is 0x%x ",chan_id,status);
+    }
+    
+    FASSERT_MSG((NULL != instance_p->chans[chan_id]), "invalid chan interrupt event !!!");
+    FGdmaChanIrqHandler(instance_p->chans[chan_id]);
+    status = FGdmaReadStatus(base_addr);
+    FGDMA_INFO("after status: 0x%x", status);
     return;
 }
 
+
 /**
  * @name: FGdmaChanRegisterEvtHandler
  * @msg: 注册GDMA通道事件回调函数
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_selftest.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_selftest.c
index fe16b3e5257..31267c12dd1 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_selftest.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_selftest.c
@@ -14,13 +14,13 @@
  * FilePath: fgdma_selftest.c
  * Date: 2022-05-20 13:39:27
  * LastEditTime: 2022-05-20 13:39:27
- * Description:  This files is for self test implementation
+ * Description:  This file is for self test implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 /***************************** Include Files *********************************/
 #include <string.h>
@@ -60,7 +60,7 @@ void FGdmaDumpRegisterVals(uintptr base_addr, u32 max_chan)
     FGDMA_DEBUG("lp[0x%x] : 0x%x", FGDMA_LP_OFFSET, FGDMA_READREG(base_addr, FGDMA_LP_OFFSET));
     FGDMA_DEBUG("qos[0x%x] : 0x%x", FGDMA_QOS_CFG_OFFSET, FGDMA_READREG(base_addr, FGDMA_QOS_CFG_OFFSET));
 
-    for (u32 chan = FGDMA_CHAN0_INDEX; chan <= max_chan; chan++)
+    for (u32 chan = 0; chan <= max_chan; chan++)
     {
         FGDMA_DEBUG("chan-%d", chan);
         FGDMA_DEBUG("   ctrl[0x%x]: 0x%x", FGDMA_CHX_CTL_OFFSET(chan), FGDMA_READREG(base_addr, FGDMA_CHX_CTL_OFFSET(chan)));
diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_sinit.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_sinit.c
index bb315ae0c03..96be6e2a1b7 100644
--- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_sinit.c
@@ -14,13 +14,13 @@
  * FilePath: fgdma_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:15
- * Description:  This files is for gdma static init
+ * Description:  This file is for gdma static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   huanghe    2021-11-5    init commit
- * 1.1   zhugengyu  2022-5-16    modify according to tech manual.
+ * 1.0   huanghe    2021/11/5    init commit
+ * 1.1   zhugengyu  2022/5/16    modify according to tech manual.
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/Kconfig b/bsp/phytium/libraries/standalone/drivers/eth/Kconfig
index c9531733fe1..f041d277642 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/eth/Kconfig
@@ -4,11 +4,11 @@ menu "Eth Configuration"
         bool
         prompt "Use FXMAC"
         default n
-
+    
     config ENABLE_FGMAC
         bool
         prompt "Use FGMAC"
-        default n
+        default n   
 
     if  ENABLE_FGMAC
         source "$STANDALONE_DIR/drivers/eth/fgmac/Kconfig"
@@ -17,6 +17,6 @@ menu "Eth Configuration"
     if  ENABLE_FXMAC
         source "$STANDALONE_DIR/drivers/eth/fxmac/Kconfig"
     endif
-
+    
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.c
index bef00ec931b..94e15135fa3 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.c
@@ -14,17 +14,18 @@
  * FilePath: fgmac.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for gmac driver .Functions in this file are the minimum required functions
+ * for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 
 /***************************** Include Files *********************************/
 #include <string.h>
-
 #include "fio.h"
 #include "ferror_code.h"
 #include "ftypes.h"
@@ -106,35 +107,35 @@ FError FGmacCfgInitialize(FGmac *instance_p, const FGmacConfig *input_config_p)
     /* indicating device is started */
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FGMAC_WARN("device is already initialized!!!");
+        FGMAC_WARN("Device is already initialized!!!");
     }
 
     /* de-initialize device instance */
     FGmacDeInitialize(instance_p);
     instance_p->config = *input_config_p;
 
-
-    /*Phy Awaken*/
-
+    /* Phy Awaken */
     ret = FGmacPhyAwaken(instance_p);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("phy awaken failed!");
+        FGMAC_ERROR("Phy awaken failed!");
         return ret;
     }
 
 
     /* initialize the gmac controller */
-    ret = FGmacReset(instance_p); // permmit failed
+    ret = FGmacReset(instance_p);
     if (FGMAC_SUCCESS != ret)
     {
-        printf("FGmacReset failed \r\n");
+        /*permit failed*/
+        FGMAC_ERROR("Gmac reset failed.");
     }
 
-
     ret = FGmacControllerConfigure(instance_p);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* initialize the gmac dma controller */
     ret = FGmacDmaConfigure(instance_p);
@@ -200,7 +201,7 @@ static FError FGmacReset(FGmac *instance_p)
     /* recover mac address after softwate reset */
     FGmacSetMacAddr(base_addr, mac_addr);
 
-    return ret;// may return error
+    return ret;
 }
 
 /**
@@ -261,9 +262,13 @@ void FGmacControllerDuplexConfig(FGmac *instance_p, u32 duplex)
 
     /* 设置双工模式 */
     if (duplex == FGMAC_PHY_MODE_FULLDUPLEX)
+    {
         reg_val |= FGMAC_CONF_DUPLEX_MODE;
+    }
     else
+    {
         reg_val &= ~FGMAC_CONF_DUPLEX_MODE;
+    }
 
     FGMAC_WRITE_REG32(base_addr, FGMAC_CONF_OFFSET, reg_val);
 
@@ -313,15 +318,23 @@ static FError FGmacControllerConfigure(FGmac *instance_p)
 
     /* 双工模式 */
     if (instance_p->config.duplex_mode)
+    {
         reg_val |= FGMAC_CONF_DUPLEX_MODE;
+    }
     else
+    {
         reg_val &= ~FGMAC_CONF_DUPLEX_MODE;
+    }
 
     /* 使能校验和卸载IPS */
     if (FGMAC_CHECKSUM_BY_HARDWARE == instance_p->config.cheksum_mode)
+    {
         reg_val |= FGMAC_CONF_IPC;
+    }
     else
+    {
         reg_val &= ~FGMAC_CONF_IPC;
+    }
 
     /* 重发DR=1, 重发一次 */
     reg_val |= FGMAC_CONF_DISABLE_RETRY;
@@ -486,7 +499,7 @@ static FError FGmacDmaConfigure(FGmac *instance_p)
 
     if (FGMAC_SUCCESS != ret)
     {
-        printf("FGmac Flush Failed\r\n");
+        FGMAC_ERROR("Gmac flush failed.");
     }
 
     /* AXI 突发长度 BLEN 16,8,4 */
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.h b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.h
index e4dc25d5fc9..03e5fbace14 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac.h
@@ -14,16 +14,22 @@
  * FilePath: fgmac.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for gmac driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 
-#ifndef  DRIVERS_ETH_FGMAC_H
-#define  DRIVERS_ETH_FGMAC_H
+#ifndef  FGMAC_H
+#define  FGMAC_H
+
+#include "ftypes.h"
+#include "fassert.h"
+#include "ferror_code.h"
+#include "fkernel.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -32,11 +38,6 @@ extern "C"
 
 /***************************** Include Files *********************************/
 
-#include "ftypes.h"
-#include "fassert.h"
-#include "ferror_code.h"
-#include "fkernel.h"
-
 #define FGMAC_PHY_MAX_NUM                         32U
 
 /************************** Constant Definitions *****************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_dma.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_dma.c
index 019c4f659a8..e7dc4a66020 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_dma.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_dma.c
@@ -14,11 +14,12 @@
  * FilePath: fgmac_dma.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file implements dma descriptor ring related functions.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/06/04    first release
  */
 
 /***************************** Include Files *********************************/
@@ -77,7 +78,7 @@ FError FGmacSetupRxDescRing(FGmac *instance_p, volatile FGmacDmaDesc *rx_desc_tb
         if TRUE, return error because DMA register can only hold 32 bit memory address */
     if ((FGMAC_DMA_IS_64_BIT_MEMORY(desc_end)) || (FGMAC_DMA_IS_64_BIT_MEMORY(buf_end)))
     {
-        FGMAC_ERROR("invalid rx descriptor memory %p or rx dma buf memory %p",
+        FGMAC_ERROR("Invalid rx descriptor memory %p or rx dma buf memory %p",
                     desc_end, buf_end);
         return FGMAC_ERR_INVALID_DMA_MEM;
     }
@@ -140,7 +141,7 @@ FError FGmacSetupTxDescRing(FGmac *instance_p, volatile FGmacDmaDesc *tx_desc_tb
         if TRUE, return error because DMA register can only hold 32 bit memory address */
     if ((FGMAC_DMA_IS_64_BIT_MEMORY(desc_end)) || (FGMAC_DMA_IS_64_BIT_MEMORY(buf_end)))
     {
-        FGMAC_ERROR("invalid rx descriptor memory %p or rx dma buf memory %p",
+        FGMAC_ERROR("Invalid rx descriptor memory %p or rx dma buf memory %p",
                     desc_end, buf_end);
         return FGMAC_ERR_INVALID_DMA_MEM;
     }
@@ -183,7 +184,7 @@ FError FGmacStartTrans(FGmac *instance_p)
     FASSERT(instance_p);
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGMAC_ERROR("device is already initialized!!!");
+        FGMAC_ERROR("Device is already initialized!!!");
         return FGMAC_ERR_NOT_READY;
     }
 
@@ -203,7 +204,7 @@ FError FGmacStopTrans(FGmac *instance_p)
     FASSERT(instance_p);
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FGMAC_ERROR("device is already initialized!!!");
+        FGMAC_ERROR("Device is already initialized!!!");
         return FGMAC_ERR_NOT_READY;
     }
 
@@ -227,7 +228,7 @@ FError FGmacRecvFrame(FGmac *instance_p)
     u32 flag = (FGMAC_DMA_RDES0_FIRST_DESCRIPTOR | FGMAC_DMA_RDES0_LAST_DESCRIPTOR);
 
     while ((0 == (FGMAC_DMA_RDES0_OWN & cur_rx_desc->status)) &&
-            (desc_cnt < rx_ring->desc_max_num))
+           (desc_cnt < rx_ring->desc_max_num))
     {
         desc_cnt++;
 
@@ -281,7 +282,9 @@ FError FGmacSendFrame(FGmac *instance_p, u32 frame_len)
     {
         buf_cnt = frame_len / max_packet_size;
         if (frame_len % max_packet_size)
+        {
             buf_cnt++;
+        }
     }
     else
     {
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_g.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_g.c
index a72ab1b34bf..ef6eb7ce02d 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_g.c
@@ -14,11 +14,13 @@
  * FilePath: fgmac_g.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for configuration table that specifies the configuration of
+ * ethernet devices .
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 /*  - This file contains a configuration table that specifies the configuration
@@ -28,29 +30,32 @@
 
 #include "fparameters.h"
 #include "fgmac.h"
+#include "fgmac_phy.h"
 
 /************************** Constant Definitions *****************************/
 
-const FGmacConfig FGMAC_CONFIG_TBL[GMAC_INSTANCE_NUM] =
+const FGmacConfig FGMAC_CONFIG_TBL[FGMAC_NUM] =
 {
-    [GMAC_INSTANCE_0] =
+    [FGMAC0_ID] =
     {
-        .instance_id  = GMAC_INSTANCE_0,
-        .base_addr = GMAC_INSTANCE_0_BASE_ADDR,
-        .irq_num = GMAC_INSTANC_0_IRQ,
+        .instance_id  = FGMAC0_ID,
+        .base_addr = FGMAC0_BASE_ADDR,
+        .irq_num = FGMAC0_IRQ_NUM,
         .irq_prority = 0,
         .cheksum_mode = FGMAC_CHECKSUM_BY_SOFTWARE,
-        .max_packet_size = GMAC_MAX_PACKET_SIZE
+        .max_packet_size = FGMAC_MAX_PACKET_SIZE,
+        .mdc_clk_hz = FGMAC_PHY_MII_ADDR_CR_250_300MHZ,
     },
 
-    [GMAC_INSTANCE_1] =
+    [FGMAC1_ID] =
     {
-        .instance_id  = GMAC_INSTANCE_1,
-        .base_addr = GMAC_INSTANCE_1_BASE_ADDR,
-        .irq_num = GMAC_INSTANC_1_IRQ,
+        .instance_id  = FGMAC1_ID,
+        .base_addr = FGMAC1_BASE_ADDR,
+        .irq_num =  FGMAC1_IRQ_NUM,
         .irq_prority = 0,
         .cheksum_mode = FGMAC_CHECKSUM_BY_SOFTWARE,
-        .max_packet_size = GMAC_MAX_PACKET_SIZE
+        .max_packet_size = FGMAC_MAX_PACKET_SIZE,
+        .mdc_clk_hz = FGMAC_PHY_MII_ADDR_CR_250_300MHZ,
     }
 };
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.c
index b4a493a2ddd..b354f143b5f 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.c
@@ -14,20 +14,19 @@
  * FilePath: fgmac_hw.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for manipulation of hardware registers .
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 #include "fassert.h"
 #include "fdebug.h"
-
 #include "fgmac.h"
 #include "fgmac_hw.h"
 
-
 /***************************** Include Files *********************************/
 
 /************************** Constant Definitions *****************************/
@@ -110,7 +109,7 @@ FError FGmacSoftwareReset(uintptr base_addr, int timeout)
 
     if ((0 >= timeout) && (reg_val & FGMAC_DMA_BUS_SWR))
     {
-        FGMAC_ERROR("reset timeout, please check phy connection!!!");
+        FGMAC_ERROR("Reset timeout, please check phy connection!!!");
         return FGMAC_ERR_TIMEOUT;
     }
 
@@ -131,7 +130,7 @@ FError FGmacFlushTxFifo(uintptr base_addr, int timeout)
 
     if ((0 >= timeout) && (reg_val & FGMAC_DMA_OP_FTF))
     {
-        FGMAC_ERROR("flush tx fifo timeout !!!");
+        FGMAC_ERROR("Flush tx fifo timeout !!!");
         return FGMAC_ERR_TIMEOUT;
     }
 
@@ -158,7 +157,7 @@ FError FGmacPhyWaitBusBusy(uintptr base_addr, int timeout)
 
     if (0 >= timeout)
     {
-        FGMAC_ERROR("timeout when wait GMII timeout");
+        FGMAC_ERROR("Wait gmii timeout");
         return FGMAC_ERR_TIMEOUT;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.h b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.h
index d192d81f4cd..cd7ba1754f5 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_hw.h
@@ -14,16 +14,16 @@
  * FilePath: fgmac_hw.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for manipulation of hardware registers .
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
-#ifndef  DRIVERS_ETH_FGMAC_HW_H
-#define  DRIVERS_ETH_FGMAC_HW_H
-
+#ifndef  FGMAC_HW_H
+#define  FGMAC_HW_H
 
 /* - 传入模块基地址，不能复杂结构体
 - hardware interface of device || low-level driver function prototypes
@@ -37,16 +37,16 @@
 note: 本文件不能引用fooxx.h
 */
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 /***************************** Include Files *********************************/
 
 #include "fkernel.h"
 #include "fio.h"
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 /************************** Constant Definitions *****************************/
 
 /** @name Register Map
@@ -269,7 +269,7 @@ extern "C"
 #define FGMAC_DMA_BUS_SWR           BIT(0) /* 软件复位 */
 #define FGMAC_DMA_BUS_DA            BIT(1) /* 设置 8xPBL 模式 */
 #define FGMAC_DMA_BUS_DSL_MASK      GENMASK(6, 2) /* 描述符跳跃长度 */
-#define FGMAC_DMA_BUS_ATDS          BIT(7)
+#define FGMAC_DMA_BUS_ATDS          BIT(7) /* 
 #define FGMAC_DMA_BUS_PBL_MASK      GENMASK(13, 8) /* 可编程突发长度 */
 #define FGMAC_DMA_BUS_PBL(x)        ((x) << 8)
 enum
@@ -551,4 +551,4 @@ FError FGmacPhyWaitBusBusy(uintptr base_addr, int timeout);
 }
 #endif
 
-#endif
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_intr.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_intr.c
index e23aabfb44b..fc9af72db5d 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_intr.c
@@ -14,11 +14,13 @@
  * FilePath: fgmac_intr.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  Functions in this file implement general purpose interrupt processing related
+ * functionality.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_sinit.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_sinit.c
index 87822e48b0c..4fc31d41537 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/fgmac_sinit.c
@@ -14,11 +14,13 @@
  * FilePath: fgmac_sinit.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file contains lookup method by device ID when success, it returns
+ * pointer to config table to be used to initialize the device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 
@@ -39,7 +41,7 @@
 
 /************************** Variable Definitions *****************************/
 
-extern const FGmacConfig FGMAC_CONFIG_TBL[GMAC_INSTANCE_NUM];
+extern const FGmacConfig FGMAC_CONFIG_TBL[FGMAC_NUM];
 
 /************************** Function Prototypes ******************************/
 /**
@@ -55,7 +57,7 @@ const FGmacConfig *FGmacLookupConfig(u32 instance_id)
     const FGmacConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)GMAC_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FGMAC_NUM; index++)
     {
         if (FGMAC_CONFIG_TBL[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.c
index 038afa1ede8..941d7d66b8a 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.c
@@ -14,11 +14,12 @@
  * FilePath: fgmac_ar803x.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for  ar803x PHYs chip
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 
@@ -78,7 +79,9 @@ static FError FGmacAr803xDebugRegRead(FGmac *instance_p, u32 phy_address, u16 de
 
     ret = FGmacWritePhyReg(instance_p, phy_address, FGMAC_AR803X_DEBUG_ADDR, debug_reg & FGMAC_AR803X_DEBUG_DATA_MASK);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     ret = FGmacReadPhyReg(instance_p, phy_address, FGMAC_AR803X_DEBUG_DATA, reg_data_p);
     return ret;
@@ -92,7 +95,9 @@ static FError FGmacAr803xMaskReg(FGmac *instance_p, u32 phy_address, u16 reg, u3
 
     ret = FGmacReadPhyReg(instance_p, phy_address, reg, &val);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     val &= ~clear;
     val |= set;
@@ -115,14 +120,16 @@ FError FGmacAr803xDisableHibernate(FGmac *instance_p)
 
     ret = FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_DEBUG_HIB_CTRL_REG, &reg_val);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     reg_val &= ~FGMAC_AR803X_PS_HIB_EN;
     ret = FGmacWritePhyReg(instance_p, instance_p->phy_addr, FGMAC_AR803X_DEBUG_DATA, reg_val);
 
     reg_val = 0;
     FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_DEBUG_HIB_CTRL_REG, &reg_val);
-    FGMAC_INFO("debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
+    FGMAC_INFO("Debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
 
     return ret;
 }
@@ -142,7 +149,9 @@ FError FFmacAr803xRxClockDelayControl(FGmac *instance_p, u32 enable_setting)
 
     ret = FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_RX_CLOCK_CTRL_REG, &reg_val);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     if (enable_setting == FGMAC_RX_CLOCK_ENABLE)
     {
@@ -157,7 +166,7 @@ FError FFmacAr803xRxClockDelayControl(FGmac *instance_p, u32 enable_setting)
 
     reg_val = 0;
     FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_RX_CLOCK_CTRL_REG, &reg_val);
-    FGMAC_INFO("debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
+    FGMAC_INFO("Debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
 
     return ret;
 }
@@ -177,7 +186,9 @@ FError FFmacAr803xTxClockDelayControl(FGmac *instance_p, u32 enable_setting)
 
     ret = FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_TX_CLOCK_CTRL_REG, &reg_val);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     if (enable_setting == FGMAC_TX_CLOCK_ENABLE)
     {
@@ -192,7 +203,7 @@ FError FFmacAr803xTxClockDelayControl(FGmac *instance_p, u32 enable_setting)
 
     reg_val = 0;
     FGmacAr803xDebugRegRead(instance_p, instance_p->phy_addr, FGMAC_AR803X_TX_CLOCK_CTRL_REG, &reg_val);
-    FGMAC_INFO("debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
+    FGMAC_INFO("Debug reg: 0x%lx, ret: 0x%lx", reg_val, ret);
 
     return ret;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.h b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.h
index 324583dca3b..65defb514d4 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/ar803x/fgmac_ar803x.h
@@ -14,29 +14,29 @@
  * FilePath: fgmac_ar803x.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for This file is for  ar803x PHYs chip
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2021/07/13    first release
  */
 
 
-#ifndef  DRIVERS_FGMAC_PHY_AR803X_H
-#define  DRIVERS_FGMAC_PHY_AR803X_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FGMAC_AR803X_H
+#define  FGMAC_AR803X_H
 
 /***************************** Include Files *********************************/
 
 #include "ftypes.h"
 #include "fassert.h"
-
 #include "fgmac_phy.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 
 /* phy id */
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.c b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.c
index 53b0d65ada3..562544262be 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.c
@@ -14,11 +14,15 @@
  * FilePath: fgmac_phy.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:53
- * Description:  This file is for
+ * Description:  This file implements functionalities to:
+ * Detect the available PHYs connected to a MAC
+ * Negotiate speed
+ * Configure speed
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ *  1.0   huanghe    2021/07/13    first release
  */
 
 /***************************** Include Files *********************************/
@@ -28,16 +32,16 @@
 #include "ferror_code.h"
 #include "ftypes.h"
 #include "fdebug.h"
-
 #include "fparameters.h"
-
 #include "fgmac_hw.h"
 #include "fgmac_phy.h"
 #include "fgmac.h"
+#include "fsleep.h"
+#include "sdkconfig.h"
+
 #ifdef  CONFIG_FGMAC_PHY_AR803X
     #include "fgmac_ar803x.h"
 #endif
-#include "fsleep.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -84,20 +88,24 @@ static FError FGmacWaitPhyAutoNegotiationEnd(FGmac *instance_p, u32 phy_address)
         reg_val = 0;
         ret = FGmacReadPhyReg(instance_p, phy_address, FGMAC_PHY_MII_STATUS_REG, &reg_val);
         if (FGMAC_SUCCESS != ret)
+        {
             break;
+        }
         fsleep_millisec(20);
     }
     while ((FGMAC_PHY_MII_SR_AUTO_NEGOT_COMPLETE != (FGMAC_PHY_MII_SR_AUTO_NEGOT_COMPLETE & reg_val)) &&
-            (0 < --timeout));
+           (0 < --timeout));
 
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     if (0 >= timeout)
     {
-        FGMAC_ERROR("auto negotiation timeout, reg_val: %#x", reg_val);
+        FGMAC_ERROR("Auto negotiation timeout, reg_val: %#x", reg_val);
         ret = FGmacReadPhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, &reg_val);
-        FGMAC_ERROR("auto negotiation timeout, FGMAC_PHY_MII_CTRL_REG reg_val: %#x", reg_val);
+        FGMAC_ERROR("Auto negotiation timeout, FGMAC_PHY_MII_CTRL_REG reg_val: %#x", reg_val);
         ret = FGMAC_ERR_TIMEOUT;
     }
 
@@ -123,7 +131,9 @@ static FError FGmacPhyAutoNegotiation(FGmac *instance_p, u32 phy_address)
         reg_val = 0;
         ret = FGmacReadPhyReg(instance_p, phy_address, FGMAC_PHY_MII_STATUS_REG, &reg_val);
         if (FGMAC_SUCCESS != ret)
+        {
             break;
+        }
         fsleep_millisec(20);
 
     }
@@ -131,17 +141,19 @@ static FError FGmacPhyAutoNegotiation(FGmac *instance_p, u32 phy_address)
 
     if (0 >= timeout)
     {
-        FGMAC_ERROR("timeout when wait phy auto negotiation ");
+        FGMAC_ERROR("Timeout when wait phy auto negotiation.");
         return FGMAC_ERR_TIMEOUT;
     }
 
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     ret = FGmacReadPhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, &reg_val);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("auto negotiation failed");
+        FGMAC_ERROR("Auto negotiation failed.");
         return ret;
     }
 
@@ -150,13 +162,15 @@ static FError FGmacPhyAutoNegotiation(FGmac *instance_p, u32 phy_address)
     ret = FGmacWritePhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, reg_val);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("auto negotiation failed");
+        FGMAC_ERROR("Auto negotiation failed.");
         return ret;
     }
 
     ret = FGmacWaitPhyAutoNegotiationEnd(instance_p, phy_address);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     return ret;
 }
@@ -177,32 +191,38 @@ static FError FGmacPhyNoneNegotiation(FGmac *instance_p, u32 phy_address)
     /* read phy control register */
     ret  = FGmacReadPhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, &control_reg);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* 设置半双工模式 */
     if (FGMAC_PHY_MODE_FULLDUPLEX == instance_p->config.duplex_mode)
+    {
         control_reg |= FGMAC_PHY_MII_CR_DUPLEX_MODE;
+    }
     else
+    {
         control_reg &= ~(FGMAC_PHY_MII_CR_DUPLEX_MODE);
+    }
 
     /* 设置速度bit6|bit13, 10b-1000M, 01b-100M, 00b-10M */
     switch (instance_p->config.speed)
     {
-    case FGMAC_PHY_SPEED_1000:
-        control_reg |= FGMAC_PHY_MII_CR_SPEED_SEL_MSB;
-        control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_LSB);
-        break;
-    case FGMAC_PHY_SPEED_100:
-        control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_MSB);
-        control_reg |= FGMAC_PHY_MII_CR_SPEED_SEL_LSB;
-        break;
-    case FGMAC_PHY_SPEED_10:
-        control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_MSB);
-        control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_LSB);
-        break;
-    default:
-        FASSERT(0);
-        break;
+        case FGMAC_PHY_SPEED_1000:
+            control_reg |= FGMAC_PHY_MII_CR_SPEED_SEL_MSB;
+            control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_LSB);
+            break;
+        case FGMAC_PHY_SPEED_100:
+            control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_MSB);
+            control_reg |= FGMAC_PHY_MII_CR_SPEED_SEL_LSB;
+            break;
+        case FGMAC_PHY_SPEED_10:
+            control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_MSB);
+            control_reg &= ~(FGMAC_PHY_MII_CR_SPEED_SEL_LSB);
+            break;
+        default:
+            FASSERT(0);
+            break;
     }
 
     /* disable auto-negotiation */
@@ -213,7 +233,7 @@ static FError FGmacPhyNoneNegotiation(FGmac *instance_p, u32 phy_address)
     ret = FGmacWritePhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, control_reg);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("disable auto-negotiation failed");
+        FGMAC_ERROR("Disable auto negotiation failed.");
         return ret;
     }
 
@@ -273,13 +293,17 @@ FError FGmacReadPhyReg(FGmac *instance_p, u32 phy_address, u16 phy_reg, u16 *phy
 
     ret = FGmacPhyWaitBusBusy(base_addr, FGMAC_RETRY_TIMES);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     FGMAC_WRITE_REG32(base_addr, FGMAC_GMII_ADDR_OFFSET, cmd_reg_val);
 
     ret = FGmacPhyWaitBusBusy(base_addr, FGMAC_RETRY_TIMES);
     if (FGMAC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     *phy_reg_val_p = FGMAC_MII_DATA_GD_MASK & FGMAC_READ_REG32(base_addr, FGMAC_GMII_DATA_OFFSET);
     return ret;
@@ -303,7 +327,7 @@ FError FGmacPhyDetect(FGmac *instance_p)
         ret = FGmacReadPhyReg(instance_p, phy_addr, FGMAC_PHY_MII_STATUS_REG, &phy_reg);
         if (ret != FGMAC_SUCCESS)
         {
-            FGMAC_ERROR("%s,  PHY operation is busy", __func__);
+            FGMAC_ERROR("%s, phy operation is busy.", __func__);
             return ret;
         }
 
@@ -319,7 +343,7 @@ FError FGmacPhyDetect(FGmac *instance_p)
                 instance_p->phy_valid_mask |= (1 << phy_addr);
                 instance_p->phy_id1 = phy_id1_reg;
 
-                FGMAC_INFO("phy_addr: [%d], phy_valid_mask: 0x%x, phy id: [0x%08x][0x%08x], phy_reg:0x%x",
+                FGMAC_INFO("Phy_addr: [%d], phy_valid_mask: 0x%x, phy id: [0x%08x][0x%08x], phy_reg:0x%x",
                            phy_addr, instance_p->phy_valid_mask, phy_id1_reg, phy_id2_reg, phy_reg);
 
                 return ret;
@@ -333,7 +357,7 @@ FError FGmacPhyDetect(FGmac *instance_p)
 
     if (invalid_count == FGMAC_PHY_MAX_NUM)
     {
-        FGMAC_ERROR("phy detect failed, phy address is not found!");
+        FGMAC_ERROR("Phy detect failed, phy address is not found!");
         return FGMAC_ERR_PHY_IS_NOT_FOUND;
     }
 
@@ -354,7 +378,7 @@ FError FGmacPhyReset(FGmac *instance_p, u32 phy_address)
     ret = FGmacWritePhyReg(instance_p, phy_address, FGMAC_PHY_MII_CTRL_REG, FGMAC_PHY_MII_CR_RESET);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("reset phy failed");
+        FGMAC_ERROR("Reset phy failed.");
         return ret;
     }
     return FGMAC_SUCCESS;
@@ -380,23 +404,27 @@ static FError FGmacGetPhySpecialStatus(FGmac *instance_p, u32 phy_address)
 
     switch (phy_special_status & FGMAC_PHY_SPECIFIC_STATUS_SPEED_MASK)
     {
-    case FGMAC_PHY_SPECIFIC_STATUS_SPEED_1000M:
-        instance_p->config.speed = FGMAC_PHY_SPEED_1000;
-        break;
-    case FGMAC_PHY_SPECIFIC_STATUS_SPEED_100M:
-        instance_p->config.speed = FGMAC_PHY_SPEED_100;
-        break;
-    case FGMAC_PHY_SPECIFIC_STATUS_SPEED_10M:
-        instance_p->config.speed = FGMAC_PHY_SPEED_10;
-        break;
-    default:
-        break;
+        case FGMAC_PHY_SPECIFIC_STATUS_SPEED_1000M:
+            instance_p->config.speed = FGMAC_PHY_SPEED_1000;
+            break;
+        case FGMAC_PHY_SPECIFIC_STATUS_SPEED_100M:
+            instance_p->config.speed = FGMAC_PHY_SPEED_100;
+            break;
+        case FGMAC_PHY_SPECIFIC_STATUS_SPEED_10M:
+            instance_p->config.speed = FGMAC_PHY_SPEED_10;
+            break;
+        default:
+            break;
     }
 
     if (phy_special_status & FGMAC_PHY_SPECIFIC_STATUS_DUPLEX_MASK)
+    {
         instance_p->config.duplex_mode = FGMAC_PHY_MODE_FULLDUPLEX;
+    }
     else
+    {
         instance_p->config.duplex_mode = FGMAC_PHY_MODE_HALFDUPLEX;
+    }
 
     return ret;
 }
@@ -418,7 +446,7 @@ FError FGmacPhyCfgInitialize(FGmac *instance_p)
     ret = FGmacPhyDetect(instance_p);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("phy detect failed!");
+        FGMAC_ERROR("Phy detect failed!");
         return ret;
     }
 
@@ -436,7 +464,7 @@ FError FGmacPhyCfgInitialize(FGmac *instance_p)
                 ret = FGmacPhyAutoNegotiation(instance_p, phy_addr);
                 if (FGMAC_SUCCESS != ret)
                 {
-                    FGMAC_ERROR("auto negotiation phy failed");
+                    FGMAC_ERROR("Auto negotiation phy failed.");
                     return ret;
                 }
             }
@@ -446,7 +474,7 @@ FError FGmacPhyCfgInitialize(FGmac *instance_p)
                 ret = FGmacPhyNoneNegotiation(instance_p, phy_addr);
                 if (FGMAC_SUCCESS != ret)
                 {
-                    FGMAC_ERROR("negotiation phy failed");
+                    FGMAC_ERROR("Negotiation phy failed.");
                     return ret;
                 }
             }
@@ -455,7 +483,7 @@ FError FGmacPhyCfgInitialize(FGmac *instance_p)
             ret = FGmacGetPhySpecialStatus(instance_p, phy_addr);
             if (FGMAC_SUCCESS != ret)
             {
-                FGMAC_ERROR("get phy special status failed");
+                FGMAC_ERROR("Get phy special status failed.");
                 return ret;
             }
 
@@ -505,7 +533,7 @@ FError  FGmacPhyAwaken(FGmac *instance_p)
     ret = FGmacPhyDetect(instance_p);
     if (FGMAC_SUCCESS != ret)
     {
-        FGMAC_ERROR("phy detect failed!");
+        FGMAC_ERROR("Phy detect failed!");
         return ret;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.h b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.h
index 6287745cf3c..8ce0ef797f0 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fgmac/phy/fgmac_phy.h
@@ -14,16 +14,24 @@
  * FilePath: fgmac_phy.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file implements functionalities to:
+ * Detect the available PHYs connected to a MAC
+ * Negotiate speed
+ * Configure speed
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ *  1.0   huanghe    2021/07/13    first release
  */
 
+#ifndef  FGMAC_PHY_H
+#define  FGMAC_PHY_H
 
-#ifndef  DRIVERS_ETH_FGMAC_PHY_H
-#define  DRIVERS_ETH_FGMAC_PHY_H
+#include "ftypes.h"
+#include "fassert.h"
+#include "fkernel.h"
+#include "fgmac.h"
 
 #ifdef __cplusplus
 extern "C"
@@ -32,11 +40,6 @@ extern "C"
 
 /***************************** Include Files *********************************/
 
-#include "ftypes.h"
-#include "fassert.h"
-#include "fkernel.h"
-#include "fgmac.h"
-
 /************************** Constant Definitions *****************************/
 #define FGMAC_PHY_MAX_NUM                         32U
 
@@ -205,6 +208,7 @@ FError FGmacReadPhyReg(FGmac *instance_p, u32 phy_address, u16 phy_reg, u16 *phy
 FError FGmacPhyCfgDeInitialize(FGmac *instance_p);
 
 FError FGmacPhyAwaken(FGmac *instance_p);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c
index ffdca1ffbf1..4b03f2782dd 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c
@@ -14,11 +14,13 @@
  * FilePath: fxmac.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for xmac driver .Functions in this file are the minimum required functions
+ * for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac.h"
@@ -39,6 +41,43 @@
 static void FXmacReset(FXmac *instance_p);
 extern FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 index);
 
+
+static void FXmacHighSpeedConfiguration(FXmac *instance_p,u32 speed)
+{
+    u32 reg_value;
+    s32 set_speed = 0;
+    switch (speed)
+    {
+        case FXMAC_SPEED_25000:
+            set_speed = 2;
+            break;
+        case FXMAC_SPEED_10000:
+            set_speed = 4;
+            break;
+        case FXMAC_SPEED_5000:
+            set_speed = 3;
+            break;
+        case FXMAC_SPEED_2500:
+            set_speed = 2;
+            break;
+        case FXMAC_SPEED_1000:
+            set_speed = 1;
+            break;
+        default:
+            set_speed = 0;
+            break;
+    }
+    /*GEM_HSMAC(0x0050) provide rate to the external*/
+    reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
+    reg_value &= ~FXMAC_GEM_HSMACSPEED_MASK;
+    reg_value |= (set_speed) &FXMAC_GEM_HSMACSPEED_MASK;
+    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC, reg_value);
+
+    reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
+
+    FXMAC_PRINT_I("FXMAC_GEM_HSMAC is %x \r\n ", reg_value);
+}
+
 /**
  * @name: FXmacSelectClk
  * @msg:  Determine the driver clock configuration based on the media independent interface
@@ -46,10 +85,10 @@ extern FError FXmacSetTypeIdCheck(FXmac *instance_p, u32 id_check, u8 index);
  * @param {u32} speed interface speed
  * @return {*}
  */
-void FXmacSelectClk(FXmac *instance_p)
+void FXmacSelectClkOld(FXmac *instance_p)
 {
     u32 reg_value;
-    s32 set_speed = 0;
+
     u32 speed = instance_p->config.speed;
     FASSERT(instance_p != NULL);
     FASSERT((speed == FXMAC_SPEED_10) || (speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_1000) || (speed == FXMAC_SPEED_2500) || (speed == FXMAC_SPEED_10000));
@@ -64,6 +103,35 @@ void FXmacSelectClk(FXmac *instance_p)
             FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_PMA_XCVR_POWER_STATE, 0x1);
         }
     }
+    else if(instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_5GBASER)
+    {
+        if(speed == FXMAC_SPEED_5000)
+        {
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL0_LN, 0x8);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL1_LN, 0x2);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_PMA_XCVR_POWER_STATE, 0x0);
+        }
+    }
+    else if(instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_2500BASEX)
+    {
+        if(speed == FXMAC_SPEED_25000)
+        {
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL0_LN, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL1_LN, 0x2);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_PMA_XCVR_POWER_STATE, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL0, 0);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL1, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL2, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL3, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL0, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL1, 0x0);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL3_0, 0x0); /*0x1c70*/
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_TX_CLK_SEL4_0, 0x0); /*0x1c74*/
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL3_0, 0x0); /*0x1c78*/
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL4_0, 0x0); /*0x1c7c*/
+        }
+    }
     else if (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
     {
         FXMAC_PRINT_I("FXMAC_PHY_INTERFACE_MODE_SGMII init");
@@ -174,39 +242,39 @@ void FXmacSelectClk(FXmac *instance_p)
         FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_RX_CLK_SEL5, 0x1); /*0x1c48*/
     }
 
+    FXmacHighSpeedConfiguration(instance_p,speed);
+}
+
+void FXmacSelectClk(FXmac *instance_p)
+{
+    u32 reg_value;
 
-    switch (speed)
+    u32 speed = instance_p->config.speed;
+    FASSERT(instance_p != NULL);
+    FASSERT((speed == FXMAC_SPEED_10) || (speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_1000) || (speed == FXMAC_SPEED_2500) || (speed == FXMAC_SPEED_10000));
+    FXMAC_PRINT_I("************* FXmacSelectClk *************** ");
+    if (instance_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
     {
-    case FXMAC_SPEED_25000:
-        set_speed = 2;
-        break;
-    case FXMAC_SPEED_10000:
-        set_speed = 4;
-        break;
-    case FXMAC_SPEED_5000:
-        set_speed = 3;
-        break;
-    case FXMAC_SPEED_2500:
-        set_speed = 2;
-        break;
-    case FXMAC_SPEED_1000:
-        set_speed = 1;
-        break;
-    default:
-        set_speed = 0;
-        break;
+        FXMAC_PRINT_I("FXMAC_PHY_INTERFACE_MODE_SGMII init");
+        if ((speed == FXMAC_SPEED_100) || (speed == FXMAC_SPEED_10))
+        {
+            FXMAC_PRINT_I("speed IS %d \r\n",speed);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_DIV_SEL1_LN, 0x1);
+            FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_SRC_SEL_LN, 0x1);
+        }
     }
-    /*GEM_HSMAC(0x0050) provide rate to the external*/
-    reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
-    reg_value &= ~FXMAC_GEM_HSMACSPEED_MASK;
-    reg_value |= (set_speed) &FXMAC_GEM_HSMACSPEED_MASK;
-    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC, reg_value);
 
-    reg_value = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_HSMAC);
-
-    FXMAC_PRINT_I("FXMAC_GEM_HSMAC is %x \r\n ", reg_value);
+    if(speed == FXMAC_SPEED_10000)
+    {
+        FXMAC_PRINT_I("FXMAC_SPEED_10000 is not set high speed\r\n");
+    }
+    else
+    {
+        FXmacHighSpeedConfiguration(instance_p,speed);
+    }
 }
 
+
 /**
  * Start the Ethernet controller as follows:
  *   - Enable transmitter if FXMAC_TRANSMIT_ENABLE_OPTION is set
@@ -403,6 +471,20 @@ static u32 FXmacClkDivGet(FXmac *instance_p)
     }
 }
 
+static u32 FXmacConfigureCaps(FXmac *instance_p)
+{
+    u32 read_regs = 0;
+    FXmacConfig *config_p;
+    instance_p->caps = 0;
+    config_p = &instance_p->config;
+    read_regs = FXMAC_READREG32(config_p->base_address, FXMAC_DESIGNCFG_DEBUG1_OFFSET);
+    if((read_regs&FXMAC_DESIGNCFG_DEBUG1_BUS_IRQCOR_MASK) == 0)
+    {
+        instance_p->caps |= FXMAC_CAPS_ISR_CLEAR_ON_WRITE;
+        FXMAC_PRINT_I("Has FXMAC_CAPS_ISR_CLEAR_ON_WRITE feature");
+    }
+}
+
 static u32 FXmacDmaWidth(FXmac *instance_p)
 {
     u32 read_regs = 0;
@@ -418,15 +500,15 @@ static u32 FXmacDmaWidth(FXmac *instance_p)
 
     switch ((read_regs & FXMAC_DESIGNCFG_DEBUG1_BUS_WIDTH_MASK) >> 25)
     {
-    case 4:
-        FXMAC_PRINT_I("bus width is 128");
-        return FXMAC_NWCFG_BUS_WIDTH_128_MASK;
-    case 2:
-        FXMAC_PRINT_I("bus width is 64");
-        return FXMAC_NWCFG_BUS_WIDTH_64_MASK;
-    default:
-        FXMAC_PRINT_I("bus width is 32");
-        return FXMAC_NWCFG_BUS_WIDTH_32_MASK;
+        case 4:
+            FXMAC_PRINT_I("bus width is 128");
+            return FXMAC_NWCFG_BUS_WIDTH_128_MASK;
+        case 2:
+            FXMAC_PRINT_I("bus width is 64");
+            return FXMAC_NWCFG_BUS_WIDTH_64_MASK;
+        default:
+            FXMAC_PRINT_I("bus width is 32");
+            return FXMAC_NWCFG_BUS_WIDTH_32_MASK;
     }
 }
 
@@ -546,9 +628,9 @@ static void FXmacReset(FXmac *instance_p)
     FXMAC_WRITEREG32(instance_p->config.base_address,
                      FXMAC_NWCTRL_OFFSET,
                      ((FXMAC_NWCTRL_STATCLR_MASK) & (u32)(~FXMAC_NWCTRL_LOOPEN_MASK)) | FXMAC_NWCTRL_MDEN_MASK);
-
+    FXmacConfigureCaps(instance_p);
     write_reg = FXmacClkDivGet(instance_p); /* mdio clock division */
-    write_reg |= FXmacDmaWidth(instance_p); /* 位宽 */
+    write_reg |= FXmacDmaWidth(instance_p); /* DMA位宽 */
 
     FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_NWCFG_OFFSET, write_reg);
 
@@ -582,7 +664,7 @@ static void FXmacReset(FXmac *instance_p)
 
     /* clear all counters */
     for (i = 0U; i < (u8)((FXMAC_LAST_OFFSET - FXMAC_OCTTXL_OFFSET) / 4U);
-            i++)
+         i++)
     {
         (void)FXMAC_READREG32(instance_p->config.base_address,
                               FXMAC_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4)));
@@ -609,7 +691,7 @@ void FXmacInitInterface(FXmac *instance_p)
     FXmacConfig *config_p;
     config_p = &instance_p->config;
 
-    if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_XGMII)
+    if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_XGMII )
     {
         config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
         config &= ~FXMAC_NWCFG_PCSSEL_MASK;
@@ -621,29 +703,37 @@ void FXmacInitInterface(FXmac *instance_p)
 
         config_p->duplex = 1;
     }
-    else if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_USXGMII)
+    else if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_USXGMII || config_p->interface == FXMAC_PHY_INTERFACE_MODE_5GBASER)
     {
+        FXMAC_PRINT_I("usx interface is %d",config_p->interface);
+        /*  network_config */
+        config_p->duplex = 1;
         config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
         config |= FXMAC_NWCFG_PCSSEL_MASK;
+        config &= ~FXMAC_NWCFG_100_MASK;
+        config &= ~FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK;
+        if (config_p->duplex == 1)
+        {
+            FXMAC_PRINT_I("is duplex");
+            config |= FXMAC_NWCFG_FDEN_MASK;
+        }
+    
         FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, config);
 
+        /* network_control */
         control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
         control |= FXMAC_NWCTRL_ENABLE_HS_MAC_MASK; /* Use high speed MAC */
         FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, control);
-
-        control = FXMAC_READREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET);
-        control &= ~(FXMAC_GEM_USX_TX_SCR_BYPASS | FXMAC_GEM_USX_RX_SCR_BYPASS);
-        control |= FXMAC_GEM_USX_RX_SYNC_RESET;
-        FXMAC_WRITEREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET, control);
-
+        
+        
+        /* High speed PCS control register */
         control = FXMAC_READREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET);
-        control &= ~FXMAC_GEM_USX_RX_SYNC_RESET;
-        control |= FXMAC_GEM_USX_TX_DATAPATH_EN;
-        control |= FXMAC_GEM_USX_SIGNAL_OK;
-
+        
         if (config_p->speed == FXMAC_SPEED_10000)
         {
+            FXMAC_PRINT_I("is 10G");
             control |= FXMAC_GEM_USX_HS_MAC_SPEED_10G;
+            control |= FXMAC_GEM_USX_SERDES_RATE_10G;
         }
         else if (config_p->speed == FXMAC_SPEED_25000)
         {
@@ -657,16 +747,70 @@ void FXmacInitInterface(FXmac *instance_p)
         {
             control |= FXMAC_GEM_USX_HS_MAC_SPEED_100M;
         }
+        else if(config_p->speed == FXMAC_SPEED_5000)
+        {
+            control |= FXMAC_GEM_USX_HS_MAC_SPEED_5G;
+            control |= FXMAC_GEM_USX_SERDES_RATE_5G;
+        }
+        
+        control &= ~(FXMAC_GEM_USX_TX_SCR_BYPASS | FXMAC_GEM_USX_RX_SCR_BYPASS);
+        control |= FXMAC_GEM_USX_RX_SYNC_RESET;
+        FXMAC_WRITEREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET, control);
+
+        control = FXMAC_READREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET);
+        control &= ~FXMAC_GEM_USX_RX_SYNC_RESET;
+        control |= FXMAC_GEM_USX_TX_DATAPATH_EN;
+        control |= FXMAC_GEM_USX_SIGNAL_OK;
 
         FXMAC_WRITEREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET, control);
+
+    }
+    else if(config_p->interface == FXMAC_PHY_INTERFACE_MODE_2500BASEX)
+    {
+        /*  network_config */
         config_p->duplex = 1;
+        config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
+        config |= FXMAC_NWCFG_PCSSEL_MASK | FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK;
+        config &= ~FXMAC_NWCFG_100_MASK;
+        
+        if (config_p->duplex == 1)
+        {
+            config |= FXMAC_NWCFG_FDEN_MASK;
+        }
+        FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, config);
+
+        /* network_control */
+        control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
+        control &= ~FXMAC_NWCTRL_ENABLE_HS_MAC_MASK;
+        control |= FXMAC_NWCTRL_TWO_PT_FIVE_GIG_MASK; /* Use high speed MAC */
+        FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, control);
+
+        /* High speed PCS control register */
+        control = FXMAC_READREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET);
+        
+        if (config_p->speed == FXMAC_SPEED_25000)
+        {
+            control |= FXMAC_GEM_USX_HS_MAC_SPEED_2_5G;
+        }
+        
+        control &= ~(FXMAC_GEM_USX_TX_SCR_BYPASS | FXMAC_GEM_USX_RX_SCR_BYPASS);
+        control |= FXMAC_GEM_USX_RX_SYNC_RESET;
+        FXMAC_WRITEREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET, control);
+
+        control = FXMAC_READREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET);
+        control &= ~FXMAC_GEM_USX_RX_SYNC_RESET;
+        control |= FXMAC_GEM_USX_TX_DATAPATH_EN;
+        control |= FXMAC_GEM_USX_SIGNAL_OK;
+
+        FXMAC_WRITEREG32(config_p->base_address, FXMAC_GEM_USX_CONTROL_OFFSET, control);
+
     }
     else if (config_p->interface == FXMAC_PHY_INTERFACE_MODE_SGMII)
     {
         config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET);
         config |= FXMAC_NWCFG_PCSSEL_MASK | FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK;
 
-        config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK);
+        config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK|FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD);
 
         if (instance_p->moudle_id >= 2)
         {
@@ -738,11 +882,6 @@ void FXmacInitInterface(FXmac *instance_p)
             config |= FXMAC_NWCFG_1000_MASK;
         }
 
-        if (config_p->duplex)
-        {
-            config |= FXMAC_NWCFG_FDEN_MASK;
-        }
-
         FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCFG_OFFSET, config);
 
         control = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET);
@@ -751,7 +890,6 @@ void FXmacInitInterface(FXmac *instance_p)
     }
 }
 
-
 static void FXmacIrqStubHandler(void)
 {
     FASSERT_MSG(0, "Please register the interrupt callback function");
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h
index 19678d929c1..a0182db38c3 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h
@@ -14,29 +14,30 @@
  * FilePath: fxmac.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for gmac driver .Functions in this file are the minimum required functions
+ * for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef DRIVERS_ETH_F_XMAC_H
-#define DRIVERS_ETH_F_XMAC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FXMAC_H
+#define FXMAC_H
 
 #include "ftypes.h"
 #include "fassert.h"
 #include "ferror_code.h"
-
 #include "fxmac_hw.h"
 #include "fxmac_bdring.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 #define FXMAC_ERR_INVALID_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x1u)
 #define FXMAC_ERR_SG_LIST FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x2u)
 #define FXMAC_ERR_GENERAL FT_MAKE_ERRCODE(ErrModBsp, ErrBspEth, 0x4u)
@@ -159,7 +160,7 @@ typedef enum
 #define FXMAC_MAX_VLAN_FRAME_SIZE (FXMAC_MTU + FXMAC_HDR_SIZE + \
                                    FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE)
 #define FXMAC_MAX_VLAN_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + \
-                                         FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE)
+        FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE)
 
 #define FXMAC_MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE)
 
@@ -186,6 +187,10 @@ typedef enum
 #define FXMAC_SPEED_10000 10000U
 #define FXMAC_SPEED_25000 25000U
 
+/*  Capability mask bits */
+#define FXMAC_CAPS_ISR_CLEAR_ON_WRITE   0x00000001 /* irq status parameters need to be written to clear after they have been read */
+
+
 /** @name Direction identifiers
  *
  *  These are used by several functions and callbacks that need
@@ -226,6 +231,8 @@ typedef enum
     FXMAC_PHY_INTERFACE_MODE_RGMII,
     FXMAC_PHY_INTERFACE_MODE_XGMII,
     FXMAC_PHY_INTERFACE_MODE_USXGMII,
+    FXMAC_PHY_INTERFACE_MODE_5GBASER ,
+    FXMAC_PHY_INTERFACE_MODE_2500BASEX
 } FXmacPhyInterface;
 
 typedef struct
@@ -240,12 +247,13 @@ typedef struct
     u32 auto_neg; /* Enable auto-negotiation - when set active high, autonegotiation operation is enabled. */
     u32 pclk_hz;
     u32 max_queue_num; /* Number of Xmac Controller Queues  */
-    u32 tx_queue_id;   /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
-    u32 rx_queue_id;   /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
+    u32 tx_queue_id;   /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
+    u32 rx_queue_id;   /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
     u32 hotplug_irq_num;
     u32 dma_brust_length; /*  burst length */
     u32 network_default_config;
-    u32 queue_irq_num[FT_XMAC_QUEUE_MAX_NUM]; /* mac0 8个 ，其他的 4个 */
+    u32 queue_irq_num[FXMAC_QUEUE_MAX_NUM]; /* mac0 8个 ，其他的 4个 */
+    u32 caps; /*  */
 } FXmacConfig;
 
 typedef struct
@@ -261,6 +269,7 @@ typedef struct
     u32 is_started;
     u32 link_status; /* indicates link status ,FXMAC_LINKUP is link up ,FXMAC_LINKDOWN is link down,FXMAC_NEGOTIATING is need to negotiating*/
     u32 options;
+    u32 caps;   /*  Capability mask bits */
 
     FXmacQueue tx_bd_queue; /* Transmit Queue */
     FXmacQueue rx_bd_queue; /* Receive Queue */
@@ -302,6 +311,7 @@ FError FXmacSetMacAddress(FXmac *instance_p, u8 *address_ptr, u8 index);
 
 FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num);
 FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num);
+boolean FXmacUsxLinkStatus(FXmac *instance_p);
 
 void FXmacStart(FXmac *instance_p);
 void FXmacStop(FXmac *instance_p);
@@ -325,6 +335,12 @@ void FXmacIntrHandler(s32 vector, void *args);
 
 void FXmacClearHash(FXmac *instance_p);
 
+
+/* debug */
+void FXmacDebugTxPrint(FXmac *instance_p);
+void FXmacDebugRxPrint(FXmac *instance_p);
+void FXmacDebugUsxPrint(FXmac *instance_p);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h
index bbe982340d1..203e39e1b56 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h
@@ -14,24 +14,25 @@
  * FilePath: fxmac_bd.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for buffer descriptor (BD) management API.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef DRIVERS_ETH_F_XMAC_BD_H
-#define DRIVERS_ETH_F_XMAC_BD_H
+#ifndef FXMAC_BD_H
+#define FXMAC_BD_H
+
+#include "ftypes.h"
+#include "string.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "string.h"
-
 
 /**
  * @name: FXMAC_BD_READ
@@ -64,7 +65,7 @@ extern "C"
  */
 #define FXMAC_BD_SET_STATUS(bd_ptr, data)           \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET, \
-                 FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | (data))
+                   FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | (data))
 
 
 /**
@@ -75,8 +76,8 @@ extern "C"
 #define FXMAC_BD_IS_RX_NEW(bd_ptr)                      \
     ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
       FXMAC_RXBUF_NEW_MASK) != 0U                   \
-         ? TRUE                                     \
-         : FALSE)
+     ? TRUE                                     \
+     : FALSE)
 
 
 /**
@@ -88,8 +89,8 @@ extern "C"
 #define FXMAC_BD_IS_TX_WRAP(bd_ptr)                     \
     ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
       FXMAC_TXBUF_WRAP_MASK) != 0U                        \
-         ? TRUE                                           \
-         : FALSE)
+     ? TRUE                                           \
+     : FALSE)
 
 
 /**
@@ -101,8 +102,8 @@ extern "C"
 #define FXMAC_BD_IS_RX_WRAP(bd_ptr)                     \
     ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
       FXMAC_RXBUF_WRAP_MASK) != 0U                        \
-         ? TRUE                                           \
-         : FALSE)
+     ? TRUE                                           \
+     : FALSE)
 
 
 
@@ -115,9 +116,9 @@ extern "C"
 #if defined(__aarch64__) || defined(__arch64__)
 #define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr)           \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET,    \
-                 (u32)((addr)&ULONG64_LO_MASK));          \
+                   (u32)((addr)&ULONG64_LO_MASK));          \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET, \
-                 (u32)(((addr)&ULONG64_HI_MASK) >> 32U));
+                   (u32)(((addr)&ULONG64_HI_MASK) >> 32U));
 #else
 #define FXMAC_BD_SET_ADDRESS_TX(bd_ptr, addr) \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET, (u32)(addr))
@@ -134,17 +135,17 @@ extern "C"
 #ifdef __aarch64__
 #define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr)                        \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET,                 \
-                 ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
-                   ~FXMAC_RXBUF_ADD_MASK) |                            \
-                  ((u32)((addr)&ULONG64_LO_MASK))));                   \
+                   ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+                     ~FXMAC_RXBUF_ADD_MASK) |                            \
+                    ((u32)((addr)&ULONG64_LO_MASK))));                   \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_HI_OFFSET,              \
-                 (u32)(((addr)&ULONG64_HI_MASK) >> 32U));
+                   (u32)(((addr)&ULONG64_HI_MASK) >> 32U));
 #else
 #define FXMAC_BD_SET_ADDRESS_RX(bd_ptr, addr)                        \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_ADDR_OFFSET,                 \
-                 ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
-                   ~FXMAC_RXBUF_ADD_MASK) |                            \
-                  (u32)(addr)))
+                   ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_ADDR_OFFSET) & \
+                     ~FXMAC_RXBUF_ADD_MASK) |                            \
+                    (u32)(addr)))
 #endif
 
 
@@ -158,9 +159,9 @@ extern "C"
  */
 #define FXMAC_BD_SET_LENGTH(bd_ptr, len_bytes)                      \
     FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET,                 \
-                 ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
-                   ~FXMAC_TXBUF_LEN_MASK) |                            \
-                  (len_bytes)))
+                   ((FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+                     ~FXMAC_TXBUF_LEN_MASK) |                            \
+                    (len_bytes)))
 
 
 /**
@@ -174,6 +175,10 @@ extern "C"
     (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
      FXMAC_RXBUF_LEN_MASK)
 
+#define FXMAC_BD_GET_TX_LENGTH(bd_ptr)                   \
+    (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+     FXMAC_TXBUF_LEN_MASK)
+
 
 /**
  * @name: FXMAC_GET_RX_FRAME_SIZE
@@ -190,7 +195,7 @@ extern "C"
 
 #define FXMAC_GET_RX_FRAME_SIZE(instance_p, bd_ptr)                   \
     (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) &            \
-    0x00003FFFU)
+     0x00003FFFU)
 
 
 
@@ -204,13 +209,13 @@ extern "C"
  */
 #define FXMAC_BD_CLEAR_TX_USED(bd_ptr)                              \
     (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET,               \
-                  FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
-                      (~FXMAC_TXBUF_USED_MASK)))
+                    FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+                    (~FXMAC_TXBUF_USED_MASK)))
 
 #define FXMAC_BD_SET_CRC(bd_ptr)                                   \
     (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET,               \
-                  FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
-                      (~FXMAC_TXBUF_NOCRC_MASK)))
+                    FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \
+                    (~FXMAC_TXBUF_NOCRC_MASK)))
 
 
 /**
@@ -222,8 +227,8 @@ extern "C"
  */
 #define FXMAC_BD_SET_LAST(bd_ptr)                                  \
     (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET,               \
-                  FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | \
-                      FXMAC_TXBUF_LAST_MASK))
+                    FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) | \
+                    FXMAC_TXBUF_LAST_MASK))
 
 
 /**
@@ -235,8 +240,8 @@ extern "C"
  */
 #define FXMAC_BD_CLEAR_LAST(bd_ptr)                                 \
     (FXMAC_BD_WRITE((bd_ptr), FXMAC_BD_STAT_OFFSET,             \
-    FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) &             \
-    ~FXMAC_TXBUF_LAST_MASK))
+                    FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) &             \
+                    ~FXMAC_TXBUF_LAST_MASK))
 
 /**
  * @name: FXMAC_BD_CLEAR
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.c
index 5459203c18e..213ba90b23c 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.c
@@ -14,11 +14,12 @@
  * FilePath: fxmac_bdring.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file implements buffer descriptor ring related functions.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac_hw.h"
@@ -49,13 +50,13 @@ static void FXmacBdSetTxWrap(uintptr bdptr);
 #define FXMAC_RING_SEEKAHEAD(ring_ptr, bdptr, num_bd)                               \
     {                                                                               \
         uintptr addr = (uintptr)(void *)(bdptr);                                    \
-                                                                                    \
+        \
         addr += ((ring_ptr)->separation * (num_bd));                                \
         if ((addr > (ring_ptr)->high_bd_addr) || ((uintptr)(void *)(bdptr) > addr)) \
         {                                                                           \
             addr -= (ring_ptr)->length;                                             \
         }                                                                           \
-                                                                                    \
+        \
         (bdptr) = (FXmacBd *)(void *)addr;                                          \
     }
 
@@ -72,13 +73,13 @@ static void FXmacBdSetTxWrap(uintptr bdptr);
 #define FXMAC_RING_SEEKBACK(ring_ptr, bdptr, num_bd)                                \
     {                                                                               \
         uintptr addr = (uintptr)(void *)(bdptr);                                    \
-                                                                                    \
+        \
         addr -= ((ring_ptr)->separation * (num_bd));                                \
         if ((addr < (ring_ptr)->base_bd_addr) || ((uintptr)(void *)(bdptr) < addr)) \
         {                                                                           \
             addr += (ring_ptr)->length;                                             \
         }                                                                           \
-                                                                                    \
+        \
         (bdptr) = (FXmacBd *)(void *)addr;                                          \
     }
 
@@ -700,15 +701,7 @@ u32 FXmacBdRingFromHwRx(FXmacBdRing *ring_ptr, u32 bd_limit,
 
             /* Move on to next BD in work group */
             cur_bd_ptr = FXMAC_BD_RING_NEXT(ring_ptr, cur_bd_ptr);
-            // if((bd_str & FXMAC_RXBUF_EOF_MASK) != 0x00000000U)
-            // {
-            //     if(bd_str &FXMAC_RXBUF_FCS_STATUS_MASK)
-            //     {
-            //         f_printk("********** error fcs data is appear ************* \r\n");
-            //         FtDumpHexWord(FXMAC_BD_READ(cur_bd_ptr,0) &(0xfffffff8),bd_str&FXMAC_RXBUF_LEN_MASK);
-            //         f_printk("********** end ************* \r\n");
-            //     }
-            // }
+
         }
 
         /* Subtract off any partial packet BDs found */
@@ -860,7 +853,7 @@ FError FXmacBdRingCheck(FXmacBdRing *ring_ptr, u8 direction)
 
     /* Verify internal counters add up */
     if ((ring_ptr->hw_cnt + ring_ptr->pre_cnt + ring_ptr->free_cnt +
-            ring_ptr->post_cnt) != ring_ptr->all_cnt)
+         ring_ptr->post_cnt) != ring_ptr->all_cnt)
     {
         return (FError)(FXMAC_ERR_SG_LIST);
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.h
index b03269e3f49..0f113e6ef0c 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bdring.h
@@ -14,24 +14,26 @@
  * FilePath: fxmac_bdring.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file ontains DMA channel related structure and constant definition
+ * as well as function prototypes.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef DRIVERS_ETH_F_XMAC_BDRING_H
-#define DRIVERS_ETH_F_XMAC_BDRING_H
+#ifndef FXMAC_BDRING_H
+#define FXMAC_BDRING_H
+
+#include "fxmac_bd.h"
+#include "ftypes.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "fxmac_bd.h"
-#include "ftypes.h"
-
 /**************************** Type Definitions *******************************/
 
 /** This is an internal structure used to maintain the DMA list */
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_debug.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_debug.c
new file mode 100644
index 00000000000..d7711c30b83
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_debug.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fxmac_debug.c
+ * Date: 2023-01-04 15:33:03
+ * LastEditTime: 2023-01-04 15:33:04
+ * Description:  This file is for user to debug xmac information.
+ * 
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
+ */
+
+#include "fxmac_hw.h"
+#include "fxmac.h"
+#include "fio.h"
+#include "fdebug.h"
+
+#define FXMAC_DEBUG_TAG "FXMAC_DEBUG"
+#define FXMAC_ERROR(format, ...) FT_DEBUG_PRINT_E(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_INFO(format, ...) FT_DEBUG_PRINT_I(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FXMAC_WARN(format, ...) FT_DEBUG_PRINT_W(FXMAC_DEBUG_TAG, format, ##__VA_ARGS__)
+
+
+void FXmacDebugTxPrint(FXmac *instance_p)
+{
+    FXmacConfig *config_p;
+    config_p = &instance_p->config;
+
+    FXMAC_INFO("octets_txed_bottom is 0x%x",FtIn32(config_p->base_address+FXMAC_OCTTXL_OFFSET));
+    FXMAC_INFO("octets_txed_top is 0x%x",FtIn32(config_p->base_address+FXMAC_OCTTXH_OFFSET));
+    FXMAC_INFO("frames_txed_ok is 0x%x",FtIn32(config_p->base_address+FXMAC_TXCNT_OFFSET));
+    FXMAC_INFO("broadcast_txed is 0x%x",FtIn32(config_p->base_address+FXMAC_TXBCCNT_OFFSET));
+    FXMAC_INFO("multicast_txed is 0x%x",FtIn32(config_p->base_address+FXMAC_TXMCCNT_OFFSET));
+    FXMAC_INFO("pause_frames_txed is 0x%x",FtIn32(config_p->base_address+FXMAC_TXPAUSECNT_OFFSET));
+    FXMAC_INFO("frames_txed_64 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX64CNT_OFFSET));
+    FXMAC_INFO("frames_txed_65 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX65CNT_OFFSET));
+    FXMAC_INFO("frames_txed_128 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX128CNT_OFFSET));
+    FXMAC_INFO("frames_txed_256 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX256CNT_OFFSET));
+    FXMAC_INFO("frames_txed_512 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX512CNT_OFFSET));
+    FXMAC_INFO("frames_txed_1024 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX1024CNT_OFFSET));
+    FXMAC_INFO("frames_txed_1519 is 0x%x",FtIn32(config_p->base_address+FXMAC_TX1519CNT_OFFSET));
+    FXMAC_INFO("tx_underruns is 0x%x",FtIn32(config_p->base_address+FXMAC_TXURUNCNT_OFFSET));
+    FXMAC_INFO("single_collisions is 0x%x",FtIn32(config_p->base_address+FXMAC_SNGLCOLLCNT_OFFSET));
+    FXMAC_INFO("multiple_collisions is 0x%x",FtIn32(config_p->base_address+FXMAC_MULTICOLLCNT_OFFSET));
+    FXMAC_INFO("excessive_collisions is 0x%x",FtIn32(config_p->base_address+FXMAC_EXCESSCOLLCNT_OFFSET));
+    FXMAC_INFO("late_collisions is 0x%x",FtIn32(config_p->base_address+FXMAC_LATECOLLCNT_OFFSET));
+    FXMAC_INFO("deferred_frames is 0x%x",FtIn32(config_p->base_address+FXMAC_TXDEFERCNT_OFFSET));
+    FXMAC_INFO("crs_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_TXCSENSECNT_OFFSET));
+}
+
+
+void FXmacDebugRxPrint(FXmac *instance_p)
+{
+    FXmacConfig *config_p;
+    config_p = &instance_p->config;
+
+    FXMAC_INFO("octets_rxed_bottom is 0x%x",FtIn32(config_p->base_address+FXMAC_OCTRXL_OFFSET));
+    FXMAC_INFO("octets_rxed_top is 0x%x",FtIn32(config_p->base_address+FXMAC_OCTRXH_OFFSET));
+    FXMAC_INFO("frames_rxed_ok is 0x%x",FtIn32(config_p->base_address+FXMAC_RXCNT_OFFSET));
+    FXMAC_INFO("broadcast_rxed is 0x%x",FtIn32(config_p->base_address+FXMAC_RXBROADCNT_OFFSET));
+    FXMAC_INFO("multicast_Rxed is 0x%x",FtIn32(config_p->base_address+FXMAC_RXMULTICNT_OFFSET));
+    FXMAC_INFO("pause_frames_rxed is 0x%x",FtIn32(config_p->base_address+FXMAC_RXPAUSECNT_OFFSET));
+    FXMAC_INFO("frames_rxed_64 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX64CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_65 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX65CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_128 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX128CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_256 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX256CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_512 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX512CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_1024 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX1024CNT_OFFSET));
+    FXMAC_INFO("frames_rxed_1519 is 0x%x",FtIn32(config_p->base_address+FXMAC_RX1519CNT_OFFSET));
+    FXMAC_INFO("undersize_frames is 0x%x",FtIn32(config_p->base_address+FXMAC_RXUNDRCNT_OFFSET));
+    FXMAC_INFO("excessive_rx_length is 0x%x",FtIn32(config_p->base_address+FXMAC_RXOVRCNT_OFFSET));
+    FXMAC_INFO("rx_jabbers is 0x%x",FtIn32(config_p->base_address+FXMAC_RXJABCNT_OFFSET));
+    FXMAC_INFO("fcs_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXFCSCNT_OFFSET));
+    FXMAC_INFO("rx_length_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXLENGTHCNT_OFFSET));
+    FXMAC_INFO("rx_symbol_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXSYMBCNT_OFFSET));
+    FXMAC_INFO("alignment_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXALIGNCNT_OFFSET));
+    FXMAC_INFO("rx_resource_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXRESERRCNT_OFFSET));
+    FXMAC_INFO("rx_overruns is 0x%x",FtIn32(config_p->base_address+FXMAC_RXORCNT_OFFSET));
+    FXMAC_INFO("rx_ip_ck_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXIPCCNT_OFFSET));
+    FXMAC_INFO("rx_tcp_ck_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXTCPCCNT_OFFSET));
+    FXMAC_INFO("rx_udp_ck_errors is 0x%x",FtIn32(config_p->base_address+FXMAC_RXUDPCCNT_OFFSET));
+}
+
+
+void FXmacDebugUsxPrint(FXmac *instance_p)
+{
+    FXmacConfig *config_p;
+    config_p = &instance_p->config;
+
+    FXMAC_INFO("USXGMII control register is 0x%x",FtIn32(config_p->base_address+FXMAC_GEM_USX_CONTROL_OFFSET));
+    FXMAC_INFO("USXGMII Status Register is 0x%x",FtIn32(config_p->base_address+FXMAC_GEM_USX_STATUS_OFFSET));
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_g.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_g.c
index b8f1b053f34..dfe1b9ce267 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_g.c
@@ -14,11 +14,12 @@
  * FilePath: fxmac_g.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file provide a template for user to define their own hardware settings.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac.h"
@@ -36,117 +37,132 @@
  * The configuration table for emacps device
  */
 
-const FXmacConfig fxmac_cfg_tbl[FT_XMAC_NUM] =
+const FXmacConfig fxmac_cfg_tbl[FXMAC_NUM] =
 {
-    [FT_XMAC0_ID] =
+    [FXMAC0_ID] =
     {
-        .instance_id = (u32)FT_XMAC0_ID,               /* Device ID */
-        .base_address = (uintptr)FT_XMAC0_BASEADDRESS, /* Device base address */
-        .extral_mode_base = FT_XMAC0_MODE_SEL_BASEADDRESS,
-        .extral_loopback_base = FT_XMAC0_LOOPBACK_SEL_BASEADDRESS,
+        .instance_id = (u32)FXMAC0_ID,               /* Device ID */
+        .base_address = (uintptr)FXMAC0_BASE_ADDR, /* Device base address */
+#if defined(FXMAC0_MODE_SEL_BASE_ADDR)
+        .extral_mode_base = FXMAC0_MODE_SEL_BASE_ADDR,
+#endif
+#if defined(FXMAC0_LOOPBACK_SEL_BASE_ADDR)
+        .extral_loopback_base = FXMAC0_LOOPBACK_SEL_BASE_ADDR,
+#endif
         .interface = FXMAC_PHY_INTERFACE_MODE_SGMII,
         .speed = 1000,
         .duplex = 1,
         .auto_neg = 1,
-        .pclk_hz = FT_XMAC0_PCLK,
+        .pclk_hz = FXMAC0_PCLK,
         .max_queue_num = 16,
         .tx_queue_id = 0,
         .rx_queue_id = 0,
-        .hotplug_irq_num = FT_XMAC0_HOTPLUG_IRQ_NUM,
+#ifdef FXMAC0_HOTPLUG_IRQ_NUM
+        .hotplug_irq_num = FXMAC0_HOTPLUG_IRQ_NUM,
+#endif
         .dma_brust_length = 16,
         .network_default_config = FXMAC_DEFAULT_OPTIONS,
         .queue_irq_num =
         {
-            FT_XMAC0_QUEUE0_IRQ_NUM,
-            FT_XMAC0_QUEUE1_IRQ_NUM,
-            FT_XMAC0_QUEUE2_IRQ_NUM,
-            FT_XMAC0_QUEUE3_IRQ_NUM,
-            FT_XMAC0_QUEUE4_IRQ_NUM,
-            FT_XMAC0_QUEUE5_IRQ_NUM,
-            FT_XMAC0_QUEUE6_IRQ_NUM,
-            FT_XMAC0_QUEUE7_IRQ_NUM
+            FXMAC0_QUEUE0_IRQ_NUM,
+            FXMAC0_QUEUE1_IRQ_NUM,
+            FXMAC0_QUEUE2_IRQ_NUM,
+            FXMAC0_QUEUE3_IRQ_NUM,
+#if defined(FXMAC0_QUEUE4_IRQ_NUM)
+            FXMAC0_QUEUE4_IRQ_NUM,
+#endif
+#if defined(FXMAC0_QUEUE5_IRQ_NUM)
+            FXMAC0_QUEUE5_IRQ_NUM,
+#endif
+#if defined(FXMAC0_QUEUE6_IRQ_NUM)
+            FXMAC0_QUEUE6_IRQ_NUM,
+#endif
+#if defined(FXMAC0_QUEUE7_IRQ_NUM)
+            FXMAC0_QUEUE7_IRQ_NUM
+#endif
         }
     },
-#ifdef FT_XMAC1_ID
-    [FT_XMAC1_ID] =
+#ifdef FXMAC1_ID
+    [FXMAC1_ID] =
     {
-        .instance_id = (u32)FT_XMAC1_ID,               /* Device ID */
-        .base_address = (uintptr)FT_XMAC1_BASEADDRESS, /* Device base address */
-        .extral_mode_base = FT_XMAC1_MODE_SEL_BASEADDRESS,
-        .extral_loopback_base = FT_XMAC1_LOOPBACK_SEL_BASEADDRESS,
+        .instance_id = (u32)FXMAC1_ID,               /* Device ID */
+        .base_address = (uintptr)FXMAC1_BASE_ADDR, /* Device base address */
+        .extral_mode_base = FXMAC1_MODE_SEL_BASE_ADDR,
+        .extral_loopback_base = FXMAC1_LOOPBACK_SEL_BASE_ADDR,
         .interface = FXMAC_PHY_INTERFACE_MODE_SGMII,
         .speed = 1000,
         .duplex = 1,
         .auto_neg = 1,
-        .pclk_hz = FT_XMAC1_PCLK,
+        .pclk_hz = FXMAC1_PCLK,
         .max_queue_num = 4,
         .tx_queue_id = 0,
         .rx_queue_id = 0,
-        .hotplug_irq_num = FT_XMAC1_HOTPLUG_IRQ_NUM,
+#if defined(FXMAC1_HOTPLUG_IRQ_NUM)
+        .hotplug_irq_num = FXMAC1_HOTPLUG_IRQ_NUM,
+#endif
         .dma_brust_length = 16,
         .network_default_config = FXMAC_DEFAULT_OPTIONS,
         .queue_irq_num =
         {
-            FT_XMAC1_QUEUE0_IRQ_NUM,
-            FT_XMAC1_QUEUE1_IRQ_NUM,
-            FT_XMAC1_QUEUE2_IRQ_NUM,
-            FT_XMAC1_QUEUE3_IRQ_NUM
+            FXMAC1_QUEUE0_IRQ_NUM,
+            FXMAC1_QUEUE1_IRQ_NUM,
+            FXMAC1_QUEUE2_IRQ_NUM,
+            FXMAC1_QUEUE3_IRQ_NUM
         }
     },
 #endif
-#ifdef FT_XMAC2_ID
-    [FT_XMAC2_ID] =
+#ifdef FXMAC2_ID
+    [FXMAC2_ID] =
     {
-        .instance_id = (u32)FT_XMAC2_ID,               /* Device ID */
-        .base_address = (uintptr)FT_XMAC2_BASEADDRESS, /* Device base address */
-        .extral_mode_base = FT_XMAC2_MODE_SEL_BASEADDRESS,
-        .extral_loopback_base = FT_XMAC2_LOOPBACK_SEL_BASEADDRESS,
+        .instance_id = (u32)FXMAC2_ID,               /* Device ID */
+        .base_address = (uintptr)FXMAC2_BASE_ADDR, /* Device base address */
+        .extral_mode_base = FXMAC2_MODE_SEL_BASE_ADDR,
+        .extral_loopback_base = FXMAC2_LOOPBACK_SEL_BASE_ADDR,
         .interface = FXMAC_PHY_INTERFACE_MODE_RGMII,
         .speed = 1000,
         .duplex = 1,
         .auto_neg = 1,
-        .pclk_hz = FT_XMAC2_PCLK,
+        .pclk_hz = FXMAC2_PCLK,
         .max_queue_num = 4,
         .tx_queue_id = 0,
         .rx_queue_id = 0,
-        .hotplug_irq_num = FT_XMAC2_HOTPLUG_IRQ_NUM,
+        .hotplug_irq_num = FXMAC2_HOTPLUG_IRQ_NUM,
         .dma_brust_length = 16,
         .network_default_config = FXMAC_DEFAULT_OPTIONS,
         .queue_irq_num =
         {
-            FT_XMAC2_QUEUE0_IRQ_NUM,
-            FT_XMAC2_QUEUE1_IRQ_NUM,
-            FT_XMAC2_QUEUE2_IRQ_NUM,
-            FT_XMAC2_QUEUE3_IRQ_NUM
+            FXMAC2_QUEUE0_IRQ_NUM,
+            FXMAC2_QUEUE1_IRQ_NUM,
+            FXMAC2_QUEUE2_IRQ_NUM,
+            FXMAC2_QUEUE3_IRQ_NUM
         }
     },
 #endif
-#ifdef FT_XMAC3_ID
-    [FT_XMAC3_ID] =
+#ifdef FXMAC3_ID
+    [FXMAC3_ID] =
     {
-        .instance_id = (u32)FT_XMAC3_ID,               /* Device ID */
-        .base_address = (uintptr)FT_XMAC3_BASEADDRESS, /* Device base address */
-        .extral_mode_base = FT_XMAC3_MODE_SEL_BASEADDRESS,
-        .extral_loopback_base = FT_XMAC3_LOOPBACK_SEL_BASEADDRESS,
+        .instance_id = (u32)FXMAC3_ID,               /* Device ID */
+        .base_address = (uintptr)FXMAC3_BASE_ADDR, /* Device base address */
+        .extral_mode_base = FXMAC3_MODE_SEL_BASE_ADDR,
+        .extral_loopback_base = FXMAC3_LOOPBACK_SEL_BASE_ADDR,
         .interface = FXMAC_PHY_INTERFACE_MODE_RGMII,
         .speed = 1000,
         .duplex = 1,
         .auto_neg = 1,
-        .pclk_hz = FT_XMAC3_PCLK,
+        .pclk_hz = FXMAC3_PCLK,
         .max_queue_num = 4,
         .tx_queue_id = 0,
         .rx_queue_id = 0,
-        .hotplug_irq_num = FT_XMAC3_HOTPLUG_IRQ_NUM,
+        .hotplug_irq_num = FXMAC3_HOTPLUG_IRQ_NUM,
         .dma_brust_length = 16,
         .network_default_config = FXMAC_DEFAULT_OPTIONS,
         .queue_irq_num =
         {
-            FT_XMAC3_QUEUE0_IRQ_NUM,
-            FT_XMAC3_QUEUE1_IRQ_NUM,
-            FT_XMAC3_QUEUE2_IRQ_NUM,
-            FT_XMAC3_QUEUE3_IRQ_NUM
+            FXMAC3_QUEUE0_IRQ_NUM,
+            FXMAC3_QUEUE1_IRQ_NUM,
+            FXMAC3_QUEUE2_IRQ_NUM,
+            FXMAC3_QUEUE3_IRQ_NUM
         }
     }
 #endif
 };
-/** @} */
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h
index f3814bd8974..0df7a81f6b9 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h
@@ -14,32 +14,31 @@
  * FilePath: fxmac_hw.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is hardware definition file. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef BSP_DRIVERS_ETH_FMAC_HW_H
-#define BSP_DRIVERS_ETH_FMAC_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FXMAC_HW_H
+#define FXMAC_HW_H
 
 #include "fparameters.h"
 #include "fio.h"
 #include "ftypes.h"
 #include "fkernel.h"
 
-#define FXMAC_RX_BUF_SIZE 1536U /* Specify the receive buffer size in \
-                                       bytes, 64, 128, ... 10240 */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define FXMAC_RX_BUF_SIZE 1536U /* Specify the receive buffer size in bytes, 64, 128, ... 10240 */
 #define FXMAC_RX_BUF_SIZE_JUMBO 10240U
 
-#define FXMAC_RX_BUF_UNIT 64U /* Number of receive buffer bytes as a \
-                                     unit, this is HW setup */
+#define FXMAC_RX_BUF_UNIT 64U /* Number of receive buffer bytes as a unit, this is HW setup */
 
 #define FXMAC_MAX_RXBD 128U /* Size of RX buffer descriptor queues */
 #define FXMAC_MAX_TXBD 128U /* Size of TX buffer descriptor queues */
@@ -48,22 +47,17 @@ extern "C"
 
 /************************** Constant Definitions *****************************/
 
-#define FXMAC_MAX_MAC_ADDR 4U /* Maxmum number of mac address \
-                                     supported */
+#define FXMAC_MAX_MAC_ADDR 4U /* Maxmum number of mac address supported */
 #define FXMAC_MAX_TYPE_ID 4U  /* Maxmum number of type id supported */
 
 #ifdef __aarch64__
-#define FXMAC_BD_ALIGNMENT 64U /* Minimum buffer descriptor alignment \
-                                     on the local bus */
+#define FXMAC_BD_ALIGNMENT 64U /* Minimum buffer descriptor alignment on the local bus */
 #else
 
-#define FXMAC_BD_ALIGNMENT 4U /* Minimum buffer descriptor alignment \
-                                     on the local bus */
+#define FXMAC_BD_ALIGNMENT 4U /* Minimum buffer descriptor alignment on the local bus */
 #endif
-#define FXMAC_RX_BUF_ALIGNMENT 4U /* Minimum buffer alignment when using    \
-                                         options that impose alignment      \
-                                         restrictions on the buffer data on \
-                                         the local bus */
+#define FXMAC_RX_BUF_ALIGNMENT 4U /* Minimum buffer alignment when using options that impose 
+                                    alignment  restrictions on the buffer data on the local bus */
 
 #define FXMAC_NWCTRL_OFFSET 0x00000000U  /* Network Control reg */
 #define FXMAC_NWCFG_OFFSET 0x00000004U   /* Network Config reg */
@@ -107,128 +101,69 @@ extern "C"
 #define FXMAC_STRETCH_OFFSET 0x000000BCU      /* IPG Stretch reg */
 #define FXMAC_REVISION_REG_OFFSET 0x000000FCU /*   identification number and module revision */
 
-#define FXMAC_OCTTXL_OFFSET 0x00000100U /* Octects transmitted Low \
-                                               reg */
-#define FXMAC_OCTTXH_OFFSET 0x00000104U /* Octects transmitted High \
-                                               reg */
-
-#define FXMAC_TXCNT_OFFSET 0x00000108U      /* Error-free Frmaes \
-                                                   transmitted counter */
-#define FXMAC_TXBCCNT_OFFSET 0x0000010CU    /* Error-free Broadcast \
-                                                   Frames counter*/
-#define FXMAC_TXMCCNT_OFFSET 0x00000110U    /* Error-free Multicast \
-                                                   Frame counter */
-#define FXMAC_TXPAUSECNT_OFFSET 0x00000114U /* Pause Frames Transmitted \
-                                                   Counter */
-#define FXMAC_TX64CNT_OFFSET 0x00000118U    /* Error-free 64 byte Frames \
-                                                   Transmitted counter */
-#define FXMAC_TX65CNT_OFFSET 0x0000011CU    /* Error-free 65-127 byte \
-                                                   Frames Transmitted \
-                                                   counter */
-#define FXMAC_TX128CNT_OFFSET 0x00000120U   /* Error-free 128-255 byte \
-                                                   Frames Transmitted  \
-                                                   counter*/
-#define FXMAC_TX256CNT_OFFSET 0x00000124U   /* Error-free 256-511 byte \
-                                                   Frames transmitted  \
-                                                   counter */
-#define FXMAC_TX512CNT_OFFSET 0x00000128U   /* Error-free 512-1023 byte \
-                                                   Frames transmitted   \
-                                                   counter */
-#define FXMAC_TX1024CNT_OFFSET 0x0000012CU  /* Error-free 1024-1518 byte \
-                                                   Frames transmitted    \
-                                                   counter */
-#define FXMAC_TX1519CNT_OFFSET 0x00000130U  /* Error-free larger than \
-                                                   1519 byte Frames   \
-                                                   transmitted counter */
-#define FXMAC_TXURUNCNT_OFFSET 0x00000134U  /* TX under run error \
-                                                   counter */
-
-#define FXMAC_SNGLCOLLCNT_OFFSET 0x00000138U   /* Single Collision Frame \
-                                                      Counter */
-#define FXMAC_MULTICOLLCNT_OFFSET 0x0000013CU  /* Multiple Collision Frame \
-                                                      Counter */
-#define FXMAC_EXCESSCOLLCNT_OFFSET 0x00000140U /* Excessive Collision Frame \
-                                                      Counter */
-#define FXMAC_LATECOLLCNT_OFFSET 0x00000144U   /* Late Collision Frame \
-                                                      Counter */
-#define FXMAC_TXDEFERCNT_OFFSET 0x00000148U    /* Deferred Transmission \
-                                                      Frame Counter */
-#define FXMAC_TXCSENSECNT_OFFSET 0x0000014CU   /* Transmit Carrier Sense \
-                                                      Error Counter */
-
-#define FXMAC_OCTRXL_OFFSET 0x00000150U /* Octects Received register \
-                                               Low */
-#define FXMAC_OCTRXH_OFFSET 0x00000154U /* Octects Received register \
-                                               High */
-
-#define FXMAC_RXCNT_OFFSET 0x00000158U       /* Error-free Frames \
-                                                    Received Counter */
-#define FXMAC_RXBROADCNT_OFFSET 0x0000015CU  /* Error-free Broadcast \
-                                                    Frames Received Counter */
-#define FXMAC_RXMULTICNT_OFFSET 0x00000160U  /* Error-free Multicast \
-                                                    Frames Received Counter */
-#define FXMAC_RXPAUSECNT_OFFSET 0x00000164U  /* Pause Frames \
-                                                    Received Counter */
-#define FXMAC_RX64CNT_OFFSET 0x00000168U     /* Error-free 64 byte Frames \
-                                                    Received Counter */
-#define FXMAC_RX65CNT_OFFSET 0x0000016CU     /* Error-free 65-127 byte \
-                                                    Frames Received Counter */
-#define FXMAC_RX128CNT_OFFSET 0x00000170U    /* Error-free 128-255 byte \
-                                                    Frames Received Counter */
-#define FXMAC_RX256CNT_OFFSET 0x00000174U    /* Error-free 256-512 byte \
-                                                    Frames Received Counter */
-#define FXMAC_RX512CNT_OFFSET 0x00000178U    /* Error-free 512-1023 byte \
-                                                    Frames Received Counter */
-#define FXMAC_RX1024CNT_OFFSET 0x0000017CU   /* Error-free 1024-1518 byte \
-                                                    Frames Received Counter */
-#define FXMAC_RX1519CNT_OFFSET 0x00000180U   /* Error-free 1519-max byte \
-                                                    Frames Received Counter */
-#define FXMAC_RXUNDRCNT_OFFSET 0x00000184U   /* Undersize Frames Received \
-                                                    Counter */
-#define FXMAC_RXOVRCNT_OFFSET 0x00000188U    /* Oversize Frames Received \
-                                                    Counter */
-#define FXMAC_RXJABCNT_OFFSET 0x0000018CU    /* Jabbers Received \
-                                                    Counter */
-#define FXMAC_RXFCSCNT_OFFSET 0x00000190U    /* Frame Check Sequence \
-                                                    Error Counter */
-#define FXMAC_RXLENGTHCNT_OFFSET 0x00000194U /* Length Field Error \
-                                                    Counter */
+#define FXMAC_OCTTXL_OFFSET 0x00000100U /* Octects transmitted Low reg */
+#define FXMAC_OCTTXH_OFFSET 0x00000104U /* Octects transmitted High reg */
+
+#define FXMAC_TXCNT_OFFSET 0x00000108U      /* Error-free Frmaes transmitted counter */
+#define FXMAC_TXBCCNT_OFFSET 0x0000010CU    /* Error-free Broadcast Frames counter*/
+#define FXMAC_TXMCCNT_OFFSET 0x00000110U    /* Error-free Multicast Frame counter */
+#define FXMAC_TXPAUSECNT_OFFSET 0x00000114U /* Pause Frames Transmitted Counter */
+#define FXMAC_TX64CNT_OFFSET 0x00000118U    /* Error-free 64 byte Frames Transmitted counter */
+#define FXMAC_TX65CNT_OFFSET 0x0000011CU    /* Error-free 65-127 byte Frames Transmitted counter */
+#define FXMAC_TX128CNT_OFFSET 0x00000120U   /* Error-free 128-255 byte Frames Transmitted counter*/
+#define FXMAC_TX256CNT_OFFSET 0x00000124U   /* Error-free 256-511 byte Frames transmitted counter */
+#define FXMAC_TX512CNT_OFFSET 0x00000128U   /* Error-free 512-1023 byte Frames transmitted counter */
+#define FXMAC_TX1024CNT_OFFSET 0x0000012CU  /* Error-free 1024-1518 byte Frames transmitted counter */
+#define FXMAC_TX1519CNT_OFFSET 0x00000130U  /* Error-free larger than 1519 byte Frames transmitted counter */
+#define FXMAC_TXURUNCNT_OFFSET 0x00000134U  /* TX under run error counter */
+
+#define FXMAC_SNGLCOLLCNT_OFFSET 0x00000138U   /* Single Collision Frame Counter */
+#define FXMAC_MULTICOLLCNT_OFFSET 0x0000013CU  /* Multiple Collision Frame Counter */
+#define FXMAC_EXCESSCOLLCNT_OFFSET 0x00000140U /* Excessive Collision Frame Counter */
+#define FXMAC_LATECOLLCNT_OFFSET 0x00000144U   /* Late Collision Frame Counter */
+#define FXMAC_TXDEFERCNT_OFFSET 0x00000148U    /* Deferred Transmission Frame Counter */
+#define FXMAC_TXCSENSECNT_OFFSET 0x0000014CU   /* Transmit Carrier Sense Error Counter */
+
+#define FXMAC_OCTRXL_OFFSET 0x00000150U /* Octects Received register Low */
+#define FXMAC_OCTRXH_OFFSET 0x00000154U /* Octects Received register High */
+
+#define FXMAC_RXCNT_OFFSET 0x00000158U       /* Error-free Frames Received Counter */
+#define FXMAC_RXBROADCNT_OFFSET 0x0000015CU  /* Error-free Broadcast Frames Received Counter */
+#define FXMAC_RXMULTICNT_OFFSET 0x00000160U  /* Error-free Multicast Frames Received Counter */
+#define FXMAC_RXPAUSECNT_OFFSET 0x00000164U  /* Pause Frames Received Counter */
+#define FXMAC_RX64CNT_OFFSET 0x00000168U     /* Error-free 64 byte Frames Received Counter */
+#define FXMAC_RX65CNT_OFFSET 0x0000016CU     /* Error-free 65-127 byte Frames Received Counter */
+#define FXMAC_RX128CNT_OFFSET 0x00000170U    /* Error-free 128-255 byte Frames Received Counter */
+#define FXMAC_RX256CNT_OFFSET 0x00000174U    /* Error-free 256-512 byte Frames Received Counter */
+#define FXMAC_RX512CNT_OFFSET 0x00000178U    /* Error-free 512-1023 byte Frames Received Counter */
+#define FXMAC_RX1024CNT_OFFSET 0x0000017CU   /* Error-free 1024-1518 byte Frames Received Counter */
+#define FXMAC_RX1519CNT_OFFSET 0x00000180U   /* Error-free 1519-max byte Frames Received Counter */
+#define FXMAC_RXUNDRCNT_OFFSET 0x00000184U   /* Undersize Frames Received Counter */
+#define FXMAC_RXOVRCNT_OFFSET 0x00000188U    /* Oversize Frames Received Counter */
+#define FXMAC_RXJABCNT_OFFSET 0x0000018CU    /* Jabbers Received Counter */
+#define FXMAC_RXFCSCNT_OFFSET 0x00000190U    /* Frame Check Sequence Error Counter */
+#define FXMAC_RXLENGTHCNT_OFFSET 0x00000194U /* Length Field Error Counter */
 #define FXMAC_RXSYMBCNT_OFFSET 0x00000198U   /* Symbol Error Counter */
 #define FXMAC_RXALIGNCNT_OFFSET 0x0000019CU  /* Alignment Error Counter */
-#define FXMAC_RXRESERRCNT_OFFSET 0x000001A0U /* Receive Resource Error \
-                                                    Counter */
+#define FXMAC_RXRESERRCNT_OFFSET 0x000001A0U /* Receive Resource Error Counter */
 #define FXMAC_RXORCNT_OFFSET 0x000001A4U     /* Receive Overrun Counter */
-#define FXMAC_RXIPCCNT_OFFSET 0x000001A8U    /* IP header Checksum Error \
-                                                    Counter */
-#define FXMAC_RXTCPCCNT_OFFSET 0x000001ACU   /* TCP Checksum Error \
-                                                    Counter */
-#define FXMAC_RXUDPCCNT_OFFSET 0x000001B0U   /* UDP Checksum Error \
-                                                    Counter */
-#define FXMAC_LAST_OFFSET 0x000001B4U        /* Last statistic counter \
-                            offset, for clearing */
+#define FXMAC_RXIPCCNT_OFFSET 0x000001A8U    /* IP header Checksum Error Counter */
+#define FXMAC_RXTCPCCNT_OFFSET 0x000001ACU   /* TCP Checksum Error Counter */
+#define FXMAC_RXUDPCCNT_OFFSET 0x000001B0U   /* UDP Checksum Error Counter */
+#define FXMAC_LAST_OFFSET 0x000001B4U        /* Last statistic counter offset, for clearing */
 
 #define FXMAC_1588_SEC_OFFSET 0x000001D0U       /* 1588 second counter */
 #define FXMAC_1588_NANOSEC_OFFSET 0x000001D4U   /* 1588 nanosecond counter */
-#define FXMAC_1588_ADJ_OFFSET 0x000001D8U       /* 1588 nanosecond \
-                               adjustment counter */
-#define FXMAC_1588_INC_OFFSET 0x000001DCU       /* 1588 nanosecond \
-                               increment counter */
-#define FXMAC_PTP_TXSEC_OFFSET 0x000001E0U      /* 1588 PTP transmit second \
-                               counter */
-#define FXMAC_PTP_TXNANOSEC_OFFSET 0x000001E4U  /* 1588 PTP transmit \
-                               nanosecond counter */
-#define FXMAC_PTP_RXSEC_OFFSET 0x000001E8U      /* 1588 PTP receive second \
-                               counter */
-#define FXMAC_PTP_RXNANOSEC_OFFSET 0x000001ECU  /* 1588 PTP receive \
-                               nanosecond counter */
-#define FXMAC_PTPP_TXSEC_OFFSET 0x000001F0U     /* 1588 PTP peer transmit \
-                               second counter */
-#define FXMAC_PTPP_TXNANOSEC_OFFSET 0x000001F4U /* 1588 PTP peer transmit \
-                              nanosecond counter */
-#define FXMAC_PTPP_RXSEC_OFFSET 0x000001F8U     /* 1588 PTP peer receive \
-                               second counter */
-#define FXMAC_PTPP_RXNANOSEC_OFFSET 0x000001FCU /* 1588 PTP peer receive \
-                              nanosecond counter */
+#define FXMAC_1588_ADJ_OFFSET 0x000001D8U       /* 1588 nanosecond adjustment counter */
+#define FXMAC_1588_INC_OFFSET 0x000001DCU       /* 1588 nanosecond increment counter */
+#define FXMAC_PTP_TXSEC_OFFSET 0x000001E0U      /* 1588 PTP transmit second counter */
+#define FXMAC_PTP_TXNANOSEC_OFFSET 0x000001E4U  /* 1588 PTP transmit nanosecond counter */
+#define FXMAC_PTP_RXSEC_OFFSET 0x000001E8U      /* 1588 PTP receive second counter */
+#define FXMAC_PTP_RXNANOSEC_OFFSET 0x000001ECU  /* 1588 PTP receive nanosecond counter */
+#define FXMAC_PTPP_TXSEC_OFFSET 0x000001F0U     /* 1588 PTP peer transmit second counter */
+#define FXMAC_PTPP_TXNANOSEC_OFFSET 0x000001F4U /* 1588 PTP peer transmit nanosecond counter */
+#define FXMAC_PTPP_RXSEC_OFFSET 0x000001F8U     /* 1588 PTP peer receive second counter */
+#define FXMAC_PTPP_RXNANOSEC_OFFSET 0x000001FCU /* 1588 PTP peer receive nanosecond counter */
 
 #define FXMAC_PCS_CONTROL_OFFSET 0x00000200U /* All PCS registers */
 
@@ -242,29 +177,26 @@ extern "C"
 
 #define FXMAC_INTQ1_STS_OFFSET 0x00000400U /* Interrupt Q1 Status reg */
 
-#define FXMAC_TXQ1BASE_OFFSET 0x00000440U /* TX Q1 Base address \
-                       reg */
-#define FXMAC_RXQ1BASE_OFFSET 0x00000480U /* RX Q1 Base address \
-                       reg */
+#define FXMAC_TXQ1BASE_OFFSET 0x00000440U /* TX Q1 Base address reg */
+#define FXMAC_RXQ1BASE_OFFSET 0x00000480U /* RX Q1 Base address reg */
 
 #define FXMAC_RXBUFQ1_SIZE_OFFSET 0x000004a0U /* Receive Buffer Size */
 #define FXMAC_RXBUFQX_SIZE_OFFSET(x) (FXMAC_RXBUFQ1_SIZE_OFFSET + (x << 2))
 #define FXMAC_RXBUFQX_SIZE_MASK GENMASK(7, 0)
 
 #define FXMAC_MSBBUF_TXQBASE_OFFSET 0x000004C8U /* MSB Buffer TX Q Base reg */
-#define FXMAC_MSBBUF_RXQBASE_OFFSET 0x000004D4U /* MSB Buffer RX Q Base \
-                           reg */
+#define FXMAC_MSBBUF_RXQBASE_OFFSET 0x000004D4U /* MSB Buffer RX Q Base reg */
 #define FXMAC_INTQ1_IER_OFFSET 0x00000600U      /* Interrupt Q1 Enable reg */
 #define FXMAC_INTQX_IER_SIZE_OFFSET(x) (FXMAC_INTQ1_IER_OFFSET + (x << 2))
 
 #define FXMAC_INTQ1_IDR_OFFSET 0x00000620U /* Interrupt Q1 Disable reg */
 #define FXMAC_INTQX_IDR_SIZE_OFFSET(x) (FXMAC_INTQ1_IDR_OFFSET + (x << 2))
 
-#define FXMAC_INTQ1_IMR_OFFSET 0x00000640U /* Interrupt Q1 Mask \
-                        reg */
+#define FXMAC_INTQ1_IMR_OFFSET 0x00000640U /* Interrupt Q1 Mask reg */
 
 #define FXMAC_GEM_USX_CONTROL_OFFSET 0x0A80 /* High speed PCS control register */
 #define FXMAC_TEST_CONTROL_OFFSET 0X0A84    /* USXGMII Test Control Register */
+#define FXMAC_GEM_USX_STATUS_OFFSET 0x0A88    /* USXGMII Status Register */
 
 #define FXMAC_GEM_SRC_SEL_LN 0x1C04
 #define FXMAC_GEM_DIV_SEL0_LN 0x1C08
@@ -316,8 +248,7 @@ extern "C"
 #define FXMAC_IXR_RXOVR_MASK BIT(10)      /* Receive overrun occurred */
 #define FXMAC_IXR_LINKCHANGE_MASK BIT(9)   /* link status change */
 #define FXMAC_IXR_TXCOMPL_MASK BIT(7)     /* Frame transmitted ok */
-#define FXMAC_IXR_TXEXH_MASK BIT(6)       /* Transmit err occurred or \
-                                               no buffers*/
+#define FXMAC_IXR_TXEXH_MASK BIT(6)       /* Transmit err occurred or no buffers*/
 #define FXMAC_IXR_RETRY_MASK BIT(5)       /* Retry limit exceeded */
 #define FXMAC_IXR_URUN_MASK BIT(4)        /* Transmit underrun */
 #define FXMAC_IXR_TXUSED_MASK BIT(3)      /* Tx buffer used bit read */
@@ -341,21 +272,15 @@ extern "C"
 
 #define FXMAC_NWCTRL_TWO_PT_FIVE_GIG_MASK BIT(29) /* 2.5G operation selected */
 
-#define FXMAC_NWCTRL_FLUSH_DPRAM_MASK BIT(18) /* Flush a packet from \
-                          Rx SRAM */
-#define FXMAC_NWCTRL_ZEROPAUSETX_MASK BIT(11) /* Transmit zero quantum \
-                                                       pause frame */
+#define FXMAC_NWCTRL_FLUSH_DPRAM_MASK BIT(18) /* Flush a packet from Rx SRAM */
+#define FXMAC_NWCTRL_ZEROPAUSETX_MASK BIT(11) /* Transmit zero quantum pause frame */
 #define FXMAC_NWCTRL_PAUSETX_MASK BIT(11)     /* Transmit pause frame */
-#define FXMAC_NWCTRL_HALTTX_MASK BIT(10)      /* Halt transmission \
-                                                  after current frame */
+#define FXMAC_NWCTRL_HALTTX_MASK BIT(10)      /* Halt transmission after current frame */
 #define FXMAC_NWCTRL_STARTTX_MASK BIT(9)      /* Start tx (tx_go) */
 
-#define FXMAC_NWCTRL_STATWEN_MASK BIT(7) /* Enable writing to \
-                                               stat counters */
-#define FXMAC_NWCTRL_STATINC_MASK BIT(6) /* Increment statistic \
-                                               registers */
-#define FXMAC_NWCTRL_STATCLR_MASK BIT(5) /* Clear statistic \
-                                               registers */
+#define FXMAC_NWCTRL_STATWEN_MASK BIT(7) /* Enable writing to stat counters */
+#define FXMAC_NWCTRL_STATINC_MASK BIT(6) /* Increment statistic registers */
+#define FXMAC_NWCTRL_STATCLR_MASK BIT(5) /* Clear statistic registers */
 #define FXMAC_NWCTRL_MDEN_MASK BIT(4)    /* Enable MDIO port */
 #define FXMAC_NWCTRL_TXEN_MASK BIT(3)    /* Enable transmit */
 #define FXMAC_NWCTRL_RXEN_MASK BIT(2)    /* Enable receive */
@@ -379,21 +304,17 @@ extern "C"
 #define FXMAC_NWCFG_CLOCK_DIV8_MASK (0U << 18)
 
 #define FXMAC_NWCFG_FCS_REMOVE BIT(17)      /* FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). */
+#define FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD    BIT(16)
 #define FXMAC_NWCFG_PAUSE_ENABLE BIT(13)    /* Pause enable - when set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. */
 #define FXMAC_NWCFG_PCSSEL_MASK BIT(11)     /* PCS Select */
 #define FXMAC_NWCFG_1000_MASK BIT(10)       /* Gigabit mode enable */
-#define FXMAC_NWCFG_1536RXEN_MASK BIT(8)    /* Enable 1536 byte \
-                                                  frames reception */
-#define FXMAC_NWCFG_UCASTHASHEN_MASK BIT(7) /* Receive unicast hash \
-                                                     frames */
-#define FXMAC_NWCFG_MCASTHASHEN_MASK BIT(6) /* Receive multicast hash \
-                                                     frames */
-#define FXMAC_NWCFG_BCASTDI_MASK BIT(5)     /* Do not receive \
-                                                 broadcast frames */
+#define FXMAC_NWCFG_1536RXEN_MASK BIT(8)    /* Enable 1536 byte frames reception */
+#define FXMAC_NWCFG_UCASTHASHEN_MASK BIT(7) /* Receive unicast hash frames */
+#define FXMAC_NWCFG_MCASTHASHEN_MASK BIT(6) /* Receive multicast hash frames */
+#define FXMAC_NWCFG_BCASTDI_MASK BIT(5)     /* Do not receive broadcast frames */
 #define FXMAC_NWCFG_COPYALLEN_MASK BIT(4)   /* Copy all frames */
 #define FXMAC_NWCFG_JUMBO_MASK BIT(3)       /* Jumbo frames */
-#define FXMAC_NWCFG_NVLANDISC_MASK BIT(2)   /* Receive only VLAN \
-                                                   frames */
+#define FXMAC_NWCFG_NVLANDISC_MASK BIT(2)   /* Receive only VLAN frames */
 #define FXMAC_NWCFG_FDEN_MASK BIT(1)        /* full duplex */
 #define FXMAC_NWCFG_100_MASK BIT(0)         /* 100 Mbps */
 #define FXMAC_NWCFG_RESET_MASK BIT(19)      /* reset value */
@@ -414,7 +335,7 @@ extern "C"
 #define FXMAC_RXBUF_UNIHASH_MASK BIT(29)          /* Unicast hashed frame */
 #define FXMAC_RXBUF_EXH_MASK BIT(27)              /* buffer exhausted */
 #define FXMAC_RXBUF_AMATCH_MASK GENMASK(26, 25)   /* Specific address \
-                                             matched */
+matched */
 #define FXMAC_RXBUF_IDFOUND_MASK BIT(24)          /* Type ID matched */
 #define FXMAC_RXBUF_IDMATCH_MASK GENMASK(23, 22)  /* ID matched mask */
 #define FXMAC_RXBUF_VLAN_MASK BIT(21)             /* VLAN tagged */
@@ -430,6 +351,7 @@ extern "C"
 #define FXMAC_RXBUF_WRAP_MASK BIT(1)        /* Wrap bit, last BD */
 #define FXMAC_RXBUF_NEW_MASK BIT(0)         /* Used bit.. */
 #define FXMAC_RXBUF_ADD_MASK GENMASK(31, 2) /* Mask for address */
+
 /*
  * @}
  */
@@ -459,24 +381,18 @@ extern "C"
 /** @name network configuration register bit definitions
  * @{
  */
-#define FXMAC_NWCFG_BADPREAMBEN_MASK BIT(29)       /* disable rejection of \
-                                                           non-standard preamble */
+#define FXMAC_NWCFG_BADPREAMBEN_MASK BIT(29)       /* disable rejection of non-standard preamble */
 #define FXMAC_NWCFG_IPDSTRETCH_MASK BIT(28)        /* enable transmit IPG */
 #define FXMAC_NWCFG_SGMIIEN_MASK BIT(27)           /* SGMII Enable */
-#define FXMAC_NWCFG_FCSIGNORE_MASK BIT(26)         /* disable rejection of \
-                                                         FCS error */
+#define FXMAC_NWCFG_FCSIGNORE_MASK BIT(26)         /* disable rejection of FCS error */
 #define FXMAC_NWCFG_HDRXEN_MASK BIT(25)            /* RX half duplex */
-#define FXMAC_NWCFG_RXCHKSUMEN_MASK BIT(24)        /* enable RX checksum \
-                                                          offload */
-#define FXMAC_NWCFG_PAUSECOPYDI_MASK BIT(23)       /* Do not copy pause \
-                                                           Frames to memory */
+#define FXMAC_NWCFG_RXCHKSUMEN_MASK BIT(24)        /* enable RX checksum offload */
+#define FXMAC_NWCFG_PAUSECOPYDI_MASK BIT(23)       /* Do not copy pause Frames to memory */
 #define FXMAC_NWCFG_DWIDTH_64_MASK BIT(21)         /* 64 bit Data bus width */
 #define FXMAC_NWCFG_MDC_SHIFT_MASK 18U             /* shift bits for MDC */
 #define FXMAC_NWCFG_MDCCLKDIV_MASK GENMASK(20, 18) /* MDC Mask PCLK divisor */
-#define FXMAC_NWCFG_FCSREM_MASK BIT(17)            /* Discard FCS from \
-                                                      received frames */
-#define FXMAC_NWCFG_LENERRDSCRD_MASK BIT(16)
-/* RX length error discard */
+#define FXMAC_NWCFG_FCSREM_MASK BIT(17)            /* Discard FCS from received frames */
+#define FXMAC_NWCFG_LENERRDSCRD_MASK BIT(16)    /* RX length error discard */
 #define FXMAC_NWCFG_RXOFFS_MASK GENMASK(15)  /* RX buffer offset */
 #define FXMAC_NWCFG_PAUSEEN_MASK BIT(13)     /* Enable pause RX */
 #define FXMAC_NWCFG_RETRYTESTEN_MASK BIT(12) /* Retry test */
@@ -507,12 +423,9 @@ extern "C"
 #define FXMAC_DMACR_TXEXTEND_MASK BIT(29)       /* Tx Extended desc mode */
 #define FXMAC_DMACR_RXEXTEND_MASK BIT(28)       /* Rx Extended desc mode */
 #define FXMAC_DMACR_ORCE_DISCARD_ON_ERR_MASK BIT(24) /* Auto Discard RX frames during lack of resource. */
-#define FXMAC_DMACR_RXBUF_MASK GENMASK(23, 16)  /* Mask bit for RX buffer \
-                                           size */
-#define FXMAC_DMACR_RXBUF_SHIFT 16U             /* Shift bit for RX buffer \
-                                                      size */
-#define FXMAC_DMACR_TCPCKSUM_MASK BIT(11)       /* enable/disable TX \
-                                                        checksum offload */
+#define FXMAC_DMACR_RXBUF_MASK GENMASK(23, 16)  /* Mask bit for RX buffer size */
+#define FXMAC_DMACR_RXBUF_SHIFT 16U             /* Shift bit for RX buffer size */
+#define FXMAC_DMACR_TCPCKSUM_MASK BIT(11)       /* enable/disable TX checksum offload */
 #define FXMAC_DMACR_TXSIZE_MASK BIT(10)         /* TX buffer memory size bit[10] */
 #define FXMAC_DMACR_RXSIZE_MASK GENMASK(9, 8)   /* RX buffer memory size bit[9:8] */
 #define FXMAC_DMACR_ENDIAN_MASK BIT(7)          /* endian configuration */
@@ -554,8 +467,7 @@ extern "C"
 #define FXMAC_TXSR_HRESPNOK_MASK BIT(8) /* Transmit hresp not OK */
 #define FXMAC_TXSR_URUN_MASK BIT(6)     /* Transmit underrun */
 #define FXMAC_TXSR_TXCOMPL_MASK BIT(5)  /* Transmit completed OK */
-#define FXMAC_TXSR_BUFEXH_MASK BIT(4)   /* Transmit buffs exhausted \
-                                           mid frame */
+#define FXMAC_TXSR_BUFEXH_MASK BIT(4)   /* Transmit buffs exhausted mid frame */
 #define FXMAC_TXSR_TXGO_MASK BIT(3)     /* Status of go flag */
 #define FXMAC_TXSR_RXOVR_MASK BIT(2)    /* Retry limit exceeded */
 #define FXMAC_TXSR_FRAMERX_MASK BIT(1)  /* Collision tx frame */
@@ -595,6 +507,7 @@ extern "C"
 /* Design Configuration Register 1 - The GEM has many parameterisation options to configure the IP during compilation stage. */
 
 #define FXMAC_DESIGNCFG_DEBUG1_BUS_WIDTH_MASK GENMASK(27, 25)
+#define FXMAC_DESIGNCFG_DEBUG1_BUS_IRQCOR_MASK BIT(23)
 
 /*GEM hs mac config register bitfields*/
 #define FXMAC_GEM_HSMACSPEED_OFFSET 0
@@ -611,14 +524,16 @@ extern "C"
 /** @name MAC address register word 1 mask
  * @{
  */
-#define FXMAC_GEM_SAB_MASK GENMASK(15, 0) /* Address bits[47:32] \
-                                               bit[31:0] are in BOTTOM */
+#define FXMAC_GEM_SAB_MASK GENMASK(15, 0) /* Address bits[47:32] bit[31:0] are in BOTTOM */
 
 /* USXGMII control register */
 #define FXMAC_GEM_USX_HS_MAC_SPEED_100M (0x0 << 14) /* 100M operation */
 #define FXMAC_GEM_USX_HS_MAC_SPEED_1G (0x1 << 14)   /* 1G operation */
 #define FXMAC_GEM_USX_HS_MAC_SPEED_2_5G (0x2 << 14) /* 2.5G operation */
+#define FXMAC_GEM_USX_HS_MAC_SPEED_5G  (0x3 << 14)  /* 5G operation */
 #define FXMAC_GEM_USX_HS_MAC_SPEED_10G (0x4 << 14)  /* 10G operation */
+#define FXMAC_GEM_USX_SERDES_RATE_5G    (0x0 << 12)
+#define FXMAC_GEM_USX_SERDES_RATE_10G    (0x1 << 12)
 #define FXMAC_GEM_USX_TX_SCR_BYPASS BIT(8)          /* RX Scrambler Bypass. Set high to bypass the receive descrambler. */
 #define FXMAC_GEM_USX_RX_SCR_BYPASS BIT(9)          /* TX Scrambler Bypass. Set high to bypass the transmit scrambler. */
 #define FXMAC_GEM_USX_RX_SYNC_RESET BIT(2)          /* RX Reset. Set high to reset the receive datapath. When low the receive datapath is enabled. */
@@ -642,6 +557,12 @@ extern "C"
 #define FXMAC_PCS_AN_LP_DUPLEX   (0x3U << FXMAC_PCS_AN_LP_DUPLEX_OFFSET) /* SGMII Bit 13: Reserved. read as 0. Bit 12 : 0 : half-duplex. 1: Full Duplex." */
 #define FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_STATUS (1U<<15) /* In sgmii mode, 0 is link down . 1 is link up */
 
+
+/* USXGMII Status Register */
+
+#define FXMAC_GEM_USX_STATUS_BLOCK_LOCK BIT(0)  /* Block Lock. A value of one indicates that the PCS has achieved block synchronization. */
+
+
 /***************** Macros (Inline Functions) Definitions *********************/
 
 #define FXMAC_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset)
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c
index 08c226740ce..63d0f66cbe1 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c
@@ -14,11 +14,12 @@
  * FilePath: fxmac_intr.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file contains functions related to interrupt handling.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac.h"
@@ -61,29 +62,29 @@ FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
 
     switch (handler_type)
     {
-    case FXMAC_HANDLER_DMASEND:
-        instance_p->send_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
-        instance_p->send_args = call_back_ref;
-        break;
-    case FXMAC_HANDLER_DMARECV:
-        instance_p->recv_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
-        instance_p->recv_args = call_back_ref;
-        break;
-    case FXMAC_HANDLER_ERROR:
-        instance_p->error_irq_handler = ((FXmacErrorIrqHandler)(void *)func_pointer);
-        instance_p->error_args = call_back_ref;
-        break;
-    case FXMAC_HANDLER_LINKCHANGE:
-        instance_p->link_change_handler = ((FXmacIrqHandler)(void *)func_pointer);
-        instance_p->link_change_args = call_back_ref;
-        break;
-    case FXMAC_HANDLER_RESTART:
-        instance_p->restart_handler = ((FXmacIrqHandler)(void *)func_pointer);
-        instance_p->restart_args = call_back_ref;
-        break;
-    default:
-        status = (FError)(FXMAC_ERR_INVALID_PARAM);
-        break;
+        case FXMAC_HANDLER_DMASEND:
+            instance_p->send_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
+            instance_p->send_args = call_back_ref;
+            break;
+        case FXMAC_HANDLER_DMARECV:
+            instance_p->recv_irq_handler = ((FXmacIrqHandler)(void *)func_pointer);
+            instance_p->recv_args = call_back_ref;
+            break;
+        case FXMAC_HANDLER_ERROR:
+            instance_p->error_irq_handler = ((FXmacErrorIrqHandler)(void *)func_pointer);
+            instance_p->error_args = call_back_ref;
+            break;
+        case FXMAC_HANDLER_LINKCHANGE:
+            instance_p->link_change_handler = ((FXmacIrqHandler)(void *)func_pointer);
+            instance_p->link_change_args = call_back_ref;
+            break;
+        case FXMAC_HANDLER_RESTART:
+            instance_p->restart_handler = ((FXmacIrqHandler)(void *)func_pointer);
+            instance_p->restart_args = call_back_ref;
+            break;
+        default:
+            status = (FError)(FXMAC_ERR_INVALID_PARAM);
+            break;
     }
     return status;
 }
@@ -97,34 +98,34 @@ FError FXmacSetHandler(FXmac *instance_p, u32 handler_type,
  * @return {*}
  * @note 目前中断只支持单queue的情况
  */
+
 void FXmacIntrHandler(s32 vector, void *args)
 {
     u32 reg_isr;
     u32 reg_qx_isr;
     u32 reg_temp;
     u32 reg_ctrl;
-    u32 tx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
-    u32 rx_queue_id; /* 0 ~ FT_XMAC_QUEUE_MAX_NUM ,Index queue number */
+    u32 tx_queue_id; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
+    u32 rx_queue_id; /* 0 ~ FXMAC_QUEUE_MAX_NUM ,Index queue number */
     FXmac *instance_p = (FXmac *)args;
     FASSERT(instance_p != NULL);
     FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY);
 
     tx_queue_id = instance_p->tx_bd_queue.queue_id;
     rx_queue_id = instance_p->rx_bd_queue.queue_id;
-    FASSERT((rx_queue_id < FT_XMAC_QUEUE_MAX_NUM) && (tx_queue_id < FT_XMAC_QUEUE_MAX_NUM))
+    FASSERT((rx_queue_id < FXMAC_QUEUE_MAX_NUM) && (tx_queue_id < FXMAC_QUEUE_MAX_NUM))
 
     /* This ISR will try to handle as many interrupts as it can in a single
      * call. However, in most of the places where the user's error handler
      * is called, this ISR exits because it is expected that the user will
      * reset the device in nearly all instances.
      */
+    reg_isr = FXMAC_READREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET);
 
     if ((u32)vector == instance_p->config.queue_irq_num[tx_queue_id])
     {
         if (tx_queue_id == 0)
         {
-            reg_isr = FXMAC_READREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET);
-
             if ((reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U)
             {
                 /* Clear TX status register TX complete indication but preserve
@@ -141,12 +142,15 @@ void FXmacIntrHandler(s32 vector, void *args)
                 }
 
                 /* add */
-                FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXCOMPL_MASK);
+                if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                {
+                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXCOMPL_MASK);
+                }
             }
 
             /* Transmit error conditions interrupt */
             if (((reg_isr & FXMAC_IXR_TX_ERR_MASK) != 0x00000000U) &&
-                    (!(reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U))
+                (!(reg_isr & FXMAC_IXR_TXCOMPL_MASK) != 0x00000000U))
             {
                 /* Clear TX status register */
                 reg_temp = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXSR_OFFSET);
@@ -156,21 +160,27 @@ void FXmacIntrHandler(s32 vector, void *args)
                     instance_p->error_irq_handler(instance_p->error_args, FXMAC_SEND, reg_temp);
                 }
                 /* add */
-                FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TX_ERR_MASK);
+                if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                {
+                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TX_ERR_MASK);
+                }
             }
 
             /* add restart */
             if ((reg_isr & FXMAC_IXR_TXUSED_MASK) != 0x00000000U)
             {
                 /* add */
-                FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXUSED_MASK);
+                if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                {
+                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_TXUSED_MASK);
+                }
 
                 if (instance_p->restart_handler)
                 {
                     instance_p->restart_handler(instance_p->restart_args);
                 }
             }
-
+            
             /* link chaged */
             if ((reg_isr & FXMAC_IXR_LINKCHANGE_MASK) != 0x00000000U)
             {
@@ -178,7 +188,11 @@ void FXmacIntrHandler(s32 vector, void *args)
                 {
                     instance_p->link_change_handler(instance_p->link_change_args);
                 }
-                FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_LINKCHANGE_MASK);
+
+                if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                {
+                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_LINKCHANGE_MASK);
+                }
             }
         }
         else /* use queue number more than 0 */
@@ -203,7 +217,7 @@ void FXmacIntrHandler(s32 vector, void *args)
 
             /* Transmit Q1 error conditions interrupt */
             if (((reg_isr & FXMAC_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
-                    ((reg_isr & FXMAC_INTQ1SR_TXCOMPL_MASK) != 0x00000000U))
+                ((reg_isr & FXMAC_INTQ1SR_TXCOMPL_MASK) != 0x00000000U))
             {
                 /* Clear Interrupt Q1 status register */
                 FXMAC_WRITEREG32(instance_p->config.base_address,
@@ -218,9 +232,6 @@ void FXmacIntrHandler(s32 vector, void *args)
     {
         if (rx_queue_id == 0)
         {
-            reg_isr = FXMAC_READREG32(instance_p->config.base_address,
-                                      FXMAC_ISR_OFFSET);
-
             /* Receive complete interrupt */
             if ((reg_isr & FXMAC_IXR_RXCOMPL_MASK) != 0x00000000U)
             {
@@ -233,8 +244,10 @@ void FXmacIntrHandler(s32 vector, void *args)
                 instance_p->recv_irq_handler(instance_p->recv_args);
 
                 /* add */
-                FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXCOMPL_MASK);
-
+                if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                {
+                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXCOMPL_MASK);
+                }
             }
 
             /* Receive error conditions interrupt */
@@ -269,13 +282,19 @@ void FXmacIntrHandler(s32 vector, void *args)
                 /* add */
                 if ((reg_isr & FXMAC_IXR_RXOVR_MASK) != 0x00000000U)
                 {
-                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXOVR_MASK);
+                    if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                    {
+                        FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_RXOVR_MASK);
+                    }
                 }
 
                 /* add */
                 if ((reg_isr & FXMAC_IXR_HRESPNOK_MASK) != 0x00000000U)
                 {
-                    FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_HRESPNOK_MASK);
+                    if(instance_p->caps& FXMAC_CAPS_ISR_CLEAR_ON_WRITE)
+                    {
+                        FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, FXMAC_IXR_HRESPNOK_MASK);
+                    }
                 }
 
                 if (reg_temp != 0)
@@ -348,7 +367,6 @@ void FXmacIntrHandler(s32 vector, void *args)
             }
         }
     }
-
 }
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c
index c4e4b0d570d..1d05fef0979 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c
@@ -14,16 +14,18 @@
  * FilePath: fxmac_options.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for options functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac_hw.h"
 #include "fxmac.h"
 #include "fassert.h"
+#include "ftypes.h"
 
 
 /**
@@ -637,7 +639,7 @@ FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address,
     /* Make sure no other PHY operation is currently in progress */
     if ((!(FXMAC_READREG32(instance_p->config.base_address,
                            FXMAC_NWSR_OFFSET) &
-            FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
+           FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
     {
         status = (FError)(FXMAC_ERR_PHY_BUSY);
     }
@@ -713,7 +715,7 @@ FError FXmacPhyRead(FXmac *instance_p, u32 phy_address,
     /* Make sure no other PHY operation is currently in progress */
     if ((!(FXMAC_READREG32(instance_p->config.base_address,
                            FXMAC_NWSR_OFFSET) &
-            FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
+           FXMAC_NWSR_MDIOIDLE_MASK)) == TRUE)
     {
         status = (FError)(FXMAC_ERR_PHY_BUSY);
     }
@@ -742,4 +744,20 @@ FError FXmacPhyRead(FXmac *instance_p, u32 phy_address,
         status = (FError)(FT_SUCCESS);
     }
     return status;
-}
\ No newline at end of file
+}
+
+boolean FXmacUsxLinkStatus(FXmac *instance_p)
+{
+    u32 reg = 0;
+    FASSERT(instance_p != NULL);
+
+    reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_GEM_USX_STATUS_OFFSET);
+    if (reg & FXMAC_GEM_USX_STATUS_BLOCK_LOCK)
+    {
+        return TRUE;
+    }
+    else
+    {
+        return FALSE;
+    }
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.c
index 4af6752555c..f8ea684af26 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.c
@@ -14,16 +14,18 @@
  * FilePath: fxmac_phy.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for phy types.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac.h"
 #include "eth_ieee_reg.h"
 #include "fdebug.h"
+#include "sdkconfig.h"
 
 #if defined(CONFIG_FXMAC_PHY_YT)
     #include "phy_yt.h"
@@ -46,26 +48,26 @@ static FError FXmacDetect(FXmac *instance_p, u32 *phy_addr_p)
     FError ret;
     instance_b = instance_p;
 
-    for (phy_addr = 0; phy_addr < FT_XMAC_PHY_MAX_NUM; phy_addr++)
+    for (phy_addr = 0; phy_addr < FXMAC_PHY_MAX_NUM; phy_addr++)
     {
         ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &phy_reg);
         if (ret != FT_SUCCESS)
         {
-            FXMAC_ERROR("%s,  PHY operation is busy", __func__);
+            FXMAC_ERROR("Phy operation is busy.");
             return ret;
         }
-        FXMAC_INFO("PHY_STATUS_REG_OFFSET is %x \r\n", phy_reg);
+        FXMAC_INFO("Phy status reg is %x", phy_reg);
         if (phy_reg != 0xffff)
         {
             ret = FXmacPhyRead(instance_p, phy_addr, PHY_IDENTIFIER_1_REG, &phy_id1_reg);
             ret |= FXmacPhyRead(instance_p, phy_addr, PHY_IDENTIFIER_2_REG, &phy_id2_reg);
-            FXMAC_INFO("phy_id1_reg is 0x%x \r\n", phy_id1_reg);
-            FXMAC_INFO("phy_id2_reg is 0x%x \r\n", phy_id2_reg);
+            FXMAC_INFO("Phy id1 reg is 0x%x", phy_id1_reg);
+            FXMAC_INFO("Phy id2 reg is 0x%x", phy_id2_reg);
             if ((ret == FT_SUCCESS) && (phy_id2_reg != 0) && (phy_id1_reg != 0xffff) && (phy_id1_reg != 0xffff))
             {
                 *phy_addr_p = phy_addr;
                 phy_addr_b = phy_addr;
-                FXMAC_INFO("phy_addr is 0x%x \r\n", phy_addr);
+                FXMAC_INFO("Phy addr is 0x%x", phy_addr);
                 return FT_SUCCESS;
             }
         }
@@ -84,12 +86,12 @@ static FError FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
     FError ret;
     volatile s32 wait;
 
-    FXMAC_INFO("Start PHY autonegotiation ");
+    FXMAC_INFO("Start phy auto negotiation.");
 
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
     control |= PHY_CONTROL_RESET_MASK;
@@ -97,16 +99,16 @@ static FError FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
     ret = FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,write PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,write PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
     for (wait = 0; wait < 100000; wait++)
         ;
-    FXMAC_INFO(" PHY reset end ");
+    FXMAC_INFO(" Phy reset end.");
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
 
@@ -115,16 +117,16 @@ static FError FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
     ret = FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,write PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,write PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
 
-    FXMAC_INFO("Waiting for PHY to complete autonegotiation.");
+    FXMAC_INFO("Waiting for phy to complete auto negotiation.");
 
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_CONTROL_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
 
@@ -136,60 +138,60 @@ static FError FXmacGetIeeePhySpeed(FXmac *instance_p, u32 phy_addr)
         ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &status);
         if (ret != FT_SUCCESS)
         {
-            FXMAC_ERROR("%s line is %d,read PHY_STATUS_REG_OFFSET is error", __func__, __LINE__);
+            FXMAC_ERROR("%s:%d,read PHY_STATUS_REG_OFFSET is error", __func__, __LINE__);
             return ret;
         }
 
 
         if (negotitation_timeout_cnt++ >= 0xfff)
         {
-            FXMAC_ERROR("autonegotiation is error ");
+            FXMAC_ERROR("Auto negotiation is error.");
             return FXMAC_PHY_AUTO_AUTONEGOTIATION_FAILED;
         }
     }
-    FXMAC_INFO("autonegotiation complete  ");
+    FXMAC_INFO("Auto negotiation complete.");
 
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_SPECIFIC_STATUS_REG, &temp);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_SPECIFIC_STATUS_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_SPECIFIC_STATUS_REG is error", __func__, __LINE__);
         return ret;
     }
 
-    FXMAC_INFO("temp is %x \r\n", temp);
+    FXMAC_INFO("Temp is 0x%x", temp);
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_STATUS_REG_OFFSET, &temp2);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_STATUS_REG_OFFSET is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_STATUS_REG_OFFSET is error", __func__, __LINE__);
         return ret;
     }
 
-    FXMAC_INFO("temp2 is %x \r\n", temp2);
+    FXMAC_INFO("Temp2 is 0x%x", temp2);
 
     if (temp & (1 << 13))
     {
-        FXMAC_INFO("duplex is full \r\n");
+        FXMAC_INFO("Duplex is full.");
         instance_p->config.duplex = 1;
     }
     else
     {
-        FXMAC_INFO("duplex is half \r\n");
+        FXMAC_INFO("Duplex is half.");
         instance_p->config.duplex = 0;
     }
 
     if ((temp & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_1000M)
     {
-        FXMAC_INFO("speed is 1000\r\n");
+        FXMAC_INFO("Speed is 1000M.");
         instance_p->config.speed = 1000;
     }
     else if ((temp & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_100M)
     {
-        FXMAC_INFO("speed is 100\r\n");
+        FXMAC_INFO("Speed is 100M.");
         instance_p->config.speed = 100;
     }
     else
     {
-        FXMAC_INFO("speed is 10\r\n");
+        FXMAC_INFO("Speed is 10M.");
         instance_p->config.speed = 10;
     }
 
@@ -200,8 +202,8 @@ void FxmaxLinkupCheck(void)
 {
     u16 temp;
     FXmacPhyRead(instance_b, phy_addr_b, PHY_SPECIFIC_STATUS_REG, &temp);
-    FXMAC_INFO("0x17 value is %x \r\n", temp);
-    FXMAC_INFO("linkup status is   %x \r\n", temp & (1 << 10));
+    FXMAC_INFO("Reg 0x17 value is 0x%x", temp);
+    FXMAC_INFO("Linkup status is 0x%x", temp & (1 << 10));
 }
 
 
@@ -213,12 +215,12 @@ static FError FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 sp
     FError ret;
     u16 specific_reg = 0;
 
-    FXMAC_INFO("manual setting ,phy_addr is %d,speed %d, duplex_mode is %d \r\n", phy_addr, speed, duplex_mode);
+    FXMAC_INFO("Manual setting ,phy_addr is %d,speed %d, duplex_mode is %d.", phy_addr, speed, duplex_mode);
 
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, &autonereg);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_AUTONEGO_ADVERTISE_REG is error.", __func__, __LINE__);
         return ret;
     }
 
@@ -227,7 +229,7 @@ static FError FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 sp
     ret = FXmacPhyWrite(instance_p, phy_addr, PHY_AUTONEGO_ADVERTISE_REG, autonereg);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,write PHY_AUTONEGO_ADVERTISE_REG is error.", __func__, __LINE__);
         return ret;
     }
 
@@ -235,10 +237,10 @@ static FError FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 sp
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, &control);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_AUTONEGO_ADVERTISE_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_AUTONEGO_ADVERTISE_REG is error.", __func__, __LINE__);
         return ret;
     }
-    FXMAC_INFO("PHY_CONTROL_REG_OFFSET is %x \r\n", control);
+    FXMAC_INFO("PHY_CONTROL_REG_OFFSET is 0x%x.", control);
 
 
     control &= ~PHY_CONTROL_LINKSPEED_1000M;
@@ -274,48 +276,48 @@ static FError FXmacConfigureIeeePhySpeed(FXmac *instance_p, u32 phy_addr, u32 sp
     ret = FXmacPhyWrite(instance_p, phy_addr, PHY_CONTROL_REG_OFFSET, control); /* Technology Ability Field */
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,write PHY_AUTONEGO_ADVERTISE_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,write PHY_AUTONEGO_ADVERTISE_REG is error.", __func__, __LINE__);
         return ret;
     }
 
     for (wait = 0; wait < 100000; wait++)
         ;
 
-    FXMAC_INFO("Manual selection completed \r\n");
+    FXMAC_INFO("Manual selection completed.");
 
     ret = FXmacPhyRead(instance_p, phy_addr, PHY_SPECIFIC_STATUS_REG, &specific_reg);
     if (ret != FT_SUCCESS)
     {
-        FXMAC_ERROR("%s line is %d,read PHY_SPECIFIC_STATUS_REG is error", __func__, __LINE__);
+        FXMAC_ERROR("%s:%d,read PHY_SPECIFIC_STATUS_REG is error.", __func__, __LINE__);
         return ret;
     }
 
-    FXMAC_INFO("specific_reg is %x \r\n", specific_reg);
+    FXMAC_INFO("Specific reg is 0x%x.", specific_reg);
 
     if (specific_reg & (1 << 13))
     {
-        FXMAC_INFO("duplex is full \r\n");
+        FXMAC_INFO("Duplex is full.");
         instance_p->config.duplex = 1;
     }
     else
     {
-        FXMAC_INFO("duplex is half \r\n");
+        FXMAC_INFO("Duplex is half.");
         instance_p->config.duplex = 0;
     }
 
     if ((specific_reg & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_1000M)
     {
-        FXMAC_INFO("speed is 1000\r\n");
+        FXMAC_INFO("Speed is 1000M.");
         instance_p->config.speed = 1000;
     }
     else if ((specific_reg & 0xC000) == PHY_SPECIFIC_STATUS_SPEED_100M)
     {
-        FXMAC_INFO("speed is 100\r\n");
+        FXMAC_INFO("Speed is 100M.");
         instance_p->config.speed = 100;
     }
     else
     {
-        FXMAC_INFO("speed is 10\r\n");
+        FXMAC_INFO("Speed is 10M.");
         instance_p->config.speed = 10;
     }
 
@@ -341,10 +343,10 @@ FError FXmacPhyInit(FXmac *instance_p, u32 speed, u32 duplex_mode, u32 autonegot
 
     if (FXmacDetect(instance_p, &phy_addr) != FT_SUCCESS)
     {
-        FXMAC_ERROR("phy is not found");
+        FXMAC_ERROR("Phy is not found.");
         return FXMAC_PHY_IS_NOT_FOUND;
     }
-    FXMAC_INFO("settings phy_addr is %d\n", phy_addr);
+    FXMAC_INFO("Setting phy addr is %d.", phy_addr);
     instance_p->phy_address = phy_addr;
     if (autonegotiation_en)
     {
@@ -356,11 +358,11 @@ FError FXmacPhyInit(FXmac *instance_p, u32 speed, u32 duplex_mode, u32 autonegot
     }
     else
     {
-        FXMAC_INFO("Set the communication speed manually");
+        FXMAC_INFO("Set the communication speed manually.");
         ret = FXmacConfigureIeeePhySpeed(instance_p, phy_addr, speed, duplex_mode);
         if (ret != FT_SUCCESS)
         {
-            FXMAC_ERROR("Failed to manually set the PHY");
+            FXMAC_ERROR("Failed to manually set the phy.");
             return ret;
         }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.h
index 49c1e1de38b..b8f4b293b43 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_phy.h
@@ -14,21 +14,23 @@
  * FilePath: fxmac_phy.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for phy configuration.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef DRIVERS_ETH_FXMAC_PHY_H
-#define DRIVERS_ETH_FXMAC_PHY_H
+#ifndef FXMAC_PHY_H
+#define FXMAC_PHY_H
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_sinit.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_sinit.c
index 13a85920368..a9ac785158b 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_sinit.c
@@ -14,24 +14,25 @@
  * FilePath: fxmac_sinit.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for the implementation of the xmac driver's static
+ * initialization functionality.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "fxmac.h"
 #include "fparameters.h"
 
-extern const FXmacConfig fxmac_cfg_tbl[FT_XMAC_NUM];
+extern const FXmacConfig fxmac_cfg_tbl[FXMAC_NUM];
 
 const FXmacConfig *FXmacLookupConfig(u32 instance_id)
 {
     const FXmacConfig *cfg_ptr = NULL;
     u32 index;
-
-    for (index = 0; index < (u32)FT_XMAC_NUM; index++)
+    for (index = 0; index < (u32)FXMAC_NUM; index++)
     {
         if (fxmac_cfg_tbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/eth_ieee_reg.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/eth_ieee_reg.h
index 02ddcee2c0d..3851bdeefa3 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/eth_ieee_reg.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/eth_ieee_reg.h
@@ -14,23 +14,24 @@
  * FilePath: eth_ieee_reg.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for phys chip register definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
-#ifndef DRIVERS_ETH_PHY_IEEE_REG_H
-#define DRIVERS_ETH_PHY_IEEE_REG_H
+#ifndef ETH_IEEE_REG_H
+#define ETH_IEEE_REG_H
+
+/***************************** Include Files *********************************/
+#include "ferror_code.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
-/***************************** Include Files *********************************/
-
-#include "ferror_code.h"
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.c
index 9aeae51ed3b..83f7726dfbd 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.c
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.c
@@ -14,11 +14,12 @@
  * FilePath: phy_yt.c
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for  yt PHYs chip
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #include "phy_yt.h"
@@ -42,18 +43,18 @@ FError PhyYtCheckConnectStatus(void *instance_p, u32 phy_addr, EthPhyWrite write
     status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa001 to 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
     status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("read_p  0x1f failed");
+        PHY_YT_ERROR("Read 0x1f reg failed.");
         return FETH_PHY_ERR_READ;
     }
 
-    PHY_YT_INFO("phy_reg0 status is 0x%x", phy_reg0);
+    PHY_YT_INFO("Phy reg0 status is 0x%x", phy_reg0);
 
     return FT_SUCCESS;
 }
@@ -66,10 +67,10 @@ FError PhyYtSetLoopBack(void *instance_p, u32 phy_addr, EthPhyWrite write_p, Eth
     status = read_p(instance_p, phy_addr, 0, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("Error setup phy loopback");
+        PHY_YT_ERROR("Error setup phy loopback.");
         return FETH_PHY_ERR_READ;
     }
-    PHY_YT_INFO("0 phy_reg0 is 0x%x \r\n", phy_reg0);
+    PHY_YT_INFO("Phy reg 0 is 0x%x", phy_reg0);
     /*
      * Enable loopback
      */
@@ -79,17 +80,17 @@ FError PhyYtSetLoopBack(void *instance_p, u32 phy_addr, EthPhyWrite write_p, Eth
     status = read_p(instance_p, phy_addr, 0, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("Error setup phy loopback");
+        PHY_YT_ERROR("Error setup phy loopback.");
         return FETH_PHY_ERR_READ;
     }
 
     status = read_p(instance_p, phy_addr, 0, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("Error setup phy loopback");
+        PHY_YT_ERROR("Error setup phy loopback.");
         return FETH_PHY_ERR_READ;
     }
-    PHY_YT_INFO("after 0 phy_reg0 is 0x%x \r\n", phy_reg0);
+    PHY_YT_INFO("Phy reg 0 is 0x%x", phy_reg0);
 
     return FT_SUCCESS;
 }
@@ -104,7 +105,7 @@ FError PhyChangeModeToSgmii(void *instance_p, u32 phy_addr, EthPhyWrite write_p,
     status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa001 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
@@ -112,33 +113,32 @@ FError PhyChangeModeToSgmii(void *instance_p, u32 phy_addr, EthPhyWrite write_p,
     status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Read reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-    PHY_YT_INFO("default 0xa001 status is 0x%x \r\n", phy_reg0);
+    PHY_YT_INFO("Default 0x1f status is 0x%x", phy_reg0);
 
     /* change mode to sds */
     status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa001 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
     status = write_p(instance_p, phy_addr, 0x1f, 0x8063);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0x8063 to reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-
     /* read changged mode */
     status = write_p(instance_p, phy_addr, 0x1e, 0xa001);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa001 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
@@ -146,13 +146,11 @@ FError PhyChangeModeToSgmii(void *instance_p, u32 phy_addr, EthPhyWrite write_p,
     status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Read reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-    PHY_YT_INFO("changged 0xa001 status is 0x%x \r\n", phy_reg0);
-
-
+    PHY_YT_INFO("Read reg 0x1f status is 0x%x", phy_reg0);
 
     return FT_SUCCESS;
 }
@@ -162,60 +160,54 @@ FError PhyChangeModeToSds(void *instance_p, u32 phy_addr, EthPhyWrite write_p, E
     FError status;
     u16 phy_reg0 = 0;
 
-
     /* read default mode */
     status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa000 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
-
     status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Read reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-    PHY_YT_INFO("default status is 0x%x \r\n", phy_reg0);
+    PHY_YT_INFO("Read reg 0x1f status is 0x%x \r\n", phy_reg0);
 
     /* change mode to sds */
     status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa000 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
     status = write_p(instance_p, phy_addr, 0x1f, 0x2);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Write 0x02 to reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-
     /* read changged mode */
     status = write_p(instance_p, phy_addr, 0x1e, 0xa000);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("write_p 0xa000 to 0x1e failed");
+        PHY_YT_ERROR("Write 0xa000 to reg 0x1e failed.");
         return FETH_PHY_ERR_READ;
     }
 
-
     status = read_p(instance_p, phy_addr, 0x1f, &phy_reg0);
     if (status != FT_SUCCESS)
     {
-        PHY_YT_ERROR("read_p 0xa001 to 0x1e failed");
+        PHY_YT_ERROR("Read reg 0x1f failed.");
         return FETH_PHY_ERR_READ;
     }
 
-    PHY_YT_INFO("changged status is 0x%x \r\n", phy_reg0);
-
-
+    PHY_YT_INFO("Read reg 0x1f status is 0x%x \r\n", phy_reg0);
 
     return FT_SUCCESS;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.h
index 4640db8511a..e223120d1b2 100644
--- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.h
+++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/phy/yt/phy_yt.h
@@ -14,30 +14,32 @@
  * FilePath: phy_yt.h
  * Date: 2022-04-06 14:46:52
  * LastEditTime: 2022-04-06 14:46:58
- * Description:  This file is for
+ * Description:  This file is for yt PHYs chip.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/06/16    first release
  */
 
 #ifndef PHY_YT_H
 #define PHY_YT_H
 
+#include "ferror_code.h"
+#include "eth_ieee_reg.h"
+
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ferror_code.h"
-#include "eth_ieee_reg.h"
-
 #define FETH_PHY_ERR_READ FT_MAKE_ERRCODE(ErrModBsp, ErrEthPhy, 0x1u)
 
 FError PhyYtSetLoopBack(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
 FError PhyYtCheckConnectStatus(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
 FError PhyChangeModeToSds(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
 FError PhyChangeModeToSgmii(void *instance_p, u32 phy_addr, EthPhyWrite write_p, EthPhyRead read_p);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/Kconfig b/bsp/phytium/libraries/standalone/drivers/gic/Kconfig
index 1bf1dc91df4..9946994e6d4 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/gic/Kconfig
@@ -3,4 +3,4 @@
         prompt "Use Generic Interrupt Controller v3"
         default y
 
-
+	
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c
index b1fa4fb5820..a1c96c46ce4 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c
@@ -14,11 +14,12 @@
  * FilePath: fgic.c
  * Date: 2022-03-28 09:30:23
  * LastEditTime: 2022-03-28 09:30:24
- * Description:  This file is for
+ * Description: This file is for the minimum required function implementations for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
 
 #include "fgic.h"
@@ -77,7 +78,7 @@ static FError FGicWaitRwp(uintptr ctrl_base, WAIT_RWP_MODE wait_mode)
     }
     else
     {
-        FGIC_DEBUG_E(" wait_mode not in WAIT_RWP_MODE ");
+        FGIC_DEBUG_E(" wait_mode not in WAIT_RWP_MODE.");
         return FGIC_CTLR_ERR_TYPE;
     }
 
@@ -85,7 +86,7 @@ static FError FGicWaitRwp(uintptr ctrl_base, WAIT_RWP_MODE wait_mode)
     {
         if (timeout_cnt ++ >= 0xffffff)
         {
-            FGIC_DEBUG_E(" wait rwp timeout ");
+            FGIC_DEBUG_E(" Wait rwp timeout.");
             return FGIC_CTLR_ERR_IN_GET;
         }
     }
@@ -285,7 +286,7 @@ FError FGicIntEnable(FGic *instance_p, s32 int_id)
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicIntEnable");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicIntEnable.");
         return FGIC_CTLR_ERR_NUM;
     }
 
@@ -318,7 +319,7 @@ FError FGicIntDisable(FGic *instance_p, s32 int_id)
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicIntDisable");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicIntDisable.");
         return FGIC_CTLR_ERR_NUM;
     }
 
@@ -353,7 +354,7 @@ FError FGicSetPriority(FGic *instance_p, s32 int_id, u32 priority)
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicSetPriority");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicSetPriority.");
         return FGIC_CTLR_ERR_IN_GET;
     }
 
@@ -387,7 +388,7 @@ u32 FGicGetPriority(FGic *instance_p, s32 int_id)
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicGetPriority");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicGetPriority.");
         return (u32)FGIC_CTLR_ERR_IN_GET;
     }
 
@@ -420,7 +421,7 @@ FError FGicSetTriggerLevel(FGic *instance_p, s32 int_id, TRIGGER_LEVEL trigger_w
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicSetTriggerLevel");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicSetTriggerLevel.");
         return FGIC_CTLR_ERR_IN_SET;
     }
 
@@ -459,7 +460,7 @@ u32 FGicGetTriggerLevel(FGic *instance_p, s32 int_id)
 
     if (int_id > instance_p->max_spi_num)
     {
-        FGIC_DEBUG_E("int_id is over max spi num for FGicGetTriggerLevel");
+        FGIC_DEBUG_E("int_id is over max spi num for FGicGetTriggerLevel.");
         return (u32)FGIC_CTLR_ERR_IN_GET;
     }
 
@@ -501,7 +502,7 @@ FError FGicSetSpiAffinityRouting(FGic *instance_p, s32 int_id, SPI_ROUTING_MODE
 
     if ((int_id > instance_p->max_spi_num)  || (int_id <= FGIC_PPI_END_ID))
     {
-        FGIC_DEBUG_E("int_id %d is out of range ", int_id);
+        FGIC_DEBUG_E("int_id %d is out of range.", int_id);
         return FGIC_CTLR_ERR_IN_SET;
     }
 
@@ -532,7 +533,7 @@ FError FGicGetAffinityRouting(FGic *instance_p, s32 int_id, SPI_ROUTING_MODE *ro
 
     if ((int_id > instance_p->max_spi_num)  || (int_id <= FGIC_PPI_END_ID))
     {
-        FGIC_DEBUG_E("int_id %d is out of range ", int_id);
+        FGIC_DEBUG_E("int_id %d is out of range.", int_id);
         return (u32)FGIC_CTLR_ERR_IN_GET;
     }
 
@@ -562,7 +563,7 @@ FError FGicGenerateSgi(FGic *instance_p, s32 int_id, u32 target_list, SGI_ROUTIN
 
     if (int_id > FGIC_SGI_END_ID)
     {
-        FGIC_DEBUG_E("int_id %d is out of range ", int_id);
+        FGIC_DEBUG_E("int_id %d is out of range.", int_id);
         return FGIC_CTLR_ERR_IN_SET;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.h
index e08236e9160..383de430d5c 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.h
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.h
@@ -14,20 +14,25 @@
  * FilePath: fgic.h
  * Date: 2022-03-28 09:30:29
  * LastEditTime: 2022-03-28 09:30:29
- * Description:  This file is for
+ * Description: This file is for detailed description of the device and driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
 
-#ifndef DRIVERS_GIC_FGIC_H
-#define DRIVERS_GIC_FGIC_H
+#ifndef FGIC_H
+#define FGIC_H
 
 #include "ftypes.h"
 #include "ferror_code.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 #define FGIC_RSGI_AFF1_OFFSET 16
 #define FGIC_RSGI_AFF2_OFFSET 32
@@ -106,4 +111,8 @@ void FGicSetPriorityGroup(FGic *instance_p, u32 binary_point);
 u32 FGicGetPriorityFilter(FGic *instance_p);
 u32 FGicGetPriorityGroup(FGic *instance_p);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.S b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.S
index 2cc1d927a30..ecd1af8c47c 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.S
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.S
@@ -14,15 +14,15 @@
  * @FilePath: fgic_cpu_interface.S
  * @Date: 2022-03-29 18:04:23
  * @LastEditTime: 2022-03-29 18:04:27
- * @Description:  This file is for 
+ * @Description:  This file is Mapping of MSR and MRS to physical and virtual CPU interface registers.
  * 
- * @Modify History: 
+ * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
 
 
-
 #ifdef __aarch64__
 
 /*
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.h
index 9bcdd84c7d1..55350005524 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.h
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_cpu_interface.h
@@ -14,17 +14,24 @@
  * FilePath: fgic_cpu_interface.h
  * Date: 2022-03-28 14:55:27
  * LastEditTime: 2022-03-28 14:55:27
- * Description:  This file is for
+ * Description:  This file is for gic register definition and operation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
 
-#ifndef DRIVERS_CPU_INTERFACE_H
-#define DRIVERS_CPU_INTERFACE_H
+
+#ifndef FGIC_CPU_INTERFACE_H
+#define FGIC_CPU_INTERFACE_H
+
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 #define FGIC_ICC_SGI1R_INTID_MASK 0xFULL  /* The INTID of the SGI. */
 
@@ -99,18 +106,18 @@ void FGicSetICC_ASGI1R(u32 intnum, u32 target_list, GICC_SGIR_IRM_BITS mode, u64
 
 /* For AArch32 state,  accesses to GIC registers that are visible in the System register */
 #define FGIC_SYS_READ32(CR, Rt) __asm__ volatile("MRC " CR  \
-                                                 : "=r"(Rt) \
-                                                 :          \
-                                                 : "memory")
+        : "=r"(Rt) \
+        :          \
+        : "memory")
 #define FGIC_SYS_WRITE32(CR, Rt) __asm__ volatile("MCR " CR \
-                                                 :         \
-                                                 : "r"(Rt) \
-                                                 : "memory")
+        :         \
+        : "r"(Rt) \
+        : "memory")
 
 #define FGIC_SYS_WRITE64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" #cp ", " #op1 ", %Q0, %R0, c" #CRm \
-                                                      :                                           \
-                                                      : "r"(Rt)                                   \
-                                                      : "memory")
+        :                                           \
+        : "r"(Rt)                                   \
+        : "memory")
 
 
 #define ICC_IAR0 "p15, 0, %0, c12, c8, 0"
@@ -543,5 +550,9 @@ static inline void FGicSetICC_ASGI1R(u32 intnum_bit, u32 target_list, GICC_SGIR_
 
 #endif
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
 
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_distributor.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_distributor.h
index 1c163dd1fba..b2fe66fed6e 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_distributor.h
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_distributor.h
@@ -14,19 +14,26 @@
  * FilePath: fgic_distributor.h
  * Date: 2022-03-28 15:18:56
  * LastEditTime: 2022-03-28 15:18:56
- * Description:  This file is for
+ * Description: This file is for gic distributor implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
-#ifndef  DRIVERS_GIC_FGIC_DISTRIBUTOR_H
-#define  DRIVERS_GIC_FGIC_DISTRIBUTOR_H
+
+#ifndef  FGIC_DISTRIBUTOR_H
+#define  FGIC_DISTRIBUTOR_H
 
 #include "fgic.h"
 #include "fgic_hw.h"
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 #define GICD_ICFGR_MODE TRIGGER_LEVEL
 #define GICD_IRPITER_MODE SPI_ROUTING_MODE
 
@@ -162,4 +169,8 @@ static inline u32 FGicGetSpiSecurity(uintptr dist_base, u32 spi_id)
     return ((group_modifier << 1) | group_status);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif // !
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_g.c b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_g.c
index 3f40151fc7e..060e87806db 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_g.c
@@ -14,12 +14,14 @@
  * FilePath: fgic_g.c
  * Date: 2022-03-30 14:57:43
  * LastEditTime: 2022-03-30 14:57:43
- * Description:  This file is for
+ * Description:  This file is for gic static configuration implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
+
 #include "fparameters.h"
 #include "fgic.h"
 
@@ -27,6 +29,6 @@ FGicConfig fgic_config[FGIC_NUM] =
 {
     {
         .instance_id = 0,                          /* Id of device */
-        .dis_base = GICV3_DISTRIBUTOR_BASEADDRESS, /* Distributor base address      */
+        .dis_base = GICV3_DISTRIBUTOR_BASE_ADDR, /* Distributor base address      */
     }
 };
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h
index a8947ebbef0..aafc131c27d 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h
@@ -14,20 +14,26 @@
  * FilePath: fgic_hw.h
  * Date: 2022-03-24 11:44:48
  * LastEditTime: 2022-03-24 11:44:48
- * Description:  This file is for
+ * Description: This file is for gic register definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
 
-#ifndef DRIVERS_GIC_FGIC_HW_H
-#define DRIVERS_GIC_FGIC_HW_H
+#ifndef FGIC_HW_H
+#define FGIC_HW_H
 
 #include "ftypes.h"
 #include "fio.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /* Distributor */
 #define FGIC_GICD_CTLR_OFFSET 0x00000000U       /* Distributor Control Register ,RW */
 #define FGIC_GICD_TYPER_OFFSET 0x00000004U      /* Interrupt Controller Type Register ,RO */
@@ -312,4 +318,8 @@
 #define FGIC_GICR_NSACR_WRITE(sgi_base, reg) FGIC_WRITEREG32(sgi_base , FGIC_GICR_NSACR_OFFSET, reg)
 #define FGIC_GICR_NSACR_READ(sgi_base) FGIC_READREG32(sgi_base , FGIC_GICR_NSACR_OFFSET)
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_redistributor.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_redistributor.h
index 23f3bf147f8..b966c7d5f75 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_redistributor.h
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_redistributor.h
@@ -14,19 +14,25 @@
  * FilePath: fgic_redistributor.h
  * Date: 2022-03-28 14:57:01
  * LastEditTime: 2022-03-28 14:57:01
- * Description:  This file is for
+ * Description:  This file is for gic redistributor implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
-#ifndef  DRIVERS_GIC_FGIC_REDISTRIBUTOR_H
-#define  DRIVERS_GIC_FGIC_REDISTRIBUTOR_H
+
+#ifndef  FGIC_REDISTRIBUTOR_H
+#define  FGIC_REDISTRIBUTOR_H
 
 #include "fgic.h"
 #include "fgic_hw.h"
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 typedef enum
 {
@@ -169,5 +175,9 @@ static inline u32 FGicNonSecureAccessRead(uintptr redis_base)
     return FGIC_GICR_NSACR_READ(redis_base + FGIC_GICR_SGI_BASE_OFFSET);
 }
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
 
diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_sinit.c b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_sinit.c
index 28b9ce2b29c..2575462de0f 100644
--- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_sinit.c
@@ -14,12 +14,15 @@
  * FilePath: fgic_sinit.c
  * Date: 2022-03-30 15:00:29
  * LastEditTime: 2022-03-30 15:00:29
- * Description:  This file is for
+ * Description: This file is for gic static variables implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/4/16   init commit
  */
+
+
 #include "fgic.h"
 
 extern FGicConfig fgic_config[FGIC_NUM];
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/Kconfig b/bsp/phytium/libraries/standalone/drivers/i2c/Kconfig
index 6f34251dd24..1195673525e 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/Kconfig
@@ -4,5 +4,5 @@ config USE_FI2C
     default n
     help
         Include FI2C driver component
-
-
+	
+	
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.c
index 43899808a80..f76e77bcf11 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fi2c.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:58
- * Description:  This files is for
+ * Description:  This file is for complete user external interface
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/2/18  modified to support i2c
  */
 
 
@@ -50,20 +52,12 @@ static const char *FI2C_ERROR_CODE_MSG[FI2C_NUM_OF_ERR_CODE] =
 {
     "FI2C_SUCCESS : fi2c success",
     "FI2C_ERR_INVAL_PARM : fi2c invalid input parameters",
-    "FI2C_ERR_NOT_READY : fi2c driver not ready",
+    "FI2C_ERR_NOT_READY : fi2c driver is not ready",
     "FI2C_ERR_TIMEOUT : fi2c wait timeout",
-    "FI2C_ERR_NOT_SUPPORT : fi2c non support operation",
+    "FI2C_ERR_NOT_SUPPORT : fi2c not support operation",
     "FI2C_ERR_INVAL_STATE : fi2c invalid state"
 };
 
-/*****************************************************************************/
-
-/* 此文件主要为了完成用户对外接口，用户可以使用这些接口直接开始工作 */
-
-/* - 包括用户API的定义和实现
-   - 同时包含必要的OPTION方法，方便用户进行配置
-   - 如果驱动可以直接进行I/O操作，在此源文件下可以将API 进行实现 */
-
 /**
  * @name: FI2cCfgInitialize
  * @msg: 完成I2C驱动实例的初始化，使之可以使用
@@ -86,7 +80,7 @@ FError FI2cCfgInitialize(FI2c *instance_p, const FI2cConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FI2C_ERROR("device is already initialized!!!");
+        FI2C_ERROR("Device is already initialized!!!");
         return FI2C_ERR_INVAL_STATE;
     }
 
@@ -164,11 +158,15 @@ static FError FI2cReset(FI2c *instance_p)
     ret = FI2cSetSpeed(base_addr, config_p->speed_rate);
 
     if (FI2C_SUCCESS == ret)
-        ret = FI2cSetEnable(base_addr, TRUE); /* enable i2c ctrl */
+    {
+        ret = FI2cSetEnable(base_addr, TRUE);    /* enable i2c ctrl */
+    }
 
     /* if init successed, and i2c is in slave mode, set slave address */
     if ((FI2C_SUCCESS == ret) && (FI2C_SLAVE == config_p->work_mode))
+    {
         ret = FI2cSetSar(base_addr, config_p->slave_addr);
+    }
 
     return ret;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.h b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.h
index 505b310f85a..9ab4c590da7 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.h
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c.h
@@ -12,24 +12,21 @@
  *
  *
  * FilePath: fi2c.h
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:37:04
- * Description:  This files is for
+ * Description:  This file is for complete user external interface definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/2/18  modified to support i2c
  */
 
 
 
-#ifndef  DRIVERS_I2C_FI2C_H
-#define  DRIVERS_I2C_FI2C_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FI2C_H
+#define  FI2C_H
 
 /***************************** Include Files *********************************/
 
@@ -37,6 +34,12 @@ extern "C"
 #include "fassert.h"
 #include "ferror_code.h"
 #include "sdkconfig.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 #define FI2C_SUCCESS          FT_SUCCESS
 #define FI2C_ERR_INVAL_PARM   FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 1)
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_g.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_g.c
index 92e122f0ad9..3c1db4baac0 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_g.c
@@ -14,11 +14,13 @@
  * FilePath: fi2c_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:36:14
- * Description:  This files is for
+ * Description:  This file is for I2C static configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/02/18  add e2000 configs
  */
 
 
@@ -44,100 +46,59 @@
  * @name: FI2C_CONFIG_TBL
  * @msg: I2C驱动的默认配置参数
  */
-#if defined(CONFIG_TARGET_E2000)
-const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
+const FI2cConfig FI2C_CONFIG_TBL[FI2C_NUM] =
 {
-    [I2C_INSTANCE_0] =
+    [FI2C0_ID] =
     {
-        .instance_id = I2C_INSTANCE_0,
-        .base_addr = I2C_0_BASEADDR,
-        .irq_num = I2C_0_INTR_IRQ,
+        .instance_id = FI2C0_ID,
+        .base_addr = FI2C0_BASE_ADDR,
+        .irq_num = FI2C0_IRQ_NUM,
         .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
+        .ref_clk_hz = FI2C_CLK_FREQ_HZ,
         .work_mode = FI2C_MASTER,
         .slave_addr = 0,
         .use_7bit_addr = TRUE,
         .speed_rate = FI2C_SPEED_STANDARD_RATE
     },
-    [I2C_INSTANCE_1] =
+#if defined(CONFIG_TARGET_E2000) || defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4) 
+    [FI2C1_ID] =
     {
-        .instance_id = I2C_INSTANCE_1,
-        .base_addr = I2C_1_BASEADDR,
-        .irq_num = I2C_1_INTR_IRQ,
+        .instance_id  = FI2C1_ID,
+        .base_addr = FI2C1_BASE_ADDR,
+        .irq_num  = FI2C1_IRQ_NUM,
         .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
+        .ref_clk_hz = FI2C_CLK_FREQ_HZ,
         .work_mode = FI2C_MASTER,
         .slave_addr = 0,
         .use_7bit_addr = TRUE,
         .speed_rate = FI2C_SPEED_STANDARD_RATE
     },
 
-    [I2C_INSTANCE_2] =
+    [FI2C2_ID] =
     {
-        .instance_id = I2C_INSTANCE_2,
-        .base_addr = I2C_2_BASEADDR,
-        .irq_num = I2C_2_INTR_IRQ,
+        .instance_id  = FI2C2_ID,
+        .base_addr = FI2C2_BASE_ADDR,
+        .irq_num  = FI2C2_IRQ_NUM,
         .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
-        .work_mode = FI2C_MASTER,
-        .slave_addr = 0,
-        .use_7bit_addr = TRUE,
-        .speed_rate = FI2C_SPEED_STANDARD_RATE
-    }
-};
-#endif
-
-#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4)
-const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM] =
-{
-    [I2C_INSTANCE_0] =
-    {
-        .instance_id  = I2C_INSTANCE_0,
-        .base_addr = I2C_0_BASEADDR,
-        .irq_num  = I2C_0_INTR_IRQ,
-        .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
-        .work_mode = FI2C_MASTER,
-        .slave_addr = 0,
-        .use_7bit_addr = TRUE,
-        .speed_rate = FI2C_SPEED_STANDARD_RATE
-    },
-    [I2C_INSTANCE_1] =
-    {
-        .instance_id  = I2C_INSTANCE_1,
-        .base_addr = I2C_1_BASEADDR,
-        .irq_num  = I2C_1_INTR_IRQ,
-        .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
-        .work_mode = FI2C_MASTER,
-        .slave_addr = 0,
-        .use_7bit_addr = TRUE,
-        .speed_rate = FI2C_SPEED_STANDARD_RATE
-    },
-
-    [I2C_INSTANCE_2] =
-    {
-        .instance_id  = I2C_INSTANCE_2,
-        .base_addr = I2C_2_BASEADDR,
-        .irq_num  = I2C_2_INTR_IRQ,
-        .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
+        .ref_clk_hz = FI2C_CLK_FREQ_HZ,
         .work_mode = FI2C_MASTER,
         .slave_addr = 0,
         .use_7bit_addr = TRUE,
         .speed_rate = FI2C_SPEED_STANDARD_RATE
     },
-    [I2C_INSTANCE_3] =
+#endif      
+#if defined(CONFIG_TARGET_D2000) || defined(CONFIG_TARGET_F2000_4) 
+    [FI2C3_ID] =
     {
-        .instance_id  = I2C_INSTANCE_3,
-        .base_addr = I2C_3_BASEADDR,
-        .irq_num  = I2C_3_INTR_IRQ,
+        .instance_id  = FI2C3_ID,
+        .base_addr = FI2C3_BASE_ADDR,
+        .irq_num  = FI2C3_IRQ_NUM,
         .irq_prority = 0,
-        .ref_clk_hz = I2C_REF_CLK_HZ,
+        .ref_clk_hz = FI2C_CLK_FREQ_HZ,
         .work_mode = FI2C_MASTER,
         .slave_addr = 0,
         .use_7bit_addr = TRUE,
         .speed_rate = FI2C_SPEED_STANDARD_RATE
     }
+#endif    
 };
-#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.c
index 6ce4679b144..efe7926ae32 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fi2c_hw.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:22
- * Description:  This files is for
+ * Description:  This file is for I2C register read/write operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/02/18  support slave mode
  */
 
 /***************************** Include Files *********************************/
@@ -102,7 +104,7 @@ FError FI2cSetEnable(uintptr addr, boolean enable)
     }
     while (0 != timeout--);
 
-    FI2C_ERROR("timeout in %sabling I2C ctrl", enable ? "en" : "dis");
+    FI2C_ERROR("Timeout in %sabling I2C ctrl.", enable ? "en" : "dis");
     return FI2C_ERR_TIMEOUT;
 }
 
@@ -193,11 +195,17 @@ static FError FI2cCalcSpeedCfg(uintptr addr, u32 speed, u32 bus_clk_hz, FI2cSpee
     u32 spk_cnt = 0;
 
     if (FI2C_SPEED_FAST_RATE <= speed)
+    {
         speed_cfg_p->speed_mode = FI2C_FAST_SPEED;
+    }
     else if (FI2C_SPEED_STANDARD_RATE <= speed)
+    {
         speed_cfg_p->speed_mode = FI2C_STANDARD_SPEED;
+    }
     else
+    {
         return FI2C_ERR_INVAL_PARM;
+    }
 
     spk_cnt = FI2C_READ_REG32(addr, FI2C_FS_SPKLEN_OFFSET);
     return FI2cCalcTiming(bus_clk_hz, spk_cnt, speed_cfg_p);
@@ -218,9 +226,11 @@ FError FI2cSetSpeed(uintptr addr, u32 speed_rate)
     u32 reg_val;
 
     memset(&speed_cfg, 0, sizeof(speed_cfg));
-    ret = FI2cCalcSpeedCfg(addr, speed_rate, I2C_REF_CLK_HZ, &speed_cfg);
+    ret = FI2cCalcSpeedCfg(addr, speed_rate, FI2C_CLK_FREQ_HZ, &speed_cfg);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* get enable setting for restore later */
     enable_status = FI2cGetEnable(addr);
@@ -229,26 +239,28 @@ FError FI2cSetSpeed(uintptr addr, u32 speed_rate)
     reg_val = ((FI2C_READ_REG32(addr, FI2C_CON_OFFSET)) & (~FI2C_CON_SPEED_MASK));
     switch (speed_cfg.speed_mode)
     {
-    case FI2C_STANDARD_SPEED:
-        reg_val |= FI2C_CON_STD_SPEED;
-        FI2C_WRITE_REG32(addr, FI2C_SS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
-        FI2C_WRITE_REG32(addr, FI2C_SS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
-        break;
-    case FI2C_FAST_SPEED:
-        reg_val |= FI2C_CON_FAST_SPEED;
-        FI2C_WRITE_REG32(addr, FI2C_FS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
-        FI2C_WRITE_REG32(addr, FI2C_FS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
-        break;
-    default:
-        ret |= FI2C_ERR_INVAL_PARM;
-        break;
+        case FI2C_STANDARD_SPEED:
+            reg_val |= FI2C_CON_STD_SPEED;
+            FI2C_WRITE_REG32(addr, FI2C_SS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
+            FI2C_WRITE_REG32(addr, FI2C_SS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
+            break;
+        case FI2C_FAST_SPEED:
+            reg_val |= FI2C_CON_FAST_SPEED;
+            FI2C_WRITE_REG32(addr, FI2C_FS_SCL_HCNT_OFFSET, speed_cfg.scl_hcnt);
+            FI2C_WRITE_REG32(addr, FI2C_FS_SCL_LCNT_OFFSET, speed_cfg.scl_lcnt);
+            break;
+        default:
+            ret |= FI2C_ERR_INVAL_PARM;
+            break;
     }
 
     FI2C_WRITE_REG32(addr, FI2C_CON_OFFSET, reg_val);
 
     /* Configure SDA Hold Time if required */
     if (0 != speed_cfg.sda_hold)
+    {
         FI2C_WRITE_REG32(addr, FI2C_SDA_HOLD_OFFSET, speed_cfg.sda_hold);
+    }
 
     /* Restore back i2c now speed set */
     if (FI2C_IC_ENABLE == enable_status)
@@ -279,7 +291,7 @@ FError FI2cWaitStatus(uintptr addr, u32 stat_bit)
 
     if (FI2C_TIMEOUT <= timeout)
     {
-        FI2C_ERROR("timeout when wait status: 0x%x", stat_bit);
+        FI2C_ERROR("Timeout when wait status: 0x%x.", stat_bit);
         return FI2C_ERR_TIMEOUT;
     }
 
@@ -298,10 +310,10 @@ FError FI2cWaitBusBusy(uintptr addr)
     u32 ret = FI2C_SUCCESS;
 
     if (((FI2C_READ_REG32(addr, FI2C_STATUS_OFFSET)) & FI2C_STATUS_MST_ACTIVITY) &&
-            (FI2C_SUCCESS != FI2cWaitStatus(addr, FI2C_STATUS_TFE)))
+        (FI2C_SUCCESS != FI2cWaitStatus(addr, FI2C_STATUS_TFE)))
     {
         ret = FI2C_ERR_TIMEOUT;
-        FI2C_ERROR("timeout when wait i2c bus busy");
+        FI2C_ERROR("Timeout when wait i2c bus busy.");
     }
 
     return ret;
@@ -321,13 +333,19 @@ FError FI2cSetTar(uintptr addr, u32 tar_addr)
     u32 reg_val = 0;
 
     if (FI2C_IC_ENABLE == enable_status)
+    {
         ret = FI2cSetEnable(addr, FALSE);
+    }
 
     if (FI2C_SUCCESS == ret)
+    {
         FI2C_WRITE_REG32(addr, FI2C_TAR_OFFSET, (tar_addr & FI2C_IC_TAR_MASK));
+    }
 
     if (FI2C_IC_ENABLE == enable_status)
+    {
         ret = FI2cSetEnable(addr, TRUE);
+    }
 
     return ret;
 }
@@ -346,13 +364,19 @@ FError FI2cSetSar(uintptr addr, u32 sar_addr)
     u32 reg_val = 0;
 
     if (FI2C_IC_ENABLE == enable_status)
+    {
         ret = FI2cSetEnable(addr, FALSE);
+    }
 
     if (FI2C_SUCCESS == ret)
+    {
         FI2C_WRITE_REG32(addr, FI2C_SAR_OFFSET, (sar_addr & FI2C_IC_SAR_MASK));
+    }
 
     if (FI2C_IC_ENABLE == enable_status)
+    {
         ret = FI2cSetEnable(addr, TRUE);
+    }
 
     return ret;
 }
@@ -377,7 +401,7 @@ FError FI2cFlushRxFifo(uintptr addr)
         if (FI2C_TIMEOUT < ++timeout)
         {
             ret = FI2C_TIMEOUT;
-            FI2C_ERROR("timeout when flush fifo");
+            FI2C_ERROR("Timeout when flush fifo.");
             break;
         }
     }
@@ -406,28 +430,44 @@ u32 FI2cClearIntrBits(uintptr addr, u32 *last_err_p)
     }
 
     if (stat & FI2C_INTR_RX_UNDER)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_RX_UNDER_OFFSET);
+    }
 
     if (stat & FI2C_INTR_RX_OVER)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_RX_OVER_OFFSET);
+    }
 
     if (stat & FI2C_INTR_TX_OVER)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_TX_OVER_OFFSET);
+    }
 
     if (stat & FI2C_INTR_RX_DONE)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_RX_DONE_OFFSET);
+    }
 
     if (stat & FI2C_INTR_ACTIVITY)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_ACTIVITY_OFFSET);
+    }
 
     if (stat & FI2C_INTR_STOP_DET)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_STOP_DET_OFFSET);
+    }
 
     if (stat & FI2C_INTR_START_DET)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_START_DET_OFFSET);
+    }
 
     if (stat & FI2C_INTR_GEN_CALL)
+    {
         FI2C_READ_REG32(addr, FI2C_CLR_GEN_CALL_OFFSET);
+    }
 
     return stat;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.h b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.h
index 1a39e679682..d082045b23c 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_hw.h
@@ -12,18 +12,20 @@
  *
  *
  * FilePath: fi2c_hw.h
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:32
- * Description:  This files is for
+ * Description:  This file is for I2C register definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/02/18  add fi2c_slave mode
  */
 
 
-#ifndef DRIVERS_I2C_FI2C_HW_H
-#define DRIVERS_I2C_FI2C_HW_H
+#ifndef FI2C_HW_H
+#define FI2C_HW_H
 
 /* - 传入模块基地址，不能复杂结构体
 - hardware interface of device || low-level driver function prototypes
@@ -34,10 +36,6 @@
 3. 一些简单外设提供直接操作接口
 4. 可以定义一些状态的接口，用于响应驱动状态的变化 */
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 /***************************** Include Files *********************************/
 
 #include "fparameters.h"
@@ -45,6 +43,11 @@ extern "C"
 #include "ferror_code.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 
 /** @name Register Map
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_intr.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_intr.c
index 85ebbd2af14..32ad762321e 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_intr.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fi2c_intr.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:38
- * Description:  This files is for
+ * Description:  This file is for I2C interrupt operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/02/18  add fi2c_master interrupt and support slave mode
  */
 
 /***************************** Include Files *********************************/
@@ -117,7 +119,7 @@ static void FI2cMasterIntrTxEmptyHandler(FI2c *instance_p)
                           FI2C_DATA_CMD_WRITE |
                           FI2C_DATA_CMD_STOP;
                 instance_p->txframe.data_buff++;
-                FI2C_INFO("Write Stop Singal");
+                FI2C_INFO("Write Stop Singal.");
             }
             else if (instance_p->status == STATUS_READ_IN_PROGRESS)
             {
@@ -265,7 +267,7 @@ u32 FI2cGetIntr(FI2c *instance_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
 
@@ -287,13 +289,13 @@ FError FI2cMasterSetupIntr(FI2c *instance_p, u32 mask)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
 
     if (FI2C_MASTER != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be master");
+        FI2C_ERROR("i2c work mode shall be master.");
         return FI2C_ERR_INVAL_STATE;
     }
 
@@ -417,13 +419,13 @@ FError FI2cSlaveSetupIntr(FI2c *instance_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
 
     if (FI2C_SLAVE != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be slave");
+        FI2C_ERROR("i2c work mode shall be slave.");
         return FI2C_ERR_INVAL_STATE;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_master.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_master.c
index 49afc9cbc3c..da45d42a31d 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_master.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_master.c
@@ -12,23 +12,17 @@
  *
  *
  * FilePath: fi2c_master.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:46
- * Description:  This files is for
+ * Description:  This file is for i2c master drivers
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
+ * 1.1  liushengming 2022/2/18  add poll mode and intr mode
  */
 
-
-/*
-    - 一些驱动模块，直接操作硬件的I/O接口，无法实现有意义的操作，此时需要针对中间件或者用户使用习惯设计此模块 （i2c,nand,eth）
-    - 部分场景适用, 分角色的 I/O 操作
-    - 此模块的函数原型，在fooxx.h 中声明一次，方便用户或者中间件层调用
-
-*/
-
 /***************************** Include Files *********************************/
 
 #include "fio.h"
@@ -36,7 +30,6 @@
 #include "fdebug.h"
 #include "fi2c_hw.h"
 #include "fi2c.h"
-#include "finterrupt.h"
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -72,15 +65,21 @@ static FError FI2cMasterStartTrans(FI2c *instance_p, u32 mem_addr, u8 mem_byte_l
 
     ret = FI2cWaitBusBusy(base_addr);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     ret = FI2cSetTar(base_addr, instance_p->config.slave_addr); /* 设备地址 */
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     while (addr_len)
     {
         ret = FI2cWaitStatus(base_addr, FI2C_STATUS_TFNF);
         if (FI2C_SUCCESS != ret)
+        {
             break;
+        }
         if (FI2C_GET_STATUS(base_addr) & FI2C_STATUS_TFNF)
         {
             addr_len--;
@@ -131,7 +130,9 @@ static FError FI2cMasterStopTrans(FI2c *instance_p)
 
     ret = FI2cWaitBusBusy(base_addr);
     if (FI2C_SUCCESS == ret)
+    {
         ret = FI2cFlushRxFifo(base_addr);
+    }
 
     return ret;
 }
@@ -160,19 +161,21 @@ FError FI2cMasterReadPoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
 
     if (FI2C_MASTER != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be master");
+        FI2C_ERROR("i2c work mode shall be master.");
         return FI2C_ERR_INVAL_STATE;
     }
 
     ret = FI2cMasterStartTrans(instance_p, mem_addr, mem_byte_len, FI2C_DATA_CMD_WRITE);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     /*for trigger rx intr*/
     while (tx_len > 0 || rx_len > 0)
     {
@@ -214,7 +217,7 @@ FError FI2cMasterReadPoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
             else if (FI2C_TIMEOUT < (++trans_timeout))
             {
                 ret = FI2C_ERR_TIMEOUT;
-                FI2C_ERROR("timeout in i2c master read");
+                FI2C_ERROR("timeout in i2c master read.");
                 break;
             }
         }
@@ -248,18 +251,20 @@ FError FI2cMasterWritePoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
     if (FI2C_MASTER != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be master");
+        FI2C_ERROR("i2c work mode shall be master.");
         return FI2C_ERR_INVAL_STATE;
     }
 
     ret = FI2cMasterStartTrans(instance_p, mem_addr, mem_byte_len, FI2C_DATA_CMD_WRITE);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     while (buf_idx)
     {
         tx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_TXFLR_OFFSET);
@@ -272,7 +277,7 @@ FError FI2cMasterWritePoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
                     reg_val = (FI2C_DATA_MASK & *buf_p) |
                               FI2C_DATA_CMD_WRITE |
                               FI2C_DATA_CMD_STOP;
-                    FI2C_INFO("Write Stop Singal");
+                    FI2C_INFO("Write Stop Singal.");
                 }
                 else
                 {
@@ -288,7 +293,7 @@ FError FI2cMasterWritePoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
             else if (FI2C_TIMEOUT < ++trans_timeout)
             {
                 ret = FI2C_ERR_TIMEOUT;
-                FI2C_ERROR("timeout in i2c master write");
+                FI2C_ERROR("Timeout in i2c master write.");
                 break;
             }
         }
@@ -320,12 +325,12 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
     if (FI2C_MASTER != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be master");
+        FI2C_ERROR("i2c work mode shall be master.");
         return FI2C_ERR_INVAL_STATE;
     }
 
@@ -336,7 +341,7 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
         if (FI2C_TIMEOUT < (++trans_timeout))
         {
             ret = FI2C_ERR_TIMEOUT;
-            FI2C_ERROR("timeout in i2c master read intr.");
+            FI2C_ERROR("Timeout in i2c master read intr.");
             break;
         }
     }
@@ -348,12 +353,16 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
     ret = FI2cMasterStartTrans(instance_p, mem_addr, mem_byte_len, FI2C_DATA_CMD_WRITE);
     instance_p->status = STATUS_READ_IN_PROGRESS;
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     mask = FI2C_GET_INTRRUPT_MASK(instance_p->config.base_addr);
     mask |= FI2C_INTR_MASTER_RD_MASK;
     ret = FI2cMasterSetupIntr(instance_p, mask);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     return ret;
 }
 
@@ -375,13 +384,13 @@ FError FI2cMasterWriteIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
     u32 trans_timeout = 0;
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FI2C_ERROR("i2c driver not ready");
+        FI2C_ERROR("i2c driver is not ready.");
         return FI2C_ERR_NOT_READY;
     }
 
     if (FI2C_MASTER != instance_p->config.work_mode)
     {
-        FI2C_ERROR("i2c work mode shall be master");
+        FI2C_ERROR("i2c work mode shall be master.");
         return FI2C_ERR_INVAL_STATE;
     }
     while (instance_p->status != STATUS_IDLE)
@@ -391,7 +400,7 @@ FError FI2cMasterWriteIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
         if (FI2C_TIMEOUT < (++trans_timeout))
         {
             ret = FI2C_ERR_TIMEOUT;
-            FI2C_ERROR("timeout in i2c master write intr.");
+            FI2C_ERROR("Timeout in i2c master write intr.");
             break;
         }
     }
@@ -400,12 +409,16 @@ FError FI2cMasterWriteIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
     instance_p->txframe.tx_cnt = 0;
     ret = FI2cMasterStartTrans(instance_p, mem_addr, mem_byte_len, FI2C_DATA_CMD_WRITE);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     instance_p->status = STATUS_WRITE_IN_PROGRESS;
     mask = FI2C_GET_INTRRUPT_MASK(instance_p->config.base_addr);
     mask |= FI2C_INTR_MASTER_WR_MASK;
     ret = FI2cMasterSetupIntr(instance_p, mask);
     if (FI2C_SUCCESS != ret)
+    {
         return ret;
+    }
     return ret;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_sinit.c b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_sinit.c
index 8ea6a12dec0..03c4e69b8da 100644
--- a/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/i2c/fi2c/fi2c_sinit.c
@@ -12,20 +12,16 @@
  *
  *
  * FilePath: fi2c_sinit.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-01 14:53:42
  * LastEditTime: 2022-02-18 08:36:52
- * Description:  This files is for
+ * Description:  This file is for implementation of driver's static initialization functionality
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  zhugengyu 2021/11/1  first commit
  */
 
-
-
-/* - This file contains the implementation of driver's static initialization functionality.
-- 驱动静态初始化  */
-
 /***************************** Include Files *********************************/
 
 #include "ftypes.h"
@@ -40,7 +36,7 @@
 
 /************************** Variable Definitions *****************************/
 
-extern const FI2cConfig FI2C_CONFIG_TBL[I2C_INSTANCE_NUM];
+extern const FI2cConfig FI2C_CONFIG_TBL[FI2C_NUM];
 /************************** Function Prototypes ******************************/
 /**
  * @name: FI2cLookupConfig
@@ -53,7 +49,7 @@ const FI2cConfig *FI2cLookupConfig(u32 instance_id)
     const FI2cConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)I2C_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FI2C_NUM; index++)
     {
         if (FI2C_CONFIG_TBL[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig b/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig
index 92b76a91f68..2012b165d23 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig
@@ -5,5 +5,5 @@ config ENABLE_FSEMAPHORE
     depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q
     help
         Select FSemaphore driver component
-
-
+	
+	
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.c b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.c
index 6409551a3a8..e74a1fa2ba0 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.c
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.c
@@ -14,7 +14,7 @@
  * FilePath: fsemaphore.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for semaphore user api implmentation
+ * Description:  This file is for semaphore user api implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -62,21 +62,25 @@ FError FSemaCfgInitialize(FSema *const instance, const FSemaConfig *input_config
 {
     FASSERT(instance && input_config);
     uintptr base_addr = input_config->base_addr;
-    FASSERT_MSG((0 != base_addr), "invalid base addr");
+    FASSERT_MSG((0 != base_addr), "invalid base addr.");
     FError ret = FSEMA_SUCCESS;
 
     if (FT_COMPONENT_IS_READY == instance->is_ready)
     {
-        FSEMA_WARN("device is already initialized!!!");
+        FSEMA_WARN("Device is already initialized!!!");
     }
 
     if (&instance->config != input_config)
+    {
         instance->config = *input_config;
+    }
 
     FSemaHwResetAll(base_addr); /* 重置所有的锁 */
 
     if (FSEMA_SUCCESS == ret)
+    {
         instance->is_ready = FT_COMPONENT_IS_READY;
+    }
 
     return ret;
 }
@@ -127,7 +131,7 @@ FError FSemaCreateLocker(FSema *const instance, FSemaLocker *const locker)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
@@ -136,14 +140,14 @@ FError FSemaCreateLocker(FSema *const instance, FSemaLocker *const locker)
         /* 分配一把未创建的锁 */
         if (NULL == instance->locker[locker_idx])
         {
-            FSEMA_INFO("allocate locker %d", locker_idx);
+            FSEMA_INFO("Allocate locker %d.", locker_idx);
             break;
         }
     }
 
     if (locker_idx >= FSEMA_NUM_OF_LOCKER)
     {
-        FSEMA_ERROR("no locker available !!!");
+        FSEMA_ERROR("No locker available !!!");
         return FSEMA_ERR_NO_AVAILABLE_LOCKER; /* 所有的锁都已经分配创建 */
     }
 
@@ -176,7 +180,7 @@ FError FSemaTryLock(FSemaLocker *const locker, u32 owner, u32 try_times, FSemaRe
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
@@ -185,10 +189,14 @@ FError FSemaTryLock(FSemaLocker *const locker, u32 owner, u32 try_times, FSemaRe
         /* 尝试获取锁 */
         lock_success = FSemaTryLockOnce(base_addr, locker->index);
         if (TRUE == lock_success)
+        {
             break;
+        }
 
         if (relax_handler)
+        {
             relax_handler(instance);
+        }
 
         try_times--;
     }
@@ -196,12 +204,12 @@ FError FSemaTryLock(FSemaLocker *const locker, u32 owner, u32 try_times, FSemaRe
     if (FALSE == lock_success)
     {
         ret = FSEMA_ERR_LOCK_TIMEOUT;
-        FSEMA_ERROR("locker-%d has been taken by owner 0x%x", locker->index, locker->owner);
+        FSEMA_ERROR("locker-%d has been taken by owner 0x%x.", locker->index, locker->owner);
     }
     else
     {
         locker->owner = owner; /* 记录当前locker的owner */
-        FSEMA_INFO("locker-%d taken success by owner 0x%x", locker->index, owner);
+        FSEMA_INFO("locker-%d  is taken successfully by owner 0x%x.", locker->index, owner);
     }
 
     return ret;
@@ -224,7 +232,7 @@ FError FSemaUnlock(FSemaLocker *const locker, u32 owner)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
@@ -263,7 +271,7 @@ FError FSemaUnlockAll(FSema *const instance)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
@@ -295,17 +303,17 @@ FError FSemaDeleteLocker(FSemaLocker *const locker)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
     if (TRUE == FSemaHwGetStatus(base_addr, locker_idx))
     {
-        FSEMA_WARN("caution, locker-%d has been taken by 0x%x !!!",
+        FSEMA_WARN("Caution, locker-%d has been taken by 0x%x !!!",
                    locker_idx, locker->owner);
     }
 
-    FASSERT_MSG((instance->locker[locker_idx] == locker), "invalid locker index %d", locker_idx);
+    FASSERT_MSG((instance->locker[locker_idx] == locker), "invalid locker index %d.", locker_idx);
 
     FSemaWriteReg(base_addr, FSEMA_RLOCK_X_REG_OFFSET(locker->index), FSEMA_RLOCK_X_UNLOCK); /* 写0解锁信号量 */
 
@@ -329,7 +337,7 @@ boolean FSemaIsLocked(FSemaLocker *locker)
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FSEMA_ERROR("device@%p not yet inited !!!", instance->config.base_addr);
+        FSEMA_ERROR("Device@%p is not yet inited !!!", instance->config.base_addr);
         return FSEMA_ERR_NOT_INIT;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.h b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.h
index 361234d1e5e..986fffe1326 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.h
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore.h
@@ -14,7 +14,7 @@
  * FilePath: fsemaphore.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:35
- * Description:  This files is for semaphore user api definition
+ * Description:  This file is for semaphore user api definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -23,18 +23,19 @@
  */
 
 
-#ifndef  DRIVERS_IPC_FSEMAPHORE_H
-#define  DRIVERS_IPC_FSEMAPHORE_H
+#ifndef  FSEMAPHORE_H
+#define  FSEMAPHORE_H
+
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+#include "ferror_code.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-#include "ftypes.h"
-#include "ferror_code.h"
-
 /************************** Constant Definitions *****************************/
 #define FSEMA_NUM_OF_LOCKER             32U
 #define FSEMA_OWNER_NONE                0U
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_g.c b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_g.c
index 1ee775f7d1f..c715ce16300 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_g.c
@@ -14,7 +14,7 @@
  * FilePath: fsemaphore_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:09
- * Description:  This files is for semaphore static variables
+ * Description:  This file is for semaphore static variables
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_hw.h b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_hw.h
index d70e93ebf5d..1266a4fdafe 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_hw.h
@@ -14,7 +14,7 @@
  * FilePath: fsemaphore_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:24:52
- * Description:  This files is for semaphore register definition
+ * Description:  This file is for semaphore register definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -23,13 +23,8 @@
  */
 
 
-#ifndef  DRIVERS_IPC_FSEMAPHORE_HW_H
-#define  DRIVERS_IPC_FSEMAPHORE_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FSEMAPHORE_HW_H
+#define  FSEMAPHORE_HW_H
 /***************************** Include Files *********************************/
 
 #include "fparameters.h"
@@ -38,6 +33,11 @@ extern "C"
 #include "fassert.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 /** @name Register Map
  *
diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_sinit.c b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_sinit.c
index 4e52d6fd1a8..2563566b697 100644
--- a/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/ipc/fsemaphore/fsemaphore_sinit.c
@@ -14,7 +14,7 @@
  * FilePath: fsemaphore_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:15
- * Description:  This files is for semaphore static init
+ * Description:  This file is for semaphore static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
diff --git a/bsp/phytium/libraries/standalone/drivers/media/Kconfig b/bsp/phytium/libraries/standalone/drivers/media/Kconfig
new file mode 100644
index 00000000000..cec2cf2e3d1
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/Kconfig
@@ -0,0 +1,22 @@
+
+
+menu "Media Configuration"
+    config ENABLE_FDC_DP
+        bool
+        prompt "USE FMEDIA"
+        default n
+        help
+            Select fdcdp driver component
+
+    config ENABLE_FDC_DP_USE_LIB
+        bool
+        prompt "USE FMEDIA LIB TO LINK"
+        default n
+        help
+            Select fdcdp driver component
+    
+
+endmenu
+
+
+
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h
new file mode 100644
index 00000000000..80452f23490
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h
@@ -0,0 +1,359 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdc.h
+ * Date: 2022-09-05 22:53:24
+ * LastEditTime: 2022-09-05 22:53:24
+ * Description:  This file is for defining the dc config and function
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDC_H
+#define FDC_H
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+
+#include "fdcdp_param.h"
+
+/************************** Constant Definitions *****************************/
+#define FMEDIA_DC_SUCCESS FT_SUCCESS
+
+/************************** Constant Definitions *****************************/
+
+#define FDC_FALSE 0
+#define FDC_TRUE 1
+#define FDCDP_PATH_NUM 2
+
+#define FDC_GOP_MAX_MODENUM 11
+
+#define FDC_PCCON_BUFFER_SIZE (1 * 1024 * 1024)
+
+typedef enum
+{
+    FDC_MULTI_MODE_CLONE = 0,
+    FDC_MULTI_MODE_HORIZONTAL,
+    FDC_MULTI_MODE_VERTICAL,
+
+    FDC_MULTI_MODE
+} FDcMultiMode;
+
+typedef enum
+{
+    FDC_ROT_0 = 0,
+    FDC_FLIP_X,
+    FDC_FLIP_Y,
+    FDC_FLIP_XY,
+    FDC_ROT_90,
+    FDC_ROT_180,
+    FDC_ROT_270,
+} FDcRotType;
+
+typedef enum
+{
+    FDC_RESET_CORE = 0,
+    FDC_RESET_AXI,
+    FDC_RESET_AHB,
+} FDcRestType;
+
+typedef enum
+{
+    FDC_PHY_DPI,
+    FDC_PHY_DP,
+} FDcPhyOutPutType;
+/*
+ * Frame buffer mode.
+ * Used in ConfFramebufferSetConfig()
+ */
+typedef enum
+{
+    FDC_PHY_LINEAR,
+    FDC_PHY_TIILED,
+} FDcPhyTilingType;
+
+typedef enum
+{
+    FDC_FORMAT_X4R4G4B4 = 0x0,
+    FDC_FORMAT_A4R4G4B4,
+    FDC_FORMAT_X1R5G5B5,
+    FDC_FORMAT_A1R5G5B5,
+    FDC_FORMAT_R5G6B5,
+    FDC_FORMAT_X8R8G8B8,
+    FDC_FORMAT_A8R8G8B8,
+    FDC_FORMAT_YUY2,
+    FDC_FORMAT_UYVY,
+    FDC_FORMAT_INDEX8,
+    FDC_FORMAT_MONOCHROME,
+    FDC_FORMAT_YV12 = 0x0F,
+    FDC_FORMAT_A8,
+    FDC_FORMAT_NV12,
+    FDC_FORMAT_NV16,
+    FDC_FORMAT_RG16,
+    FDC_FORMAT_RB,
+    FDC_FORMAT_NV12_10BIT,
+    FDC_FORMAT_A2R10G10B10,
+    FDC_FORMAT_NV16_10BIT,
+    FDC_FORMAT_INDEX1,
+    FDC_FORMAT_INDEX2,
+    FDC_FORMAT_INDEX4,
+    FDC_FORMAT_P010
+} FDcVideoFormate;
+
+typedef enum
+{
+    FDC_OUTPUT_RGB565 = 0,
+    FDC_OUTPUT_RGB666,
+    FDC_OUTPUT_RGB888,
+    FDC_OUTPUT_RGB1010,
+} FDcOutputColor;
+
+/**************************** Type Definitions *******************************/
+
+typedef struct
+{
+    u32 instance_id;         /* dc id */
+    uintptr dcch_baseaddr;   /* DC channel register address*/
+    uintptr dcctrl_baseaddr; /* DC control register address */
+    u32 irq_num;             /* Device intrrupt id */
+} FDcConfig;
+
+typedef struct
+{
+    u32 visble_line;       /*  Visible Number of  lines */
+    u32 total_line;        /*  Total Number of  lines. */
+    u32 sync_start;        /* Start of  sync pulse. */
+    u32 sync_end;          /* End of  sync pulse. */
+    boolean sync_polarity; /* Polarity of the  sync pulse.1 - positive , 0 - negative.  */
+} FDcDisplayTimmingConfig;
+
+typedef struct
+{
+    FDcDisplayTimmingConfig horizontal;
+    FDcDisplayTimmingConfig vertical;
+    boolean timing_dirty;      /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcSyncParameter; /* horizontal and vertical  timing parameter */
+
+typedef struct
+{
+    u32 color_format;      /* color format. */
+    uintptr framebuffer_p; /* Starting address of the frame buffer. */
+    u32 tiling_mode;       /* tile mode */
+    u32 yuv_type;          /* unused , reserved */
+    u32 stride;            /* memory image line span , --- FDcWidthToStride */
+    u32 a_stride;          /* Processing is consistent with memory image line spans */
+    boolean fb_dirty;      /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcDisplayFramebuffer;
+
+typedef struct
+{
+    boolean data_enable_polarity; /* Data Enable polarity , 1 - positive , 0 - negative. */
+    boolean data_polarity;        /* Data polarity , 1 - positive , 0 - negative. */
+    boolean clock_polarity;       /* Clock polarity , 1 - positive , 0 - negative. */
+    boolean panel_dirty;          /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcDisplayPanel;
+
+typedef struct
+{
+#define gama_index_max 256
+    boolean gamma_enable; /*enable the gamma*/
+    u32 gamma;
+    boolean gamma_dirty; /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcDisplayGamma;
+
+typedef struct
+{
+    boolean enable;
+    u32 red_channel;      /* red channel of dither*/
+    u32 green_channel;    /* red green of dither*/
+    u32 blue_channel;     /* blue channel of dither*/
+    u32 table_low;        /* the low level of dither*/
+    u32 table_high;       /* the high level of dither*/
+    boolean dither_dirty; /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcDisplayDither;
+
+typedef struct
+{
+    boolean outputenable;
+    u32 output_type; /* Output format , 0 - DPI mode , 1 - DP mode. */
+
+    /* dp mode */
+    u32 dp_format; /* DC output color format, 0 - 565 , 1 - RGB666 , 2 - RGB888 , 3 - RGB101010. */
+
+    /* dpi mode  */
+    u32 dpi_type;          /* the dc output mode */
+    u32 dpi_format;        /* DC output type , 1 - RGB666 , 2 - RGB888 , 3 - RGB101010. */
+    u32 dpi_actime;        /* DC active time*/
+    u32 dpi_period[2];     /*the period time of dc */
+    u32 dpi_eor_assert[2]; /* params, unused*/
+    u32 dpi_cs_assert[2];  /* params, unused*/
+    boolean dpi_polarity;  /*the polarity of output data */
+    boolean output_dirty;  /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+
+} FDcDisplayDpMode;
+
+typedef struct
+{
+    boolean enable;
+    u64 phys_addr;    /* Address of the cursor shape. */
+    u32 type;             /* Cursor type , 0 - disable , 1 - mask mode , 2 - argb mode. */
+    u32 x;                /* X location of cursor's hotspot. */
+    u32 y;                /* Y location of cursor's hotspot. */
+    u32 hot_x;            /* Vertical offset to cursor hotspot. */
+    u32 hot_y;            /* Horizontal offset to cursor hotspot. */
+    u32 bg_color;         /* The background color for Masked cursors . Format is ARGB8888. */
+    u32 fg_color;         /* The foreground color for Masked cursors . Format is ARGB8888. */
+    boolean cursor_dirty; /* if value is FDC_TRUE , when using the FDcCoreCommit interface, the parameters will be updated  */
+} FDcDisplayCursor;
+
+typedef struct
+{
+    u32 y_address;
+    u32 u_address;
+    u32 v_address;
+    u32 u_stride;
+    u32 v_stride;
+    u32 rot_angle;
+    u32 alpha_mode;
+    u32 alpha_value;
+    /* Original size in pixel before rotation and scale. */
+    u32 width;
+    u32 height;
+    u32 tile_mode;
+    u32 scale;
+    u32 scale_factorx;
+    u32 scale_factory;
+    u32 filter_tap;
+    u32 horizontal_filtertap;
+#define HOR_KERNEL_MAX 128
+    u32 horkernel[128];
+#define VER_KERNEL_MAX 128
+    u32 verkernel[128];
+    u32 swizzle;
+    u32 uv_swizzle;
+    u32 color_key;
+    u32 colorkey_high;
+    u32 bg_color;
+    u32 trans_parency;
+    u32 clear_fb;
+    u32 clear_value;
+    u32 initial_offsetx;
+    u32 initial_offsety;
+    u32 compressed;
+} FDcDisplayVideoMode;
+
+typedef struct
+{
+    u32 pixelclock; /* the pixelclock of dc */
+    u32 horpixel;   /*horizontal pixel */
+    u32 verpixel;   /*vertical pixel */
+    FDcSyncParameter FDcSyncParameter;
+} FDcDtdTable;
+
+typedef struct
+{
+    FDcDtdTable dtd_table; /*the table of dtd params*/
+    FDcSyncParameter sync_parameter[FDC_GOP_MAX_MODENUM];
+    FDcDisplayFramebuffer framebuffer;
+    FDcDisplayPanel panel;
+    FDcDisplayGamma gamma;
+    FDcDisplayDither dither;
+    FDcDisplayDpMode dp_mode;
+    FDcDisplayVideoMode video_mode; /*the params of video*/
+    FDcDisplayCursor cursor;
+} FDcCurrentConfig;
+
+typedef struct
+{
+    FDcCurrentConfig fdc_current_config;
+    FDcConfig config;
+    u32 multimode; /* The display mode of the device , including clone, horizontal and vertical display*/
+
+} FDcCtrl;
+
+/************************** Function Prototypes ******************************/
+
+/*Initialization of dc configuration parameter */
+FError FDcConfigInit(FDcCtrl *instance_p, FDcDpDisplaySetting *gop_mode, u32 mode_id);
+
+/* config to ddr */
+
+/*config the panel data of core data */
+void FDcPanelSetConfig(FDcCtrl *instance_p, boolean data_enable_polarity, boolean data_polarity, boolean clock_Polarity);
+
+/* set the horizontal timing parameter */
+void FDcDisplaySetHorizontal(FDcCtrl *instance_p, u32 mode_id, u32 total_pixels, u32 line_pixels, u32 hsync_start, u32 hsync_end, boolean hsync_polarity);
+
+/* set the vertical timing parameter */
+void FDcDisplaySetVertical(FDcCtrl *instance_p, u32 mode_id, u32 line_pixels, u32 total_pixels, u32 vsync_start, u32 vsync_end, boolean vsync_polarity);
+/* select core data about dc output mode , DP mode or DPI mode */
+void FDcOutputSelect(FDcCtrl *instance_p, FDcPhyOutPutType output_type);
+
+/* config core data about dc output formort , DP mode or DPI mode */
+void FDcOutputDpformat(FDcCtrl *instance_p, FDcOutputColor format);
+
+/* config tilemode and color format of vedio */
+void FDcTilemodeSetConfig(FDcCtrl *instance_p, FDcVideoFormate format, FDcPhyTilingType tiling);
+
+/* core data config about framebuffer parameter */
+void FDcFramebufferSetFramebuffer(FDcCtrl *instance_p, FDcDisplayVideoMode *fdc_video_params);
+
+/* config core data about dither enable */
+void FDcDitherEnable(FDcCtrl *instance_p, boolean enable);
+
+/* update config */
+
+/* enable core data about gamma */
+void FDcGammaEnable(FDcCtrl *instance_p, boolean enable);
+
+/* config register about all dc parameters include video framebuffer  address and stride
+the main function interface to set the dc parameters*/
+FError FDcCoreCommit(FDcCtrl *instance_p, u32 mode_id);
+
+/* direct update config */
+
+/* commit display configuration about timing parameter*/
+void FDcDisplayCommit(FDcCtrl *instance_p, u32 mode_id);
+
+/* config register about dc output mode， DP or DPI */
+void FDcOutputCommit(FDcCtrl *instance_p);
+
+/* config register about panel */
+void FDcPanelCommit(FDcCtrl *instance_p);
+
+/* config register about cursor parameter */
+void FDcCursorCommit(FDcCtrl *instance_p);
+
+/* cursor setting */
+
+/* enable the cursor */
+void FDcCursorEnable(FDcCtrl *instance_p, boolean enable);
+
+/* config core data about cursor hotspot */
+void FDcCursorSetHotspot(FDcCtrl *instance_p, uintptr x, uintptr y);
+
+/* config core data about location of the cursor on the owning display */
+void FDcCursorSetPos(FDcCtrl *instance_p, uintptr x, uintptr y);
+
+/* Config register about vedio parameter and framebuffer */
+void FDcFramebufferCommit(FDcCtrl *instance_p);
+
+/* common setting */
+
+/* according to the width, calculate the stride */
+FError FDcWidthToStride(u32 width, u32 color_depth, u32 multimode);
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h
similarity index 51%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.h
rename to bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h
index 513332661bd..ca387a920bd 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.h
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h
@@ -11,31 +11,32 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: fpsci.h
- * Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:34:06
- * Description:  This files is for
+ * FilePath: fdc_hw.h
+ * Date: 2022-09-10 14:53:42
+ * LastEditTime: 2022-09-18 08:29:10
+ * Description:  This file is for Handling the hardware register and
+ *               providing some function interface
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
  */
+#ifndef FDC_COMMON_HW_H
+#define FDC_COMMON_HW_H
 
-
-#ifndef BSP_ARCH_AARMV8_AARCH64_PSCI_H
-#define BSP_ARCH_AARMV8_AARCH64_PSCI_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+/***************************** Include Files *********************************/
 
 #include "ftypes.h"
 #include "ferror_code.h"
-void PsciCpuReset(void);
-FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr);
+#include "fdc.h"
+
+/*set pixel clock in kilohertz unit by configurating register */
+FError FDcReqChangePixel(FDcCtrl *instance_p, u32 pixel_clk);
+
+/* soft reset DC by configurating register */
+void FDcHwFramebufferReset(FDcCtrl *instance_p, u32 num, FDcRestType type);
 
-#ifdef __cplusplus
-}
+/* Get mode number by width and height */
+FError FDcResToModeNum(u32 width, u32 height);
 #endif
-#endif // !BSP_ARCH_AARMV8_AARCH64_PSCI_H
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h
new file mode 100644
index 00000000000..dfae755c13e
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdc_hw.h
+ * Date: 2022-09-10 14:53:42
+ * LastEditTime: 2022-09-18 08:29:10
+ * Description:  This file is for providing some hardware register and function definition
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDC_HW_H
+#define FDC_HW_H
+
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fkernel.h"
+
+/**************************** Type Definitions *******************************/
+
+#define FDC_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
+#define FDC_WRITE_REG32(addr, reg_value) FtOut32(addr, (u32)(reg_value))
+#define FDC_PHY_ALIGN(data, Offset) ((data + Offset - 1) & ~(Offset - 1))
+
+/************************** Constant Definitions *****************************/
+
+/*
+AHB Byte Address
+DC Ctrl Register*/
+#define FDC_AQ_HI_CLOCK_CONTROL 0x0000
+#define FDC_AQ_HI_IDLE 0x0004
+#define FDC_AQ_AXI_STATUS 0x000C
+#define FDC_AQ_INTR_ENBL 0x0014
+#define FDC_AQ_INTR_ACKNOWLEDGE 0x0010
+#define FDC_GC_TOTAL_READS 0x0040
+#define FDC_GC_TOTAL_CYCLES 0x0078
+#define FDC_CTRL_CH0_PIXEL_CLOCK 0x00F0
+#define FDC_CTRL_CH1_PIXEL_CLOCK 0x00F4
+
+/* Each Dc Core Register */
+#define FDC_GCREG_FRAMEBUFFERADDR_LOW 0x400
+#define FDC_GCREG_FRAMEBUFFERADDR_HIGH 0x404
+#define FDC_GCREG_FRAMEBUFFERSTRIDE0 0x408
+#define FDC_GCREG_DISPLAYDITHERCONFIG0 0x410
+#define FDC_GCREG_PANEL_CONFIG0 0x418
+#define FDC_GCREG_DISPLAY_DITHERTABLELOW0 0x420
+#define FDC_GCREG_DISPLAY_DITHERTABLEHIGH0 0x428
+#define FDC_GCREG_HDISPLAY0 0x430
+#define FDC_GCREG_HSYNC0 0x438
+#define FDC_GCREG_VDISPLAY0 0x440
+#define FDC_GCREG_VSYNC0 0x448
+#define FDC_GCREG_DISPLAY_CURLOCATION0 0x450
+#define FDC_GCREG_GAMMAINDEX0 0x458
+#define FDC_GCREG_GAMMADATA0 0x460
+#define FDC_GCREG_CURSOR_CONFIG 0x468
+#define FDC_GCREG_CURSOR_ADDR_LOW 0x46C
+#define FDC_GCREG_CURSOR_ADDR_HIGH 0x490
+#define FDC_GCREG_CURSOR_LOCATION 0x470
+#define FDC_GCREG_CURSOR_BACKGROUND 0x474
+#define FDC_GCREG_CURSOR_FORGEGROUND 0x478
+#define FDC_GCREG_DISPLAY_INTR 0x47C
+#define FDC_GCREG_DISPLAY_INTR_ENABLE 0x480
+#define FDC_GCREG_CURSOR_MODCLKGATECONTROL 0x484
+#define FDC_GCREG_DEBUGCOUNTER_SELECT0 0x4D0
+#define FDC_GCREG_DEBUGCOUNTER_VALUE0 0x4D8
+#define FDC_GCREG_FRAMEBUFFER_COLORKEY0 0x508
+#define FDC_GCREG_FRAMEBUFFER_COLORKEYHIGH0 0x510
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0 0x518
+#define FDC_GCREG_FRAMEBUFFER_SCALECONFIG0 0x520
+#define FDC_GCREG_FRAMEBUFFER_BGCOLOR0 0x528
+#define FDC_GCREG_FRAMEBUFFER_UPPLANARADDR_LOW 0x530
+#define FDC_GCREG_FRAMEBUFFER_UPPLANARADDR_HIGH 0x534
+#define FDC_GCREG_FRAMEBUFFER_VPPLANARADDR_LOW 0x538
+#define FDC_GCREG_FRAMEBUFFER_VPPLANARADDR_HIGH 0x53C
+#define FDC_GCREG_FRAMEBUFFER_USTRIDE0 0x800
+#define FDC_GCREG_FRAMEBUFFER_VSTRIDE0 0x808
+#define FDC_GCREG_FRAMEBUFFER_SIZE0 0x810
+#define FDC_GCREG_FRAMEBUFFER_SCALEFACTORX0 0x828
+#define FDC_GCREG_FRAMEBUFFER_SCALEFACTORY0 0x830
+#define FDC_GCREG_HORIFILTERKERNEL_INDEX0 0x838
+#define FDC_GCREG_HORI_FILTERKERNEL0 0xA00
+#define FDC_GCREG_VERTI_FILTERKERNEL_INDEX0 0xA08
+#define FDC_GCREG_VERTI_FILTERKERNEL0 0xA10
+#define FDC_GCREG_FRAMEBUFFER_CLEARVALUE0 0xA18
+#define FDC_GCREG_FRAMEBUFFER_INITOFFSET0 0xA20
+#define FDC_GCREG_MODCLKGATE_CONTROL0 0xA28
+#define FDC_GCREG_READ_OT 0xCC8
+#define FDC_GCREG_DPCONFIG0 0xCD0
+
+/* FDC_GCREG_FRAMEBUFFER_SIZE0 */
+#define FDC_GCREG_FRAMEBUFFER_SIZE0_HEIGHT_SET(x) SET_REG32_BITS((x), 29, 15) /* the height of window size of the framebuffer in memory - in pixels*/
+#define FDC_GCREG_FRAMEBUFFER_SIZE0_WIDTH_SET(x) SET_REG32_BITS((x), 14, 0)   /* the width of window size of the framebuffer in memory -in pixels*/
+/* FDC_GCREG_FRAMEBUFFER_SCALECONFIG0 */
+#define FDC_GCREG_FRAMEBUFFER_SCALECONFIG0_H_FILTER_TAP_SET(x) SET_REG32_BITS((x), 7, 4) /* the number of horizontal filter tap*/
+#define FDC_GCREG_FRAMEBUFFER_SCALECONFIG0_V_FILTER_TAP_SET(x) SET_REG32_BITS((x), 3, 0) /* the number of vertial filter tap*/
+/* FDC_GCREG_FRAMEBUFFER_INITOFFSET0 */
+#define FDC_GCREG_FRAMEBUFFER_INITOFFSET0_Y_SET(x) SET_REG32_BITS((x), 31, 16) /* Y location of the framebuffer scalar source offset register */
+#define FDC_GCREG_FRAMEBUFFER_INITOFFSET0_X_SET(x) SET_REG32_BITS((x), 15, 0)  /* X  location of the framebuffer scalar source offset register */
+
+/* FDC_GCREG_FRAMEBUFFER_CONFIG0 */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_FORMAT_SET(x) SET_REG32_BITS((x), 31, 26)      /* framebuffer configuration register  can see the struct in the VIDEO_FORMAT*/
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_UV_SWIZZLE BIT(25)                             /* UV swizzle */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_SWIZZLE_SET(x) SET_REG32_BITS((x), 24, 23)     /* swizzle mode ,0:ARGB, 1:RGBA, 2:ABGR, 3:BGRA */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_SCALE BIT(22)                                  /* scale of config, 0:disable, 1:enable */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_TILE_MODE_SET(x) SET_REG32_BITS((x), 21, 17)   /* set the tilemode */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_YUV_SET(x) SET_REG32_BITS((x), 16, 14)         /* yuv standard, 1: 709*bt709, 3:2020*bt2020*/
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_ROT_ANGLE_SET(x) SET_REG32_BITS((x), 13, 11)   /* the angle of the rot, 0:roto, 1:flip_x, 2:flip_y, 3:flip_xy, 5:rot180 */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_TRANSPARENCY_SET(x) SET_REG32_BITS((x), 10, 9) /* transparency of framebuffer */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_CLEAR BIT(8)                                   /* the source of the pixel value ,enable :from dcregframebufferclear value,disable: from memory */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_FLIP_PROGRESS BIT(6)                           /* 0:NO, 1:YES, related to the framebuffer address and the vblank */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_UNDERFLOW BIT(5)                               /* 0:NO, 1:YES, related to the display fifo underflows */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_RESET BIT(4)                                   /*  enable reset for the display controller */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_VALID BIT(3)                                   /* decided if you can copy a set of registers ar the next vblank */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_GAMMA BIT(2)                                   /* gamma is enabled,rgb channel will be routed */
+#define FDC_GCREG_FRAMEBUFFER_CONFIG0_OUTPUT BIT(0)                                  /* output is enabled ,pixels will be displayed */
+
+/* FDC_GCREG_CURSOR_CONFIG */
+#define FDC_GCREG_CURSOR_CONFIG_HOT_SPOT_X_SET(x) SET_REG32_BITS((x), 20, 16) /* horizontal offset to the cursor hotspot */
+#define FDC_GCREG_CURSOR_CONFIG_HOT_SPOT_Y_SET(x) SET_REG32_BITS((x), 12, 8)  /* vertical offset to the cursor hotspot */
+#define FDC_GCREG_CURSOR_CONFIG_HOT_FORMAT_SET(x) SET_REG32_BITS((x), 1, 0)   /* format of the cursor,0: disabled, 1:masked, 2:ARGB888   \
+                                                                                                                                       \ \
+/* FDC_GCREG_CURSOR_LOCATION */
+#define FDC_GCREG_CURSOR_LOCATION_Y_SET(x) SET_REG32_BITS((x), 31, 16)        /* Y location of cursor hotspot */
+#define FDC_GCREG_CURSOR_LOCATION_X_SET(x) SET_REG32_BITS((x), 15, 0)         /* X location of cursor hotspot */
+
+/* FDC_GCREG_HSYNC0 */
+#define FDC_GCREG_HSYNC0_POLARITY BIT(31)                        /* polarity of the horizontal sync pulse */
+#define FDC_GCREG_HSYNC0_PULSE BIT(30)                           /* horizontal sync pulse control */
+#define FDC_GCREG_HSYNC0_END_SET(x) SET_REG32_BITS((x), 29, 15)  /* end of horizontal sync pulse */
+#define FDC_GCREG_HSYNC0_START_SET(x) SET_REG32_BITS((x), 14, 0) /* start of the horizontal sync pulse */
+
+/* FDC_GCREG_VSYNC0 */
+#define FDC_GCREG_VSYNC0_POLARITY BIT(31)                        /* polarity of the vertical sync pulse */
+#define FDC_GCREG_VSYNC0_PULSE BIT(30)                           /* vertical sync pulse control */
+#define FDC_GCREG_VSYNC0_END_SET(x) SET_REG32_BITS((x), 29, 15)  /* end of vertical sync pulse */
+#define FDC_GCREG_VSYNC0_START_SET(x) SET_REG32_BITS((x), 14, 0) /* start of the vertical sync pulse */
+
+/* FDC_GCREG_VDISPLAY */
+#define FDC_GCREG_VDISPLAY_TOTAL_SET(x) SET_REG32_BITS((x), 30, 16)      /* total number of vertical pixels */
+#define FDC_GCREG_VDISPLAY_DISPLAY_END_SET(x) SET_REG32_BITS((x), 14, 0) /* visible number of vertical pixels */
+
+/* FDC_GCREG_HDISPLAY0 */
+#define FDC_GCREG_HDISPLAY0_TOTAL_SET(x) SET_REG32_BITS((x), 30, 16)      /* total number of horizontal pixels */
+#define FDC_GCREG_HDISPLAY0_DISPLAY_END_SET(x) SET_REG32_BITS((x), 14, 0) /* visible number of vertical pixels */
+
+/* FDC_GCREG_PANEL_CONFIG0 */
+#define FDC_GCREG_PANEL_CONFIG0_DATA_CLOCK_POLATITY BIT(9) /* data clock polarity*/
+#define FDC_GCREG_PANEL_CONFIG0_DATA_CLOCK_ENABLE BIT(8)   /* data enable enable */
+#define FDC_GCREG_PANEL_CONFIG0_DATA_POLARITY BIT(5)       /* data enable polarity */
+#define FDC_GCREG_PANEL_CONFIG0_DATA_ENABLE BIT(4)         /* data enable  */
+#define FDC_GCREG_PANEL_CONFIG0_DATA_DE_POLATITY BIT(1)    /* data enable polarity */
+#define FDC_GCREG_PANEL_CONFIG0_DATA_DE BIT(0)             /* data enable  enabled/disabled */
+
+/* FDC_GCREG_DISPLAYDITHERCONFIG0 */
+#define FDC_GCREG_DISPLAYDITHERCONFIG0_ENABLE BIT(31)
+
+/* FDC_GCREG_GAMMAINDEX0 */
+#define FDC_GCREG_GAMMAINDEX0_INDEX_SET(x) SET_REG32_BITS((x), 7, 0) /*gamma table index register ,index into gamma table */
+
+/* FDC_GCREG_GAMMADATA0 */
+#define FDC_GCREG_GAMMADATA0_RED_SET(x) SET_REG32_BITS((x), 29, 20)   /* red translation value */
+#define FDC_GCREG_GAMMADATA0_GREEN_SET(x) SET_REG32_BITS((x), 19, 10) /* green translation value */
+#define FDC_GCREG_GAMMADATA0_BLUE_SET(x) SET_REG32_BITS((x), 9, 0)    /* blue translation value */
+
+/*FDC_GCREG_DISPLAY_INTR_ENABLE */
+#define FDC_GCREG_DISPLAY_INTR_ENABLE_DC1_UNDERFLOW BIT(5) /* dc1 underflow interrupt enable */
+#define FDC_GCREG_DISPLAY_INTR_ENABLE_DC1_INTR BIT(4)      /* dc1 frame complete interrupt enable */
+#define FDC_GCREG_DISPLAY_INTR_ENABLE_DC0_UNDERFLOW BIT(1) /* dc0 underflow interrupt enable */
+#define FDC_GCREG_DISPLAY_INTR_ENABLE_DC0_INTR BIT(0)      /* dc0 frame complete interrupt enable */
+
+/**************************************************************************************/
+
+/* write the data to the channel of DcDp */
+void FDcChannelRegWrite(uintptr addr, uintptr offset, u32 data);
+
+/* read the data from the channel of DcDp */
+FError FDcChannelRegRead(uintptr addr, uintptr offset);
+
+/* write Dc control register */
+void FDcCtrlRegWrite(uintptr addr, uintptr offset, u32 data);
+
+/* read Dc control register */
+FError FDcCtrlRegRead(uintptr addr, uintptr offset);
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h
new file mode 100644
index 00000000000..0afce2cf4ac
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdcdp.h
+ * Date: 2022-09-05 17:28:55
+ * LastEditTime: 2022-09-05 17:28:55
+ * Description:  This file is for providing the general config of dc and dp
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------  -------- --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDCDP_H
+#define FDCDP_H
+
+#include "fdc.h"
+#include "fdp.h"
+#include "ftypes.h"
+#include "fparameters.h"
+#include "fdcdp_param.h"
+
+#define FDP_DISPLAY_REFRESH_RATE_60 60
+#define FDP_DISPLAY_REFRESH_RATE_59 59
+#define FDP_DISPLAY_REFRESH_RATE_40 40
+#define FDP_DISPLAY_REFRESH_RATE_30 30
+
+#define FDP_DISPLAY_COLOR_DEPTH_32 32
+#define FDP_DISPLAY_COLOR_DEPTH_16 16
+
+#define FDP_EDP_LIGHTTURNON_CMD 101
+#define FDP_EDP_LIGHTTURNOFF_CMD 102
+#define FDP_EDP_OPENPWR_CMD 103
+#define FDP_EDP_POWEROFF_CMD 104
+#define FDP_LIGHT_ADJUST_CMD 0x1
+#define FDP_CMD_STATE_OFFSET 28
+#define FDP_LIGHT_VALUE_OFFSET 21
+
+#define FDP_ALL_CHANNEL                           0xffffffff
+
+#define FDP_MRAM_SIZE (3840 * 2160 * 4)
+
+
+typedef enum
+{
+    FDCDP_HPD_IRQ_CONNECTED = 0, /* hpd 中断 */
+    FDCDP_HPD_IRQ_DISCONNECTED,
+    FDCDP_AUX_REPLY_TIMEOUT,
+    FDCDP_AUX_REPLY_ERROR,
+
+    FDCDP_INTR_MAX_NUM
+} FDcDpIntrEventType;
+
+typedef void (*FMediaIntrHandler)(void *param, u32 index);
+
+typedef struct 
+{
+  FDcDpIntrEventType type;  /* data */
+  FMediaIntrHandler  handler;
+  void *param;
+} FMediaIntrConfig;
+
+typedef struct
+{
+    /* fdc instace object */
+    FDcCtrl dc_instance_p[FDCDP_INSTANCE_NUM];
+    /* fdp instace object */
+    FDpCtrl dp_instance_p[FDCDP_INSTANCE_NUM];
+    /* user config */
+    /* resolution */
+    /* color depth */
+    FDcDpDisplaySetting display_setting[FDCDP_DISPLAY_ID_MAX_NUM];
+    /* gamma parameter */
+    /* .... */
+    /* uintptr fb_p[FDCDP_INSTANCE_NUM];*/
+    u32 is_ready; /* Device is ininitialized and ready*/
+    FMediaIntrConfig intr_event[FDCDP_INTR_MAX_NUM];
+    
+    void *args;
+    u32 connect_flg[FDCDP_INSTANCE_NUM];
+    u32 connect_changed_flg[FDCDP_INSTANCE_NUM];
+} FDcDp;
+
+const FDpConfig *FDpLookupConfig(u32 instance_id);
+const FDcConfig *FDcLookupConfig(u32 instance_id);
+/*get the default config*/
+FError FDcDpGetDefaultConfig(FDcDp *instance_p, u32 channel_num);
+
+/*register the interrupt*/
+void FDcDpRegisterHandler(FDcDp *instance_p, FMediaIntrConfig *intr_event_p);
+
+/*the interrupt handler*/
+void FDcDpInterruptHandler(s32 vector, void *args);
+
+/*enable the interrupt*/
+void FDcDpIrqEnable(FDcDp *instance_p, FDcDpIntrEventType intr_event_p);
+
+/* init the DcDp */
+FError FDcDpInitial(FDcDp *instance_p, u32 channel_num, u32 mode_id,u32 multi_mode);
+
+/*the basic params init*/
+FError FDcDpSetBasicParam(FDcDp *instance_p, u32 channel_num, u32 mode_id);
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h
new file mode 100644
index 00000000000..95893b121d0
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdcdp_multi_display.h
+ * Date: 2023-02-05 18:27:47
+ * LastEditTime: 2023-02-10 11:02:47
+ * Description:  This file is for defining the dp multidisplay config
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------  -------- --------------------------------------
+ *  1.0  Wangzq     2023/02/10  Modify the format and establish the version
+ */
+
+#ifndef FDCDP_MULTI_DISPLAY_H
+#define FDCDP_MULTI_DISPLAY_H
+
+#include "ftypes.h"
+#include "fparameters.h"
+
+typedef struct
+{
+    uintptr dp0_framebuffer;/* data */
+    uintptr dp1_framebuffer;
+    u32     multi_mode;
+} FDcDpFrameBuffer;
+
+/*set the frambbuffer of multidisplay*/
+FError FDcDpMultiDisplayFrameBufferSet(FDcDp *instance_p, u32 channel_num, u32 multi_mode);
+
+/*return the framebuffer*/
+FDcDpFrameBuffer *FDcDpGetFramebuffer(FDcDp *instance_p);
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h
new file mode 100644
index 00000000000..0a11d981839
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdcdp_param.h
+ * Date: 2022-09-05 17:31:47
+ * LastEditTime: 2022-09-05 17:31:47
+ * Description:  This file is for providing some general config and params of dc and dp
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------  -------- --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDCDP_PARAM_H
+#define FDCDP_PARAM_H
+
+#include "ftypes.h"
+#include "fparameters.h"
+#include "ferror_code.h"
+
+#define FMEDIA_DEFAULT_PARAM_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 1)
+#define FMEDIA_ERR_PIXEL FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 3)
+#define FMEDIA_ERR_EDID FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 4)
+#define FMEDIA_ERR_HPD_DISCONNECTED  FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 5)
+#define FMEDIA_AUX_CONNECT_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 7)
+#define FMEDIA_TRAIN_TIME_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 8)
+#define FMEDIA_REACH_MAX_VOLTAGE FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 9)
+
+typedef enum
+{
+    FDCDP_DISPLAY_ID_640_480 = 0,
+    FDCDP_DISPLAY_ID_800_600,
+    FDCDP_DISPLAY_ID_1024_768,
+    FDCDP_DISPLAY_ID_1280_720,
+    FDCDP_DISPLAY_ID_1366_768,
+    FDCDP_DISPLAY_ID_1920_1080,
+    FDCDP_DISPLAY_ID_1600_1200,
+    FDCDP_DISPLAY_ID_1280_800,
+    FDCDP_DISPLAY_ID_800_480,
+    FDCDP_DISPLAY_ID_1280_768,
+    FDCDP_DISPLAY_ID_1280_1024,
+    FDCDP_DISPLAY_ID_MAX_NUM
+
+} FDcDpDisplayId;
+typedef struct
+{
+    u32 width;
+    u32 height;
+    u32 color_depth;  /*  value follow the  DISPLAY_REFRESH_RATE_XX */
+    u32 refresh_rate; /*  value follow the  DISPLAY_COLOR_DEPTH_XX */
+    FDcDpDisplayId id;
+} FDcDpDisplaySetting;
+
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h
new file mode 100644
index 00000000000..e6f6c215614
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdp.h
+ * Date: 2022-09-08 14:53:42
+ * LastEditTime: 2022-09-08 14:53:42
+ * Description:  This file is for defining the dp config and function
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDP_H
+#define FDP_H
+
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+#include "fparameters_comm.h"
+#include "fdcdp_param.h"
+#include "fdc.h"
+
+/************************** Constant Definitions *****************************/
+#define FMEDIA_DP_SUCCESS FT_SUCCESS
+
+/************************** Constant Definitions *****************************/
+
+#define FDP_HAS_TRAINED 1
+#define FDP_NOT_TRAINED 0
+
+#define FDP_IS_HPD_ON 1
+#define FDP_IS_HPD_OFF 0
+
+#define FDP_DIS_CONNECTED 1
+#define FDP_IS_CONNECTED 0
+
+#define DP_GOP_MAX_MODENUM 11
+
+typedef enum
+{
+    FDP_TRAINING_OFF = 0,
+    FDP_TRAINING_PATTERN_1,
+    FDP_TRAINING_PATTERN_2,
+    FDP_TRAINING_PATTERN_3
+} FDpTrainPattern;
+
+typedef enum
+{
+    FDP_BIT_DEPTH_6 = 0,
+    FDP_BIT_DEPTH_8,
+    FDP_BIT_DEPTH_10,
+    FDP_BIT_DEPTH_12,
+    FDP_BIT_DEPTH_16,
+    FDP_BIT_DEPTH_RESERVE
+} FDpBitDepth;
+
+typedef enum
+{
+    FDP_PWR_MODE_D0 = 1,
+    FDP_PWR_MODE_D3 = 2,
+} FDpPwrMode; /* the power state of dp_phy */
+
+typedef struct
+{
+    u16 h_total;
+    u16 v_total;
+    boolean h_polarity;      /*0 - active high , 1 - active low  */
+    boolean v_polarity;      /*0 - active high , 1 - active low   */
+    u16 hs_width;            /* Horizontal Sync Pulse Width in pixels. */
+    u16 vs_width;            /* Vertical Sync Pulse Width in lines. */
+    u16 h_res;               /* Horizontal Addressable video in lines. */
+    u16 v_res;               /* Vertical Addressable video in lines. */
+    u16 h_start;             /* Horizontal Blanking in pixels minus  Horizontal Front Proch in pixels. */
+    u16 v_start;             /* Vertical Blanking in pixels minus  Vertical Front Proch in pixels. */
+    boolean h_user_polarity; /* Horizontal Sync Polarity. */
+    boolean v_user_polarity; /* Vertical Sync Polarity. */
+} FDpSyncParameter;
+
+typedef struct
+{
+    u32 lane_count;      /* The Number of lanes */
+    u32 link_rate;       /* Main link bandwidth. 162 - 1.62   270 - 2  540 -  810 - 8.1G */
+    u8 bit_depth;        /* Bit depth per color.For example , 6 means that Bit depth per color is 6 bits. */
+    u8 color_rep_format; /* Color representation format. 0 - RGB , 1 - YCbCr 4:2:2 , 2 - YCbCr 4:4:4 , other - Reserved. */
+    u8 clock_mode;       /* clock_mode   Clocking mode for the user data. 0 - asynchronous clock , 1 - synchronous clock. */
+    u32 pixel_clock;     /* pixel clock frequence in megahertz unit */
+    u8 transfer_size;    /* Transfer unit size.This parameter is usually 64. */
+    u8 dis_type;         /* index of video mode description structure */
+} FDpTransmissionConfig;
+
+typedef struct
+{
+    u32 dp_hpd_on;  /* whether the dp is connected or not，1-connected，0-disconnected */
+    u32 dp_trained; /* whether the dp has been trained or not，1-trained，0-distrained */
+    u32 dp_connect; /* whether the source has been connected with sink or not ,1-trained，0-distrained */
+} FDpStatus;
+
+typedef struct
+{
+    u32 pixel_clock; /* the pixelclock of dp */
+    u32 horPixel;   /* horizontal pixel */
+    u32 verPixel;   /*vertical pixel */
+    FDpSyncParameter sync_parameter[DP_GOP_MAX_MODENUM];
+} FDpDtdTable;
+
+typedef struct
+{
+    /* 设置参数 */
+    FDpSyncParameter sync_parameter[DP_GOP_MAX_MODENUM];
+
+    FDpTransmissionConfig transmission_config;
+
+    /* 当前状态 */
+    FDpStatus status;
+
+    u8 down_spread_enable;
+#define dtd_list_max 4
+    /* edid 缓冲数据 */
+    FDpDtdTable dtd_table[dtd_list_max]; /* the max dtd num is 4 */
+
+} FDpCurrentConfig;
+
+typedef struct
+{
+    u32 instance_id;
+    uintptr dp_channe_base_addr;
+    uintptr dp_phy_base_addr;
+    u32 irq_num;
+} FDpConfig;
+
+typedef struct
+{
+    FDpCurrentConfig fdp_current_config;
+    FDpConfig config;
+} FDpCtrl;
+
+/* dp init */
+FError FDpInit(FDcCtrl *dc_config, FDpCtrl *instance_p, FDcDpDisplaySetting *gop_mode, u32 mode_id);
+
+/* Initialization of dp configuration parameter */
+void FDpConfigInit(FDpCtrl *instance_p, FDcDpDisplaySetting *gop_mode);
+
+/* Dp connect to sink */
+FError FDpConnect(FDpCtrl *instance_p);
+
+/* Convert display resolution number to pixel clock frequence in megahertz unit */
+FError FDpDistypeToPixelClock(u8 mode_Num);
+
+/* sets the output of the transmitter core to the specified training pattern */
+void FDpConfigTxTrainingPattern(FDpCtrl *instance_p, FDpTrainPattern train_pattern);
+
+/* Force the transmitter core to use the alternate scrambler reset value */
+FError FDpConfigTraingPattern(FDpCtrl *instance_p);
+
+/* Config Main Stream Attributes.It is must to reset reset phy link after main
+  stream attributes configuration*/
+void FDpConfigMainStreamAttr(FDpCtrl *instance_p, FDpTransmissionConfig *fdp_trans_config, FDpSyncParameter *fdp_sync_config);
+
+/*Dp link training*/
+
+/*Set sink device to D0(normal operation mode).*/
+FError FDpWakeUpSink(FDpCtrl *instance_p);
+
+FError FDpStartLinkTrain(FDpCtrl *instance_p, u8 lane_count, u32 link_rate);
+
+/* Get the status of all lanes */
+FError FDpTxGetTrainingStatus(FDpCtrl *instance_p, u8 *train_status);
+
+/* Determine whether retraining is needed at present.*/
+FError FDpSinkNeedReTrain(FDpCtrl *instance_p); /* not use*/
+
+/*Check the overall training status of the specified nameber of lanes and Tps type.*/
+FError FDpCheckTrainingStatus(FDpCtrl *instance_p, u8 lane_count, u8 tpsn, u8 *value);
+
+/*Check the HPD status*/
+FError FDpCheckHpdStatus(FDpCtrl *instance_p);
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h
new file mode 100644
index 00000000000..276b0dafb4e
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdp_aux.h
+ * Date: 2022-09-08 14:53:42
+ * LastEditTime: 2022-09-08 14:53:42
+ * Description:  This file is for Handling the aux register and
+ *               providing some function interface
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+#ifndef FDP_AUX_H
+#define FDP_AUX_H
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+
+
+#define AUX_TIMEOUT 1
+#define AUX_CONNECT 0
+#define dtd_list_max 4
+
+typedef struct
+{
+    u32 pixel_clock;
+    u32 hor_pixel;
+    u32 ver_pixel;
+    u32 hor_blanking;
+    u32 ver_blanking;
+    u32 hor_sync_front;
+    u32 ver_sync_front;
+    u32 hor_sync_width;
+    u32 ver_sync_width;
+    u8 hor_polarity;
+    u8 ver_polarity;
+} Auxtable;
+/*Initialize AUX channel include aux clock Initialization, dp timer Initialization
+  and interrupt mask. */
+FError FDpInitAux(FDpCtrl *instance_p);
+
+/*Wait util that an aux reply has been recieved*/
+FError FDpWaitAuxReply(FDpCtrl *instance_p);
+
+/*translate the dp information the dpsync*/
+FError FDpTimingToDpSync(Auxtable *instance_p, FDpSyncParameter *sync);
+
+/*translate the dc information the dcsync*/
+FError FDpTimingToDcSync(Auxtable *instance_p, FDcSyncParameter *sync);
+
+/* write phy register through aux channel.*/
+FError FDpSinkDpcdWrite(FDpCtrl *instance_p, u32 addr, u8 data);
+
+/* Read phy register through aux channel. */
+FError FDpSinkDpcdRead(FDpCtrl *instance_p, u32 addr, u8 *data);
+
+/* Get edid information form sink*/
+FError FDpGetEdid(FDpCtrl *instance_p, u8 *buffer);
+
+/*translate the edid information to the struct*/
+FError FDpParseDpEdidDtdList(u8 *buffer, Auxtable *list);
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h
new file mode 100644
index 00000000000..89fb78e6a7b
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdp_hw.h
+ * Date: 2022-09-08 14:53:42
+ * LastEditTime: 2022-09-08 14:53:42
+ * Description:  This file is for providing some hardware register and function definition
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+
+#ifndef FDP_HW_H
+#define FDP_HW_H
+
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+#include "fio.h"
+#include "fkernel.h"
+
+/****************************************************************************/
+/**
+* This macro writes the given register.
+* @param    base_addr is the base address of the device.
+* @param    reg_offset is the register offset to be written.
+* @param    data is the 32-bit value to write to the register.
+* @return   None.
+* @note     None.
+*****************************************************************************/
+#define FDP_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
+
+#define FDP_WRITE_REG32(addr, reg_value) FtOut32(addr, (u32)(reg_value))
+
+#define FDC_PHY_ALIGN(data, Offset) ((data + Offset - 1) & ~(Offset - 1))
+
+#define FDP_SETBIT(base_addr, reg_offset, data)      FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))
+
+#define FDP_CLEARBIT(base_addr, reg_offset, data)     FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
+
+/*
+ TX Registers
+*/
+#define FDPTX_LINK_BW_SET 0x0000
+#define FDP_TX_LANE_COUNT_SET  0x0004
+#define FDP_TX_ENHANCED_FRAME_EN 0x0008
+#define FDP_TX_TRAINING_PATTERN_SET 0x000c
+
+#define FDP_TX_LINK_QUAL_PATTERN_SET 0x0010
+#define FDP_TX_SCRAMBLING_DISABLE 0x0014
+#define FDP_TX_DOWNSPREAD_CTRL 0x0018
+#define FDP_TX_ALT_SCRAMBLER_RESET 0x001c
+#define FDP_TX_HBR2_SCRAMBLER_RESET 0x0020
+#define FDP_TX_DISPLAYPORT_VERSION 0x0024
+#define FDP_TX_LANE_REMAP 0x002C
+
+#define FDP_TX_ENABLE 0x0080
+#define FDP_TX_ENABLE_MAIN_STREAM 0x0084
+#define FDP_TX_ENABLE_SEC_STREAM 0x0088
+#define FDP_TX_SEC_DATA_WINDOW 0x008C
+#define FDP_TX_LINK_SOFT_RESET 0x0090
+#define FDP_TR_INPUT_COURCE_ENABLE 0x0094
+
+#define FDP_TX_FORCE_SCRAMBLER_RESET 0x00C0
+#define FDP_TX_SOURCE_CONTROL_STATUS 0x00C4
+#define FDP_TX_DATA_CONTROL 0x00C8
+
+#define FDP_TX_CORE_CAPABILITY 0x00F8
+#define FDP_TX_CORE_ID 0x00FC
+
+#define FDP_TX_CMD_REG 0x0100
+#define FDP_TX_FIFO 0x0104
+#define FDP_TX_ADDRESS_REG 0x0108
+#define FDP_TX_CLK_DIVIDER 0x010C
+#define FDP_TX_AUX_REPLY_TIMEOUT_INTERVAL 0x0110
+#define FDP_TX_SINK_HPD_STATE 0x0128
+#define FDP_TX_STATUS 0x0130
+#define FDP_TX_RCV_FIFO 0x0134
+#define FDP_TX_RCV_REPLY_REG 0x0138
+#define FDP_TX_RCV_REPLY_COUNT 0x013C
+
+#define FDP_TX_INTERRUPT 0x0140
+#define FDP_TX_INTERRUPT_MASK 0x0144
+#define FDP_TX_RCV_DATA_COUNT 0x0148
+#define FDP_TX_AUX_TRANSACTION_STATUS 0x014C
+#define FDP_TX_TIMER 0x0158
+
+/*
+ Main Link registers
+*/
+#define FDPTX_MAIN_LINK_HTOTAL 0x0180
+#define FDPTX_MAIN_LINK_VTOTAL 0x0184
+#define FDPTX_MAIN_LINK_POLARITY 0x0188
+#define FDPTX_MAIN_LINK_HSWIDTH 0x018C
+#define FDPTX_MAIN_LINK_VSWIDTH 0x0190
+#define FDPTX_MAIN_LINK_HRES 0x0194
+#define FDPTX_MAIN_LINK_VRES 0x0198
+#define FDPTX_MAIN_LINK_HSTART 0x019C
+#define FDPTX_MAIN_LINK_VSTART 0x01A0
+#define FDPTX_MAIN_LINK_MISC0 0x01A4
+#define FDPTX_MAIN_LINK_MISC1 0x01A8
+#define FDPTX_M_VID 0x01AC
+#define FDPTX_TRANSFER_UNIT_SIZE 0x01B0
+#define FDPTX_N_VID 0x01B4
+#define FDPTX_USER_PIXEL_WIDTH 0x01B8
+#define FDPTX_DATA_PER_LANE 0x01BC
+#define FDPTX_INTERLACED 0x01C0
+#define FDPTX_USER_POLARITY 0x01C4
+#define FDPTX_USER_CONTROL 0x01C8
+
+#define FDP_TX_AUX_ERROR_MASK BIT(6) //AUX reply error
+#define FDP_TX_GP_TIME_MASK BIT(4) // 通用定时器中断
+#define FDP_TX_AUX_TIMEOUT_MASK BIT(3) //因等待 AUX reply 超时发起中断
+#define FDP_TX_AUX_RECEIVED_MASK BIT(2) //接收到 AUX reply 发起中断
+#define FDP_TX_HPD_INTR_MASK BIT(1) //hpd irq 中断
+#define FDP_TX_HPD_EVENT_MASK BIT(0)//HPD 连接或断开事件 中断
+
+#define FDP_TX_STATUS_AUX_ERROR BIT(6) 
+#define FDP_TX_STATUS_GP_TIME BIT(4) 
+#define FDP_TX_STATUS_AUX_TIMEOUT BIT(3)
+#define FDP_TX_STATUS_AUX_RECEIVED BIT(2) 
+#define FDP_TX_STATUS_HPD_INTR BIT(1) 
+#define FDP_TX_STATUS_HPD_EVENT BIT(0)
+
+/*
+  eDP CRC registers
+*/
+#define FDPTX_EDP_CRC_ENABLE 0x01D0
+#define FDPTX_EDP_CRC_RED 0x01D4
+#define FDPTX_EDP_CRC_GREEN 0x01D8
+#define FDPTX_EDP_CRC_BLUE 0x01DC
+
+/* write the data to the channel of dp */
+void FDpChannelRegWrite(uintptr addr,  uintptr offset, u32 data);
+
+/* read the data from the channel of dp */
+FError FDpChannelRegRead(uintptr addr, uintptr offset);
+
+/* write FdpPhy control register */
+void FDpPhyRegWrite(uintptr addr,uintptr offset, u32 data);
+
+/* read FdpPhy control register */
+FError FDpPhyRegRead(uintptr addr,  uintptr offset);
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h
new file mode 100644
index 00000000000..c8316b89427
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h
@@ -0,0 +1,349 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fdp_phy.h
+ * Date: 2022-09-08 14:53:42
+ * LastEditTime: 2022-09-08 14:53:42
+ * Description:  This file is for providing the dp phy register and function
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ *  1.0  Wangzq     2022/12/20   Modify the format and establish the version
+ */
+#ifndef FDP_PHY_H
+#define FDP_PHY_H
+
+#include "fdp.h"
+/*
+** DPCD Address
+*/
+#define DPCD_REV 0x00000
+#define MAX_LINK_RATE 0x00001
+#define MAX_LANE_COUNT 0x00002
+#define MAX_DOWNSPREAD 0x00003
+#define NORP_DP_PWR_VOLTAGE_CAP 0x00004
+#define DOWN_STRAM_PORT_PRESENT 0x00005
+#define MAIN_LINK_CHANNEL_CODING 0x00006
+#define DOWN_STREAM_PORT_COUNT 0x00007
+#define RECEIVE_PORT0_CAP_0 0x00008
+#define RECEIVE_PORT0_CAP_1 0x00009
+#define RECEIVE_PORT1_CAP_0 0x0000A
+#define RECEIVE_PORT1_CAP_1 0x0000B
+#define I2C_SPEED_CONTROL_CAPABILITIES 0x0000C
+#define EDP_CONFIGURATION_CAP 0x0000D
+#define TRAINING_AUX_RD_INTERVAL 0x0000E
+#define ADAPTOR_CAP 0x0000F
+
+#define MSTM_CAP 0x00021
+#define NUMBER_OF_AUDIO_ENDPOINTS 0x00022
+#define AV_SYNC_DATA_BLOCK_DEC 0x00023
+#define AV_SYNC_DATA_BLOCK_DEC_LOW 0x00024
+#define AV_SYNC_DATA_BLOCK_DEC_HIGH 0x00025
+#define AV_SYNC_DATA_BLOCK_PP_LOW 0x00026
+#define AV_SYNC_DATA_BLOCK_PP_HIGH 0x00027
+#define AV_SYNC_DATA_BLOCK_INTER 0x00028
+#define AV_SYNC_DATA_BLOCK_PROG 0x00029
+#define AV_SYNC_DATA_BLOCK_REP_LOW 0x0002A
+#define AV_SYNC_DATA_BLOCK_DEL_LOW 0x0002B
+#define AV_SYNC_DATA_BLOCK_DEL_MID 0x0002C
+#define AV_SYNC_DATA_BLOCK_DEL_HIGH 0x0002D
+
+#define RX_GTC_VALUE_0 0x00054
+#define RX_GTC_VALUE_1 0x00055
+#define RX_GTC_VALUE_2 0X00056
+#define RX_GTC_VALUE_3 0X00057
+#define RX_GTC_MSTR_REQ 0x00058
+#define RX_GTC_FREQ_LOCK_DONE 0x00059
+#define RX_GTC_PHASE_SKEW_OFFSET_0 0x0005A
+#define RX_GTC_PHASE_SKEW_OFFSET_1 0x0005B
+#define DSC_SUPPORT 0x00060
+#define DSC_ALGORITHM_REVISION 0x00061
+#define DSC_RC_BUFFER_CLOCK_SIZE 0x00062
+#define DSC_RC_BUFFER_SIZE 0x00063
+#define DSC_SLICE_BAPABILITIES_1 0x00064
+#define DSC_LINE_BUFFER_BLT_DEPTH 0x00065
+#define DSC_BLOCK_PREDICTION_SUPPORT 0x00066
+#define MAX_BITS_PER_PIXEL_SUPPORTED 0x00067
+#define DSC_COLOR_FORMAT_CAPABILITIES 0x00069
+#define DSC_COLOR_DEPTH_CAPABILITIES 0x0006A
+#define PEAK_DSC_THROUGHPUT 0x0006B
+#define DSC_MAX_SLICE_WIDTH 0x0006C
+#define DSC_SLICE_CAPABILITIES_2 0x0006D
+#define MIN_BITS_PER_PIXEL_SUPPORTED 0x0006E
+
+#define PANELSELFREF_CAPSUP_REV 0x00070
+#define PANEL_SELF_REFRESH_CAPABILITIES 0x00071
+#define DETAILED_CAPABILITIES_INFO 0x00080 /*80-8F \
+                                            */
+#define FEC_CAPABILITY 0x00090
+
+#define LINK_BW_SET 0x00100
+#define LANE_COUNT_SET 0x00101
+#define TRAINING_PATTERN_SET 0x00102
+#define TRAINING_LANE0_SET 0x00103
+#define TRAINING_LANE1_SET 0x00104
+#define TRAINING_LANE2_SET 0x00105
+#define TRAINING_LANE3_SET 0x00106
+#define DOWNSPREAD_CTRL 0x00107
+#define MAIN_LINK_CHANNEL_CODING_SET 0x00108
+#define I2C_SPEED_CONTROL_STATUS 0x00109
+#define EDP_CONFIGURATION_SET 0x0010A
+#define LINK_QUAL_LANE0_SET 0x0010B
+#define LINK_QUAL_LANE1_SET 0x0010C
+#define LINK_QUAL_LANE2_SET 0x0010D
+#define LINK_QUAL_LANE3_SET 0x0010E
+#define MSTM_CTRL 0x00111
+#define AUDIO_DELAY_7_0 0x00112
+#define AUDIO_DELAY_15_8 0x00113
+#define AUDIO_DELAY_23_16 0x00114
+#define LINK_RATE_SET_TX_GTC_CAPABILITY 0x00115
+#define UPSTREAM_DEVICE_DP_PWR_NEED 0x00118
+#define EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT 0x00119
+#define FEC_CONFIGURATION 0x00120
+#define TX_GTC_VALUE_7_0 0x00154
+#define TX_GTC_VALUE_15_8 0x00155
+#define TX_GTC_VALUE_23_16 0x00156
+#define TX_GTC_VALUE_31_24 0x00157
+#define RX_GTC_VALUE_PHASE_SKEW_EN 0x00158
+#define TX_GTC_FREQ_LOCK_DONE 0x00159
+#define TX_GTC_PHASE_CKEW_OFFERT_7_0 0x0015A
+#define TX_GTC_PHASE_CKEW_OFFERT_15_8 0x0015B
+#define DSC_ENABLE 0x00160
+#define ADAPTOR_CTRL 0x001A0
+#define BRANCH_DEVICE_CTRL 0x001A1
+#define PAYLOAD_ALLOCATE_SET 0x001C0
+#define PAYLOAD_ALLOCATE_START_TIME_SLOT 0x001C1
+#define PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x001C2
+
+#define SINK_COUNT 0x00200
+#define DEVICE_SERVICE_IRQ_VECTOR 0x00201
+#define LANE0_1_STATUS 0x00202
+#define LANE2_3_STATUS 0x00203
+#define LANE_ALIGN_STATUS_UPDATED 0x00204
+#define SINK_STATUS 0x00205
+#define ADJUST_REQUEST_LANE0_1 0x00206
+#define ADJUST_REQUEST_LANE2_3 0x00207
+#define TRAINING_SCORE_LANE0 0x00208
+#define TRAINING_SCORE_LANE1 0x00209
+#define TRAINING_SCORE_LANE2 0x0020A
+#define TRAINING_SCORE_LANE3 0x0020B
+#define SYMBOL_ERROR_COUNT_LANE0_LOW 0x00210
+#define SYMBOL_ERROR_COUNT_LANE0_HIGH 0x00211
+#define SYMBOL_ERROR_COUNT_LANE1_LOW 0x00212
+#define SYMBOL_ERROR_COUNT_LANE1_HIGH 0x00213
+#define SYMBOL_ERROR_COUNT_LANE2_LOW 0x00214
+#define SYMBOL_ERROR_COUNT_LANE2_HIGH 0x00215
+#define SYMBOL_ERROR_COUNT_LANE3_LOW 0x00216
+#define SYMBOL_ERROR_COUNT_LANE3_HIGH 0x00217
+#define TEST_REQUEST 0x00208
+#define TEST_LINK_RATE 0x00219
+#define TEST_LANE_COUNT 0x00220
+#define TEST_PATTERN 0x00221
+#define TEST_H_TOTAL_HIGH 0x00222
+#define TEST_H_TOTAL_LOW 0x00223
+#define TEST_V_TOTAL_HIGH 0x00224
+#define TEST_V_TOTAL_LOW 0x00225
+#define TEST_H_START_HIGH 0x00226
+#define TEST_H_START_LOW 0x00227
+#define TEST_V_START_HIGH 0x00228
+#define TEST_V_START_LOW 0x00229
+#define TEST_HSYNC_HIGH 0x0022A
+#define TEST_HSYNC_LOW 0x0022B
+#define TEST_VSYNC_HIGH 0x0022C
+#define TEST_VSYNC_LOW 0x0022D
+#define TEST_H_WIDTH_HIGH 0x0022E
+#define TEST_H_WIDTH_LOW 0x0022F
+#define TEST_V_HEIGHT_HIGH 0x00230
+#define TEST_V_HEIGHT_LOW 0x00231
+#define TEST_MISC_LOW 0x00232
+#define TEST_MISC_HIGH 0x00233
+#define TEST_REFRESH_RATE_NUMERATOR 0x00234
+#define TEST_CRC_R_CR_LOW 0x00240
+#define TEST_CRC_R_CR_HIGH 0x00241
+#define TEST_CRC_G_Y_LOW 0x00242
+#define TEST_CRC_G_Y_HIGH 0x00243
+#define TEST_CRC_B_CB_LOW 0x00244
+#define TEST_CRC_B_CB_HIGH 0x00245
+#define TEST_CRC_COUNT 0x00246
+#define PHY_TEST_PATTERN 0x00248
+#define HBR2_COMPLIANCE_SCRAMBLER_RESET_7_0 0x0024A
+#define HBR2_COMPLIANCE_SCRAMBLER_RESET_15_8 0x0024B
+#define TEST_80BIT_CUSTOM_PATTERN_7_0 0x00250
+#define TEST_80BIT_CUSTOM_PATTERN_15_8 0x00251
+#define TEST_80BIT_CUSTOM_PATTERN_23_16 0x00252
+#define TEST_80BIT_CUSTOM_PATTERN_31_24 0x00253
+#define TEST_80BIT_CUSTOM_PATTERN_39_32 0x00254
+#define TEST_80BIT_CUSTOM_PATTERN_47_40 0x00255
+#define TEST_80BIT_CUSTOM_PATTERN_55_48 0x00256
+#define TEST_80BIT_CUSTOM_PATTERN_63_56 0x00257
+#define TEST_80BIT_CUSTOM_PATTERN_71_64 0x00258
+#define TEST_80BIT_CUSTOM_PATTERN_79_72 0x00259
+#define CONTINUOUS_80BIT_PATTERN_FROM_DPRX_AUX_CH_CAP 0x0025A
+#define CONTINUOUS_80BIT_PATTERN_FROM_DPRX_AUX_CH_CTRL 0x0025B
+#define TEST_RESPONSE 0x00260
+#define TEST_EDID_CHECHSUM 0x00261
+#define TEST_SINK 0x00270
+#define TEST_AUDIO_MODE 0x00271
+#define TEST_AUDIO_PATTERN_TYPE 0x00272
+#define TEST_AUDIO_PERIOD_CH_1 0x00273
+#define TEST_AUDIO_PERIOD_CH_2 0x00274
+#define TEST_AUDIO_PERIOD_CH_3 0x00275
+#define TEST_AUDIO_PERIOD_CH_4 0x00276
+#define TEST_AUDIO_PERIOD_CH_5 0x00277
+#define TEST_AUDIO_PERIOD_CH_6 0x00278
+#define TEST_AUDIO_PERIOD_CH_7 0x00279
+#define TEST_AUDIO_PERIOD_CH_8 0x0027A
+#define FEC_STATUS 0x00280
+#define FEC_ERROR_COUNT0 0x00281
+#define FEC_ERROR_COUNT1 0x00282
+#define PAYLOAD_TABLE_UPDATE_STATUS 0x002C0
+
+#define IEEE_OUI 0x00300
+#define DEVICE_ID_STRING 0x00303
+#define HARDWARE_REVISION 0x00309
+#define FIRMWARE_SOFTWARE_MAJOR_REV 0x0030A
+#define FIRMWARE_SOFTWARE_MINOR_REV 0x0030B
+
+#define SET_POWER_SET_DP_PWR_VALTAGE 0x00600
+
+#define SINK_COUNT_ESI 0x02002
+#define DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
+#define DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x02004
+#define LINK_SERVICE_IRQ_VECTOR_ESI0 0x02005
+#define LANE0_1_STATUS_ESI 0x0200C
+#define LANE2_3_STATUS_ESI 0x0200D
+#define LANE_ALIGN_STATUS_UPDATED_ESI 0x0200E
+#define SINK_STATUS_ESI 0x0200F
+
+#define LINK_TRAINING_TPS1 0x01
+#define LINK_TRAINING_TPS2 0x02
+#define LINK_TRAINING_TPS3 0x03
+#define LINK_TRAINING_TPS4 0x07
+
+/*
+ DP PHY Register
+*/
+#define REG_32BIT_SEL 0x40000
+#define REG_EB_MODE 0x40004
+#define REG_RX_EQ_TRAINING 0x40008
+#define REG_RX_TERMINATION 0x4000c
+#define REG_128B_ENC_BYP 0x40010
+#define REG_TX_ONE_ZEROS 0x40014
+#define REG_TX_PATTTERN 0x40018
+#define REG_RXSTARTHIGH 0x4001c
+#define REG_LINKEVAL_MERIT 0x40020
+#define REG_MODE 0x40034
+#define REG_L1_SS_SEL 0x40038
+#define REG_RX_ELEC_IDLE_DET_EN 0x4003c
+#define REG_TX_CMN_MODE_EN 0x40040
+#define REG_FULLRT_DIV 0x40048
+#define REG_MISC 0x4004c
+#define REG_XCVR_POWER_STATE_REQ 0x402bc /*  0x40210*/
+#define REG_PLLCLK_EN 0x40214
+#define REG_PMA_STANDARD_MODE 0x40218
+#define REG_PMA_DATA_WIDTH 0x4021c
+#define REG_TX_ELEC_IDLE 0x40220
+#define REG_TX_DEEMPH_0 0x40224
+#define REG_GET_LOCAL_PRESET 0x40228
+#define REG_LOCAL_PRESET_INDEX 0x4022c
+#define REG_PMA_VMARGIN 0x40230
+#define REG_PMA_LOW_POWER_SWING 0x40234
+#define REG_PMA_RX_EQ_TRAINING_DATA_VALID 0x40238
+#define REG_PMA_RX_EQ_EVAL 0x4023c
+#define REG_MAC_SRC_SEL 0x40240
+#define REG_DIV_SEL0 0x40244
+#define REG_PMA_TX_RCV_DETECT 0x40248
+#define REG_PHY_MODE 0x4024c
+#define REG_APB_RESET_DEASSERT 0x40250
+#define REG_PHY_RESET_DEASSERT 0x40254
+#define REG_PHY_RESET_LINK_DEASSERT 0x40258
+#define REG_PHY_INTERRUPT 0x4025c
+#define REG_SGMII_DPSEL_INIT 0x40260
+
+#define PHY_PLL_CFG 0x30038
+#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x684
+#define XCVR_DIAG_HSCLK_SEL 0x10398
+#define XCVR_DIAG_HSCLK_DIV 0x1039c
+#define XCVR_DIAG_PLLDRC_CTRL 0x10394
+#define CMN_PLL0_DSM_DIAG_M0 0x250
+#define CMN_PLL0_VCOCAL_REFTIM_START 0x218
+#define CMN_PLL0_VCOCAL_TCTRL 0x208
+#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x690
+#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x694
+#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x698
+#define CMN_PLL0_INTDIV_M0 0x240
+#define CMN_PLL0_FRACDIVL_M0 0x244
+#define CMN_PLL0_FRACDIVH_M0 0x248
+#define CMN_PLL0_HIGH_THR_M0 0x24c
+#define CMN_PDIAG_PLL0_CTRL_M0 0x680
+#define CMN_PLL0_VCOCAL_PLLCNT_START 0x220
+#define CMN_PLL0_LOCK_REFCNT_START 0x270
+#define CMN_PLL0_LOCK_PLLCNT_START 0x278
+#define CMN_PLL0_LOCK_PLLCNT_THR 0x27c
+#define TX_PSC_A0 0x10400
+#define TX_PSC_A2 0x10408
+#define TX_PSC_A3 0x1040c
+#define RX_PSC_A0 0x20000
+#define RX_PSC_A2 0x20008
+#define RX_PSC_A3 0x2000c
+#define RX_PSC_CAL 0x20018
+#define XCVR_DIAG_BIDI_CTRL 0x103a8
+#define RX_REE_GCSM1_CTRL 0x20420
+#define RX_REE_GCSM2_CTRL 0x20440
+#define RX_REE_PERGCSM_CTRL 0x20460
+#define TX_DIAG_ACYA 0x1079c
+#define TX_TXCC_CTRL 0x10100
+#define DRV_DIAG_TX_DRV 0x10318
+#define TX_TXCC_MGNFS_MULT_000 0x10140
+#define TX_TXCC_CPOST_MULT_00 0x10130
+#define PHY_PMA_CMN_CTRL2 0x38004
+#define PHY_PMA_PLL_RAW_CTRL 0x3800c
+
+FError FDptxPhyGetLaneCount(FDpCtrl *instance_p, u8 *lanecount);
+
+FError FDpTxPhyGetLinkRate(FDpCtrl *instance_p, u32 *linkrate);
+
+/* DP phy date rate change.*/
+void FDpLinkPhyChangeRate(FDpCtrl *instance_p, u32 link_rate);
+
+/* Get sink ENHANCED_FRAME_CAP */
+FError FDpTxPhyGetEnhancedFrameCap(FDpCtrl *instance_p);
+
+/* configure the PHY for the specified link rate */
+FError FDpTxPhyUpdateLinkRate(FDpCtrl *instance_p, u32 link_rate);
+
+/* set the lane count in the PHY */
+void FDpTxPhySetLaneCount(FDpCtrl *instance_p, u32 lane_count);
+
+/*Get voltage swing of a specified lane.Voltage swing has three levels*/
+FError FDpTxSourceVswingForValue(FDpCtrl *instance_p, u8 lane_num);
+
+/* Get pre-emphasis level of a specified lane*/
+FError FDpTxSourcePreemphasisForValue(FDpCtrl *instance_p, u8 lane_num);
+
+/*  Get sink TPS4 support.*/
+FError FDpTxPhyTps4Supported(FDpCtrl *instance_p);
+
+/*  Get sink TPS3 support.*/
+FError FDpTxPhyTps3Supported(FDpCtrl *instance_p);
+
+/*  Get Swing and pre-emphasis level form sink*/
+FError FDpTxPhyGetAdjustRequest(FDpCtrl *instance_p, u8 *swing, u8 *pre_emphasis);
+
+/*Display phy initialization */
+void FDpLinkPhyInit(FDpCtrl *instance_p, u32 link_rate);
+
+/* Voltage swing and pre-emphasis training.*/
+void FDpLinkPhyChangeVsWing(FDpCtrl *instance_p, u32 vswing, u32 pre_emphasis);
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/Kconfig b/bsp/phytium/libraries/standalone/drivers/mio/Kconfig
index 018035d6e8d..f92d3360c1e 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/mio/Kconfig
@@ -2,7 +2,7 @@ menu "Hardware Mio Configuration"
     config ENABLE_MIO
         bool
         prompt "Use Mio"
-        depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q
+        depends on TARGET_E2000 || TARGET_TARDIGRADE
 
         default n
 endmenu
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.c b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.c
index ab35e436aa9..7c24c102ed9 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.c
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.c
@@ -1,25 +1,27 @@
 /*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
  * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
  * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
+ * See the Phytium Public License for more details. 
+ *  
+ * 
  * FilePath: fmio.c
  * Date: 2022-07-06 15:01:30
  * LastEditTime: 2022-07-06 15:01:30
- * Description:  This file is for
+ * Description:  This file is for user external interface
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming  2022/07/06  first commit
  */
+
 #include <string.h>
 #include "fmio_hw.h"
 #include "fmio.h"
@@ -27,6 +29,7 @@
 /***************** Macros (Inline Functions) Definitions *********************/
 #define FMIO_DEBUG_TAG "MIO"
 #define FMIO_ERROR(format, ...)   FT_DEBUG_PRINT_E(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FMIO_WARN(format, ...)    FT_DEBUG_PRINT_W(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FMIO_INFO(format, ...)    FT_DEBUG_PRINT_I(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FMIO_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FMIO_DEBUG_TAG, format, ##__VA_ARGS__)
 
@@ -41,26 +44,25 @@ FError FMioFuncInit(FMioCtrl *instance_p, u32 mio_type)
 {
     FASSERT(instance_p);
 
-    FError ret = FMIO_SUCCESS;
-
-    /*
-        * If the device is started, disallow the initialize and return a Status
-        * indicating it is started.  This allows the user to de-initialize the device
-        * and reinitialize, but prevents a user from inadvertently
-        * initializing.
-    */
-    if (FT_COMPONENT_IS_READY == instance_p->is_ready)
-    {
-        FMIO_ERROR("device is already initialized!!!");
-        return FMIO_ERR_INVAL_STATE;
-    }
-
-    ret = FMioSelectFunc(instance_p->config.mio_base_addr, mio_type);
-    if (FMIO_SUCCESS == ret)
-    {
-        instance_p->is_ready = FT_COMPONENT_IS_READY;
-    }
-    return ret;
+	FError ret = FMIO_SUCCESS;
+
+	/*
+		* If the device is started, disallow the initialize and return a Status
+		* indicating it is started.  This allows the user to de-initialize the device
+		* and reinitialize, but prevents a user from inadvertently
+		* initializing.
+	*/
+	if (FT_COMPONENT_IS_READY == instance_p->is_ready)
+	{
+		FMIO_WARN("Device is already initialized.");
+	}
+
+    ret = FMioSelectFunc(instance_p->config.mio_base_addr,mio_type);
+	if (FMIO_SUCCESS == ret)
+	{
+		instance_p->is_ready = FT_COMPONENT_IS_READY;
+	}
+	return ret;
 }
 
 /**
@@ -72,16 +74,16 @@ FError FMioFuncInit(FMioCtrl *instance_p, u32 mio_type)
 FError FMioFuncDeinit(FMioCtrl *instance_p)
 {
     FASSERT(instance_p);
-    FError ret = FMIO_SUCCESS;
+	FError ret = FMIO_SUCCESS;
 
-    instance_p->is_ready = 0;
+	instance_p->is_ready = 0;
 
-    /* 重新配置成默认IIC模式 */
-    ret = FMioSelectFunc(instance_p->config.mio_base_addr, FMIO_FUNC_SET_I2C);
+	/* 重新配置成默认IIC模式 */
+	ret = FMioSelectFunc(instance_p->config.mio_base_addr, FMIO_FUNC_SET_I2C);
 
-    memset(instance_p, 0, sizeof(*instance_p));
+	memset(instance_p, 0, sizeof(*instance_p));
 
-    return ret;
+	return ret;
 }
 
 /**
@@ -90,24 +92,24 @@ FError FMioFuncDeinit(FMioCtrl *instance_p)
  * @return {uintptr}
  * @param {FMioCtrl} *instance_p
  */
-uintptr FMioFuncGetAddress(FMioCtrl *instance_p, u32 mio_type)
+uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type)
 {
-    FASSERT(instance_p);
-    FError ret = FMIO_SUCCESS;
-
-    if (instance_p->is_ready != FT_COMPONENT_IS_READY)
-    {
-        FMIO_ERROR("Mio instance_id: %d ,not init.", instance_p->config.instance_id);
-        return FMIO_ERR_NOT_READY;
-    }
+	FASSERT(instance_p);
+	FError ret = FMIO_SUCCESS;
+	
+	if (instance_p->is_ready != FT_COMPONENT_IS_READY)
+	{
+		FMIO_ERROR("Mio instance_id: %d ,not init.",instance_p->config.instance_id );
+		return FMIO_ERR_NOT_READY;
+	}
 
     if (FMioGetFunc(instance_p->config.mio_base_addr) != mio_type)
     {
-        FMIO_ERROR("Mio instance_id: %d ,mio_type error,please init type first.", instance_p->config.instance_id);
+        FMIO_ERROR("Mio instance_id: %d ,mio_type error, initialize the type first.", instance_p->config.instance_id);
         return FMIO_ERR_INVAL_STATE;
     }
 
-    return instance_p->config.func_base_addr;
+	return instance_p->config.func_base_addr;
 }
 
 /**
@@ -116,22 +118,22 @@ uintptr FMioFuncGetAddress(FMioCtrl *instance_p, u32 mio_type)
  * @return {u32}中断号
  * @param {FMioCtrl} *instance_p
  */
-u32 FMioFuncGetIrqNum(FMioCtrl *instance_p, u32 mio_type)
+u32 FMioFuncGetIrqNum(FMioCtrl *instance_p,u32 mio_type)
 {
-    FASSERT(instance_p);
-    FError ret = FMIO_SUCCESS;
-
-    if (instance_p->is_ready != FT_COMPONENT_IS_READY)
-    {
-        FMIO_ERROR("Mio instance_id: %d ,not init.", instance_p->config.instance_id);
-        return FMIO_ERR_NOT_READY;
-    }
+	FASSERT(instance_p);
+	FError ret = FMIO_SUCCESS;
+	
+	if (instance_p->is_ready != FT_COMPONENT_IS_READY)
+	{
+		FMIO_ERROR("Mio instance_id: %d ,not init.",instance_p->config.instance_id);
+		return FMIO_ERR_NOT_READY;
+	}
 
     if (FMioGetFunc(instance_p->config.mio_base_addr) != mio_type)
     {
-        FMIO_ERROR("Mio instance_id: %d ,mio_type error,please init type first.", instance_p->config.instance_id);
+        FMIO_ERROR("Mio instance_id: %d ,mio_type error, initialize the type first.", instance_p->config.instance_id);
         return FMIO_ERR_INVAL_STATE;
     }
 
-    return instance_p->config.irq_num;
+	return instance_p->config.irq_num;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.h b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.h
index 5343130addf..20645951973 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.h
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio.h
@@ -14,15 +14,16 @@
  * FilePath: fmio.h
  * Date: 2022-06-21 15:40:06
  * LastEditTime: 2022-06-21 15:40:06
- * Description:  This file is for
+ * Description:  This file is for user external interface definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming  2022/06/21  first commit
  */
 
-#ifndef DRIVERS_MIO_FMIO_H
-#define DRIVERS_MIO_FMIO_H
+#ifndef FMIO_H
+#define FMIO_H
 
 #ifdef __cplusplus
 extern "C"
@@ -47,9 +48,9 @@ extern "C"
 
 typedef struct
 {
-    u32     instance_id;        /*mio id*/
+    u32     instance_id;    /*mio id*/
     uintptr func_base_addr; /*I2C or UART function address*/
-    u32     irq_num;     /* Device intrrupt id */
+    u32     irq_num;        /* Device intrrupt id */
     uintptr mio_base_addr;  /*MIO control address*/
 } FMioConfig;               /*mio configs*/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_g.c b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_g.c
index e018aa64521..09fd293ab6d 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_g.c
@@ -14,12 +14,12 @@
  * FilePath: fmio_g.c
  * Date: 2022-06-20 21:05:07
  * LastEditTime: 2022-06-20 21:05:07
- * Description:  This file is for mio
+ * Description:  This file is for mio static configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 0.1.0  liu       2022.06.20    init
+ * 1.0  liushengming 2022/06/20    first commit
  */
 
 /***************************** Include Files *********************************/
@@ -29,102 +29,104 @@
 
 /************************** Constant Definitions *****************************/
 
-const FMioConfig FMioConfigTbl[MIO_INSTANCE_NUM] =
+const FMioConfig FMioConfigTbl[FMIO_NUM] =
 {
     {
-        .instance_id = MIO_INSTANCE_0,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_0),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_0),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_0)
+        .instance_id = FMIO0_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO0_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO0_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO0_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_1,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_1),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_1),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_1)
+        .instance_id = FMIO1_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO1_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO1_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO1_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_2,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_2),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_2),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_2)
+        .instance_id = FMIO2_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO2_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO2_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO2_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_3,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_3),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_3),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_3)
+        .instance_id = FMIO3_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO3_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO3_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO3_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_4,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_4),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_4),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_4)
+        .instance_id = FMIO4_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO4_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO4_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO4_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_5,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_5),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_5),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_5)
+        .instance_id = FMIO5_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO5_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO5_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO5_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_6,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_6),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_6),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_6)
+        .instance_id = FMIO6_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO6_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO6_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO6_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_7,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_7),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_7),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_7)
+        .instance_id = FMIO7_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO7_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO7_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO7_ID)
     },
+#if defined(CONFIG_TARGET_E2000)
     {
-        .instance_id = MIO_INSTANCE_8,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_8),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_8),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_8)
+        .instance_id = FMIO8_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO8_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO8_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO8_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_9,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_9),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_9),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_9)
+        .instance_id = FMIO9_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO9_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO9_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO9_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_10,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_10),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_10),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_10)
+        .instance_id = FMIO10_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO10_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO10_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO10_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_11,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_11),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_11),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_11)
+        .instance_id = FMIO11_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO11_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO11_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO11_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_12,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_12),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_12),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_12)
+        .instance_id = FMIO12_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO12_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO12_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO12_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_13,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_13),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_13),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_13)
+        .instance_id = FMIO13_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO13_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO13_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO13_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_14,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_14),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_14),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_14)
+        .instance_id = FMIO14_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO14_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO14_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO14_ID)
     },
     {
-        .instance_id = MIO_INSTANCE_15,
-        .func_base_addr = FMIO_BASE_ADDR(MIO_INSTANCE_15),
-        .irq_num = FMIO_IRQ_NUM(MIO_INSTANCE_15),
-        .mio_base_addr = FMIO_BASE_SET_ADDR(MIO_INSTANCE_15)
+        .instance_id = FMIO15_ID,
+        .func_base_addr = FMIO_BASE_ADDR(FMIO15_ID),
+        .irq_num = FMIO_IRQ_NUM(FMIO15_ID),
+        .mio_base_addr = FMIO_BASE_SET_ADDR(FMIO15_ID)
     }
+#endif
 };
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.c b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.c
index 336d93c52ee..c0773f88f1d 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.c
@@ -14,12 +14,12 @@
  * FilePath: fmio_hw.c
  * Date: 2022-06-20 21:05:23
  * LastEditTime: 2022-06-20 21:05:23
- * Description:  This file is for mio
+ * Description:  This file is for mio hardware operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 0.1.0    liushengming  2022.06.20    init
+ * 1.0  liushengming 2022/06/20 first commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.h b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.h
index acc1699fae8..35120d04452 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_hw.h
@@ -14,20 +14,15 @@
  * FilePath: fmio_hw.h
  * Date: 2022-06-20 21:05:34
  * LastEditTime: 2022-06-20 21:05:34
- * Description:  This file is for mio
+ * Description:  This file is for mio hardware define
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 0.1.0  liushengming  2022.06.20  init
+ * 1.0  liushengming  2022/06/20  init
  */
-#ifndef DRIVERS_MIO_FMIO_HW_H
-#define DRIVERS_MIO_FMIO_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FMIO_HW_H
+#define FMIO_HW_H
 
 #include "fparameters.h"
 #include "fio.h"
@@ -35,6 +30,11 @@ extern "C"
 #include "fdebug.h"
 #include "ferror_code.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 
 /************************** Constant Definitions *****************************/
 
@@ -56,7 +56,9 @@ enum
 {
     FMIO_FUNC_SET_I2C = 0b00,
     FMIO_FUNC_SET_UART = 0b01,
-
+#if defined(TARDIGRADE)
+    FMIO_FUNC_SET_PWM = 0b10,
+#endif
     FMIO_NUM_OF_MIO_FUNC
 };
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_sinit.c b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_sinit.c
index a971924e37e..e1dbac3c6ff 100644
--- a/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/mio/fmio/fmio_sinit.c
@@ -14,12 +14,12 @@
  * FilePath: fmio_sinit.c
  * Date: 2022-06-20 20:33:25
  * LastEditTime: 2022-06-20 20:33:25
- * Description:  This file is for mio
+ * Description:  This file is for mio static initialization functionality
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 0.1.0  liushengming  2022.06.20  init
+ * 1.0  liushengming  2022/06/20  first commit
  */
 #include "ftypes.h"
 #include "fparameters.h"
@@ -28,7 +28,7 @@
 #include "fmio_hw.h"
 
 
-extern FMioConfig FMioConfigTbl[MIO_INSTANCE_NUM];
+extern FMioConfig FMioConfigTbl[FMIO_NUM];
 
 /***************** Macros (Inline Functions) Definitions *********************/
 #define FMIO_DEBUG_TAG "MIO"
@@ -44,11 +44,11 @@ extern FMioConfig FMioConfigTbl[MIO_INSTANCE_NUM];
  */
 const FMioConfig *FMioLookupConfig(u32 instance_id)
 {
-    FASSERT(instance_id < MIO_INSTANCE_NUM);
+    FASSERT(instance_id < FMIO_NUM);
     const FMioConfig *pconfig = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)MIO_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FMIO_NUM; index++)
     {
         if (FMioConfigTbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/Kconfig b/bsp/phytium/libraries/standalone/drivers/mmc/Kconfig
index 31805318a87..4a7b0bf8b9c 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/Kconfig
@@ -3,7 +3,6 @@ config ENABLE_FSDMMC
     prompt "Use FSdmmc"
     default n
     depends on USE_SDMMC
-    depends on TARGET_F2000_4 || TARGET_D2000
     help
         Select FSdmmc driver component
 
@@ -12,8 +11,7 @@ config ENABLE_FSDIO
     prompt "Use FSdio"
     default n
     depends on USE_SDMMC
-    depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q
     help
         Select FSdio driver component
-
-
+	
+	
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c
index 771e4ff9ca2..51e20c0a5c1 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio.c
  * Date: 2022-05-26 16:27:54
  * LastEditTime: 2022-05-26 16:27:54
- * Description:  This files is for SDIO user function implementation
+ * Description:  This file is for SDIO user function implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -67,18 +67,20 @@ FError FSdioCfgInitialize(FSdio *const instance_p, const FSdioConfig *input_conf
 
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FSDIO_WARN("device is already initialized!!!");
+        FSDIO_WARN("Device is already initialized!!!");
     }
 
     if (&instance_p->config != input_config_p)
+    {
         instance_p->config = *input_config_p;
+    }
 
     ret = FSdioReset(instance_p); /* reset the device */
 
     if (FSDIO_SUCCESS == ret)
     {
         instance_p->is_ready = FT_COMPONENT_IS_READY;
-        FSDIO_INFO("device initialize success !!!");
+        FSDIO_INFO("Device initialize success !!!");
     }
 
     return ret;
@@ -125,7 +127,7 @@ FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz)
     u32 first_uhs_div, tmp_ext_reg, div_reg;
     FError ret = FSDIO_SUCCESS;
 
-    FSDIO_INFO("set clk as %ld", input_clk_hz);
+    FSDIO_INFO("set clk as %ld.", input_clk_hz);
 
     /* must set 2nd stage clcok first then set 1st stage clock */
     /* experimental uhs setting  --> 2nd stage clock, below setting parameters get from
@@ -149,18 +151,22 @@ FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz)
     /* update uhs setting */
     ret = FSdioUpdateExternalClk(base_addr, tmp_ext_reg);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     FSdioSetClock(base_addr, FALSE); /* disable clock */
 
     /* send private cmd to update clock */
     ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* experimental clk divide setting -- 1st stage clock */
     first_uhs_div = 1 + FSDIO_UHS_CLK_DIV_GET(tmp_ext_reg);
-    div = FSDIO_CLK_RATE_HZ / (2 * first_uhs_div * input_clk_hz);
+    div = FSDIO_CLK_FREQ_HZ / (2 * first_uhs_div * input_clk_hz);
     if (div > 2)
     {
         sample = div / 2 + 1;
@@ -179,20 +185,43 @@ FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz)
                FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET),
                FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET));
 
-    FSDIO_INFO("UHS_REG_EXT ext: 0x%x, CLKDIV: 0x%x",
-               FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET),
-               FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET));
-
     FSdioSetClock(base_addr, TRUE); /* enable clock */
 
     /* update clock for 1 stage clock */
     ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
+    FSDIO_INFO("FSdioSetClkFreq done.");
     return ret;
 }
 
+/**
+ * @name: FSdioGetClkFreq
+ * @msg: Get the real Card clock freqency
+ * @return {u32} real clock freqency in Hz
+ * @param {FSdio} *instance_p, SDIO controller instance
+ */
+u32 FSdioGetClkFreq(FSdio *const instance_p)
+{
+    FASSERT(instance_p);
+    uintptr base_addr = instance_p->config.base_addr;
+
+    u32 uhs_reg_val = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET);
+    u32 first_uhs_div = 1 + FSDIO_UHS_CLK_DIV_GET(uhs_reg_val);
+
+    u32 div_reg_val = FSDIO_READ_REG(base_addr, FSDIO_CLKDIV_OFFSET);
+    u32 div = FSDIO_CLK_DIVDER_GET(div_reg_val);
+
+    FSDIO_INFO("uhs_reg_val = 0x%x, div_reg_val = 0x%x", uhs_reg_val, div_reg_val);
+    FSDIO_INFO("first_div = %d, second_div = %d", first_uhs_div, div);
+    u32 real_clk_hz = FSDIO_CLK_FREQ_HZ / (2 * first_uhs_div * div);
+
+    return real_clk_hz;
+}
+
 /**
  * @name: FSdioWaitClkReady
  * @msg: Wait clock ready after modify clock setting
@@ -213,7 +242,7 @@ static FError FSdioWaitClkReady(uintptr base_addr, int retries)
 
     if (!(reg_val & FSDIO_CLK_READY) && (retries <= 0))
     {
-        FSDIO_ERROR("wait clk ready timeout !!! status: 0x%x",
+        FSDIO_ERROR("Wait clk ready timeout !!! status: 0x%x",
                     reg_val);
         return FSDIO_ERR_TIMEOUT;
     }
@@ -239,7 +268,9 @@ static FError FSdioUpdateExternalClk(uintptr base_addr, u32 uhs_reg_val)
     {
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_GPIO_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
     while (!(reg_val & FSDIO_CLK_READY));
 
@@ -263,12 +294,16 @@ FError FSdioResetCtrl(uintptr base_addr, u32 reset_bits)
     {
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_CNTRL_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
     while (reset_bits & reg_val);
 
     if (retries <= 0)
+    {
         return FSDIO_ERR_TIMEOUT;
+    }
 
     return FSDIO_SUCCESS;
 }
@@ -290,13 +325,61 @@ FError FSdioResetBusyCard(uintptr base_addr)
         FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_CONTROLLER_RESET);
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
     while (reg_val & FSDIO_STATUS_DATA_BUSY);
 
     return (retries <= 0) ? FSDIO_ERR_BUSY : FSDIO_SUCCESS;
 }
 
+/**
+ * @name: FSdioPollWaitBusyCard
+ * @msg: poll wait until card not busy
+ * @return {FError} FSDIO_SUCCESS if exit with card not busy
+ * @param {FSdio *const} instance_p, instance of controller
+ */
+FError FSdioPollWaitBusyCard(FSdio *const instance_p)
+{
+    FASSERT(instance_p);
+    FASSERT(instance_p->relax_handler);
+    uintptr base_addr = instance_p->config.base_addr;
+    u32 reg_val;
+    FError err = FSDIO_SUCCESS;
+    int retries = FSDIO_TIMEOUT;
+    const u32 busy_bits = FSDIO_STATUS_DATA_BUSY | FSDIO_STATUS_DATA_STATE_MC_BUSY;
+
+    reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
+    if (reg_val & busy_bits)
+    {
+        FSDIO_WARN("Card is busy, waiting ...");
+    }
+
+    do
+    {
+        reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
+        if (--retries <= 0)
+        {
+            break;
+        }
+
+        if (instance_p->relax_handler)
+        {
+            instance_p->relax_handler();    /* wait card busy could be time-consuming */
+        }
+    }
+    while (reg_val & busy_bits);   /* wait busy bits empty */
+
+    if (--retries <= 0)
+    {
+        FSDIO_ERROR("Wait card busy timeout !!!");
+        err = FSDIO_ERR_TIMEOUT;
+    }
+
+    return err;
+}
+
 /**
  * @name: FSdioRestartClk
  * @msg: restart controller clock from error status
@@ -315,12 +398,16 @@ FError FSdioRestartClk(uintptr base_addr)
     {
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_CMD_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
     while (reg_val & FSDIO_CMD_START);
 
     if (retries <= 0)
+    {
         return FSDIO_ERR_TIMEOUT;
+    }
 
     /* update clock */
     FSdioSetClock(base_addr, FALSE);
@@ -330,7 +417,9 @@ FError FSdioRestartClk(uintptr base_addr)
 
     ret = FSdioUpdateExternalClk(base_addr, uhs);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     FSDIO_WRITE_REG(base_addr, FSDIO_CLKDIV_OFFSET, clk_div);
 
@@ -376,7 +465,7 @@ static FError FSdioReset(FSdio *const instance_p)
     ret = FSdioUpdateExternalClk(base_addr, reg_val);
     if (FSDIO_SUCCESS != ret)
     {
-        FSDIO_ERROR("update extern clock failed !!!");
+        FSDIO_ERROR("Update extern clock failed !!!");
         return ret;
     }
 
@@ -387,15 +476,19 @@ static FError FSdioReset(FSdio *const instance_p)
 
     /* set voltage as 3.3v */
     if (FSDIO_SD_1_8V_VOLTAGE == instance_p->config.voltage)
+    {
         FSdioSetVoltage1_8V(base_addr, TRUE);
+    }
     else
+    {
         FSdioSetVoltage1_8V(base_addr, FALSE);
+    }
 
     /* reset controller and card */
     ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
     if (FSDIO_SUCCESS != ret)
     {
-        FSDIO_ERROR("reset controller failed !!!");
+        FSDIO_ERROR("Reset controller failed !!!");
         return ret;
     }
 
@@ -403,15 +496,19 @@ static FError FSdioReset(FSdio *const instance_p)
     ret = FSdioSendPrivateCmd(base_addr, FSDIO_CMD_UPD_CLK, 0U);
     if (FSDIO_SUCCESS != ret)
     {
-        FSDIO_ERROR("update clock failed !!!");
+        FSDIO_ERROR("Update clock failed !!!");
         return ret;
     }
 
     /* reset card for no-removeable media, e.g. eMMC */
     if (TRUE == instance_p->config.non_removable)
+    {
         FSDIO_SET_BIT(base_addr, FSDIO_CARD_RESET_OFFSET, FSDIO_CARD_RESET_ENABLE);
+    }
     else
+    {
         FSDIO_CLR_BIT(base_addr, FSDIO_CARD_RESET_OFFSET, FSDIO_CARD_RESET_ENABLE);
+    }
 
     /* clear interrupt status */
     FSDIO_WRITE_REG(base_addr, FSDIO_INT_MASK_OFFSET, 0U);
@@ -424,7 +521,9 @@ static FError FSdioReset(FSdio *const instance_p)
 
     /* enable card detect interrupt */
     if (FALSE == instance_p->config.non_removable)
+    {
         FSDIO_SET_BIT(base_addr, FSDIO_INT_MASK_OFFSET, FSDIO_INT_CD_BIT);
+    }
 
     /* enable controller and internal DMA */
     FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_INT_ENABLE | FSDIO_CNTRL_USE_INTERNAL_DMAC);
@@ -437,7 +536,7 @@ static FError FSdioReset(FSdio *const instance_p)
     FSdioSetDescriptor(base_addr, (uintptr)NULL); /* set decriptor list as NULL */
     FSdioResetIDMA(base_addr);
 
-    FSDIO_INFO("init hardware done !!!");
+    FSDIO_INFO("Init hardware done !!!");
     return ret;
 }
 
@@ -456,27 +555,39 @@ FError FSdioRestart(FSdio *const instance_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return FSDIO_ERR_NOT_INIT;
     }
 
     /* reset controller */
     ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* reset controller if in busy state */
     ret = FSdioResetBusyCard(base_addr);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* reset clock */
     ret = FSdioRestartClk(base_addr);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* reset internal DMA */
     FSdioResetIDMA(base_addr);
 
     return ret;
+}
+
+void FSdioRegisterRelaxHandler(FSdio *const instance_p, FSdioRelaxHandler relax_handler)
+{
+    FASSERT(instance_p);
+    instance_p->relax_handler = relax_handler;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h
index 6d1f0ba4b91..a2e2fed38fd 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h
@@ -14,7 +14,7 @@
  * FilePath: fsdio.h
  * Date: 2022-05-26 16:20:52
  * LastEditTime: 2022-05-26 16:20:53
- * Description:  This files is for sdio user interface definition
+ * Description:  This file is for sdio user interface definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -22,15 +22,11 @@
  * 1.0   zhugengyu  2021/12/2    init
  * 1.1   zhugengyu  2022/6/6     modify according to tech manual.
  * 1.2   zhugengyu  2022/7/15    adopt to e2000
+ * 1.3   zhugengyu  2022/11/23   fix multi-block rw issues
  */
 
-#ifndef  DRIVERS_FSDIO_H
-#define  DRIVERS_FSDIO_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FSDIO_H
+#define  FSDIO_H
 
 /***************************** Include Files *********************************/
 
@@ -38,19 +34,24 @@ extern "C"
 #include "ferror_code.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 /************************** Constant Definitions *****************************/
 
 /* SDIO driver error code */
-#define FSDIO_SUCCESS           FT_SUCCESS
-#define FSDIO_ERR_TIMEOUT       FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 1)
-#define FSDIO_ERR_NOT_INIT      FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 2)
-#define FSDIO_ERR_SHORT_BUF     FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 3)
-#define FSDIO_ERR_NOT_SUPPORT   FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 4)
-#define FSDIO_ERR_INVALID_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 5)
-#define FSDIO_ERR_TRANS_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 6)
-#define FSDIO_ERR_CMD_TIMEOUT   FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 7)
-#define FSDIO_ERR_NO_CARD       FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 8)
-#define FSDIO_ERR_BUSY          FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 9)
+#define FSDIO_SUCCESS               FT_SUCCESS
+#define FSDIO_ERR_TIMEOUT           FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 1)
+#define FSDIO_ERR_NOT_INIT          FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 2)
+#define FSDIO_ERR_SHORT_BUF         FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 3)
+#define FSDIO_ERR_NOT_SUPPORT       FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 4)
+#define FSDIO_ERR_INVALID_STATE     FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 5)
+#define FSDIO_ERR_TRANS_TIMEOUT     FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 6)
+#define FSDIO_ERR_CMD_TIMEOUT       FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 7)
+#define FSDIO_ERR_NO_CARD           FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 8)
+#define FSDIO_ERR_BUSY              FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 9)
+#define FSDIO_ERR_DMA_BUF_UNALIGN   FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 10)
 
 typedef enum
 {
@@ -80,7 +81,6 @@ typedef enum
     FSDIO_NUM_OF_EVT
 } FSdioEvtType; /* SDIO event type */
 
-#define FSDIO_DEFAULT_BLOCK_SZ          512U
 #define FSDIO_SD_400KHZ                 400000U
 #define FSDIO_SD_25_MHZ                 25000000U
 #define FSDIO_SD_50_MHZ                 50000000U
@@ -88,7 +88,7 @@ typedef enum
 typedef struct _FSdio FSdio;
 
 typedef void (*FSdioRelaxHandler)(void);
-typedef void (*FSdioEvtHandler)(FSdio *const instance_p, void *args);
+typedef void (*FSdioEvtHandler)(FSdio *const instance_p, void *args, u32 status, u32 dmac_status);
 
 typedef struct
 {
@@ -155,6 +155,7 @@ typedef struct
     FSdioTransMode trans_mode;  /* Trans mode, PIO/DMA */
     FSdioVoltageType voltage;   /* Card voltage type */
     boolean        non_removable; /* No removeable media, e.g eMMC */
+    boolean        filp_resp_byte_order; /* Some SD protocol implmentation may not do byte-order filp */
 } FSdioConfig; /* SDIO intance configuration */
 
 typedef struct _FSdio
@@ -164,6 +165,8 @@ typedef struct _FSdio
     FSdioIDmaDescList   desc_list;   /* DMA descriptor list, valid in DMA trans mode */
     FSdioEvtHandler     evt_handlers[FSDIO_NUM_OF_EVT]; /* call-backs for interrupt event */
     void                *evt_args[FSDIO_NUM_OF_EVT]; /* arguments for event call-backs */
+    FSdioRelaxHandler   relax_handler;
+    u32                 prev_cmd; /* record previous command code */
 } FSdio; /* SDIO intance */
 /************************** Variable Definitions *****************************/
 
@@ -186,17 +189,20 @@ FError FSdioSetIDMAList(FSdio *const instance_p, volatile FSdioIDmaDesc *desc, u
 /* Set the Card clock freqency */
 FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz);
 
+/* Get the real Card clock freqency */
+u32 FSdioGetClkFreq(FSdio *const instance_p);
+
 /* Start command and data transfer in DMA mode */
 FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
 
 /* Wait DMA transfer finished by poll */
-FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
 
 /* Start command and data transfer in PIO mode */
 FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
 
 /* Wait PIO transfer finished by poll */
-FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax);
+FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
 
 /* Get cmd response and received data after wait poll status or interrupt signal */
 FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
@@ -216,9 +222,15 @@ FError FSdioRestart(FSdio *const instance_p);
 /* Register event call-back function as handler for interrupt events */
 void FSdioRegisterEvtHandler(FSdio *const instance_p, FSdioEvtType evt, FSdioEvtHandler handler, void *handler_arg);
 
+/* Register sleep call-back function */
+void FSdioRegisterRelaxHandler(FSdio *const instance_p, FSdioRelaxHandler relax_handler);
+
 /* Dump all register value of SDIO instance */
 void FSdioDumpRegister(uintptr base_addr);
 
+/* Dump command and data info */
+void FSdioDumpCmdInfo(FSdioCmdData *const cmd_data);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c
index 0bcd30d9604..8c163b40f0a 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_cmd.c
  * Date: 2022-06-01 14:23:59
  * LastEditTime: 2022-06-01 14:24:00
- * Description:  This files is for SDIO command related function
+ * Description:  This file is for SDIO command related function
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -29,6 +29,7 @@
 #include "ftypes.h"
 
 #include "fcache.h"
+#include "fswap.h"
 
 #include "fsdio_hw.h"
 #include "fsdio.h"
@@ -36,6 +37,7 @@
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
+#define FSDIO_EXT_APP_CMD       55U
 
 /***************** Macros (Inline Functions) Definitions *********************/
 #define FSDIO_DEBUG_TAG "FSDIO-CMD"
@@ -57,14 +59,21 @@ FError FSdioSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg)
     {
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_STATUS_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
     while (FSDIO_STATUS_DATA_BUSY & reg_val);
 
     if (retries <= 0)
+    {
         return FSDIO_ERR_BUSY;
+    }
 
     FSDIO_WRITE_REG(base_addr, FSDIO_CMD_ARG_OFFSET, arg);
+
+    FSDIO_DATA_BARRIER(); /* drain writebuffer */
+
     FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, FSDIO_CMD_START | cmd);
 
     retries = FSDIO_TIMEOUT;
@@ -72,9 +81,11 @@ FError FSdioSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg)
     {
         reg_val = FSDIO_READ_REG(base_addr, FSDIO_CMD_OFFSET);
         if (--retries <= 0)
+        {
             break;
+        }
     }
-    while (FSDIO_CMD_START & reg_val);
+    while (FSDIO_CMD_START & reg_val);   /* wait until command send done */
 
     return (retries <= 0) ? FSDIO_ERR_TIMEOUT : FSDIO_SUCCESS;
 }
@@ -136,7 +147,9 @@ FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 
     raw_cmd |= FSDIO_CMD_INDX_SET(cmd_data_p->cmdidx);
 
-    FSDIO_DEBUG("============[CMD-%d]@0x%x begin ============", cmd_data_p->cmdidx, base_addr);
+    FSDIO_DEBUG("============[%s-%d]@0x%x begin ============",
+                (FSDIO_EXT_APP_CMD == instance_p->prev_cmd) ? "ACMD" : "CMD", cmd_data_p->cmdidx,
+                base_addr);
     FSDIO_DEBUG("    cmd: 0x%x", raw_cmd);
     FSDIO_DEBUG("    arg: 0x%x", cmd_data_p->cmdarg);
 
@@ -144,11 +157,31 @@ FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
     FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR,
                           FSDIO_INTS_CMD_MASK, TRUE);
 
-    FSdioSendPrivateCmd(base_addr, raw_cmd, cmd_data_p->cmdarg);
+    ret = FSdioSendPrivateCmd(base_addr, raw_cmd, cmd_data_p->cmdarg);
     FSDIO_INFO("cmd send done ...");
     return ret;
 }
 
+static void FSdioFlipByteOrder(u32 *response, fsize_t size)
+{
+    /*
+        swap response and convert byte order
+        resp[0] = bswap32(resp[3])
+        resp[1] = bswap32(resp[2])
+        resp[2] = bswap32(resp[1])
+        resp[3] = bswap32(resp[0])
+    */
+    FASSERT(size % (2 * sizeof(u32)) == 0);
+    const fsize_t n_words = size / sizeof(uint32_t);
+    for (int i = 0; i < (int)n_words / 2; ++i)
+    {
+        u32 left = __builtin_bswap32(response[i]);
+        u32 right = __builtin_bswap32(response[n_words - i - 1]);
+        response[i] = right;
+        response[n_words - i - 1] = left;
+    }
+}
+
 /**
  * @name: FSdioGetCmdResponse
  * @msg: Get cmd response and received data after wait poll status or interrupt signal
@@ -167,7 +200,7 @@ FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return FSDIO_ERR_NOT_INIT;
     }
 
@@ -188,6 +221,15 @@ FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data
             cmd_data_p->response[1] = FSDIO_READ_REG(base_addr, FSDIO_RESP1_OFFSET);
             cmd_data_p->response[2] = FSDIO_READ_REG(base_addr, FSDIO_RESP2_OFFSET);
             cmd_data_p->response[3] = FSDIO_READ_REG(base_addr, FSDIO_RESP3_OFFSET);
+
+            /* according to SD spec. 136 bits R2 is send-back in reverse order and big-end,
+               some SD protocol will do this reverse and ntol itself, other do not,
+               filp_resp_byte_order is to compilant with those not */
+            if (instance_p->config.filp_resp_byte_order)
+            {
+                FSdioFlipByteOrder(cmd_data_p->response, sizeof(u32) * 4);
+            }
+
             FSDIO_DEBUG("    resp: 0x%x-0x%x-0x%x-0x%x",
                         cmd_data_p->response[0], cmd_data_p->response[1],
                         cmd_data_p->response[2], cmd_data_p->response[3]);
@@ -195,16 +237,23 @@ FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data
         else
         {
             cmd_data_p->response[0] = FSDIO_READ_REG(base_addr, FSDIO_RESP0_OFFSET);
+            cmd_data_p->response[1] = 0U;
+            cmd_data_p->response[2] = 0U;
+            cmd_data_p->response[3] = 0U;
             FSDIO_DEBUG("    resp: 0x%x", cmd_data_p->response[0]);
         }
     }
 
     cmd_data_p->success = TRUE; /* cmd / data transfer finished successful */
-    FSDIO_DEBUG("============[CMD-%d]@0x%x end  ============", cmd_data_p->cmdidx, base_addr);
+    FSDIO_DEBUG("============[%s-%d]@0x%x end  ============",
+                (FSDIO_EXT_APP_CMD == instance_p->prev_cmd) ? "ACMD" : "CMD",
+                cmd_data_p->cmdidx, base_addr);
 
     /* disable related interrupt */
     FSdioSetInterruptMask(instance_p, FSDIO_GENERAL_INTR, FSDIO_INTS_CMD_MASK | FSDIO_INTS_DATA_MASK, FALSE);
     FSdioSetInterruptMask(instance_p, FSDIO_IDMA_INTR, FSDIO_DMAC_INTS_MASK, FALSE);
 
+    instance_p->prev_cmd = cmd_data_p->cmdidx; /* record previous command */
+
     return ret;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c
index 9fc1507d39f..549f48652ab 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_dma.c
  * Date: 2022-06-01 14:21:41
  * LastEditTime: 2022-06-01 14:21:42
- * Description:  This files is for DMA related function implementation
+ * Description:  This file is for DMA related function implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -29,7 +29,6 @@
 #include "fassert.h"
 #include "ftypes.h"
 
-#include "fcache.h"
 
 #include "fsdio_hw.h"
 #include "fsdio.h"
@@ -47,6 +46,7 @@
 
 /************************** Function Prototypes ******************************/
 extern FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
+extern FError FSdioPollWaitBusyCard(FSdio *const instance_p);
 
 /*****************************************************************************/
 /**
@@ -101,7 +101,7 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
 
     if (buf_num > instance_p->desc_list.desc_num)
     {
-        FSDIO_ERROR("descriptor is short for transfer %d < %d",
+        FSDIO_ERROR("Descriptor is too short to transfer %d < %d.",
                     instance_p->desc_list.desc_num, buf_num);
         return FSDIO_ERR_SHORT_BUF;
     }
@@ -109,7 +109,7 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
     memset((void *)instance_p->desc_list.first_desc, 0,
            sizeof(FSdioIDmaDesc) * instance_p->desc_list.desc_num);
 
-    FSDIO_INFO("%d of descriptor in use", buf_num);
+    FSDIO_INFO("%d of descriptor is in using.", buf_num);
     for (loop = 0U; loop < buf_num; loop++)
     {
         cur_desc = &(instance_p->desc_list.first_desc[loop]);
@@ -127,6 +127,12 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
 
         /* set data buffer for transfer */
         buff_addr = (uintptr)data_p->buf + (uintptr)(loop * data_p->blksz);
+        if (buff_addr % data_p->blksz) /* make sure buffer aligned and not cross page boundary */
+        {
+            FSDIO_ERROR("Data buffer 0x%x do not align.", buff_addr);
+            return FSDIO_ERR_DMA_BUF_UNALIGN;
+        }
+
 #ifdef __aarch64__
         cur_desc->addr_hi = UPPER_32_BITS(buff_addr);
         cur_desc->addr_lo = LOWER_32_BITS(buff_addr);
@@ -137,6 +143,12 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
 
         /* set address of next descriptor entry, NULL for last entry */
         desc_addr = is_last ? 0U : (uintptr)&instance_p->desc_list.first_desc[loop + 1];
+        if (desc_addr % sizeof(FSdioIDmaDesc)) /* make sure dma descriptor aligned and not cross page boundary */
+        {
+            FSDIO_ERROR("dma descriptor 0x%x do not align.", desc_addr);
+            return FSDIO_ERR_DMA_BUF_UNALIGN;
+        }
+
 #ifdef __aarch64__
         cur_desc->desc_hi = UPPER_32_BITS(desc_addr);
         cur_desc->desc_lo = LOWER_32_BITS(desc_addr);
@@ -147,8 +159,7 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p
     }
 
     /* flush cache of descripor list and transfer buffer */
-    FCacheDCacheFlushRange((uintptr)instance_p->desc_list.first_desc, sizeof(FSdioIDmaDesc) * instance_p->desc_list.desc_num);
-    FCacheDCacheFlushRange((uintptr)data_p->buf, data_p->datalen);
+    FSDIO_DATA_BARRIER();
 
     FSdioDumpDMADescriptor(instance_p, buf_num);
     return FSDIO_SUCCESS;
@@ -174,9 +185,13 @@ static FError FSdioDMATransferData(FSdio *const instance_p, FSdioData *data_p)
     /* fill transfer buffer to DMA descriptor */
     ret = FSdioSetupDMADescriptor(instance_p, data_p);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
+
+    FSDIO_DATA_BARRIER();
 
-    FSDIO_INFO("descriptor@%p, trans bytes: %d, block size: %d",
+    FSDIO_INFO("Descriptor@%p, trans bytes: %d, block size: %d",
                instance_p->desc_list.first_desc,
                data_p->datalen,
                data_p->blksz);
@@ -207,29 +222,40 @@ FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return FSDIO_ERR_NOT_INIT;
     }
 
     if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
     {
-        FSDIO_ERROR("device is not configure in DMA transfer mode");
+        FSDIO_ERROR("Device is not configure in DMA transfer mode.");
         return FSDIO_ERR_INVALID_STATE;
     }
 
     /* for removable media, check if card exists */
     if ((FALSE == instance_p->config.non_removable) &&
-            (FALSE == FSdioCheckIfCardExists(base_addr)))
+        (FALSE == FSdioCheckIfCardExists(base_addr)))
     {
-        FSDIO_ERROR("card not detected !!!");
+        FSDIO_ERROR("Card is not detected !!!");
         return FSDIO_ERR_NO_CARD;
     }
 
+    /* wait previous command finished and card not busy */
+    ret = FSdioPollWaitBusyCard(instance_p);
+    if (FSDIO_SUCCESS != ret)
+    {
+        return ret;
+    }
+
+    FSDIO_WRITE_REG(base_addr, FSDIO_RAW_INTS_OFFSET, 0xffffe);
+
     /* reset fifo and DMA before transfer */
-    FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
+
     ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* enable use of DMA */
     FSDIO_SET_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_USE_INTERNAL_DMAC);
@@ -257,7 +283,7 @@ FError FSdioDMATransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
  * @param {FSdioCmdData} *cmd_data_p, contents of transfer command and data
  * @param {FSdioRelaxHandler} relax, handler of relax when wait busy
  */
-FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax)
+FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 {
     FASSERT(instance_p);
     FASSERT(cmd_data_p);
@@ -266,65 +292,56 @@ FError FSdioPollWaitDMAEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
     int delay;
     const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA;
     uintptr base_addr = instance_p->config.base_addr;
+    const u32 wait_bits = (NULL == cmd_data_p->data_p) ? FSDIO_INT_CMD_BIT : (FSDIO_INT_CMD_BIT | FSDIO_INT_DTO_BIT);
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return FSDIO_ERR_NOT_INIT;
     }
 
     if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
     {
-        FSDIO_ERROR("device is not configure in DMA transfer mode");
+        FSDIO_ERROR("Device is not configure in DMA transfer mode.");
         return FSDIO_ERR_INVALID_STATE;
     }
 
-    /* wait command done or timeout */
+    /* wait command done or data timeout */
     delay = FSDIO_TIMEOUT;
     do
     {
         reg_val = FSdioGetRawStatus(base_addr);
-        if (relax)
-            relax();
+
+        if (delay % 1000 == 0)
+        {
+            FSDIO_DEBUG("reg_val = 0x%x", reg_val);
+        }
+
+        if (instance_p->relax_handler)
+        {
+            instance_p->relax_handler();
+        }
     }
-    while (!(FSDIO_INT_CMD_BIT & reg_val) && (--delay > 0));
+    while (((wait_bits & reg_val) != wait_bits) && (--delay > 0));
+
+    /* clear status to ack data done */
+    FSdioClearRawStatus(base_addr);
 
-    if (!(FSDIO_INT_CMD_BIT & reg_val) && (delay <= 0))
+    if (((wait_bits & reg_val) != wait_bits) && (delay <= 0))
     {
-        FSDIO_ERROR("wait cmd done timeout, raw ints: 0x%x", reg_val);
+        FSDIO_ERROR("Wait cmd done timeout, raw ints: 0x%x.", reg_val);
         return FSDIO_ERR_CMD_TIMEOUT;
     }
 
     if (NULL != cmd_data_p->data_p) /* wait data transfer done or timeout */
     {
-        delay = FSDIO_TIMEOUT;
-        do
-        {
-            reg_val = FSDIO_READ_REG(base_addr, FSDIO_RAW_INTS_OFFSET);
-            if (relax)
-                relax();
-        }
-        while (!(FSDIO_INT_DTO_BIT & reg_val) && (--delay > 0));
-
-        /* clear status to ack data done */
-        FSdioClearRawStatus(base_addr);
-
-        if (!(FSDIO_INT_DTO_BIT & reg_val) && (delay <= 0))
-        {
-            FSDIO_ERROR("wait DMA transfer timeout, raw ints: 0x%x", reg_val);
-            return FSDIO_ERR_TRANS_TIMEOUT;
-        }
-
         /* invalidate cache of transfer buffer */
         if (read)
         {
-            FCacheDCacheInvalidateRange((uintptr)cmd_data_p->data_p, cmd_data_p->data_p->datalen);
+            FSDIO_DATA_BARRIER();
         }
     }
 
-    /* clear status to ack cmd done */
-    FSdioClearRawStatus(base_addr);
-
     if (FSDIO_SUCCESS == ret)
     {
         ret = FSdioGetCmdResponse(instance_p, cmd_data_p);
@@ -349,13 +366,13 @@ FError FSdioSetIDMAList(FSdio *const instance_p, volatile FSdioIDmaDesc *desc, u
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return FSDIO_ERR_NOT_INIT;
     }
 
     if (FSDIO_IDMA_TRANS_MODE != instance_p->config.trans_mode)
     {
-        FSDIO_ERROR("device is not configure in DMA transfer mode");
+        FSDIO_ERROR("Device is not configure in DMA transfer mode.");
         return FSDIO_ERR_INVALID_STATE;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_g.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_g.c
index 78b00cc0e1e..c7bdf08f2b9 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_g.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:37:44
- * Description:  This files is for static init
+ * Description:  This file is for static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -40,26 +40,28 @@
 
 /************************** Variable Definitions *****************************/
 
-const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_HOST_INSTANCE_NUM] =
+const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_NUM] =
 {
-    [FSDIO_HOST_INSTANCE_0] =
+    [FSDIO0_ID] =
     {
-        .instance_id  = FSDIO_HOST_INSTANCE_0,
-        .base_addr    = FSDIO_HOST_0_BASE_ADDR,
-        .irq_num      = FSDIO_HOST_0_IRQ_NUM,
+        .instance_id  = FSDIO0_ID,
+        .base_addr    = FSDIO0_BASE_ADDR,
+        .irq_num      = FSDIO0_IRQ_NUM,
         .trans_mode   = FSDIO_IDMA_TRANS_MODE,
         .voltage      = FSDIO_SD_3_3V_VOLTAGE,
-        .non_removable  = FALSE
+        .non_removable  = FALSE,
+        .filp_resp_byte_order = FALSE
     },
 
-    [FSDIO_HOST_INSTANCE_1] =
+    [FSDIO1_ID] =
     {
-        .instance_id = FSDIO_HOST_INSTANCE_1,
-        .base_addr   = FSDIO_HOST_1_BASE_ADDR,
-        .irq_num     = FSDIO_HOST_1_IRQ_NUM,
+        .instance_id = FSDIO1_ID,
+        .base_addr   = FSDIO1_BASE_ADDR,
+        .irq_num     = FSDIO1_IRQ_NUM,
         .trans_mode  = FSDIO_IDMA_TRANS_MODE,
         .voltage     = FSDIO_SD_3_3V_VOLTAGE,
-        .non_removable  = FALSE
+        .non_removable  = FALSE,
+        .filp_resp_byte_order = FALSE
     }
 };
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h
index a0a1a0b1b62..33a7edf1937 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h
@@ -14,7 +14,7 @@
  * FilePath: fsdio_hw.h
  * Date: 2022-05-26 15:32:34
  * LastEditTime: 2022-05-26 15:32:35
- * Description:  This files is for SDIO register function definition
+ * Description:  This file is for SDIO register function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -23,20 +23,28 @@
  * 1.1   zhugengyu  2022/5/26    modify according to tech manual.
  */
 
-#ifndef DRIVERS_FSDIO_HW_H
-#define DRIVERS_FSDIO_HW_H
+#ifndef FSDIO_HW_H
+#define FSDIO_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 /***************************** Include Files *********************************/
+
 #include "fparameters.h"
 #include "fio.h"
 #include "ftypes.h"
 #include "fassert.h"
 #include "fkernel.h"
 
+#ifdef __aarch64__
+#include "faarch64.h"
+#else
+#include "fcp15.h"
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 
 /** @name Register Map
@@ -118,8 +126,10 @@ extern "C"
 #define FSDIO_CLK_DRV_SET(x)     SET_REG32_BITS((x), 15, 8)
 #define FSDIO_CLK_DIVIDER_SET(x) SET_REG32_BITS((x), 7, 0) /* 分频系数 =  2 * bit[7:0] */
 #define FSDIO_CLK_DIV(samp, drv, div) FSDIO_CLK_SAMPLE_SET(samp) | \
-                                      FSDIO_CLK_DRV_SET(drv) | \
-                                      FSDIO_CLK_DIVIDER_SET(div)
+    FSDIO_CLK_DRV_SET(drv) | \
+    FSDIO_CLK_DIVIDER_SET(div)
+
+#define FSDIO_CLK_DIVDER_GET(div_reg)  GET_REG32_BITS((div_reg), 7, 0)
 
 /** @name FSDIO_CLKENA_OFFSET Register
  */
@@ -164,10 +174,10 @@ extern "C"
 
 #define FSDIO_INT_ALL_BITS GENMASK(16, 0)
 #define FSDIO_INTS_CMD_MASK (FSDIO_INT_RE_BIT | FSDIO_INT_CMD_BIT | FSDIO_INT_RCRC_BIT | \
-                            FSDIO_INT_RTO_BIT | FSDIO_INT_HTO_BIT | FSDIO_INT_HLE_BIT)
+                             FSDIO_INT_RTO_BIT | FSDIO_INT_HTO_BIT | FSDIO_INT_HLE_BIT)
 
 #define FSDIO_INTS_DATA_MASK (FSDIO_INT_DTO_BIT | FSDIO_INT_DCRC_BIT | FSDIO_INT_DRTO_BIT | \
-                             FSDIO_INT_SBE_BCI_BIT)
+                              FSDIO_INT_SBE_BCI_BIT)
 
 /** @name FSDIO_CMD_OFFSET Register
  */
@@ -362,6 +372,7 @@ enum
 #define FSDIO_CLR_BIT(addr, reg_off, bits)      FtClearBit32((addr) + (u32)(reg_off), bits)
 #define FSDIO_SET_BIT(addr, reg_off, bits)      FtSetBit32((addr) + (u32)(reg_off), bits)
 
+#define FSDIO_DATA_BARRIER()                    WMB()
 /************************** Function Prototypes ******************************/
 FError FSdioSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg);
 FError FSdioResetCtrl(uintptr base_addr, u32 reset_bits);
@@ -378,9 +389,13 @@ static inline void FSdioSetClock(uintptr base_addr, boolean enable)
 {
     u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_CLKENA_OFFSET);
     if (enable)
+    {
         reg_val |= FSDIO_CLKENA_CCLK_ENABLE;
+    }
     else
+    {
         reg_val &= ~FSDIO_CLKENA_CCLK_ENABLE;
+    }
     FSDIO_WRITE_REG(base_addr, FSDIO_CLKENA_OFFSET, reg_val);
 }
 
@@ -388,9 +403,13 @@ static inline void FSdioSetPower(uintptr base_addr, boolean enable)
 {
     u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_PWREN_OFFSET);
     if (enable)
+    {
         reg_val |= FSDIO_PWREN_ENABLE;
+    }
     else
+    {
         reg_val &= ~FSDIO_PWREN_ENABLE;
+    }
     FSDIO_WRITE_REG(base_addr, FSDIO_PWREN_OFFSET, reg_val);
 }
 
@@ -398,9 +417,13 @@ static inline void FSdioSetExtClock(uintptr base_addr, boolean enable)
 {
     u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET);
     if (enable)
+    {
         reg_val |= FSDIO_UHS_EXT_CLK_ENA;
+    }
     else
+    {
         reg_val &= ~FSDIO_UHS_EXT_CLK_ENA;
+    }
     FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_EXT_OFFSET, reg_val);
 }
 
@@ -408,9 +431,13 @@ static inline void FSdioSetVoltage1_8V(uintptr base_addr, boolean v1_8)
 {
     u32 reg_val = FSDIO_READ_REG(base_addr, FSDIO_UHS_REG_OFFSET);
     if (v1_8)
+    {
         reg_val |= FSDIO_UHS_REG_VOLT_180;
+    }
     else
-        reg_val &= ~FSDIO_UHS_REG_VOLT_180; /* 3.3v */
+    {
+        reg_val &= ~FSDIO_UHS_REG_VOLT_180;    /* 3.3v */
+    }
     FSDIO_WRITE_REG(base_addr, FSDIO_UHS_REG_OFFSET, reg_val);
 }
 
@@ -526,18 +553,18 @@ static inline void FSdioSetBusWidth(uintptr base_addr, u32 width)
 
     switch (width)
     {
-    case 1:
-        reg_val = FSDIO_CARD0_WIDTH2_1BIT;
-        break;
-    case 4:
-        reg_val = FSDIO_CARD0_WIDTH2_4BIT;
-        break;
-    case 8:
-        reg_val = FSDIO_CARD0_WIDTH1_8BIT;
-        break;
-    default:
-        FASSERT_MSG(0, "invalid bus width %d", width);
-        break;
+        case 1:
+            reg_val = FSDIO_CARD0_WIDTH2_1BIT;
+            break;
+        case 4:
+            reg_val = FSDIO_CARD0_WIDTH2_4BIT;
+            break;
+        case 8:
+            reg_val = FSDIO_CARD0_WIDTH1_8BIT;
+            break;
+        default:
+            FASSERT_MSG(0, "invalid bus width %d", width);
+            break;
     }
 
     FSDIO_WRITE_REG(base_addr, FSDIO_CTYPE_OFFSET, reg_val);
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c
index 333795b2db6..4cd69976343 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_intr.c
  * Date: 2022-06-01 15:08:58
  * LastEditTime: 2022-06-01 15:08:58
- * Description:  This files is for SDIO interrupt related function implementation
+ * Description:  This file is for SDIO interrupt related function implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -42,18 +42,18 @@
 #define FSDIO_INFO(format, ...)    FT_DEBUG_PRINT_I(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FSDIO_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSDIO_DEBUG_TAG, format, ##__VA_ARGS__)
 
-#define FSDIO_CALL_EVT_HANDLER(instance_p, evt)                   \
+#define FSDIO_CALL_EVT_HANDLER(instance_p, evt, status, dmac_status)                   \
     if (instance_p->evt_handlers[evt])                            \
     {                                                             \
-        instance_p->evt_handlers[evt](instance_p, instance_p->evt_args[evt]); \
+        instance_p->evt_handlers[evt](instance_p, instance_p->evt_args[evt], status, dmac_status); \
     }
 
 static const u32 cmd_err_ints_mask = FSDIO_INT_RTO_BIT | FSDIO_INT_RCRC_BIT | FSDIO_INT_RE_BIT |
                                      FSDIO_INT_DCRC_BIT | FSDIO_INT_DRTO_BIT |
-                                     FSDIO_INT_SBE_BCI_BIT | FSDIO_INT_HLE_BIT;
+                                     FSDIO_INT_SBE_BCI_BIT;
 
 static const u32 dmac_err_ints_mask = FSDIO_DMAC_INT_ENA_FBE | FSDIO_DMAC_INT_ENA_DU |
-                                      FSDIO_DMAC_INT_ENA_AIS;
+                                      FSDIO_DMAC_INT_ENA_NIS | FSDIO_DMAC_INT_ENA_AIS;
 /************************** Function Prototypes ******************************/
 
 /*****************************************************************************/
@@ -73,7 +73,7 @@ u32 FSdioGetInterruptMask(FSdio *const instance_p, FSdioIntrType type)
 
     if (0 == instance_p->config.base_addr)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return mask;
     }
 
@@ -106,7 +106,7 @@ void FSdioSetInterruptMask(FSdio *const instance_p, FSdioIntrType type, u32 set_
 
     if (0 == instance_p->config.base_addr)
     {
-        FSDIO_ERROR("device is not yet initialized!!!");
+        FSDIO_ERROR("Device is not yet initialized!!!");
         return;
     }
 
@@ -153,9 +153,9 @@ void FSdioInterruptHandler(s32 vector, void *param)
     dmac_evt_mask = FSDIO_READ_REG(base_addr, FSDIO_DMAC_INT_EN_OFFSET);
 
     if (!(events & FSDIO_INT_ALL_BITS) &&
-            !(dmac_events & FSDIO_DMAC_STATUS_ALL_BITS))
+        !(dmac_events & FSDIO_DMAC_STATUS_ALL_BITS))
     {
-        FSDIO_DEBUG("irq exit with no action");
+        FSDIO_DEBUG("irq exit with no action.");
         return; /* no interrupt status */
     }
 
@@ -163,11 +163,12 @@ void FSdioInterruptHandler(s32 vector, void *param)
 
     FSDIO_DEBUG("events:0x%x,mask:0x%x,dmac_events:%x,dmac_mask:0x%x", events, event_mask, dmac_events, dmac_evt_mask);
 
+    /* clear interrupt status */
     FSDIO_WRITE_REG(base_addr, FSDIO_RAW_INTS_OFFSET, events);
     FSDIO_WRITE_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET, dmac_events);
 
     if (((events & event_mask) == 0) &&
-            ((dmac_events & dmac_evt_mask == 0)))
+        ((dmac_events & dmac_evt_mask == 0)))
     {
         return; /* no need to handle interrupt */
     }
@@ -176,32 +177,32 @@ void FSdioInterruptHandler(s32 vector, void *param)
     if (((events & event_mask) & FSDIO_INT_CD_BIT) && (FALSE == instance_p->config.non_removable))
     {
         FSDIO_DEBUG("sd status changed here ! status:[%d]", FSDIO_READ_REG(base_addr, FSDIO_CARD_DETECT_OFFSET));
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CARD_DETECTED);
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CARD_DETECTED, events, dmac_events);
+    }
+
+    /* handle error state */
+    if ((dmac_events & dmac_err_ints_mask) || (events & cmd_err_ints_mask))
+    {
+        FSDIO_ERROR("ERR:events:0x%x,mask:0x%x,dmac_evts:0x%x,dmac_mask:0x%x",
+                    events, event_mask, dmac_events, dmac_evt_mask);
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_ERR_OCCURE, events, dmac_events);
     }
 
     if ((events & FSDIO_INT_DTO_BIT) && (events & FSDIO_INT_CMD_BIT)) /* handle cmd && data done */
     {
-        FSDIO_DEBUG("cmd and data over");
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE);
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE);
+        FSDIO_DEBUG("Cmd and data over !!!");
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE, events, dmac_events);
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE, events, dmac_events);
     }
     else if (events & FSDIO_INT_CMD_BIT) /* handle cmd done */
     {
-        FSDIO_DEBUG("cmd over");
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE);
+        FSDIO_DEBUG("Cmd over !!!");
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_CMD_DONE, events, dmac_events);
     }
     else if (events & FSDIO_INT_DTO_BIT) /* handle data done */
     {
-        FSDIO_DEBUG("data over");
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE);
-    }
-
-    /* handle error state */
-    if ((dmac_events & dmac_err_ints_mask) || (events & cmd_err_ints_mask))
-    {
-        FSDIO_ERROR("ERR:events:0x%x,mask:0x%x,dmac_evts:0x%x,dmac_mask:0x%x",
-                    events, event_mask, dmac_events, dmac_evt_mask);
-        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_ERR_OCCURE);
+        FSDIO_DEBUG("Data over !!!");
+        FSDIO_CALL_EVT_HANDLER(instance_p, FSDIO_EVT_DATA_DONE, events, dmac_events);
     }
 
     return;
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c
index dfe4f1b5a90..488f10be0c2 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_pio.c
  * Date: 2022-06-01 14:21:47
  * LastEditTime: 2022-06-01 14:21:47
- * Description:  This files is for PIO transfer related function implementation
+ * Description:  This file is for PIO transfer related function implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -28,8 +28,6 @@
 #include "fassert.h"
 #include "ftypes.h"
 
-#include "fcache.h"
-
 #include "fsdio_hw.h"
 #include "fsdio.h"
 
@@ -46,6 +44,7 @@
 
 /************************** Function Prototypes ******************************/
 extern FError FSdioTransferCmd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p);
+extern FError FSdioPollWaitBusyCard(FSdio *const instance_p);
 
 /*****************************************************************************/
 /**
@@ -64,13 +63,6 @@ static FError FSdioPIOWriteData(FSdio *const instance_p, FSdioData *data_p)
     const u32 wr_times = data_p->datalen / sizeof(u32); /* u8 --> u32 */
     u32 *wr_buf = (u32 *)data_p->buf;
 
-    /* while in PIO mode, max data transferred is 0x800 */
-    if (data_p->datalen > FSDIO_MAX_FIFO_CNT)
-    {
-        FSDIO_ERROR("Fifo do not support write more than 0x%x", FSDIO_MAX_FIFO_CNT);
-        return FSDIO_ERR_NOT_SUPPORT;
-    }
-
     /* write fifo data */
     FSDIO_WRITE_REG(base_addr, FSDIO_CMD_OFFSET, FSDIO_CMD_DAT_WRITE);
     for (loop = 0; loop < wr_times; loop++)
@@ -100,7 +92,7 @@ FError FSdioPIOReadData(FSdio *const instance_p, FSdioData *data_p)
     /* while in PIO mode, max data transferred is 0x800 */
     if (data_p->datalen > FSDIO_MAX_FIFO_CNT)
     {
-        FSDIO_ERROR("Fifo do not support write more than 0x%x", FSDIO_MAX_FIFO_CNT);
+        FSDIO_ERROR("Fifo do not support writing more than 0x%x.", FSDIO_MAX_FIFO_CNT);
         return FSDIO_ERR_NOT_SUPPORT;
     }
 
@@ -138,27 +130,43 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 
     if (FSDIO_PIO_TRANS_MODE != instance_p->config.trans_mode)
     {
-        FSDIO_ERROR("device is not configure in PIO transfer mode");
+        FSDIO_ERROR("device is not configure in PIO transfer mode.");
         return FSDIO_ERR_INVALID_STATE;
     }
 
     /* for removable media, check if card exists */
     if ((FALSE == instance_p->config.non_removable) &&
-            (FALSE == FSdioCheckIfCardExists(base_addr)))
+        (FALSE == FSdioCheckIfCardExists(base_addr)))
     {
-        FSDIO_ERROR("card not detected !!!");
+        FSDIO_ERROR("card is not detected !!!");
         return FSDIO_ERR_NO_CARD;
     }
 
+    /* wait previous command finished and card not busy */
+    ret = FSdioPollWaitBusyCard(instance_p);
+    if (FSDIO_SUCCESS != ret)
+    {
+        return ret;
+    }
+
     /* reset fifo and not use DMA */
     FSDIO_CLR_BIT(base_addr, FSDIO_CNTRL_OFFSET, FSDIO_CNTRL_USE_INTERNAL_DMAC);
     ret = FSdioResetCtrl(base_addr, FSDIO_CNTRL_FIFO_RESET);
     if (FSDIO_SUCCESS != ret)
+    {
         return ret;
+    }
     FSDIO_CLR_BIT(base_addr, FSDIO_BUS_MODE_OFFSET, FSDIO_BUS_MODE_DE);
 
     if (NULL != cmd_data_p->data_p)
     {
+        /* while in PIO mode, max data transferred is 0x800 */
+        if (cmd_data_p->data_p->datalen > FSDIO_MAX_FIFO_CNT)
+        {
+            FSDIO_ERROR("Fifo do not support writing more than 0x%x.", FSDIO_MAX_FIFO_CNT);
+            return FSDIO_ERR_NOT_SUPPORT;
+        }
+
         /* set transfer data length and block size */
         FSdioSetTransBytes(base_addr, cmd_data_p->data_p->datalen);
         FSdioSetBlockSize(base_addr, cmd_data_p->data_p->blksz);
@@ -166,8 +174,8 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
         if (FALSE == read) /* if need to write, write to fifo before send command */
         {
             /* invalide buffer for data to write */
-            FCacheDCacheInvalidateRange((uintptr)cmd_data_p->data_p->buf,
-                                        cmd_data_p->data_p->datalen);
+
+            FSDIO_DATA_BARRIER();
 
             ret = FSdioPIOWriteData(instance_p, cmd_data_p->data_p);
         }
@@ -189,7 +197,7 @@ FError FSdioPIOTransfer(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
  * @param {FSdioCmdData} *cmd_data_p, contents of transfer command and data
  * @param {FSdioRelaxHandler} relax, handler of relax when wait busy
  */
-FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p, FSdioRelaxHandler relax)
+FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data_p)
 {
     FASSERT(instance_p);
     FASSERT(cmd_data_p);
@@ -208,7 +216,7 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
 
     if (FSDIO_PIO_TRANS_MODE != instance_p->config.trans_mode)
     {
-        FSDIO_ERROR("device is not configure in PIO transfer mode");
+        FSDIO_ERROR("device is not configure in PIO transfer mode.");
         return FSDIO_ERR_INVALID_STATE;
     }
 
@@ -217,8 +225,10 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
     do
     {
         reg_val = FSdioGetRawStatus(base_addr);
-        if (relax)
-            relax();
+        if (instance_p->relax_handler)
+        {
+            instance_p->relax_handler();
+        }
     }
     while (!(FSDIO_INT_CMD_BIT & reg_val) && (--delay > 0));
 
@@ -236,8 +246,10 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
         do
         {
             reg_val = FSdioGetRawStatus(base_addr);
-            if (relax)
-                relax();
+            if (instance_p->relax_handler)
+            {
+                instance_p->relax_handler();
+            }
         }
         while (!(FSDIO_INT_DTO_BIT & reg_val) && (--delay > 0));
 
@@ -249,7 +261,7 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data
 
         if (!(FSDIO_INT_DTO_BIT & reg_val) && (delay <= 0))
         {
-            FSDIO_ERROR("wait PIO transfer timeout, raw ints: 0x%x", reg_val);
+            FSDIO_ERROR("wait PIO transfer timeout, raw ints: 0x%x.", reg_val);
             return FSDIO_ERR_TRANS_TIMEOUT;
         }
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_selftest.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_selftest.c
index 34e8b8520ab..cf962e2cd1a 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_selftest.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_selftest.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_selftest.c
  * Date: 2022-06-02 11:49:44
  * LastEditTime: 2022-06-02 11:49:45
- * Description:  This files is for SDIO self-test function
+ * Description:  This file is for SDIO self-test function
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -100,4 +100,33 @@ void FSdioDumpRegister(uintptr base_addr)
     FSDIO_DUMPER(base_addr, FSDIO_UHS_REG_EXT_OFFSET, "uhsregext");
     FSDIO_DUMPER(base_addr, FSDIO_EMMC_DDR_REG_OFFSET, "emmcddr");
     FSDIO_DUMPER(base_addr, FSDIO_ENABLE_SHIFT_OFFSET, "enableshift");
+}
+
+/**
+ * @name: FSdioDumpCmdInfo
+ * @msg: Dump command and data info
+ * @return {NONE}
+ * @param {FSdioCmdData *const} cmd_data, info data of SD command and data
+ */
+void FSdioDumpCmdInfo(FSdioCmdData *const cmd_data)
+{
+    FSDIO_DEBUG("cmd struct @%p", cmd_data);
+    FSDIO_DEBUG("   opcode: %d", cmd_data->cmdidx);
+    FSDIO_DEBUG("   arg: 0x%x", cmd_data->cmdarg);
+    FSDIO_DEBUG("   resp@%p: 0x%x 0x%x 0x%x 0x%x",
+                cmd_data->response,
+                cmd_data->response[0],
+                cmd_data->response[1],
+                cmd_data->response[2],
+                cmd_data->response[3]);
+    FSDIO_DEBUG("   flag: 0x%x", cmd_data->flag);
+    FSDIO_DEBUG("   data @%p", cmd_data->data_p);
+
+    if (cmd_data->data_p)
+    {
+        FSDIO_DEBUG("   buf: %p, len: %d", cmd_data->data_p->buf,
+                    cmd_data->data_p->datalen);
+        FSDIO_DEBUG("   blk sz: %d", cmd_data->data_p->blksz);
+        FSDIO_DEBUG("   blk cnt: %d", cmd_data->data_p->blkcnt);
+    }
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_sinit.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_sinit.c
index 3111024e725..87241841567 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_sinit.c
@@ -14,7 +14,7 @@
  * FilePath: fsdio_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:48:41
- * Description:  This files is for static init
+ * Description:  This file is for static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -37,7 +37,7 @@
 
 /************************** Variable Definitions *****************************/
 
-extern const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_HOST_INSTANCE_NUM];
+extern const FSdioConfig FSDIO_CONFIG_TBL[FSDIO_NUM];
 
 /************************** Function Prototypes ******************************/
 /**
@@ -51,7 +51,7 @@ const FSdioConfig *FSdioLookupConfig(u32 instance_id)
     const FSdioConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FSDIO_HOST_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FSDIO_NUM; index++)
     {
         if (FSDIO_CONFIG_TBL[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.c
index cb15f014642..0fea8b152b1 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.c
@@ -14,7 +14,8 @@
  * FilePath: fsdmmc.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:55:23
- * Description:  This files is for
+ * Description:  This file is for functions in this file are the minimum required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -31,7 +32,7 @@
 #include "ftypes.h"
 #include "fdebug.h"
 
-#include "fcache.h"
+
 #include "fsleep.h"
 
 #include "fsdmmc_hw.h"
@@ -83,7 +84,7 @@ FError FSdmmcCfgInitialize(FSdmmc *instance_p, const FSdmmcConfig *input_config_
     */
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FSDMMC_WARN("device is already initialized!!!");
+        FSDMMC_WARN("Device is already initialized!!!");
     }
 
     /*
@@ -101,7 +102,7 @@ FError FSdmmcCfgInitialize(FSdmmc *instance_p, const FSdmmcConfig *input_config_
     */
     if (!FSdmmcCheckIfCardExists(base_addr))
     {
-        FSDMMC_ERROR("storage device not found !!! 0x%x", base_addr);
+        FSDMMC_ERROR("Storage device not found !!! 0x%x", base_addr);
         return FSDMMC_ERR_CARD_NO_FOUND;
     }
 
@@ -110,7 +111,9 @@ FError FSdmmcCfgInitialize(FSdmmc *instance_p, const FSdmmcConfig *input_config_
     */
     ret = FSdmmcReset(base_addr);
     if (FSDMMC_SUCCESS == ret)
+    {
         instance_p->is_ready = FT_COMPONENT_IS_READY;
+    }
 
     return ret;
 }
@@ -149,14 +152,22 @@ u32 FSdmmcMakeRawCmd(FSdmmcCmd *cmd_p)
     raw_cmd |= FSDMMC_CMD_SETTING_CMDI(cmd_p->cmdidx);
 
     if (cmd_p->flag & FSDMMC_CMD_FLAG_ADTC)
-        raw_cmd |= FSDMMC_CMD_SETTING_TRTY(0b10); /* adtc指令 */
+    {
+        raw_cmd |= FSDMMC_CMD_SETTING_TRTY(0b10);    /* adtc指令 */
+    }
 
     if (0 == (cmd_p->flag & FSDMMC_CMD_FLAG_EXP_RESP))
+    {
         raw_cmd |= FSDMMC_CMD_NO_RESP;
+    }
     else if (cmd_p->flag & FSDMMC_CMD_FLAG_EXP_LONG_RESP)
+    {
         raw_cmd |= FSDMMC_CMD_RESP_136_BIT;
+    }
     else
+    {
         raw_cmd |= FSDMMC_CMD_RESP_48_BIT;
+    }
 
     return raw_cmd;
 }
@@ -175,7 +186,9 @@ static FError FSdmmcWaitCmdEnd(uintptr base_addr, FSdmmcCmd *cmd_p)
 
     ret = FSdmmcWaitStatus(base_addr, FSDMMC_TIMEOUT);
     if (FSDMMC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     if (cmd_p->flag & FSDMMC_CMD_FLAG_EXP_RESP)
     {
@@ -269,22 +282,24 @@ FError FSdmmcSendData(uintptr base_addr, boolean read, FSdmmcCmd *cmd_p)
 
     if ((dat_p->datalen >= FSDMMC_DMA_ADDR_ALIGN) && (dat_p->datalen % FSDMMC_DMA_ADDR_ALIGN != 0))
     {
-        FSDMMC_ERROR("invalid size: total = %d ", dat_p->datalen);
+        FSDMMC_ERROR("Invalid size: total = %d.", dat_p->datalen);
         return FSDMMC_ERR_INVALID_BUF;
     }
 
     if (((uintptr)(dat_p->buf) % FSDMMC_DMA_ADDR_ALIGN) != 0)
     {
-        FSDMMC_ERROR("buffer %p can not be used for DMA", dat_p->buf);
+        FSDMMC_ERROR("Buffer %p can not be used for DMA.", dat_p->buf);
         return FSDMMC_ERR_INVALID_BUF;
     }
 
     card_addr = cmd_p->cmdarg;
     blk_cnt = dat_p->datalen / dat_p->blksz;
     if (dat_p->datalen % dat_p->blksz)
+    {
         blk_cnt++;
+    }
 
-    FSDMMC_INFO("data len: %d, card addr: 0x%x, blk cnt: %d, is %s",
+    FSDMMC_INFO("Data len: %d, card addr: 0x%x, blk cnt: %d, is %s",
                 dat_p->datalen, card_addr, blk_cnt, read ? "read" : "write");
 
     if (read)
@@ -299,7 +314,7 @@ FError FSdmmcSendData(uintptr base_addr, boolean read, FSdmmcCmd *cmd_p)
     else
     {
         /* invalidate write buf */
-        FCacheDCacheInvalidateRange((uintptr)dat_p->buf, dat_p->datalen);
+        FSDMMC_DATA_BARRIER();
 
         /* write data */
         FSdmmcSetWriteDMA(base_addr, (uintptr)card_addr, blk_cnt, dat_p->buf);
@@ -324,17 +339,23 @@ static FError FSdmmcTransferDataPoll(uintptr base_addr, FSdmmcCmd *cmd_p)
 
     ret = FSdmmcSendData(base_addr, read, cmd_p);
     if (FSDMMC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     ret = FSdmmcWaitCmdEnd(base_addr, cmd_p);
     if (FSDMMC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     ret = FSdmmcWaitDMAStatus(base_addr, read, FSDMMC_TIMEOUT);
     if (FSDMMC_SUCCESS != ret)
+    {
         return ret;
+    }
 
-    FCacheDCacheInvalidateRange((uintptr)dat_p->buf, dat_p->datalen);
+    FSDMMC_DATA_BARRIER();
     return ret;
 }
 
@@ -354,7 +375,7 @@ FError FSdmmcPollTransfer(FSdmmc *instance_p, FSdmmcCmd *cmd_data_p)
 
     if (FALSE == FSdmmcCheckIfCardExists(base_addr))
     {
-        FSDMMC_ERROR("card not found !!! fsdio ctrl base 0x%x", base_addr);
+        FSDMMC_ERROR("Card not found !!! fsdio ctrl base 0x%x.", base_addr);
         return FSDMMC_ERR_CARD_NO_FOUND;
     }
 
@@ -365,7 +386,7 @@ FError FSdmmcPollTransfer(FSdmmc *instance_p, FSdmmcCmd *cmd_data_p)
         ret = FSdmmcTransferDataPoll(base_addr, cmd_data_p);
         if (FSDMMC_SUCCESS != ret)
         {
-            FSDMMC_ERROR("trans data failed 0x%x", ret);
+            FSDMMC_ERROR("Transfer data failed 0x%x.", ret);
             return ret;
         }
 
@@ -378,7 +399,7 @@ FError FSdmmcPollTransfer(FSdmmc *instance_p, FSdmmcCmd *cmd_data_p)
         ret = FSdmmcTransferCmdPoll(base_addr, cmd_data_p);
         if (FSDMMC_SUCCESS != ret)
         {
-            FSDMMC_ERROR("send cmd failed 0x%x", ret);
+            FSDMMC_ERROR("Send cmd failed 0x%x.", ret);
             return ret;
         }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.h
index 25573e68afe..7805a17679d 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.h
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc.h
@@ -14,7 +14,8 @@
  * FilePath: fsdmmc.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:55:57
- * Description:  This files is for
+ * Description:  This file is for functions in this file are the minimum required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -22,20 +23,19 @@
  * 1.0   zhugengyu  2021/12/2    init
  */
 
-#ifndef  DRIVERS_MMC_FSDMMC_H
-#define  DRIVERS_MMC_FSDMMC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
+#ifndef  FSDMMC_H
+#define  FSDMMC_H
 /***************************** Include Files *********************************/
 
 #include "ftypes.h"
 #include "ferror_code.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 #define FSDMMC_SUCCESS           FT_SUCCESS
 #define FSDMMC_ERR_NOT_READY     FT_MAKE_ERRCODE(ErrModBsp, ErrBspMmc, 1)
@@ -112,7 +112,7 @@ typedef struct
     u32     irq_num[FSDMMC_INTR_NUM];
 } FSdmmcConfig;
 
-typedef void (*FSdmmcEventHandler)(void *instance_p);
+typedef void (*FSdmmcEventHandler)(void *args);
 
 /**
  * This typedef contains driver instance data. The user is required to allocate a
@@ -124,6 +124,7 @@ typedef struct
     FSdmmcConfig config;      /* Current active configs */
     u32          is_ready;    /* Device is initialized and ready */
     FSdmmcEventHandler evt_handler[FSDMMC_EVT_NUM];
+    void         *evt_args[FSDMMC_EVT_NUM];
 } FSdmmc; /* Device instance */
 
 /************************** Variable Definitions *****************************/
@@ -163,7 +164,7 @@ void FSdmmcErrInterrupHandler(s32 vector, void *param);
 void FSdmmcDmaInterrupHandler(s32 vector, void *param);
 
 /* 注册中断事件响应函数 */
-void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler);
+void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler, void *args);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.c
index d2c4da00c48..08ba04333e2 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.c
@@ -14,7 +14,7 @@
  * FilePath: fsdmmc_dma.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:49:31
- * Description:  This files is for
+ * Description:  This file is dma descriptor management API.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -68,7 +68,7 @@ void FSdmmcSetReadDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, void *b
     FSDMMC_INFO("sd card: 0x%x:0x%x ==> mem space: 0x%x:0x%x",
                 srch, srcl, dsth, dstl);
 
-    FSDMMC_INFO("read %d blks from 0x%x", blk_cnt, card_addr);
+    FSDMMC_INFO("Read %d blks from 0x%x", blk_cnt, card_addr);
 
     /* DMA 复位 */
     FSDMMC_SET_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
@@ -82,7 +82,9 @@ void FSdmmcSetReadDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, void *b
     FSdmmcClearBDInterruptStatus(base_addr);
     FSdmmcClearNormalInterruptStatus(base_addr);
 
-    FSDMMC_INFO("base addr: 0x%x buf_p: %p", base_addr, buf_p);
+    FSDMMC_INFO("Base addr: 0x%x buf_p: %p", base_addr, buf_p);
+
+    FSDMMC_DATA_BARRIER();
 
     /* DMA 读卡地址配置：4 个 cycle
     系统低 4B-系统高 4B-SD 低 4B- SD 高 4B */
@@ -116,7 +118,7 @@ void FSdmmcSetWriteDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, const
     FSDMMC_INFO("mem space: 0x%x:0x%x ==> sd card: 0x%x:0x%x",
                 srch, srcl, dsth, dstl);
 
-    FSDMMC_INFO("write %d blks from 0x%x", blk_cnt, card_addr);
+    FSDMMC_INFO("Write %d blks from 0x%x", blk_cnt, card_addr);
 
     /* DMA 复位 */
     FSDMMC_SET_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_BDRST);
@@ -130,6 +132,8 @@ void FSdmmcSetWriteDMA(uintptr base_addr, uintptr card_addr, u32 blk_cnt, const
     FSdmmcClearBDInterruptStatus(base_addr);
     FSdmmcClearNormalInterruptStatus(base_addr);
 
+    FSDMMC_DATA_BARRIER();
+
     /* DMA 写卡地址配置：4 个 cycle
     系统低 4B-系统高 4B-SD 低 4B- SD 高 4B */
     FSDMMC_WRITE_REG(base_addr, FSDMMC_DAT_IN_M_TX_BD_REG_OFFSET, srcl);
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.h
index 06cff5d8f43..51fb27175ce 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.h
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_dma.h
@@ -14,7 +14,7 @@
  * FilePath: fsdmmc_dma.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:51:25
- * Description:  This files is for
+ * Description:  This file is dma descriptormanagement API.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -22,15 +22,15 @@
  * 1.0   zhugengyu  2021/12/2    init
  */
 
-#ifndef  DRIVERS_MMC_FSDMMC_DMA_H
-#define  DRIVERS_MMC_FSDMMC_DMA_H
+#ifndef  FSDMMC_DMA_H
+#define  FSDMMC_DMA_H
+/***************************** Include Files *********************************/
+#include "ftypes.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
-/***************************** Include Files *********************************/
-#include "ftypes.h"
 
 /************************** Constant Definitions *****************************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_g.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_g.c
index bef9e3f28d5..5824c107675 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_g.c
@@ -14,7 +14,8 @@
  * FilePath: fsdmmc_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:53:31
- * Description:  This files is for
+ * Description:  This file contains a configuration table that specifies the configuration of
+ * the fsdmmc devices in the system.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -43,17 +44,17 @@
 
 /************************** Variable Definitions *****************************/
 
-const FSdmmcConfig FSDMMC_CONFIG_TBL[FSDMMC_HOST_INSTANCE_NUM] =
+const FSdmmcConfig FSDMMC_CONFIG_TBL[FSDMMC_NUM] =
 {
-    [FSDMMC_HOST_INSTANCE_0] =
+    [FSDMMC0_ID] =
     {
-        .instance_id = FSDMMC_HOST_INSTANCE_0, /* Id of device*/
-        .base_addr   = FSDMMC_HOST_0_BASEADDR,
+        .instance_id = FSDMMC0_ID, /* Id of device*/
+        .base_addr   = FSDMMC0_BASE_ADDR,
         .irq_num =
         {
-            [FSDMMC_CMD_INTR] = FSDMMC_HOST_0_CMD_INTR_IRQ,
-            [FSDMMC_DMA_BD_INTR] = FSDMMC_HOST_0_DMA_INTR_IRQ,
-            [FSDMMC_ERROR_INTR] = FSDMMC_HOST_0_ERR_INTR_IRQ
+            [FSDMMC_CMD_INTR] = FSDMMC0_CMD_IRQ_NUM,
+            [FSDMMC_DMA_BD_INTR] = FSDMMC0_DMA_IRQ_NUM,
+            [FSDMMC_ERROR_INTR] = FSDMMC0_ERR_IRQ_NUM
         }
     }
 };
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.c
index 155f388561d..ce66d249782 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.c
@@ -14,7 +14,7 @@
  * FilePath: fsdmmc_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:54:02
- * Description:  This files is for
+ * Description:  This file contains macros that can be used to access the device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -25,7 +25,6 @@
 /***************************** Include Files *********************************/
 #include "fassert.h"
 #include "fdebug.h"
-
 #include "fsdmmc_hw.h"
 #include "fsdmmc.h"
 
@@ -63,11 +62,11 @@ FError FSdmmcSoftwareReset(uintptr base_addr, int retries)
         reg_val = FSDMMC_READ_REG(base_addr, FSDMMC_STATUS_REG_OFFSET);
     }
     while (!(reg_val & FSDMMC_STATUS_IDIE) &&
-            (retries-- > 0));
+           (retries-- > 0));
 
     if (!(reg_val & FSDMMC_STATUS_IDIE) && (retries <= 0))
     {
-        FSDMMC_ERROR("software reset timeout!!! status: 0x%x", reg_val);
+        FSDMMC_ERROR("Software reset timeout!!! status: 0x%x", reg_val);
         return FSDMMC_ERR_TIMEOUT;
     }
 
@@ -96,20 +95,20 @@ static const char *FSdmmcGetRespTypeStr(u32 hw_cmd)
 
     switch (FSDMMC_CMD_RESP_MASK & hw_cmd)
     {
-    case FSDMMC_CMD_NO_RESP:
-        str = "NONE";
-        break;
-    case FSDMMC_CMD_RESP_136_BIT:
-        str = "LONG";
-        break;
-    case FSDMMC_CMD_RESP_48_BIT:
-        str = "SHORT";
-        break;
-    case FSDMMC_CMD_RESP_48_BIT_BUSY_CHECK:
-        str = "SHORT CHECK BUSY";
-        break;
-    default:
-        FASSERT(0);
+        case FSDMMC_CMD_NO_RESP:
+            str = "NONE";
+            break;
+        case FSDMMC_CMD_RESP_136_BIT:
+            str = "LONG";
+            break;
+        case FSDMMC_CMD_RESP_48_BIT:
+            str = "SHORT";
+            break;
+        case FSDMMC_CMD_RESP_48_BIT_BUSY_CHECK:
+            str = "SHORT CHECK BUSY";
+            break;
+        default:
+            FASSERT(0);
     }
 
     return str;
@@ -133,6 +132,8 @@ void FSdmmcSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg)
     /* 设置命令 */
     FSDMMC_WRITE_REG(base_addr, FSDMMC_CMD_SETTING_REG_OFFSET, cmd);
 
+    FSDMMC_DATA_BARRIER();
+
     /* 设置参数，同时触发发送命令 */
     FSDMMC_WRITE_REG(base_addr, FSDMMC_ARGUMENT_REG_OFFSET, FSDMMC_ARGUMENT_MASK & arg);
 
@@ -154,7 +155,9 @@ FError FSdmmcReset(uintptr base_addr)
 
     ret = FSdmmcSoftwareReset(base_addr, FSDMMC_TIMEOUT);
     if (FSDMMC_SUCCESS != ret)
+    {
         return ret;
+    }
 
     /* set card detection */
     FSDMMC_WRITE_REG(base_addr, FSDMMC_SD_SEN_REG_OFFSET, 0x0);
@@ -207,13 +210,13 @@ FError FSdmmcWaitStatus(uintptr base_addr, int retries)
 
     if (FSDMMC_NORMAL_INT_STATUS_EI & status)
     {
-        FSDMMC_ERROR("error status: 0x%x,  remain retries: %d", status, retries);
+        FSDMMC_ERROR("Error status: 0x%x,  remain retries: %d", status, retries);
         FSdmmcReset(base_addr);
         return FSDMMC_ERR_CMD_FAILED;
     }
     else if (0 >= retries)
     {
-        FSDMMC_ERROR("wait timeout!!! status 0x%x", status);
+        FSDMMC_ERROR("Wait timeout!!! status 0x%x", status);
         return FSDMMC_ERR_TIMEOUT;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h
index 623f2af31de..82220a99fcf 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h
@@ -14,7 +14,7 @@
  * FilePath: fsdmmc_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:54:24
- * Description:  This files is for
+ * Description:  This file contains macros that can be used to access the device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -22,19 +22,26 @@
  * 1.0   zhugengyu  2021/12/2    init
  */
 
-#ifndef  DRIVERS_MMC_FSDMMC_HW_H
-#define  DRIVERS_MMC_FSDMMC_HW_H
+#ifndef  FSDMMC_HW_H
+#define  FSDMMC_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 /***************************** Include Files *********************************/
 
 #include "fparameters.h"
 #include "fio.h"
 #include "fkernel.h"
 
+#ifdef __aarch64__
+#include "faarch64.h"
+#else
+#include "fcp15.h"
+#endif
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 
 /** @name Register Map
@@ -288,6 +295,7 @@ extern "C"
 /**************************** Type Definitions *******************************/
 
 /************************** Variable Definitions *****************************/
+#define FSDMMC_DATA_BARRIER()                    WMB()
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_intr.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_intr.c
index 5fa29e8737e..9df432336b9 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_intr.c
@@ -14,7 +14,8 @@
  * FilePath: fsdmmc_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:54:53
- * Description:  This files is for
+ * Description:  This file contains the functions that are related to interrupt processing
+ * for the fsdmmc device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -40,11 +41,11 @@
 /**************************** Type Definitions *******************************/
 
 /***************** Macros (Inline Functions) Definitions *********************/
-static void FSdmmcCallEvtHandler(FSdmmcEventHandler handler, FSdmmc *instance_p)
+static void FSdmmcCallEvtHandler(FSdmmcEventHandler handler, void *arg)
 {
     if (NULL != handler)
     {
-        handler((void *)instance_p);
+        handler(arg);
     }
 }
 
@@ -70,18 +71,18 @@ u32 FSdmmcGetInterruptMask(uintptr base_addr, u32 intr_type)
 
     switch (intr_type)
     {
-    case FSDMMC_CMD_INTR:
-        mask = FSDMMC_READ_REG(base_addr, FSDMMC_NORMAL_INT_EN_REG_OFFSET);
-        break;
-    case FSDMMC_ERROR_INTR:
-        mask = FSDMMC_READ_REG(base_addr, FSDMMC_ERROR_INT_EN_REG_OFFSET);
-        break;
-    case FSDMMC_DMA_BD_INTR:
-        mask = FSDMMC_READ_REG(base_addr, FSDMMC_BD_ISR_EN_REG_OFFSET);
-        break;
-    default:
-        FASSERT(0);
-        break;
+        case FSDMMC_CMD_INTR:
+            mask = FSDMMC_READ_REG(base_addr, FSDMMC_NORMAL_INT_EN_REG_OFFSET);
+            break;
+        case FSDMMC_ERROR_INTR:
+            mask = FSDMMC_READ_REG(base_addr, FSDMMC_ERROR_INT_EN_REG_OFFSET);
+            break;
+        case FSDMMC_DMA_BD_INTR:
+            mask = FSDMMC_READ_REG(base_addr, FSDMMC_BD_ISR_EN_REG_OFFSET);
+            break;
+        default:
+            FASSERT(0);
+            break;
     }
 
     return mask;
@@ -102,24 +103,28 @@ void FSdmmcSetInterruptMask(uintptr base_addr, u32 intr_type, u32 mask, boolean
     u32 new_mask = 0;
 
     if (TRUE == enable)
+    {
         new_mask = old_mask | mask;
+    }
     else
+    {
         new_mask = old_mask & (~mask);
+    }
 
     switch (intr_type)
     {
-    case FSDMMC_CMD_INTR:
-        FSDMMC_WRITE_REG(base_addr, FSDMMC_NORMAL_INT_EN_REG_OFFSET, new_mask);
-        break;
-    case FSDMMC_ERROR_INTR:
-        FSDMMC_WRITE_REG(base_addr, FSDMMC_ERROR_INT_EN_REG_OFFSET, new_mask);
-        break;
-    case FSDMMC_DMA_BD_INTR:
-        FSDMMC_WRITE_REG(base_addr, FSDMMC_BD_ISR_EN_REG_OFFSET, new_mask);
-        break;
-    default:
-        FASSERT(0);
-        break;
+        case FSDMMC_CMD_INTR:
+            FSDMMC_WRITE_REG(base_addr, FSDMMC_NORMAL_INT_EN_REG_OFFSET, new_mask);
+            break;
+        case FSDMMC_ERROR_INTR:
+            FSDMMC_WRITE_REG(base_addr, FSDMMC_ERROR_INT_EN_REG_OFFSET, new_mask);
+            break;
+        case FSDMMC_DMA_BD_INTR:
+            FSDMMC_WRITE_REG(base_addr, FSDMMC_BD_ISR_EN_REG_OFFSET, new_mask);
+            break;
+        default:
+            FASSERT(0);
+            break;
     }
 
     return;
@@ -145,17 +150,20 @@ void FSdmmcCmdInterrupHandler(s32 vector, void *param)
 
     if (status & FSDMMC_NORMAL_INT_STATUS_CR) /* 卡移除中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CARD_REMOVED], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CARD_REMOVED],
+                             instance_p->evt_args[FSDMMC_EVT_CARD_REMOVED]);
     }
 
     if (status & FSDMMC_NORMAL_INT_STATUS_CC) /* 命令完成中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_DONE], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_DONE],
+                             instance_p->evt_args[FSDMMC_EVT_CMD_DONE]);
     }
 
     if (status & FSDMMC_NORMAL_INT_STATUS_EI) /* 命令错误中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_ERROR], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_ERROR],
+                             instance_p->evt_args[FSDMMC_EVT_CMD_ERROR]);
     }
 
     FSdmmcClearNormalInterruptStatus(base_addr);
@@ -181,12 +189,14 @@ void FSdmmcDmaInterrupHandler(s32 vector, void *param)
 
     if (status & FSDMMC_BD_ISR_REG_DAIS) /* DMA 错误中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_ERROR], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_ERROR],
+                             instance_p->evt_args[FSDMMC_EVT_DATA_ERROR]);
     }
 
     if (status & FSDMMC_BD_ISR_REG_RESPE) /* 读 SD 卡操作，AXI BR 通道完成中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_READ_DONE], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_READ_DONE],
+                             instance_p->evt_args[FSDMMC_EVT_DATA_READ_DONE]);
     }
 
     if (status & FSDMMC_BD_ISR_REG_DATFRAX) /* AXI 总线强制释放中断*/
@@ -216,7 +226,8 @@ void FSdmmcDmaInterrupHandler(s32 vector, void *param)
 
     if (status & FSDMMC_BD_ISR_REG_TRS) /* DMA 传输完成中断*/
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_WRITE_DONE], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_DATA_WRITE_DONE],
+                             instance_p->evt_args[FSDMMC_EVT_DATA_WRITE_DONE]);
     }
 
     FSdmmcClearBDInterruptStatus(base_addr);
@@ -241,7 +252,8 @@ void FSdmmcErrInterrupHandler(s32 vector, void *param)
 
     if (status & FSDMMC_ERROR_INT_STATUS_CNR) /* 命令响应错误中断 */
     {
-        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_RESP_ERROR], instance_p);
+        FSdmmcCallEvtHandler(instance_p->evt_handler[FSDMMC_EVT_CMD_RESP_ERROR],
+                             instance_p->evt_args[FSDMMC_EVT_CMD_RESP_ERROR]);
     }
 
     if (status & FSDMMC_ERROR_INT_STATUS_CIR) /* 命令索引错误中断 */
@@ -273,10 +285,11 @@ void FSdmmcErrInterrupHandler(s32 vector, void *param)
  * @note 此函数用于设置FSDMMC中断时注册，被注册的函数被FSdmmcCmdInterrupHandler、FSdmmcErrInterrupHandler
  * 和FSdmmcDmaInterrupHandler调用
  */
-void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler)
+void FSdmmcRegisterInterruptHandler(FSdmmc *instance_p, u32 event, FSdmmcEventHandler handler, void *args)
 {
     FASSERT(instance_p);
     instance_p->evt_handler[event] = handler;
+    instance_p->evt_args[event] = args;
 }
 
 /**
@@ -295,7 +308,7 @@ FError FSdmmcInterruptTransfer(FSdmmc *instance_p, FSdmmcCmd *cmd_data_p)
 
     if (FALSE == FSdmmcCheckIfCardExists(base_addr))
     {
-        FSDMMC_ERROR("card not found !!! fsdio ctrl base 0x%x", base_addr);
+        FSDMMC_ERROR("Card not found !!! fsdio ctrl base 0x%x", base_addr);
         return FSDMMC_ERR_CARD_NO_FOUND;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_sinit.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_sinit.c
index 96d040abe17..d554fa6cd21 100644
--- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_sinit.c
@@ -14,8 +14,9 @@
  * FilePath: fsdmmc_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:55:09
- * Description:  This files is for
- *
+ * Description:  This file contains the implementation of the fsdmmc driver's static
+ * initialization functionality.
+ * 
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
@@ -41,7 +42,7 @@
 
 /************************** Variable Definitions *****************************/
 
-extern const FSdmmcConfig FSDMMC_CONFIG_TBL[FSDMMC_HOST_INSTANCE_NUM];
+extern const FSdmmcConfig FSDMMC_CONFIG_TBL[FSDMMC_NUM];
 
 /************************** Function Prototypes ******************************/
 /**
@@ -56,7 +57,7 @@ const FSdmmcConfig *FSdmmcLookupConfig(u32 instance_id)
     const FSdmmcConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FSDMMC_HOST_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FSDMMC_NUM; index++)
     {
         if (FSDMMC_CONFIG_TBL[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/Kconfig b/bsp/phytium/libraries/standalone/drivers/nand/Kconfig
index 2740b716bf0..4638b049f9e 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/nand/Kconfig
@@ -1,33 +1,33 @@
 
 menu "NAND Configuration"
     menu "FNAND ip config"
-        choice
-        prompt "choice fnand driver"
+		choice
+		prompt "choice fnand driver"
         config ENABLE_FNAND
             bool
             prompt "Use FNAND"
-
-        if ENABLE_FNAND
-            config FNAND_COMMON_DEBUG_EN
-                bool
-                prompt "Use FNAND common mode debug"
-
-            config FNAND_DMA_DEBUG_EN
-                bool
-                prompt "Use FNAND DMA mode debug"
-
-            config FNAND_TOGGLE_DEBUG_EN
-                bool
-                prompt "Use FNAND toggle mode debug"
-
-            config FNAND_ONFI_DEBUG_EN
-                bool
-                prompt "Use FNAND onfi mode debug"
-
-        endif
-
-        endchoice
-    endmenu
+            
+		if ENABLE_FNAND
+			config FNAND_COMMON_DEBUG_EN
+				bool
+            	prompt "Use FNAND common mode debug"
+			
+			config FNAND_DMA_DEBUG_EN
+				bool
+            	prompt "Use FNAND DMA mode debug"
+			
+			config FNAND_TOGGLE_DEBUG_EN
+				bool
+            	prompt "Use FNAND toggle mode debug"
+
+			config FNAND_ONFI_DEBUG_EN
+				bool
+            	prompt "Use FNAND onfi mode debug"
+
+		endif
+
+		endchoice
+	endmenu 
 
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.c
index 5396ff26006..1cc2e5067e1 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.c
@@ -14,11 +14,13 @@
  * FilePath: fnand.c
  * Date: 2022-05-10 14:53:42
  * LastEditTime: 2022-05-10 08:56:27
- * Description:  This files is for
+ * Description:  This file is for  functions in this file are the minimum required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 #include "fnand.h"
 #include "fnand_hw.h"
@@ -130,7 +132,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,
         }
         else
         {
-            FNAND_DEBUG_E("The lack of wait_irq_fun_p");
+            FNAND_DEBUG_E("The member wait_irq_fun_p of instance_p is null");
             FNAND_WRITEREG(config_p->base_address, FNAND_INTRMASK_OFFSET, FNAND_INTRMASK_ALL_INT_MASK);
             return FNAND_ERR_IRQ_LACK_OF_CALLBACK;
         }
@@ -145,7 +147,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,
             {
                 if (timeout_cnt++ >= 0xffffff)
                 {
-                    FNAND_DEBUG_E("FNAND_CMD_TYPE is send timeout");
+                    FNAND_DEBUG_E("FNAND_CMD_TYPE is sending timeout");
                     return FNAND_OP_TIMEOUT;
                 }
             }
@@ -156,7 +158,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,
             {
                 if (timeout_cnt++ >= 0xffffff)
                 {
-                    FNAND_DEBUG_E("FNAND_CMD_TYPE is send timeout");
+                    FNAND_DEBUG_E("FNAND_CMD_TYPE is sending timeout");
                     return FNAND_OP_TIMEOUT;
                 }
             }
@@ -167,7 +169,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,
             {
                 if (timeout_cnt++ >= 0xffffff)
                 {
-                    FNAND_DEBUG_E("FNAND_CMD_TYPE is send timeout");
+                    FNAND_DEBUG_E("FNAND_CMD_TYPE is sending timeout");
                     return FNAND_OP_TIMEOUT;
                 }
             }
@@ -178,7 +180,7 @@ FError FNandSendCmd(FNand *instance_p, struct FNandDmaDescriptor *descriptor_p,
             {
                 if (timeout_cnt++ >= 0xffffff)
                 {
-                    FNAND_DEBUG_E("FNAND_CMD_TYPE is send timeout");
+                    FNAND_DEBUG_E("FNAND_CMD_TYPE is sending timeout");
                     return FNAND_OP_TIMEOUT;
                 }
             }
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.h
index 2ded2317a59..12c1012ad2c 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand.h
@@ -14,19 +14,16 @@
  * FilePath: fnand.h
  * Date: 2022-05-07 15:40:42
  * LastEditTime: 2022-05-07 15:40:42
- * Description:  This files is for
+ * Description:  This file is for  functions in this file are the minimum required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
-#ifndef DRIVERS_NAND_FNAND_H
-#define DRIVERS_NAND_FNAND_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FNAND_H
+#define FNAND_H
 
 
 #include "ftypes.h"
@@ -36,6 +33,13 @@ extern "C"
 #include "fparameters.h"
 #include "fkernel.h"
 
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
 #define FNAND_ERR_OPERATION FT_CODE_ERR(ErrModBsp, ErrNand, 0x1u)
 #define FNAND_ERR_INVAILD_PARAMETER FT_CODE_ERR(ErrModBsp, ErrNand, 0x2u)
 #define FNAND_IS_BUSY FT_CODE_ERR(ErrModBsp, ErrNand, 0x3u)
@@ -52,9 +56,9 @@ extern "C"
 
 #define FNAND_MAX_BLOCKS 32768    /* Max number of Blocks */
 #define FNAND_MAX_PAGE_SIZE 16384 /* Max page size of NAND \
-                    flash */
+flash */
 #define FNAND_MAX_SPARE_SIZE 1024  /* Max spare bytes of a NAND \
-                    flash page */
+flash page */
 
 
 /* dma */
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.c
index 50bfada9de5..655c24270fb 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_bbm.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:12
- * Description:  This files is for
+ * Description:  This file implements the bad block management (BBM) functionality.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -137,35 +138,33 @@ static void FNandConvertBbt(FNand *instance_p, u8 *buf, u32 chip_addr)
         * Loop through the every 4 blocks in the bitmap
         */
         for (block_index = 0; block_index < FNAND_BBT_ENTRY_NUM_BLOCKS;
-                block_index++)
+             block_index++)
         {
             block_shift = FNAND_BBTBLOCKSHIFT(block_index);
             block_type = (data >> block_shift) &
                          FNAND_BLOCK_TYPE_MASK;
-            // FNAND_BBM_DEBUG_E("block_offset %d,block_shift %d",block_offset,block_shift);
-            // FNAND_BBM_DEBUG_E("block_type is %d \r\n",block_type);
             switch (block_type)
             {
-            case FNAND_FLASH_BLOCK_FACTORY_BAD:
-                /* Factory bad block */
-                instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
-                    FNAND_BLOCK_FACTORY_BAD << block_shift;
-                break;
-            case FNAND_FLASH_BLOCK_RESERVED:
-                /* Reserved block */
-                instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
-                    FNAND_BLOCK_RESERVED << block_shift;
-                break;
-            case FNAND_FLASH_BLOCK_BAD:
-                /* Bad block due to wear */
-                instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
-                    FNAND_BLOCK_BAD << block_shift;
-                break;
-            default:
-                /* Good block */
-                /* The BBT entry already defaults to
-                        * zero */
-                break;
+                case FNAND_FLASH_BLOCK_FACTORY_BAD:
+                    /* Factory bad block */
+                    instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
+                        FNAND_BLOCK_FACTORY_BAD << block_shift;
+                    break;
+                case FNAND_FLASH_BLOCK_RESERVED:
+                    /* Reserved block */
+                    instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
+                        FNAND_BLOCK_RESERVED << block_shift;
+                    break;
+                case FNAND_FLASH_BLOCK_BAD:
+                    /* Bad block due to wear */
+                    instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
+                        FNAND_BLOCK_BAD << block_shift;
+                    break;
+                default:
+                    /* Good block */
+                    /* The BBT entry already defaults to
+                            * zero */
+                    break;
             }
         }
     }
@@ -292,12 +291,12 @@ static FError FNandWriteBbt(FNand *instance_p,
                          FNAND_BLOCK_TYPE_MASK;
             switch (block_type)
             {
-            case FNAND_BLOCK_BAD:
-            case FNAND_BLOCK_FACTORY_BAD:
-                continue;
-            default:
-                /* Good Block */
-                break;
+                case FNAND_BLOCK_BAD:
+                case FNAND_BLOCK_FACTORY_BAD:
+                    continue;
+                default:
+                    /* Good Block */
+                    break;
             }
             desc_p->page_offset = block *
                                   instance_p->nand_geometry[chip_addr].pages_per_block;
@@ -337,7 +336,7 @@ static FError FNandWriteBbt(FNand *instance_p,
          * Calculate the bit mask for 4 blocks at a time in loop
          */
         for (block_index = 0; block_index < FNAND_BBT_ENTRY_NUM_BLOCKS;
-                block_index++)
+             block_index++)
         {
             block_shift = FNAND_BBTBLOCKSHIFT(block_index);
             buf[block_offset] &= ~(mask[Data &
@@ -345,15 +344,13 @@ static FError FNandWriteBbt(FNand *instance_p,
                                    << block_shift);
             Data >>= FNAND_BBT_BLOCK_SHIFT;
         }
-        // FNAND_BBM_DEBUG_I("buf[%d] 0x%x",block_offset,buf[block_offset]);
+
     }
 
     /*
      * Write the Bad Block Table(BBT) to flash
      */
-    // printf("erase_p is %p \r\n",instance_p->erase_p);
     ret = FNandEraseBlock(instance_p, block, chip_addr);
-    //instance_p->erase_p(instance_p, block, chip_addr);
     if (ret != FT_SUCCESS)
     {
         return ret;
@@ -412,8 +409,8 @@ static void FNandCreateBbt(FNand *instance_p, u32 chip_addr)
      * Scan all the blocks for factory marked bad blocks
      */
     for (block_index = 0; block_index <
-            instance_p->nand_geometry[chip_addr].num_blocks;
-            block_index++)
+         instance_p->nand_geometry[chip_addr].num_blocks;
+         block_index++)
     {
         /*
          * Block offset in Bad Block Table(BBT) entry
@@ -445,11 +442,11 @@ static void FNandCreateBbt(FNand *instance_p, u32 chip_addr)
              * pattern
              */
             for (length = 0; length <
-                    instance_p->bbt_manager[chip_addr].bb_pattern.length;
-                    length++)
+                 instance_p->bbt_manager[chip_addr].bb_pattern.length;
+                 length++)
             {
                 if (buf[instance_p->bbt_manager[chip_addr].bb_pattern.offset + length] !=
-                        instance_p->bbt_manager[chip_addr].bb_pattern.pattern[length])
+                    instance_p->bbt_manager[chip_addr].bb_pattern.pattern[length])
                 {
                     /* Bad block found */
                     instance_p->bbt_manager[chip_addr].bbt[block_offset] |=
@@ -480,14 +477,14 @@ FError FNandSearchBbt(FNand *instance_p, FNandBbtDesc *desc, u32 chip_addr)
     ver_offset = desc->ver_offset;
     max_blocks = desc->max_blocks;
     sig_length = desc->sig_length;
-    FNAND_BBM_DEBUG_I("FNandSearchBbt is start 0x%x", start_block);
-    FNAND_BBM_DEBUG_I("pages_per_block is start %d", instance_p->nand_geometry[chip_addr].pages_per_block);
+    FNAND_BBM_DEBUG_I("FNandSearchBbt starts at 0x%x", start_block);
+    FNAND_BBM_DEBUG_I("Pages_per_block starts at %d", instance_p->nand_geometry[chip_addr].pages_per_block);
     for (block = 0; block < max_blocks; block++)
     {
         pageoff = (start_block - block) *
                   instance_p->nand_geometry[chip_addr].pages_per_block;
-        FNAND_BBM_DEBUG_I("block 0x%x", block);
-        FNAND_BBM_DEBUG_I("%s, pageoff is 0x%x", __func__, pageoff);
+        FNAND_BBM_DEBUG_I("Block 0x%x", block);
+        FNAND_BBM_DEBUG_I("%s, Pageoff is 0x%x", __func__, pageoff);
         ret = FNandReadPageOOb(instance_p, pageoff, buf, 0, sizeof(buf), chip_addr);
         if (ret != FT_SUCCESS)
         {
@@ -565,11 +562,11 @@ FError FNandReadBbt(FNand *instance_p, u32 chip_addr)
             /*
             * Valid BBT & Mirror BBT found
             */
-            FNAND_BBM_DEBUG_I("desc_p->version > mirror_desc_p->version read page is %d", desc_p->page_offset);
+            FNAND_BBM_DEBUG_I("The desc_p->version > mirror_desc_p->version is not null , the page_offset is %d", desc_p->page_offset);
             ret = FNandReadPage(instance_p, desc_p->page_offset, buf, 0, bbtlen, NULL, 0, 0, chip_addr);
             if (ret != FT_SUCCESS)
             {
-                FNAND_BBM_DEBUG_I("desc_p->version > mirror_desc_p->version read page is error 0x%x", ret);
+                FNAND_BBM_DEBUG_I("The desc_p->version > mirror_desc_p->version is not null , the FNandReadPage is error 0x%x", ret);
                 return ret;
             }
             /*
@@ -590,11 +587,11 @@ FError FNandReadBbt(FNand *instance_p, u32 chip_addr)
         }
         else if (desc_p->version < mirror_desc_p->version)
         {
-            FNAND_BBM_DEBUG_I("desc_p->version < mirror_desc_p->version read page is %d", mirror_desc_p->page_offset);
+            FNAND_BBM_DEBUG_I("desc_p->version < mirror_desc_p->version is not null, the page_offset is %d", mirror_desc_p->page_offset);
             ret = FNandReadPage(instance_p, mirror_desc_p->page_offset, buf, 0, bbtlen, NULL, 0, 0, chip_addr);
             if (ret != FT_SUCCESS)
             {
-                FNAND_BBM_DEBUG_I("desc_p->version < mirror_desc_p->version read page is error 0x%x", ret);
+                FNAND_BBM_DEBUG_I("desc_p->version < mirror_desc_p->version is not null, the FNandReadPage is error 0x%x", ret);
                 return ret;
             }
             /*
@@ -616,12 +613,12 @@ FError FNandReadBbt(FNand *instance_p, u32 chip_addr)
         else
         {
             /* Both are up-to-date */
-            FNAND_BBM_DEBUG_I("Both are up-to-date read page is %d", desc_p->page_offset);
+            FNAND_BBM_DEBUG_I("Both are up-to-date, the page_offset is %d", desc_p->page_offset);
 
             ret = FNandReadPage(instance_p, desc_p->page_offset, buf, 0, bbtlen, NULL, 0, 0, chip_addr);
             if (ret != FT_SUCCESS)
             {
-                FNAND_BBM_DEBUG_I("Both are up-to-date read page is error 0x%x", ret);
+                FNAND_BBM_DEBUG_I("Both are up-to-date, the FNandReadPage is error 0x%x", ret);
                 return ret;
             }
 
@@ -702,7 +699,7 @@ FError FNandReadBbt(FNand *instance_p, u32 chip_addr)
 static void FNandBbtDumpDebug(FNand *instance_p)
 {
     int i;
-    FNAND_BBM_DEBUG_W("/********************* master bbt descriptor **********************/");
+    FNAND_BBM_DEBUG_W("/********************* Master bbt descriptor **********************/");
 
     FNAND_BBM_DEBUG_I("page_offset 0x%x", instance_p->bbt_manager[0].bbt_desc.page_offset);  /* Page offset where BBT resides */
     FNAND_BBM_DEBUG_I("sig_offset 0x%x", instance_p->bbt_manager[0].bbt_desc.sig_offset);   /* Signature offset in Spare area */
@@ -711,12 +708,12 @@ static void FNandBbtDumpDebug(FNand *instance_p)
     FNAND_BBM_DEBUG_I("max_blocks 0x%x", instance_p->bbt_manager[0].bbt_desc.max_blocks);   /* Max blocks to search for BBT */
     for (i = 0; i < 4; i++)
     {
-        FNAND_BBM_DEBUG_I("signature[%d] %c", i, instance_p->bbt_manager[0].bbt_desc.signature[i]);
+        FNAND_BBM_DEBUG_I("Signature[%d] %c", i, instance_p->bbt_manager[0].bbt_desc.signature[i]);
     }
     FNAND_BBM_DEBUG_I("version 0x%x", instance_p->bbt_manager[0].bbt_desc.version);       /* BBT version */
     FNAND_BBM_DEBUG_I("valid 0x%x", instance_p->bbt_manager[0].bbt_desc.valid);        /* BBT descriptor is valid or not */
 
-    FNAND_BBM_DEBUG_W("/********************* mirror bbt descriptor **********************/");
+    FNAND_BBM_DEBUG_W("/********************* Mirror bbt descriptor **********************/");
     FNAND_BBM_DEBUG_I("page_offset 0x%x", instance_p->bbt_manager[0].bbt_mirror_desc.page_offset);  /* Page offset where BBT resides */
     FNAND_BBM_DEBUG_I("sig_offset 0x%x", instance_p->bbt_manager[0].bbt_mirror_desc.sig_offset);   /* Signature offset in Spare area */
     FNAND_BBM_DEBUG_I("ver_offset 0x%x", instance_p->bbt_manager[0].bbt_mirror_desc.ver_offset);   /* Offset of BBT version */
@@ -730,7 +727,7 @@ static void FNandBbtDumpDebug(FNand *instance_p)
     FNAND_BBM_DEBUG_I("valid 0x%x", instance_p->bbt_manager[0].bbt_mirror_desc.valid);        /* BBT descriptor is valid or not */
 
 
-    FNAND_BBM_DEBUG_W("/********************* bbt info **********************/");
+    FNAND_BBM_DEBUG_W("/********************* Bbt info **********************/");
     FtDumpHexWord((const u32 *)instance_p->bbt_manager[0].bbt, instance_p->nand_geometry[0].num_blocks >>
                   FNAND_BBT_BLOCK_SHIFT);
 }
@@ -791,7 +788,7 @@ FError FNandScanBbt(FNand *instance_p, u32 chip_addr)
     }
     else
     {
-        FNAND_BBM_DEBUG_I("old bbt is valid");
+        FNAND_BBM_DEBUG_I("Old bbt is valid");
         FNandBbtDumpDebug(instance_p) ;
     }
 
@@ -825,9 +822,13 @@ FError FNandIsBlockBad(FNand *instance_p, u32 block, u32 chip_addr)
     BlockType = (data >> block_shift) & FNAND_BLOCK_TYPE_MASK;
 
     if (BlockType != FNAND_BLOCK_GOOD)
+    {
         return FT_SUCCESS;
+    }
     else
+    {
         return FNAND_VALUE_FAILURE;
+    }
 }
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.h
index 41595531478..aa525c8d592 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_bbm.h
@@ -14,25 +14,27 @@
  * FilePath: fnand_bbm.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:17
- * Description:  This files is for
+ * Description:  This file implements the Bad Block Management (BBM) functionality.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
-#ifndef DRIVERS_NAND_FNAND_BBM_H
-#define DRIVERS_NAND_FNAND_BBM_H
+#ifndef FNAND_BBM_H
+#define FNAND_BBM_H
+
+#include "ftypes.h"
+#include "fnand.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "fnand.h"
-
 /************************** Constant Definitions *****************************/
 /*
  * Block definitions for RAM based Bad Block Table (BBT)
@@ -54,38 +56,38 @@ extern "C"
                              second page               \
                              for bad block             \
                              information               \
-                             */
+*/
 #define FNAND_BBT_DESC_PAGE_OFFSET 0       /* Page offset of Bad \
-                             Block Table Desc */
+Block Table Desc */
 #define FNAND_BBT_DESC_SIG_OFFSET 8        /* Bad Block Table \
-                             signature offset */
+signature offset */
 #define FNAND_BBT_DESC_VER_OFFSET 12       /* Bad block Table \
-                             version offset */
+version offset */
 #define FNAND_BBT_DESC_SIG_LEN 4           /* Bad block Table \
-                                 signature length */
+signature length */
 #define FNAND_BBT_DESC_MAX_BLOCKS 4        /* Bad block Table \
-                             max blocks */
+max blocks */
 
 #define FNAND_BBT_BLOCK_SHIFT 2              /* Block shift value \
-                                   for a block in BBT */
+for a block in BBT */
 #define FNAND_BBT_ENTRY_NUM_BLOCKS 4         /* Num of blocks in \
-                               one BBT entry */
+one BBT entry */
 #define FNAND_BB_PATTERN_OFFSET_SMALL_PAGE 5 /* Bad block pattern \
-                           offset in a page */
+offset in a page */
 #define FNAND_BB_PATTERN_LENGTH_SMALL_PAGE 1 /* Bad block pattern \
-                           length */
+length */
 #define FNAND_BB_PATTERN_OFFSET_LARGE_PAGE 0 /* Bad block pattern \
                            offset in a large                      \
-                           page */
+page */
 #define FNAND_BB_PATTERN_LENGTH_LARGE_PAGE 2 /* Bad block pattern \
-                           length */
+length */
 #define FNAND_BB_PATTERN 0xFF                /* Bad block pattern \
                                to search in a page                \
-                               */
+*/
 #define FNAND_BLOCK_TYPE_MASK 0x03           /* Block type mask */
 #define FNAND_BLOCK_SHIFT_MASK 0x06          /* Block shift mask \
                                for a Bad Block Table             \
-                               entry byte */
+entry byte */
 
 /**************************** Type Definitions *******************************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.c
index 00627cc2f9c..6cd6ad9e54f 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_common_cmd.c
  * Date: 2022-06-24 03:51:06
  * LastEditTime: 2022-06-24 03:51:07
- * Description:  This file is for
+ * Description:  This file is for nand generic command documentation
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #include "fnand_common_cmd.h"
@@ -79,9 +80,9 @@
  * loss).
  */
 #define __DIVIDE(dividend, divisor) ({                      \
-    (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
-                   DIV_ROUND_UP(dividend, divisor) :        \
-                   DIV_ROUND_UP_ULL(dividend, divisor));        \
+        (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
+                               DIV_ROUND_UP(dividend, divisor) :        \
+                               DIV_ROUND_UP_ULL(dividend, divisor));        \
     })
 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
@@ -184,7 +185,7 @@ static FError FNandFlashReadStatus(FNand *instance_p, u32 chip_addr)
         return ret;
     }
 
-    FNAND_COMMON_DEBUG_I("read status is 0x%x", instance_p->dma_data_buffer.data_buffer[0]);
+    FNAND_COMMON_DEBUG_I("Read status is 0x%x", instance_p->dma_data_buffer.data_buffer[0]);
 
     return (instance_p->dma_data_buffer.data_buffer[0] == 0xe0) ? FT_SUCCESS : FNAND_IS_BUSY;
 }
@@ -379,7 +380,6 @@ static FError FNandPageWriteHwEcc(FNand *instance_p, u32 page_addr, u8 *buf, u32
     {
         nand_state = FNAND_READREG(instance_p->config.base_address, FNAND_STATE_OFFSET);
     }
-    // printf("write after nand_state 0x%x \r\n",nand_state);
     while (FNandFlashReadStatus(instance_p, chip_addr) == FNAND_IS_BUSY)
         ; /* wait i/o idle */
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.h
index 2c2733d5bd3..0b0b95c2585 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_common_cmd.h
@@ -14,11 +14,12 @@
  * FilePath: fnand_common_cmd.h
  * @Date: 2022-07-05 19:01:01
  * @LastEditTime: 2022-07-05 19:01:02
- * @Description:  This file is for
+ * @Description:  This file is for nand generic command documentation
  *
  * @Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #ifndef DRIVERS_NAND_COMMON_CMD_H
@@ -27,6 +28,10 @@
 #include "ftypes.h"
 #include "fnand.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 /*
  * Mandatory commands
  */
@@ -36,31 +41,31 @@
 
 #define NAND_CMD_CHANGE_READ_COLUMN1 0x05 /* NAND Random data Read \
                       Column command (1st                         \
-                      cycle) */
+cycle) */
 #define NAND_CMD_CHANGE_READ_COLUMN2 0xE0 /* NAND Random data Read \
                       Column command (2nd                         \
-                      cycle) */
+cycle) */
 #define NAND_CMD_BLOCK_ERASE1 0x60        /* NAND Block Erase \
-                          (1st cycle) */
+(1st cycle) */
 #define NAND_CMD_BLOCK_ERASE2 0xD0        /* NAND Block Erase \
-                          (2nd cycle) */
+(2nd cycle) */
 
 #define NAND_CMD_PAGE_PROG1 0x80          /* NAND Page Program \
                           command (1st cycle)                      \
-                          */
+*/
 #define NAND_CMD_PAGE_PROG2 0x10          /* NAND Page Program \
                           command (2nd cycle)                      \
-                          */
+*/
 
 #define NAND_CMD_CHANGE_WRITE_COLUMN 0x85 /* NAND Change Write \
-                         Column command */
+Column command */
 #define NAND_CMD_READ_ID 0x90             /* NAND Read ID \
-                              command */
+command */
 #define NAND_CMD_READ_PARAM_PAGE 0xEC     /* NAND Read \
                           Parameter Page                   \
-                          command */
+command */
 #define NAND_CMD_RESET 0xFF               /* NAND Reset \
-                          command */
+command */
 
 #define NAND_END_CMD_NONE 0xfff /* No End command */
 
@@ -70,5 +75,9 @@ FError FNandFlashReset(FNand *instance_p, u32 chip_addr) ;
 FError FNandFlashReadId(FNand *instance_p, u8 address, u8 *id_buffer, u32 buffer_length, u32 chip_addr);
 void FNandFlashFuncRegister(FNand *instance_p);
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.c
index 0c76bce917e..2395ceefdcb 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_dma.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:22
- * Description:  This files is for
+ * Description:  This file is dma descriptor management API.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -46,12 +47,12 @@
 
 void FNandDmaDump(struct FNandDmaDescriptor *descriptor_p)
 {
-    FNAND_DMA_DEBUG_I("Phytium NFC cmd dump:\n");
-    FNAND_DMA_DEBUG_I("cmd0:%x, cmd1:%x, ctrl:%x, page_cnt:%d\n",
+    FNAND_DMA_DEBUG_I("Phytium NFC cmd dump: ");
+    FNAND_DMA_DEBUG_I("cmd0:%x, cmd1:%x, ctrl:%x, page_cnt:%d ",
                       descriptor_p->cmd0, descriptor_p->cmd1, descriptor_p->cmd_ctrl.ctrl, descriptor_p->page_cnt);
-    FNAND_DMA_DEBUG_I("mem_addr_first:%02x %02x %02x %02x %02x\n",
+    FNAND_DMA_DEBUG_I("mem_addr_first:%02x %02x %02x %02x %02x ",
                       descriptor_p->mem_addr_first[0], descriptor_p->mem_addr_first[1], descriptor_p->mem_addr_first[2], descriptor_p->mem_addr_first[3], descriptor_p->mem_addr_first[4]);
-    FNAND_DMA_DEBUG_I("addr:%02x %02x %02x %02x %02x\n",
+    FNAND_DMA_DEBUG_I("addr:%02x %02x %02x %02x %02x ",
                       descriptor_p->addr[0], descriptor_p->addr[1], descriptor_p->addr[2], descriptor_p->addr[3], descriptor_p->addr[4]);
 
     FNAND_DMA_DEBUG_I(" csel : 0x%x  ", descriptor_p->cmd_ctrl.nfc_ctrl.csel);
@@ -72,7 +73,7 @@ static void FNandAddrCorrect(struct FNandDmaDescriptor *descriptor_p,
     int i, j;
     if (addr_length == 0 || addr_p == NULL)
     {
-        FNAND_DMA_DEBUG_I("addr_p is null ,Calibration is not required ");
+        FNAND_DMA_DEBUG_I("The addr_p is null , Calibration is not required ");
         return;
     }
 
@@ -100,7 +101,6 @@ FError FNandDmaPack(FNandCmdFormat *cmd_format,
     u32 i;
     FASSERT(cmd_format != NULL);
     FASSERT(descriptor_p != NULL);
-    // printf(" descriptor_p is %p \r\n",descriptor_p);
     descriptor_p->cmd_ctrl.ctrl = 0;
 
     /* cmd */
@@ -119,7 +119,7 @@ FError FNandDmaPack(FNandCmdFormat *cmd_format,
     /* addr */
     FNandAddrCorrect(descriptor_p, pack_data_p->addr_p, pack_data_p->addr_length);
     descriptor_p->cmd_ctrl.nfc_ctrl.cmd_type = cmd_format->cmd_type; /* cmd type */
-    FNAND_DMA_DEBUG_I("cmd_type is %x \r\n", descriptor_p->cmd_ctrl.nfc_ctrl.cmd_type);
+    FNAND_DMA_DEBUG_I("cmd_type is %x", descriptor_p->cmd_ctrl.nfc_ctrl.cmd_type);
     if (pack_data_p->contiune_dma)
     {
         descriptor_p->cmd_ctrl.nfc_ctrl.nc = 1;
@@ -138,10 +138,14 @@ FError FNandDmaPack(FNandCmdFormat *cmd_format,
     }
 
     if (cmd_format->auto_rs)
+    {
         descriptor_p->cmd_ctrl.nfc_ctrl.auto_rs = 1;
+    }
 
     if (cmd_format->ecc_en)
+    {
         descriptor_p->cmd_ctrl.nfc_ctrl.ecc_en = 1;
+    }
 
     /* invalid descriptor and buffer */
     FCacheDCacheInvalidateRange((intptr)descriptor_p, sizeof(struct FNandDmaDescriptor));
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.h
index 4e792eaa4d9..65a75826cb5 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_dma.h
@@ -14,23 +14,25 @@
  * FilePath: fnand_dma.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:27
- * Description:  This files is for
+ * Description:  This file is dma descriptor management API. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
-#ifndef DRIVERS_NAND_FNAND_DMA_H
-#define DRIVERS_NAND_FNAND_DMA_H
+#ifndef FNAND_DMA_H
+#define FNAND_DMA_H
+
+#include "ftypes.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-
 #define FNAND_CMDCTRL_TYPE_RESET 0x00    /* reset */
 #define FNAND_CMDCTRL_TYPE_SET_FTR 0x01  /* Set features */
 #define FNAND_CMDCTRL_TYPE_GET_FTR 0x02  /* Get features */
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.c
index f76f28544c6..e547eed19d1 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_ecc.c
  * Date: 2022-05-12 14:17:42
  * LastEditTime: 2022-05-12 15:56:27
- * Description:  This files is for
+ * Description:  This file is for ecc validation related api
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -45,59 +46,99 @@ u32 FNandGetEccTotalLength(u32 bytes_per_page, u32 ecc_strength)
     int ecc_total = 0;
     switch (bytes_per_page)
     {
-    case 0x200:
-        if (ecc_strength == 8)
-            ecc_total = 0x0D;
-        else if (ecc_strength == 4)
-            ecc_total = 7;
-        else if (ecc_strength == 2)
-            ecc_total = 4;
-        else
-            ecc_total = 0;
-        break;
-    case 0x800:
-        if (ecc_strength == 8)
-            ecc_total = 0x34;
-        else if (ecc_strength == 4)
-            ecc_total = 0x1a;
-        else if (ecc_strength == 2)
-            ecc_total = 0xd;
-        else
-            ecc_total = 0;
-        break;
-    case 0x1000:
-        if (ecc_strength == 8)
-            ecc_total = 0x68;
-        else if (ecc_strength == 4)
-            ecc_total = 0x34;
-        else if (ecc_strength == 2)
-            ecc_total = 0x1a;
-        else
-            ecc_total = 0;
-        break;
-    case 0x2000:
-        if (ecc_strength == 8)
-            ecc_total = 0xD0;
-        else if (ecc_strength == 4)
-            ecc_total = 0x68;
-        else if (ecc_strength == 2)
-            ecc_total = 0x34;
-        else
-            ecc_total = 0;
-        break;
-    case 0x4000:
-        if (ecc_strength == 8)
-            ecc_total = 0x1A0;
-        if (ecc_strength == 4)
-            ecc_total = 0xD0;
-        else if (ecc_strength == 2)
-            ecc_total = 0x68;
-        else
+        case 0x200:
+            if (ecc_strength == 8)
+            {
+                ecc_total = 0x0D;
+            }
+            else if (ecc_strength == 4)
+            {
+                ecc_total = 7;
+            }
+            else if (ecc_strength == 2)
+            {
+                ecc_total = 4;
+            }
+            else
+            {
+                ecc_total = 0;
+            }
+            break;
+        case 0x800:
+            if (ecc_strength == 8)
+            {
+                ecc_total = 0x34;
+            }
+            else if (ecc_strength == 4)
+            {
+                ecc_total = 0x1a;
+            }
+            else if (ecc_strength == 2)
+            {
+                ecc_total = 0xd;
+            }
+            else
+            {
+                ecc_total = 0;
+            }
+            break;
+        case 0x1000:
+            if (ecc_strength == 8)
+            {
+                ecc_total = 0x68;
+            }
+            else if (ecc_strength == 4)
+            {
+                ecc_total = 0x34;
+            }
+            else if (ecc_strength == 2)
+            {
+                ecc_total = 0x1a;
+            }
+            else
+            {
+                ecc_total = 0;
+            }
+            break;
+        case 0x2000:
+            if (ecc_strength == 8)
+            {
+                ecc_total = 0xD0;
+            }
+            else if (ecc_strength == 4)
+            {
+                ecc_total = 0x68;
+            }
+            else if (ecc_strength == 2)
+            {
+                ecc_total = 0x34;
+            }
+            else
+            {
+                ecc_total = 0;
+            }
+            break;
+        case 0x4000:
+            if (ecc_strength == 8)
+            {
+                ecc_total = 0x1A0;
+            }
+            if (ecc_strength == 4)
+            {
+                ecc_total = 0xD0;
+            }
+            else if (ecc_strength == 2)
+            {
+                ecc_total = 0x68;
+            }
+            else
+            {
+                ecc_total = 0;
+            }
+            break;
+        default:
             ecc_total = 0;
-        break;
-    default:
-        ecc_total = 0;
-        break;
+            break;
     }
 
     FNAND_ECC_DEBUG_I("[%s %d]writesize: 0x%x, ecc strength: %d, ecc_total: 0x%x\n", __func__, __LINE__, bytes_per_page, ecc_strength, ecc_total);
@@ -202,7 +243,7 @@ s32 FNandCorrectEcc(uintptr_t base_address, u32 ecc_step_size, u32 hw_ecc_steps,
     int stat = 0;
     if (!buf)
     {
-        FNAND_ECC_DEBUG_E("page buffer is null");
+        FNAND_ECC_DEBUG_E("Page buffer is null");
         return -1;
     }
 
@@ -210,18 +251,9 @@ s32 FNandCorrectEcc(uintptr_t base_address, u32 ecc_step_size, u32 hw_ecc_steps,
     for (i = 0; i < hw_ecc_steps; i++)
     {
         for (j = 0; j < 4; j++)
-        {
-            // value = FNAND_READREG(base_address, 0xB8 + 4 * (2 * i + j));
+        {        
             value = FNAND_READREG(base_address, 0xB8 + 0x10 * i + 4 * j);
-            // FNAND_ECC_DEBUG_W("index:%x i is %d ,j is %d ",
-            //       0xB8 + 0x10 * i + 4*j,i,j);
-            if (value)
-            {
-                // FNAND_ECC_DEBUG_W("offset:%x value:0x%08x\n",
-                //   0xB8 + 0x10 * i + 4*j, value);
-                //phytium_nfc_data_dump2(nfc, nfc->dma_buf + (ecc_step_size * i + tmp/8)/512, 512);
-            }
-
+         
             tmp = value & 0xFFFF;
             if (tmp && (tmp <= 4096))
             {
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.h
index 3c0bbe5bd9f..9c98ae75027 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_ecc.h
@@ -14,24 +14,30 @@
  * FilePath: fnand_ecc.h
  * Date: 2022-05-12 11:17:42
  * LastEditTime: 2022-05-12 13:56:27
- * Description:  This files is for
+ * Description:  This file is for ecc validation related api
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
-#ifndef DRIVERS_NAND_FNAND_ECC_H
-#define DRIVERS_NAND_FNAND_ECC_H
+#ifndef FNAND_ECC_H
+#define FNAND_ECC_H
 
 #include "ftypes.h"
 #include "fnand_hw.h"
 #include "stdio.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 static inline void FNandEnableHwEcc(uintptr_t base_address)
 {
     FNAND_SETBIT(base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_ECC_EN_MASK);
-    // printf("base_address is %p ,value is 0x%x  \r\n",base_address,FNAND_READREG(base_address,FNAND_CTRL0_OFFSET));
+    
 }
 
 
@@ -42,4 +48,9 @@ static inline void FNandDisableHwEcc(uintptr_t base_address)
 
 u32 FNandGetEccTotalLength(u32 bytes_per_page, u32 ecc_strength);
 s32 FNandCorrectEcc(uintptr_t base_address, u32 ecc_step_size, u32 hw_ecc_steps, u8 *buf, u32 length);
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_g.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_g.c
index 4686dbe8325..294c63cd38c 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_g.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:31
- * Description:  This files is for
+ * Description:  This file is for configuration table for devices
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #include "fnand.h"
@@ -31,7 +32,7 @@ FNandConfig FNandConfigTable[FNAND_NUM] =
     {
         .instance_id = FNAND_INSTANCE0,  /* Id of device*/
         .irq_num = FNAND_IRQ_NUM,     /* Irq number */
-        .base_address = FNAND_BASEADDRESS,
+        .base_address = FNAND_BASE_ADDR,
         .ecc_strength = 8, /* 每次ecc 步骤纠正的位数 */
         .ecc_step_size = 512 /* 进行读写操作时，单次ecc 的步骤的跨度 */
     },
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.c
index e72a98a260a..9b6cafc8a22 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:36
- * Description:  This files is for
+ * Description:  This file contains macros that can be used to access the device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #include "fnand_hw.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.h
index cf71a2d04cf..d49df564dc0 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_hw.h
@@ -14,27 +14,31 @@
  * FilePath: fnand_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:40
- * Description:  This files is for
+ * Description:  This file contains macros that can be used to access the device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
-#ifndef DRIVERS_NAND_FNAND_HW_H
-#define DRIVERS_NAND_FNAND_HW_H
+#ifndef FNAND_HW_H
+#define FNAND_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 
 #include "fkernel.h"
 #include "ftypes.h"
 #include "fio.h"
 #include "fkernel.h"
 
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
 #define FNAND_CTRL0_OFFSET 0x00000000U
 #define FNAND_CTRL1_OFFSET 0x00000004U
 #define FNAND_MADDR0_OFFSET 0x00000008U
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.c
index 4b6c90713fb..51abd5100c8 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.c
@@ -14,11 +14,13 @@
  * FilePath: fnand_id.c
  * Date: 2022-07-06 08:34:27
  * LastEditTime: 2022-07-06 08:34:27
- * Description:  This file is for
+ * Description:  This file is for functions in this file are the read id required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 #include "fdebug.h"
 #include "fnand.h"
@@ -78,7 +80,9 @@ static int FnandIdHasPeriod(u8 *id_data_p, int arrlen, int period)
     for (i = 0; i < period; i++)
         for (j = i + period; j < arrlen; j += period)
             if (id_data_p[i] != id_data_p[j])
+            {
                 return 0;
+            }
     return 1;
 }
 
@@ -88,24 +92,34 @@ static int FNandIdLen(u8 *id_data_p, int data_length)
 
     for (last_nonzero = data_length - 1; last_nonzero >= 0; last_nonzero--)
         if (id_data_p[last_nonzero])
+        {
             break;
+        }
 
     /* All zeros */
     if (last_nonzero < 0)
+    {
         return 0;
+    }
 
     /* Calculate wraparound period */
     for (period = 1; period < data_length; period++)
         if (FnandIdHasPeriod(id_data_p, data_length, period))
+        {
             break;
+        }
 
     /* There's a repeated pattern */
     if (period < data_length)
+    {
         return period;
+    }
 
     /* There are trailing zeros */
     if (last_nonzero < data_length - 1)
+    {
         return last_nonzero + 1;
+    }
 
     /* No pattern detected */
     return data_length;
@@ -167,7 +181,7 @@ static FError FNandIdDetect(FNand *instance_p, u32 chip_addr)
     /* step 5 compare ID string and device id */
     if (id_data[0] != maf_id || id_data[1] != dev_id)
     {
-        FNAND_ID_DEBUG_E("second ID read did not match %02x,%02x against %02x,%02x\n",
+        FNAND_ID_DEBUG_E("Second ID read did not match %02x,%02x against %02x,%02x\n",
                          maf_id, dev_id, id_data[0], id_data[1]);
         return FNAND_ERR_NOT_MATCH;
     }
@@ -183,15 +197,15 @@ static FError FNandIdDetect(FNand *instance_p, u32 chip_addr)
         return FNAND_ERR_NOT_MATCH;
     }
 
-    FNAND_ID_DEBUG_I("find manufacturer");
+    FNAND_ID_DEBUG_I("Find manufacturer");
     if (manufacturer_p->ops->detect)
     {
-        FNAND_ID_DEBUG_I("manufacturer_p->ops->detect");
+        FNAND_ID_DEBUG_I("manufacturer_p->ops->detect function work");
         return manufacturer_p->ops->detect(instance_p, &nand_id, chip_addr);
     }
     else
     {
-        FNAND_ID_DEBUG_E("manufacturer detect is empty");
+        FNAND_ID_DEBUG_E("Manufacturer detect is empty");
         return FNAND_ERR_NOT_MATCH;
     }
 
@@ -208,7 +222,7 @@ FError FNandDetect(FNand *instance_p)
         ret = FNandIdDetect(instance_p, i);
         if (ret != FT_SUCCESS)
         {
-            FNAND_ID_DEBUG_W("normal flash is not found");
+            FNAND_ID_DEBUG_W("Normal flash is not found");
         }
         else
         {
@@ -221,7 +235,7 @@ FError FNandDetect(FNand *instance_p)
         ret = FNandToggleInit(instance_p, i); /* toggle 1.0 */
         if (ret != FT_SUCCESS)
         {
-            FNAND_ID_DEBUG_W("toggle flash is not found");
+            FNAND_ID_DEBUG_W("Toggle flash is not found");
         }
         else
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.h
index ccc80290c23..23a5d0551b7 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_id.h
@@ -14,22 +14,28 @@
  * FilePath: fnand_id.h
  * Date: 2022-07-06 14:19:15
  * LastEditTime: 2022-07-06 14:19:15
- * Description:  This file is for
+ * Description:  This file is for functions in this file are the read id required functions
+ * for this driver. 
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
-#ifndef DRIVERS_NAND_DRIVER_FNAND
-#define DRIVERS_NAND_DRIVER_FNAND
+#ifndef FNAND_ID_H
+#define FNAND_ID_H
 
 
 #include "ftypes.h"
 #include "fnand.h"
 
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 
 struct FNandManuFacturerOps
@@ -49,5 +55,8 @@ typedef struct
 
 FError FNandDetect(FNand *instance_p);
 
+#ifdef __cplusplus
+}
+#endif
 
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_intr.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_intr.c
index b4bdb48ea8b..6150cb9c92b 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_intr.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:46
- * Description:  This files is for
+ * Description:  This file contains functions related to fnand interrupt handling.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_option.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_option.c
index 285e17e9463..c10349aa9d8 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_option.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_option.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_option.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:51
- * Description:  This files is for
+ * Description:  This file is for options functions for the fnand component.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -44,13 +45,13 @@ FError FNandSetOption(FNand *instance_p, u32 options, u32 value)
 
     switch (options)
     {
-    case FNAND_OPS_INTER_MODE_SELECT:
-        FASSERT(FNAND_TOG_ASYN_DDR >= value) ;
-        FNAND_CLEARBIT(config_p->base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_INTER_MODE(3UL)) ;
-        FNAND_SETBIT(config_p->base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_INTER_MODE((unsigned long)value)) ;
-        break;
-    default:
-        return FNAND_ERR_INVAILD_PARAMETER;
+        case FNAND_OPS_INTER_MODE_SELECT:
+            FASSERT(FNAND_TOG_ASYN_DDR >= value) ;
+            FNAND_CLEARBIT(config_p->base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_INTER_MODE(3UL)) ;
+            FNAND_SETBIT(config_p->base_address, FNAND_CTRL0_OFFSET, FNAND_CTRL0_INTER_MODE((unsigned long)value)) ;
+            break;
+        default:
+            return FNAND_ERR_INVAILD_PARAMETER;
     }
 
     return FT_SUCCESS;
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_sinit.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_sinit.c
index f6e714ece06..c49a91cf83f 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_sinit.c
@@ -14,11 +14,13 @@
  * FilePath: fnand_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:56:56
- * Description:  This files is for
+ * Description:  This file contains the implementation of the fnand driver's static
+ * initialization functionality.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.c
index d8c364485a8..62f86ed34ef 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_timing.c
  * Date: 2022-05-09 14:53:42
  * LastEditTime: 2022-05-09 08:56:27
- * Description:  This files is for
+ * Description:   This file is for timings configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 #include "ferror_code.h"
 #include "fnand.h"
@@ -339,92 +340,92 @@ FError FNandTimingInterfaceUpdate(FNand *instance_p, u32 chip_addr)
     FNAND_CLEARBIT(config_p->base_address, FNAND_CTRL1_OFFSET, FNAND_CTRL1_SAMPL_PHASE_MAKE(0xffffUL)); /* clear sampl_phase */
     switch (instance_p->inter_mode[chip_addr])
     {
-    case FNAND_ASYN_SDR:
-        if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            target_timming_data = fnand_timing_asy_mode4;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(4UL) ;
-        }
-        else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            target_timming_data = fnand_timing_asy_mode3;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
-        }
-        else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            target_timming_data = fnand_timing_asy_mode2;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(6UL) ;
-        }
-        else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            target_timming_data = fnand_timing_asy_mode1;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
-        }
-        else
-        {
-            target_timming_data = fnand_timing_asy_mode0;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(1UL) ;
-        }
-        ret = FNandMemcpyToReg16(instance_p, FNAND_ASY_TIMING0_OFFSET, 4, target_timming_data, FNAND_TIMING_ASY_NUM);
-        if (ret != FT_SUCCESS)
-        {
-            return  ret;
-        }
-        FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
-        FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 1);
-        break;
-    case FNAND_ONFI_DDR:
-        if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x30);
-            target_timming_data = fnand_timing_syn_mode4;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0xdUL) ;
-        }
-        else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x18);
-            target_timming_data = fnand_timing_syn_mode3;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
-        }
-        else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x20);
-            target_timming_data = fnand_timing_syn_mode2;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x8UL) ;
-        }
-        else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
-        {
-            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
-            target_timming_data = fnand_timing_syn_mode1;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
-        }
-        else
-        {
-            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
-            target_timming_data = fnand_timing_syn_mode0;
-            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
-        }
-        ret =  FNandMemcpyToReg16(instance_p, FNAND_SYN_TIMING6_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
-        if (ret != FT_SUCCESS)
-        {
-            return  ret;
-        }
-        FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
-        break;
-    case FNAND_TOG_ASYN_DDR:
-        value = FNAND_CTRL1_SAMPL_PHASE_MAKE(8UL);
-        target_timming_data = fnand_timing_tog_ddr_mode0;
-        ret = FNandMemcpyToReg16(instance_p, FNAND_TOG_TIMING13_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
-        if (ret != FT_SUCCESS)
-        {
-            return  ret;
-        }
-        FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0xc8);
-        FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
-        break;
-    default:
-        FNAND_TIMING_DEBUG_E("Error inter_mode is %x", instance_p->inter_mode[chip_addr]);
-        return  FNAND_ERR_INVAILD_PARAMETER;
+        case FNAND_ASYN_SDR:
+            if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                target_timming_data = fnand_timing_asy_mode4;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(4UL) ;
+            }
+            else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                target_timming_data = fnand_timing_asy_mode3;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
+            }
+            else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                target_timming_data = fnand_timing_asy_mode2;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(6UL) ;
+            }
+            else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                target_timming_data = fnand_timing_asy_mode1;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
+            }
+            else
+            {
+                target_timming_data = fnand_timing_asy_mode0;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(1UL) ;
+            }
+            ret = FNandMemcpyToReg16(instance_p, FNAND_ASY_TIMING0_OFFSET, 4, target_timming_data, FNAND_TIMING_ASY_NUM);
+            if (ret != FT_SUCCESS)
+            {
+                return  ret;
+            }
+            FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
+            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 1);
+            break;
+        case FNAND_ONFI_DDR:
+            if (FNAND_TIMING_MODE4 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x30);
+                target_timming_data = fnand_timing_syn_mode4;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0xdUL) ;
+            }
+            else if (FNAND_TIMING_MODE3 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x18);
+                target_timming_data = fnand_timing_syn_mode3;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(5UL) ;
+            }
+            else if (FNAND_TIMING_MODE2 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x20);
+                target_timming_data = fnand_timing_syn_mode2;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x8UL) ;
+            }
+            else if (FNAND_TIMING_MODE1 == (instance_p->timing_mode[chip_addr] & 0xf))
+            {
+                FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
+                target_timming_data = fnand_timing_syn_mode1;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
+            }
+            else
+            {
+                FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0x40);
+                target_timming_data = fnand_timing_syn_mode0;
+                value = FNAND_CTRL1_SAMPL_PHASE_MAKE(0x12UL) ;
+            }
+            ret =  FNandMemcpyToReg16(instance_p, FNAND_SYN_TIMING6_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
+            if (ret != FT_SUCCESS)
+            {
+                return  ret;
+            }
+            FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
+            break;
+        case FNAND_TOG_ASYN_DDR:
+            value = FNAND_CTRL1_SAMPL_PHASE_MAKE(8UL);
+            target_timming_data = fnand_timing_tog_ddr_mode0;
+            ret = FNandMemcpyToReg16(instance_p, FNAND_TOG_TIMING13_OFFSET, 4, target_timming_data, FNAND_TIMING_SYN_NUM);
+            if (ret != FT_SUCCESS)
+            {
+                return  ret;
+            }
+            FNAND_WRITEREG(config_p->base_address, FNAND_INTERVAL_OFFSET, 0xc8);
+            FNAND_SETBIT(config_p->base_address, FNAND_CTRL1_OFFSET, value);
+            break;
+        default:
+            FNAND_TIMING_DEBUG_E("Error inter_mode is %x", instance_p->inter_mode[chip_addr]);
+            return  FNAND_ERR_INVAILD_PARAMETER;
     }
 
     return FT_SUCCESS;
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.h
index 8289e1cc32b..a0336640cf6 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/fnand_timing.h
@@ -14,17 +14,26 @@
  * FilePath: fnand_timing.h
  * Date: 2022-04-28 18:53:58
  * LastEditTime: 2022-04-28 18:53:58
- * Description:  This file is for
+ * Description:  This file is for timings configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
-#ifndef DRIVERS_NAND_FNAND
-#define DRIVERS_NAND_FNAND
+
+#ifndef FNAND_TIMING_H
+#define FNAND_TIMING_H
 
 #include "ftypes.h"
 
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
 /**
  * struct FNandSdrTimings - SDR NAND chip timings
  *
@@ -118,7 +127,9 @@ struct FNandSdrTimings
     u32 tWW_min;
 };
 
-
+#ifdef __cplusplus
+}
+#endif
 
 #endif
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.c
index 4ba74b30e7f..59ce0a10ac4 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_onfi.c
  * Date: 2022-07-05 19:10:40
  * LastEditTime: 2022-07-05 19:10:41
- * Description:  This file is for
+ * Description:  This file is for onfi type nand
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -83,9 +84,9 @@
  * loss).
  */
 #define __DIVIDE(dividend, divisor) ({                      \
-    (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
-                   DIV_ROUND_UP(dividend, divisor) :        \
-                   DIV_ROUND_UP_ULL(dividend, divisor));        \
+        (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
+                               DIV_ROUND_UP(dividend, divisor) :        \
+                               DIV_ROUND_UP_ULL(dividend, divisor));        \
     })
 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
@@ -115,7 +116,9 @@ static u16 FNandOnfiCrc16(u16 crc, u8 const *p, size_t len)
     {
         crc ^= *p++ << 8;
         for (i = 0; i < 8; i++)
+        {
             crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+        }
     }
 
     return crc;
@@ -135,7 +138,9 @@ static void FNandSanitizeString(u8 *s, fsize_t len)
     for (i = 0; i < len - 1; i++)
     {
         if (s[i] < ' ' || s[i] > 127)
+        {
             s[i] = '?';
+        }
     }
 
 }
@@ -258,7 +263,7 @@ FError FNandOnfiInit(FNand *instance_p, u32 chip_addr)
     ret = FNandFlashReadId(instance_p, 0x20, id, sizeof(id), chip_addr);
     if (ret != FT_SUCCESS || strncmp(id, "ONFI", sizeof(id) - 1))
     {
-        FNAND_ONFI_DEBUG_E("20H read id is %s ", id);
+        FNAND_ONFI_DEBUG_E("The id value read out from 20H is %s", id);
         return FNAND_NOT_FET_TOGGLE_MODE;
     }
 
@@ -271,7 +276,7 @@ FError FNandOnfiInit(FNand *instance_p, u32 chip_addr)
     ret = FNandOnfiReadParamPage(instance_p, NULL, 0, chip_addr);
     if (ret != FT_SUCCESS)
     {
-        FNAND_ONFI_DEBUG_E("read device id table is error");
+        FNAND_ONFI_DEBUG_E("An error occured when reading device id table");
         return FNAND_NOT_FET_TOGGLE_MODE;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.h
index aab88922095..f023aeeb119 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_onfi.h
@@ -14,11 +14,12 @@
  * FilePath: fnand_onfi.h
  * Date: 2022-07-05 19:10:47
  * LastEditTime: 2022-07-05 19:10:47
- * Description:  This file is for
+ * Description:  This file is for onfi type nand
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 #ifndef DRIVERS_NAND_FNAND_ONFI_H
 #define DRIVERS_NAND_FNAND_ONFI_H
@@ -26,12 +27,16 @@
 #include "ftypes.h"
 #include "fnand.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 #define ONFI_CMD_READ_ID 0x90             /* ONFI Read ID \
-                              command */
+command */
 #define ONFI_CMD_READ_PARAM_PAGE 0xEC     /* ONFI Read \
                           Parameter Page                   \
-                          command */
+command */
 
 
 #define ONFI_END_CMD_NONE 0xfff /* No End command */
@@ -103,5 +108,8 @@ struct OnfiNandGeometry
     u16 crc;
 } __attribute__((__packed__));
 
+#ifdef __cplusplus
+}
+#endif
 
 #endif // !1
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.c
index af1913f036f..b402506c301 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_toggle.c
  * Date: 2022-07-05 20:00:31
  * LastEditTime: 2022-07-05 20:00:31
- * Description:  This file is for
+ * Description:  This file is for toggle nand
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #include "fnand.h"
@@ -79,9 +80,9 @@
  * loss).
  */
 #define __DIVIDE(dividend, divisor) ({                      \
-    (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
-                   DIV_ROUND_UP(dividend, divisor) :        \
-                   DIV_ROUND_UP_ULL(dividend, divisor));        \
+        (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ?  \
+                               DIV_ROUND_UP(dividend, divisor) :        \
+                               DIV_ROUND_UP_ULL(dividend, divisor));        \
     })
 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
@@ -119,7 +120,9 @@ static u16 FNandToggleCrc16(u16 crc, u8 const *p, size_t len)
     {
         crc ^= *p++ << 8;
         for (i = 0; i < 8; i++)
+        {
             crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
+        }
     }
 
     return crc;
@@ -139,7 +142,9 @@ static void FNandSanitizeString(u8 *s, fsize_t len)
     for (i = 0; i < len - 1; i++)
     {
         if (s[i] < ' ' || s[i] > 127)
+        {
             s[i] = '?';
+        }
     }
 
 }
@@ -259,7 +264,7 @@ FError FNandToggleInit(FNand *instance_p, u32 chip_addr)
     ret = FNandFlashReadId(instance_p, 0x40, id, sizeof(id), chip_addr);
     if (ret != FT_SUCCESS || strncmp(id, "JEDEC", sizeof(id) - 1))
     {
-        FNAND_TOGGLE_DEBUG_E("40H read id is %s ", id);
+        FNAND_TOGGLE_DEBUG_E("The id value read out from 40H is %s ", id);
         return FNAND_NOT_FET_TOGGLE_MODE;
     }
 
@@ -283,7 +288,7 @@ FError FNandToggleInit(FNand *instance_p, u32 chip_addr)
     ret = FNandToggleReadParamPage(instance_p, NULL, 0, chip_addr);
     if (ret != FT_SUCCESS)
     {
-        FNAND_TOGGLE_DEBUG_E("read device id table is error");
+        FNAND_TOGGLE_DEBUG_E("An error occured when reading device id table");
         return FNAND_NOT_FET_TOGGLE_MODE;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.h b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.h
index 229a6234e6f..38513ca0642 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.h
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toggle.h
@@ -14,24 +14,27 @@
  * FilePath: fnand_toggle.h
  * Date: 2022-07-05 20:00:45
  * LastEditTime: 2022-07-05 20:00:45
- * Description:  This file is for
+ * Description:  This file is for toggle nand
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 #ifndef DRIVERS_NAND_FNAND_TOGGLE_H
 #define DRIVERS_NAND_FNAND_TOGGLE_H
 
+
+#include "ftypes.h"
+#include "fnand.h"
+
+
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "fnand.h"
-
 
 /*
  * Mandatory commands
@@ -42,31 +45,31 @@ extern "C"
 
 #define TOGGLE_CMD_CHANGE_READ_COLUMN1 0x05 /* TOGGLE Change Read \
                       Column command (1st                         \
-                      cycle) */
+cycle) */
 #define TOGGLE_CMD_CHANGE_READ_COLUMN2 0xE0 /* TOGGLE Change Read \
                       Column command (2nd                         \
-                      cycle) */
+cycle) */
 #define TOGGLE_CMD_BLOCK_ERASE1 0x60        /* TOGGLE Block Erase \
-                          (1st cycle) */
+(1st cycle) */
 #define TOGGLE_CMD_BLOCK_ERASE2 0xD0        /* TOGGLE Block Erase \
-                          (2nd cycle) */
+(2nd cycle) */
 #define TOGGLE_CMD_READ_STATUS 0x70         /* TOGGLE Read status \
-                          command */
+command */
 #define TOGGLE_CMD_PAGE_PROG1 0x80          /* TOGGLE Page Program \
                           command (1st cycle)                      \
-                          */
+*/
 #define TOGGLE_CMD_PAGE_PROG2 0x10          /* TOGGLE Page Program \
                           command (2nd cycle)                      \
-                          */
+*/
 #define TOGGLE_CMD_CHANGE_WRITE_COLUMN 0x85 /* TOGGLE Change Write \
-                         Column command */
+Column command */
 #define TOGGLE_CMD_READ_ID 0x90             /* TOGGLE Read ID \
-                              command */
+command */
 #define TOGGLE_CMD_READ_PARAM_PAGE 0xEC     /* TOGGLE Read \
                           Parameter Page                   \
-                          command */
+command */
 #define TOGGLE_CMD_RESET 0xFF               /* TOGGLE Reset \
-                          command */
+command */
 
 #define TOGGLE_END_CMD_NONE 0xfff /* No End command */
 
diff --git a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toshiba.c b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toshiba.c
index c6d366c3e92..1f570217b1c 100644
--- a/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toshiba.c
+++ b/bsp/phytium/libraries/standalone/drivers/nand/fnand/manufacturer/fnand_toshiba.c
@@ -14,11 +14,12 @@
  * FilePath: fnand_toshiba.c
  * Date: 2022-07-06 08:32:43
  * LastEditTime: 2022-07-06 08:32:44
- * Description:  This file is for
+ * Description:  This file is for toshiba nand
  *
  * Modify History:
  *  Ver   Who  Date   Changes
  * ----- ------  -------- --------------------------------------
+ * 1.0   huanghe    2022/05/10    first release
  */
 
 
@@ -98,12 +99,12 @@ FError toshiba_nand_decode_id(FNand *instance_p, FNandId *id_p, u32 chip_addr)
 
     switch (id_p->data[1])
     {
-    case 0xf0:
-        return TC58NVM9S3ETAI0_CHECK(instance_p, id_p, chip_addr) ;
-        break;
-    default:
-        FNAND_T_NAND_DEBUG_E("Driver not supported 0x%x device", id_p->data[1]) ;
-        return FNAND_ERR_NOT_MATCH;
+        case 0xf0:
+            return TC58NVM9S3ETAI0_CHECK(instance_p, id_p, chip_addr) ;
+            break;
+        default:
+            FNAND_T_NAND_DEBUG_E("Driver not supported 0x%x device", id_p->data[1]) ;
+            return FNAND_ERR_NOT_MATCH;
     }
 }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/Kconfig b/bsp/phytium/libraries/standalone/drivers/pcie/Kconfig
index 5d00a5bed09..c4476fa4913 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/Kconfig
@@ -4,6 +4,6 @@ menu "Pcie Configuration"
         bool
         prompt "Use F_PCIE"
         default n
-
+        
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c
index 470a37fc14e..93f3aa6c92d 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: fpcie.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:28
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:28
+ * Description: This file is for the minimum required function implementations for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 /***************************** Include Files *********************************/
@@ -45,7 +46,6 @@
 #define FPCIE_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(FPCIE_DEBUG_TAG, format, ##__VA_ARGS__)
 
 
-
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -56,13 +56,13 @@ extern int FPcieEpCleanBar(FPcie *instance_p, u32 peu_num, u32 bar_num) ;
 
 static void FPcieShowRegion(const char *name, struct FPcieRegion *region)
 {
-    FPCIE_DEBUG_I("PCI Autoconfig: Bus %s region: [%llx-%llx],\n"
-                  "\t\tPhysical Memory [%llx-%llx]", name,
+    FPCIE_DEBUG_I("Pci auto config: bus %s region: [0x%llx-0x%llx],\n"
+                  "\t\tphysical memory [0x%llx-0x%llx]", name,
                   (unsigned long long)region->bus_start,
                   (unsigned long long)(region->bus_start + region->size - 1),
                   (unsigned long long)region->phys_start,
                   (unsigned long long)(region->phys_start + region->size - 1));
-    FPCIE_DEBUG_I("bus_lower is %llx ", (unsigned long long)region->bus_lower) ;
+    FPCIE_DEBUG_I("Bus lower is 0x%llx", (unsigned long long)region->bus_lower) ;
 }
 
 /**
@@ -81,29 +81,29 @@ static void FPcieRegionConfigInit(FPcie *instance_p, struct FPcieRegion *regs, u
     {
         switch (regs[i].flags)
         {
-        case FPCIE_REGION_IO:
-            memset(&instance_p->mem_io, 0, sizeof(struct FPcieRegion)) ;
-            memcpy(&instance_p->mem_io, regs, sizeof(struct FPcieRegion)) ;
-            instance_p->mem_io.exist_flg = FPCIE_REGION_EXIST_FLG ;
-            instance_p->mem_io.bus_lower = instance_p->mem_io.phys_start;
-            FPcieShowRegion("I/O", &instance_p->mem_io);
-            break;
-        case FPCIE_REGION_MEM:
-            memset(&instance_p->mem, 0, sizeof(struct FPcieRegion)) ;
-            memcpy(&instance_p->mem, regs, sizeof(struct FPcieRegion)) ;
-            instance_p->mem.exist_flg = FPCIE_REGION_EXIST_FLG ;
-            instance_p->mem.bus_lower = instance_p->mem.phys_start;
-            FPcieShowRegion("Memory", &instance_p->mem);
-            break;
-        case (PCI_REGION_PREFETCH|FPCIE_REGION_MEM):
-            memset(&instance_p->mem_prefetch, 0, sizeof(struct FPcieRegion)) ;
-            memcpy(&instance_p->mem_prefetch, regs, sizeof(struct FPcieRegion)) ;
-            instance_p->mem_prefetch.exist_flg = FPCIE_REGION_EXIST_FLG ;
-            instance_p->mem_prefetch.bus_lower = instance_p->mem_prefetch.phys_start;
-            FPcieShowRegion("Prefetchable Mem", &instance_p->mem_prefetch);
-            break;
-        default:
-            break;
+            case FPCIE_REGION_IO:
+                memset(&instance_p->mem_io, 0, sizeof(struct FPcieRegion)) ;
+                memcpy(&instance_p->mem_io, regs, sizeof(struct FPcieRegion)) ;
+                instance_p->mem_io.exist_flg = FPCIE_REGION_EXIST_FLG ;
+                instance_p->mem_io.bus_lower = instance_p->mem_io.phys_start;
+                FPcieShowRegion("I/O", &instance_p->mem_io);
+                break;
+            case FPCIE_REGION_MEM:
+                memset(&instance_p->mem, 0, sizeof(struct FPcieRegion)) ;
+                memcpy(&instance_p->mem, regs, sizeof(struct FPcieRegion)) ;
+                instance_p->mem.exist_flg = FPCIE_REGION_EXIST_FLG ;
+                instance_p->mem.bus_lower = instance_p->mem.phys_start;
+                FPcieShowRegion("Memory", &instance_p->mem);
+                break;
+            case (PCI_REGION_PREFETCH|FPCIE_REGION_MEM):
+                memset(&instance_p->mem_prefetch, 0, sizeof(struct FPcieRegion)) ;
+                memcpy(&instance_p->mem_prefetch, regs, sizeof(struct FPcieRegion)) ;
+                instance_p->mem_prefetch.exist_flg = FPCIE_REGION_EXIST_FLG ;
+                instance_p->mem_prefetch.bus_lower = instance_p->mem_prefetch.phys_start;
+                FPcieShowRegion("Prefetchable Mem", &instance_p->mem_prefetch);
+                break;
+            default:
+                break;
         }
     }
 }
@@ -160,26 +160,6 @@ FError FPcieCfgInitialize(FPcie *instance_p, FPcieConfig *config_p) //用于从
 
     instance_p->is_ready = FT_COMPONENT_IS_READY;
 
-    /* 关闭当前所有misc 中断  */
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C0);
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C1);
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU0_C2);
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C0);
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C1);
-    // FPcieMiscIrqDisable(instance_p, FPCIE_PEU1_C2);
-
-    /* 清空ep模式下所有配置地址 */
-    // for (i = 0; i <= FPCIE_PEU1_C2; i++)
-    // {
-    //     /* code */
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_0);
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_1);
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_2);
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_3);
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_4);
-    //     FPcieEpCleanBar(instance_p, i, FPCIE_BAR_5);
-    // }
-
     return (FT_SUCCESS);
 }
 
@@ -188,7 +168,6 @@ u32 FPcieFindCapability(FPcie *instance_p, u32 bdf, u32 cid_type, u32 cid, u32 *
 
     u32 reg_value;
     u32 next_cap_offset;
-    //u32 ret;
 
     if (cid_type == PCIE_CAP)
     {
@@ -196,7 +175,9 @@ u32 FPcieFindCapability(FPcie *instance_p, u32 bdf, u32 cid_type, u32 cid, u32 *
         /* Serach in PCIe configuration space */
         FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCIE_CAPABILITY_LIST, &reg_value);
         if (reg_value == 0xffffffff)
+        {
             return -1;
+        }
 
         next_cap_offset = (reg_value & 0xff);
         while (next_cap_offset)
@@ -235,63 +216,63 @@ const char *FPcieClassStr(u8 class)
 {
     switch (class)
     {
-    case FPCI_CLASS_NOT_DEFINED:
-        return "Build before PCI Rev2.0";
-        break;
-    case FPCI_BASE_CLASS_STORAGE:
-        return "Mass storage controller";
-        break;
-    case FPCI_BASE_CLASS_NETWORK:
-        return "Network controller";
-        break;
-    case FPCI_BASE_CLASS_DISPLAY:
-        return "Display controller";
-        break;
-    case FPCI_BASE_CLASS_MULTIMEDIA:
-        return "Multimedia device";
-        break;
-    case FPCI_BASE_CLASS_MEMORY:
-        return "Memory controller";
-        break;
-    case FPCI_BASE_CLASS_BRIDGE:
-        return "Bridge device";
-        break;
-    case FPCI_BASE_CLASS_COMMUNICATION:
-        return "Simple comm. controller";
-        break;
-    case FPCI_BASE_CLASS_SYSTEM:
-        return "Base system peripheral";
-        break;
-    case FPCI_BASE_CLASS_INPUT:
-        return "Input device";
-        break;
-    case FPCI_BASE_CLASS_DOCKING:
-        return "Docking station";
-        break;
-    case FPCI_BASE_CLASS_PROCESSOR:
-        return "Processor";
-        break;
-    case FPCI_BASE_CLASS_SERIAL:
-        return "Serial bus controller";
-        break;
-    case FPCI_BASE_CLASS_INTELLIGENT:
-        return "Intelligent controller";
-        break;
-    case FPCI_BASE_CLASS_SATELLITE:
-        return "Satellite controller";
-        break;
-    case FPCI_BASE_CLASS_CRYPT:
-        return "Cryptographic device";
-        break;
-    case FPCI_BASE_CLASS_SIGNAL_PROCESSING:
-        return "DSP";
-        break;
-    case FPCI_CLASS_OTHERS:
-        return "Does not fit any class";
-        break;
-    default:
-        return  "???";
-        break;
+        case FPCI_CLASS_NOT_DEFINED:
+            return "Build before PCI Rev2.0";
+            break;
+        case FPCI_BASE_CLASS_STORAGE:
+            return "Mass storage controller";
+            break;
+        case FPCI_BASE_CLASS_NETWORK:
+            return "Network controller";
+            break;
+        case FPCI_BASE_CLASS_DISPLAY:
+            return "Display controller";
+            break;
+        case FPCI_BASE_CLASS_MULTIMEDIA:
+            return "Multimedia device";
+            break;
+        case FPCI_BASE_CLASS_MEMORY:
+            return "Memory controller";
+            break;
+        case FPCI_BASE_CLASS_BRIDGE:
+            return "Bridge device";
+            break;
+        case FPCI_BASE_CLASS_COMMUNICATION:
+            return "Simple comm. controller";
+            break;
+        case FPCI_BASE_CLASS_SYSTEM:
+            return "Base system peripheral";
+            break;
+        case FPCI_BASE_CLASS_INPUT:
+            return "Input device";
+            break;
+        case FPCI_BASE_CLASS_DOCKING:
+            return "Docking station";
+            break;
+        case FPCI_BASE_CLASS_PROCESSOR:
+            return "Processor";
+            break;
+        case FPCI_BASE_CLASS_SERIAL:
+            return "Serial bus controller";
+            break;
+        case FPCI_BASE_CLASS_INTELLIGENT:
+            return "Intelligent controller";
+            break;
+        case FPCI_BASE_CLASS_SATELLITE:
+            return "Satellite controller";
+            break;
+        case FPCI_BASE_CLASS_CRYPT:
+            return "Cryptographic device";
+            break;
+        case FPCI_BASE_CLASS_SIGNAL_PROCESSING:
+            return "DSP";
+            break;
+        case FPCI_CLASS_OTHERS:
+            return "Does not fit any class";
+            break;
+        default:
+            return  "???";
+            break;
     };
 }
 
@@ -308,7 +289,7 @@ int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
 
     if (!res)
     {
-        printf("No resource\n");
+        FPCIE_DEBUG_E("No resource.");
         goto error;
     }
 
@@ -316,21 +297,18 @@ int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size,
 
     if (addr - res->bus_start + size > res->size)
     {
-        printf("No room in resource");
+        FPCIE_DEBUG_E("No room in resource.");
         goto error;
     }
 
     if (upper_32_bits(addr) && !supports_64bit)
     {
-        printf("Cannot assign 64-bit address to 32-bit-only resource\n");
+        FPCIE_DEBUG_E("Cannot assign 64-bit address to 32-bit-only resource.");
         goto error;
     }
 
     res->bus_lower = addr + size;
 
-    //printf("address=0x%llx bus_lower=0x%llx\n", (unsigned long long)addr,
-    //        (unsigned long long)res->bus_lower);
-
     *bar = addr;
     return 0;
 
@@ -362,17 +340,21 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
               FPCIE_COMMAND_MASTER;
 
     for (bar = FPCIE_BASE_ADDRESS_0;
-            bar < FPCIE_BASE_ADDRESS_0 + (bars_num * 4); bar += 4)
+         bar < FPCIE_BASE_ADDRESS_0 + (bars_num * 4); bar += 4)
     {
         /* Tickle the BAR and get the response */
         if (!enum_only)
+        {
             FPcieEcamWriteConfig32bit(instance_p->config.ecam, bdf, bar, 0xffffffff);
+        }
 
         FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, bar, &bar_response);
 
         /* If BAR is not implemented go to the next BAR */
         if (!bar_response)
+        {
             continue;
+        }
 
         found_mem64 = 0;
 
@@ -382,15 +364,15 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
             bar_size = ((~(bar_response & FPCIE_BASE_ADDRESS_IO_MASK))
                         & 0xffff) + 1;
             if (!enum_only)
+            {
                 bar_res = io;
+            }
 
-            //printf("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
-            //        bar_nr, (unsigned long long)bar_size);
         }
         else
         {
             if ((bar_response & FPCIE_BASE_ADDRESS_MEM_TYPE_MASK) ==
-                    FPCIE_BASE_ADDRESS_MEM_TYPE_64)
+                FPCIE_BASE_ADDRESS_MEM_TYPE_64)
             {
                 u32 bar_response_upper;
                 u64 bar64;
@@ -407,7 +389,9 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
                 bar_size = ~(bar64 & FPCIE_BASE_ADDRESS_MEM_MASK)
                            + 1;
                 if (!enum_only)
+                {
                     found_mem64 = 1;
+                }
             }
             else
             {
@@ -426,10 +410,6 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
                     bar_res = mem;
                 }
             }
-
-            //printf("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
-            //        bar_nr, bar_res == prefetch ? "Prf" : "Mem",
-            //        (unsigned long long)bar_size);
         }
 
         if (!enum_only && FPcieAutoRegionAllocate(bar_res, bar_size,
@@ -459,8 +439,6 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
         cmdstat |= (bar_response & FPCIE_BASE_ADDRESS_SPACE) ?
                    FPCIE_COMMAND_IO : FPCIE_COMMAND_MEMORY;
 
-        //printf("\n");
-
         bar_nr++;
     }
 
@@ -478,8 +456,7 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
             if (bar_response)
             {
                 bar_size = -(bar_response & ~1);
-                //printf("PCI Autoconfig: ROM, size=%#x, ",
-                //        (unsigned int)bar_size);
+                
                 if (FPcieAutoRegionAllocate(mem, bar_size,
                                             &bar_value,
                                             false) == 0)
@@ -488,7 +465,6 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
 
                 }
                 cmdstat |= FPCIE_COMMAND_MEMORY;
-                //printf("\n");
             }
         }
     }
@@ -496,7 +472,9 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num,
     /* PCI_COMMAND_IO must be set for VGA device */
     FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCI_CLASS_DEVICE_REG, &class);
     if (class == FPCI_CLASS_DISPLAY_VGA)
+    {
         cmdstat |= FPCIE_COMMAND_IO;
+    }
 
     FPcieEcamWriteConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, cmdstat);
     FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_CACHE_LINE_SIZE_REG,
@@ -694,35 +672,36 @@ int FPcieAutoConfigDevice(FPcie *instance_p, u32 bdf)
 
     switch (class)
     {
-    case FPCI_CLASS_BRIDGE_PCI:
-        FPcieAutoSetupDevice(instance_p, bdf, 2, pci_mem, pci_prefetch, pci_io,
-                             enum_only);
+        case FPCI_CLASS_BRIDGE_PCI:
+            FPcieAutoSetupDevice(instance_p, bdf, 2, pci_mem, pci_prefetch, pci_io,
+                                 enum_only);
 
-        n = FPcieHoseProbeBus(instance_p, bdf);
-        if (n < 0)
-            return n;
-        break;
+            n = FPcieHoseProbeBus(instance_p, bdf);
+            if (n < 0)
+            {
+                return n;
+            }
+            break;
 
-    case FPCI_CLASS_BRIDGE_CARDBUS:
-        /*
-         * just do a minimal setup of the bridge,
-         * let the OS take care of the rest
-         */
-        FPcieAutoSetupDevice(instance_p, bdf, 0, pci_mem, pci_prefetch, pci_io,
-                             enum_only);
+        case FPCI_CLASS_BRIDGE_CARDBUS:
+            /*
+             * just do a minimal setup of the bridge,
+             * let the OS take care of the rest
+             */
+            FPcieAutoSetupDevice(instance_p, bdf, 0, pci_mem, pci_prefetch, pci_io,
+                                 enum_only);
 
-        printf("PCI Autoconfig: Found P2CardBus bridge, device %d\n", FPCIE_DEV(bdf));
+            FPCIE_DEBUG_I("PCI auto config: Found P2CardBus bridge, device %d.", FPCIE_DEV(bdf));
 
-        break;
+            break;
 
-    case FPCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
-        printf("PCI AutoConfig: Found PowerPC device\n");
-    /* fall through */
+        case FPCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
+            FPCIE_DEBUG_I("PCI auto config: Found PowerPC device.");
 
-    default:
-        FPcieAutoSetupDevice(instance_p, bdf, 6, pci_mem, pci_prefetch, pci_io,
-                             enum_only);
-        break;
+        default:
+            FPcieAutoSetupDevice(instance_p, bdf, 6, pci_mem, pci_prefetch, pci_io,
+                                 enum_only);
+            break;
     }
 
     return FT_SUCCESS;
@@ -742,10 +721,12 @@ FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struc
     u32 data;
     char buf_bdf_print[20];
     found_multi = false;
-    end = FPCIE_BDF(bus_num, FT_PCIE_CFG_MAX_NUM_OF_DEV - 1,
-                    FT_PCIE_CFG_MAX_NUM_OF_FUN - 1);
-    for (bdf = FPCIE_BDF(bus_num, 0, 0); bdf <= end;    //使用bus的seq成员来进行扫描，其实相当于secondory_bus号
-            bdf += FPCIE_BDF(0, 0, 1))
+    end = FPCIE_BDF(bus_num, FPCIE_CFG_MAX_NUM_OF_DEV - 1,
+                    FPCIE_CFG_MAX_NUM_OF_FUN - 1);
+
+    /* 使用bus的seq成员来进行扫描，其实相当于secondory_bus号 */
+    for (bdf = FPCIE_BDF(bus_num, 0, 0); bdf <= end;    
+         bdf += FPCIE_BDF(0, 0, 1))
     {
         u32 class;
 
@@ -759,23 +740,32 @@ FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struc
         }
 
         if (!FPCIE_FUNC(bdf))
+        {
             found_multi = false;
+        }
         if (FPCIE_FUNC(bdf) && !found_multi)
+        {
             continue;
+        }
 
         /* Check only the first access, we don't expect problems */
         FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_VENDOR_REG, &vendor) ;
 
         if (vendor == 0xffff || vendor == 0x0000)
+        {
             continue;
+        }
 
         FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_HEADER_TYPE_REG, &header_type) ;
 
         if (!FPCIE_FUNC(bdf))
+        {
             found_multi = header_type & 0x80;
-
-        FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &device) ;  //读取deviceid
-        FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCI_CLASS_REVISION, &class) ; //读取classcode
+        }
+        
+        /* 读取deviceid, classcode */
+        FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_DEVICE_ID_REG, &device) ;  
+        FPcieEcamReadConfig32bit(instance_p->config.ecam, bdf, FPCI_CLASS_REVISION, &class) ; 
         class >>= 8;
 
         FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_CLASS_CODE_REG, &class_show) ;
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.h b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.h
index c8ca7077dc6..30f01911210 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.h
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.h
@@ -12,21 +12,18 @@
  *
  *
  * FilePath: fpcie.h
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:37
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:37
+ * Description: This file is for detailed description of the device and driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
-
-#ifndef DRIVERS_FPCIE_H
-#define DRIVERS_FPCIE_H
-
-
-
+#ifndef FPCIE_H
+#define FPCIE_H
 
 /************************** Constant Definitions *****************************/
 
@@ -36,11 +33,6 @@
 
 /************************** Function Prototypes ******************************/
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
 /***************************** Include Files *********************************/
 
 #include "ftypes.h"
@@ -48,6 +40,11 @@ extern "C"
 #include "fpcie_dma.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 #ifdef __aarch64__
 #define CONFIG_SYS_PCI_64BIT    1
 #endif
@@ -174,16 +171,16 @@ typedef struct
     uintptr_t peu0_config_address;
     uintptr_t peu1_config_address;
 
-    uintptr_t control_c0_address;       //0x29900000
-    uintptr_t control_c1_address;       //0x29910000
+    uintptr_t control_c0_address;       
+    uintptr_t control_c1_address;       
     uintptr_t control_c2_address;
     uintptr_t control_c3_address;
     uintptr_t control_c4_address;
     uintptr_t control_c5_address;
 
-#ifdef FT_PCI_INTX_EOI
-    uintptr_t intx_peux_stat_address[FT_PCI_INTX_SATA_NUM] ;
-    uintptr_t intx_control_eux_cx_address[FT_PCI_INTX_CONTROL_NUM] ;
+#ifdef FPCI_INTX_EOI
+    uintptr_t intx_peux_stat_address[FPCI_INTX_SATA_NUM] ;
+    uintptr_t intx_control_eux_cx_address[FPCI_INTX_CONTROL_NUM] ;
 #endif
 
     u32 io_base_addr;
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_common.h b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_common.h
index 3b7c1efef76..74d914fe234 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_common.h
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_common.h
@@ -12,27 +12,27 @@
  *
  *
  * FilePath: fpcie_common.h
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:57:24
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:57:24
+ * Description: This file is for pcie common features definition. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
+#ifndef FPCIE_COMMON_H
+#define FPCIE_COMMON_H
 
-#ifndef DRIVERS_FPCIE_COMMON_H
-#define DRIVERS_FPCIE_COMMON_H
+#include "fpcie_hw.h"
+#include "fkernel.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "fpcie_hw.h"
-#include "fkernel.h"
-
 /******************** Macros (Inline Functions) Definitions *******************/
 
 /* Device classes and subclasses */
@@ -226,13 +226,11 @@ extern "C"
 
 #define FPCIE_HEADER_TYPE_REG       0x0e    /* 8 bits */
 
-
 #define FPCIE_REVISION_ID_REG       0x08    /* Revision ID */
 #define FPCIE_CLASS_PROG_REG        0x09    /* Reg. Level Programming Interface */
 #define FPCIE_CLASS_DEVICE_REG      0x0a    /* Device class */
 #define FPCIE_CLASS_CODE_REG        0x0b    /* Device class code */
 
-
 #define FPCIE_PREF_MEMORY_BASE_REG  0x24    /* Prefetchable memory range behind */
 #define FPCIE_PREF_MEMORY_LIMIT_REG     0x26
 #define FPCIE_PREF_LIMIT_UPPER32_REG        0x2c
@@ -241,18 +239,14 @@ extern "C"
 #define FPCIE_PREF_RANGE_TYPE_64    0x01
 #define FPCIE_PREF_RANGE_MASK       ~0x0f
 
-
 #define FPCI_CLASS_BRIDGE_PCI       0x0604
 #define FPCI_CLASS_BRIDGE_CARDBUS   0x0607
 #define FPCI_CLASS_PROCESSOR_POWERPC    0x0b20
 #define FPCI_CLASS_DISPLAY_VGA      0x0300
 
-
-
 #define FPCIE_CFG_FUN_NOT_IMP_MASK 0xFFFF
 #define FPCIE_CFG_HEADER_TYPE_MASK 0x007F0000
 
-
 /*
  * Base addresses specify locations in memory or I/O space.
  * Decoded size can be determined by writing a value of
@@ -479,10 +473,6 @@ extern "C"
 #define  FPCI_CAP_ID_EA     0x14    /* PCI Enhanced Allocation */
 #define  FPCI_CAP_ID_MAX        PCI_CAP_ID_EA
 
-/* Extended Capabilities (PCI-X 2.0 and Express) */
-//#define PCI_EXT_CAP_ID(header)        (header & 0x0000ffff)
-//#define PCI_EXT_CAP_VER(header)       ((header >> 16) & 0xf)
-//#define PCI_EXT_CAP_NEXT(header)  ((header >> 20) & 0xffc)
 
 #define FPCI_EXT_CAP_ID_ERR 0x01    /* Advanced Error Reporting */
 #define FPCI_EXT_CAP_ID_VC  0x02    /* Virtual Channel Capability */
@@ -524,8 +514,6 @@ extern "C"
 #define FPCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET                    0x28
 #define FPCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING            0x20
 
-
-
 /*
  * Address Translation Registers
  */
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_config.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_config.c
index 1fc5f4ad6a0..79c97b8ca21 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_config.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_config.c
@@ -12,19 +12,19 @@
  *
  *
  * FilePath: fpcie_config.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:57:30
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:57:30
+ * Description: This file is for pcie miscellaneous interrupt enable or disable. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 #include "fpcie.h"
 #include "fpcie_hw.h"
 
-
 /***************************** Include Files *********************************/
 
 /************************** Constant Definitions *****************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.c
index 721e8d2d259..e601dbd7d78 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: fpcie_dma.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:57:38
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:57:38
+ * Description: This file is for pcie dma implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 
@@ -28,7 +29,7 @@
 #include "ftypes.h"
 #include "fcache.h"
 #include "fkernel.h"
-
+#include "fdebug.h"
 /***************************** Include Files *********************************/
 
 /************************** Constant Definitions *****************************/
@@ -39,7 +40,7 @@
 
 /***************** Macros (Inline Functions) Definitions *********************/
 
-#include "fdebug.h"
+
 #define FPCIE_DMA_DEBUG_TAG "FPCIE_DMA"
 #define FPCIE_DMA_ERROR(format, ...) FT_DEBUG_PRINT_E(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FPCIE_DMA_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(FPCIE_DMA_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -149,15 +150,15 @@ void FPcieDmaWrite(uintptr bar_address, struct FPcieDmaDescriptor *desc)
  */
 FError FPcieDmaPollDone(struct FPcieDmaDescriptor *desc, u32 wait_cnt)
 {
-    FPCIE_DMA_DEBUG_I("desc axi_bus_status :[0x%02x]", desc->axi_bus_status);
-    FPCIE_DMA_DEBUG_I("desc pcie_bus_status:[0x%02x]", desc->pcie_bus_status);
-    FPCIE_DMA_DEBUG_I("desc channel_status :[0x%02x]", desc->channel_status);
+    FPCIE_DMA_DEBUG_I("Desc axi_bus_status :[0x%02x].", desc->axi_bus_status);
+    FPCIE_DMA_DEBUG_I("Desc pcie_bus_status:[0x%02x].", desc->pcie_bus_status);
+    FPCIE_DMA_DEBUG_I("Desc channel_status :[0x%02x].", desc->channel_status);
 
     while (wait_cnt > 0)
     {
         if (desc->channel_status == 0x1)
         {
-            FPCIE_DMA_DEBUG_I("dma channel transfer done ");
+            FPCIE_DMA_DEBUG_I("Dma channel transfer done.");
             return FT_SUCCESS;
         }
         wait_cnt--;
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.h b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.h
index 6e0d54bdba1..999b22bbe77 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.h
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_dma.h
@@ -12,24 +12,25 @@
  *
  *
  * FilePath: fpcie_dma.h
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:57:51
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:57:51
+ * Description: This file is for pcie dma definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
-#ifndef DRIVERS_FPCIE_DMA_H
-#define DRIVERS_FPCIE_DMA_H
+#ifndef FPCIE_DMA_H
+#define FPCIE_DMA_H
+
+#include "ftypes.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
-#include "ftypes.h"
-
 
 /***************************** Include Files *********************************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_ep.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_ep.c
index cad384e18cf..a0d7dc7b0e7 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_ep.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_ep.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: fpcie_ep.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:57:59
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:57:59
+ * Description: This file is for pcie endpoint device operation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 #include "fpcie.h"
@@ -49,8 +50,6 @@
 
 /************************** Function Prototypes ******************************/
 
-
-
 int FPcieEpSetBar(FPcie *instance_p, u32 peu_num, u32 bar_num, u64 bar_mem_addr, u64 bar_mem_size, int flags)
 {
     u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
@@ -79,19 +78,31 @@ int FPcieEpSetBar(FPcie *instance_p, u32 peu_num, u32 bar_num, u64 bar_mem_addr,
         boolean is_64bits = sz > SZ_2G;
 
         if (is_64bits && (bar_num & 1))
+        {
             return FPCIE_ERR_INVALID_PARAM;
+        }
 
         if (is_64bits && !(flags & FPCIE_BASE_ADDRESS_MEM_TYPE_64))
+        {
             flags |= FPCIE_BASE_ADDRESS_MEM_TYPE_64;
+        }
 
         if (is_64bits && is_prefetch)
+        {
             ctrl = FPCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
+        }
         else if (is_prefetch)
+        {
             ctrl = FPCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
+        }
         else if (is_64bits)
+        {
             ctrl = FPCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
+        }
         else
+        {
             ctrl = FPCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
+        }
     }
 
     addr0 = LOWER_32_BITS(bar_mem_addr);
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_g.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_g.c
index 2f05d516967..a0154c38378 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_g.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: fpcie_g.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:58:07
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:58:07
+ * Description: This file is for pcie static configuration implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 
@@ -28,47 +29,47 @@
 #include "sdkconfig.h"
 
 
-FPcieConfig FPcieConfigTable[FT_PCIE_NUM] =
+FPcieConfig FPcieConfigTable[FPCIE_NUM] =
 {
     {
-        .instance_id = FT_PCIE0_ID, /* Id of device*/
-        .irq_num = FT_PCIE0_MISC_IRQ_NUM,     // Irq number
-        .ecam = FT_PCI_CONFIG_BASEADDR,  /* The Memory way */
-        .peu0_config_address = FT_PCI_EU0_CONFIG_BASEADDR,
-        .peu1_config_address = FT_PCI_EU1_CONFIG_BASEADDR,
-        .control_c0_address = FT_PCI_EU0_C0_CONTROL_BASEADDR,
-        .control_c1_address = FT_PCI_EU0_C1_CONTROL_BASEADDR,
-        .control_c2_address = FT_PCI_EU0_C2_CONTROL_BASEADDR,
-        .control_c3_address = FT_PCI_EU1_C0_CONTROL_BASEADDR,
-        .control_c4_address = FT_PCI_EU1_C1_CONTROL_BASEADDR,
-        .control_c5_address = FT_PCI_EU1_C2_CONTROL_BASEADDR,
-#ifdef FT_PCI_INTX_EOI
+        .instance_id = FPCIE0_ID, /* Id of device*/
+        .irq_num = FPCIE0_MISC_IRQ_NUM,     // Irq number
+        .ecam = FPCI_CONFIG_BASE_ADDR,  /* The Memory way */
+        .peu0_config_address = FPCI_EU0_CONFIG_BASE_ADDR,
+        .peu1_config_address = FPCI_EU1_CONFIG_BASE_ADDR,
+        .control_c0_address = FPCI_EU0_C0_CONTROL_BASE_ADDR,
+        .control_c1_address = FPCI_EU0_C1_CONTROL_BASE_ADDR,
+        .control_c2_address = FPCI_EU0_C2_CONTROL_BASE_ADDR,
+        .control_c3_address = FPCI_EU1_C0_CONTROL_BASE_ADDR,
+        .control_c4_address = FPCI_EU1_C1_CONTROL_BASE_ADDR,
+        .control_c5_address = FPCI_EU1_C2_CONTROL_BASE_ADDR,
+#ifdef FPCI_INTX_EOI
         .intx_peux_stat_address =
         {
-            [0] = FT_PCI_INTX_PEU0_STAT,
-            [1] = FT_PCI_INTX_PEU1_STAT,
+            [0] = FPCI_INTX_PEU0_STAT,
+            [1] = FPCI_INTX_PEU1_STAT,
         },
         .intx_control_eux_cx_address =
         {
-            [0] = FT_PCI_INTX_EU0_C0_CONTROL,
-            [1] = FT_PCI_INTX_EU0_C1_CONTROL,
-            [2] = FT_PCI_INTX_EU0_C2_CONTROL,
-            [3] = FT_PCI_INTX_EU1_C0_CONTROL,
-            [4] = FT_PCI_INTX_EU1_C1_CONTROL,
-            [5] = FT_PCI_INTX_EU1_C2_CONTROL,
+            [0] = FPCI_INTX_EU0_C0_CONTROL,
+            [1] = FPCI_INTX_EU0_C1_CONTROL,
+            [2] = FPCI_INTX_EU0_C2_CONTROL,
+            [3] = FPCI_INTX_EU1_C0_CONTROL,
+            [4] = FPCI_INTX_EU1_C1_CONTROL,
+            [5] = FPCI_INTX_EU1_C2_CONTROL,
         },
 #endif
-        .io_base_addr = FT_PCI_IO_CONFIG_BASEADDR,
-        .io_size = FT_PCI_IO_CONFIG_REG_LENGTH,
-        .npmem_base_addr = FT_PCI_MEM32_BASEADDR,
-        .npmem_size = FT_PCI_MEM32_REG_LENGTH,
-        .pmem_base_addr = FT_PCI_MEM64_BASEADDR, /* Prefetchable memory */
-        .pmem_size = FT_PCI_MEM64_REG_LENGTH,
-        .inta_irq_num = FT_PCI_INTA_IRQ_NUM,
-        .intb_irq_num = FT_PCI_INTB_IRQ_NUM,
-        .intc_irq_num = FT_PCI_INTC_IRQ_NUM,
-        .intd_irq_num = FT_PCI_INTD_IRQ_NUM,
-        .need_skip = FT_PCI_NEED_SKIP
+        .io_base_addr = FPCI_IO_CONFIG_BASE_ADDR,
+        .io_size = FPCI_IO_CONFIG_REG_LENGTH,
+        .npmem_base_addr = FPCI_MEM32_BASE_ADDR,
+        .npmem_size = FPCI_MEM32_REG_LENGTH,
+        .pmem_base_addr = FPCI_MEM64_BASE_ADDR, /* Prefetchable memory */
+        .pmem_size = FPCI_MEM64_REG_LENGTH,
+        .inta_irq_num = FPCI_INTA_IRQ_NUM,
+        .intb_irq_num = FPCI_INTB_IRQ_NUM,
+        .intc_irq_num = FPCI_INTC_IRQ_NUM,
+        .intd_irq_num = FPCI_INTD_IRQ_NUM,
+        .need_skip = FPCI_NEED_SKIP
     }
 };
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.c
index 3850bab7c5f..d8beaedface 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.c
@@ -13,12 +13,13 @@
  *
  * FilePath: fpcie_hw.c
  * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:58:12
- * Description:  This files is for
+ * LastEditTime: 2022-08-18 08:58:12
+ * Description: This file is for pcie register operation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 #include "fpcie_hw.h"
@@ -116,7 +117,9 @@ FError FPcieSkipDevice(uintptr ecam_addr, s32 bdf)
     {
         pos = FPCIE_READREG_BYTE(addr, pos) ;
         if (pos < 0x40)/* 超过Capability Pointer所代表的空间offset最大范围 */
+        {
             break;
+        }
         pos &= ~3 ; /* offset 第两位对齐 */
         id = FPCIE_READREG_BYTE(addr, pos) ;  /* PCI Express Cap ID */
         if (id == 0xff)
@@ -151,12 +154,12 @@ static s32 FPcieGetFf(enum FPcieSize size)
 {
     switch (size)
     {
-    case FPCIE_SIZE_8:
-        return 0xff;
-    case FPCIE_SIZE_16:
-        return 0xffff;
-    default:
-        return 0xffffffff;
+        case FPCIE_SIZE_8:
+            return 0xff;
+        case FPCIE_SIZE_16:
+            return 0xffff;
+        default:
+            return 0xffffffff;
     }
 }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.h b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.h
index b6c1c1906c1..96a4c5d0b0f 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_hw.h
@@ -12,28 +12,28 @@
  *
  *
  * FilePath: fpcie_hw.h
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:58:22
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:58:22
+ * Description: This file is for pcie register definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
+#ifndef FPCIE_HW_H
+#define FPCIE_HW_H
 
-#ifndef DRIVERS_FPCIE_HW_H
-#define DRIVERS_FPCIE_HW_H
+#include "ftypes.h"
+#include "fio.h"
+#include "ferror_code.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "fio.h"
-#include "ferror_code.h"
-
 /***************************** Include Files *********************************/
 
 /************************** Constant Definitions *****************************/
@@ -226,8 +226,6 @@ extern "C"
 #define FPCIE_ECAM_FUN_SHIFT 12 /**< Function Number Shift Value */
 #define FPCIE_ECAM_REG_SHIFT 2  /**< Register Number Shift Value */
 #define FPCIE_ECAM_BYT_SHIFT 0  /**< Byte Offset Shift Value */
-/*@}*/
-
 
 #define FPCIE_BUS(d)        (((d) >> 16) & 0xff)
 /*
@@ -318,7 +316,7 @@ void FPcieEcamWriteConfig16bit(uintptr ecam_addr, s32 bdf, u32 offset, u16 value
 
 void FPcieEcamWriteConfig32bit(uintptr ecam_addr, s32 bdf, u32 offset, u32 value);
 
-FError FPcieSkipDevice(uintptr ecam_addr, s32 bdf) ;
+FError FPcieSkipDevice(uintptr ecam_addr, s32 bdf);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.c
similarity index 64%
rename from bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.c
rename to bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.c
index bcf0992e11d..1bc17a7051b 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.c
@@ -11,18 +11,17 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: fpcir_intx.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:42
- * Description:  This files is for
+ * FilePath: fpcie_intr.c
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:42
+ * Description: This file is for pcie interrupt handler implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
-
-
 /***************************** Include Files *********************************/
 #include "fpcie.h"
 #include "fpcie_common.h"
@@ -30,7 +29,6 @@
 #include "fparameters.h"
 #include "fdebug.h"
 
-
 /***************** Macros (Inline Functions) Definitions *********************/
 
 #define FPCIE_INTX_DEBUG_TAG "FPCIE_INTX"
@@ -89,36 +87,36 @@ FError FPcieIntxRegiterIrqHandler(FPcie *instance_p,
         FPcieEcamReadConfig8bit(instance_p->config.ecam, bdf, FPCIE_INTERRUPT_PIN_REG, &interrupt_pin) ;
         switch (interrupt_pin)
         {
-        case 0x1: /* INTA# */
-            interrupt_line = instance_p->config.inta_irq_num ;
-            instance_p->inta_fun[i] = *intx_fun_p;  //中断函数，写入的是pcie instance的成员，一个pcie rc只有一个中断处理函数？
-            instance_p->inta_fun[i].bdf  = bdf; //一个中断函数对应一个bdf号
-            break ;
-        case 0x2: /* INTB# */
-            interrupt_line = instance_p->config.intb_irq_num ;
-            instance_p->intb_fun[i] = *intx_fun_p;
-            instance_p->intb_fun[i].bdf  = bdf;
-            break ;
-        case 0x3: /* INTC# */
-            interrupt_line = instance_p->config.intc_irq_num ;
-            instance_p->intc_fun[i] = *intx_fun_p;
-            instance_p->intc_fun[i].bdf  = bdf;
-            break ;
-        case 0x4: /* INTD# */
-            interrupt_line = instance_p->config.intd_irq_num ;
-            instance_p->intd_fun[i] = *intx_fun_p;
-            instance_p->intd_fun[i].bdf  = bdf;
-            break ;
-        default:
-            FPCIE_INTX_DEBUG_E("Error interrupt pin") ;
-            return FPCIE_NOT_FOUND;
+            case 0x1: /* INTA# */
+                interrupt_line = instance_p->config.inta_irq_num ;
+                instance_p->inta_fun[i] = *intx_fun_p;  //中断函数，写入的是pcie instance的成员，一个pcie rc只有一个中断处理函数？
+                instance_p->inta_fun[i].bdf  = bdf; //一个中断函数对应一个bdf号
+                break ;
+            case 0x2: /* INTB# */
+                interrupt_line = instance_p->config.intb_irq_num ;
+                instance_p->intb_fun[i] = *intx_fun_p;
+                instance_p->intb_fun[i].bdf  = bdf;
+                break ;
+            case 0x3: /* INTC# */
+                interrupt_line = instance_p->config.intc_irq_num ;
+                instance_p->intc_fun[i] = *intx_fun_p;
+                instance_p->intc_fun[i].bdf  = bdf;
+                break ;
+            case 0x4: /* INTD# */
+                interrupt_line = instance_p->config.intd_irq_num ;
+                instance_p->intd_fun[i] = *intx_fun_p;
+                instance_p->intd_fun[i].bdf  = bdf;
+                break ;
+            default:
+                FPCIE_INTX_DEBUG_E("Error interrupt pin.") ;
+                return FPCIE_NOT_FOUND;
         }
 
         FPcieEcamWriteConfig8bit(instance_p->config.ecam, bdf, FPCIE_INTERRUPT_LINE_REG, interrupt_line) ;
     }
     else
     {
-        FPCIE_INTX_DEBUG_E("Pcie intx not match header type") ;
+        FPCIE_INTX_DEBUG_E("Pcie intx not match header type.") ;
         return FPCIE_NOT_FOUND;
     }
 
@@ -138,21 +136,21 @@ static void FPcieIntxCallback(FPcie *instance_p, u8 INTx_NUM)
         {
             switch (INTx_NUM)
             {
-            case INTA:
-                instance_p->inta_fun[i].IntxCallBack(instance_p->inta_fun[i].args);
-                break;
-            case INTB:
-                instance_p->intb_fun[i].IntxCallBack(instance_p->intb_fun[i].args);
-                break;
-            case INTC:
-                instance_p->intc_fun[i].IntxCallBack(instance_p->intc_fun[i].args);
-                break;
-            case INTD:
-                instance_p->intd_fun[i].IntxCallBack(instance_p->intd_fun[i].args);
-                break;
-            default:
-                printf("%s: error intx num\n", __func__);
-                break;
+                case INTA:
+                    instance_p->inta_fun[i].IntxCallBack(instance_p->inta_fun[i].args);
+                    break;
+                case INTB:
+                    instance_p->intb_fun[i].IntxCallBack(instance_p->intb_fun[i].args);
+                    break;
+                case INTC:
+                    instance_p->intc_fun[i].IntxCallBack(instance_p->intc_fun[i].args);
+                    break;
+                case INTD:
+                    instance_p->intd_fun[i].IntxCallBack(instance_p->intd_fun[i].args);
+                    break;
+                default:
+                    FPCIE_INTX_DEBUG_E("%s: error intx num.", __func__);
+                    break;
 
             }
         }
@@ -163,7 +161,7 @@ static void FPcieIntxCallback(FPcie *instance_p, u8 INTx_NUM)
 
 static void FPcieIntxIrqEoi(FPcie *instance_p, u32 intx_idx)
 {
-#ifdef FT_PCI_INTX_EOI
+#ifdef FPCI_INTX_EOI
     u32 status = 0 ;
     u32 istatus = 0, imask = 0 ;
     int i ;
@@ -171,7 +169,7 @@ static void FPcieIntxIrqEoi(FPcie *instance_p, u32 intx_idx)
 
     imask = 1 << (3 - intx_idx);
     istatus = (1 << intx_idx) << 24;
-    for (i = 0; i < FT_PCI_INTX_CONTROL_NUM; i++, status >>= 4)
+    for (i = 0; i < FPCI_INTX_CONTROL_NUM; i++, status >>= 4)
     {
         if (imask & status)
         {
@@ -200,25 +198,23 @@ void FPcieIntxIrqHandler(s32 vector, void *args)        //中断响应函数
 
     switch (vector)
     {
-    case FT_PCI_INTA_IRQ_NUM:       //如果响应的是INTA中断，则调用pcie_obj中INTA的中断处理函数
-        FPcieIntxCallback(instance_p, INTA) ;
-        FPcieIntxIrqEoi(instance_p, 0) ;
-        break;
-    case FT_PCI_INTB_IRQ_NUM:
-        FPcieIntxCallback(instance_p, INTA) ;
-        FPcieIntxIrqEoi(instance_p, 1) ;
-        break;
-    case FT_PCI_INTC_IRQ_NUM:
-        FPcieIntxCallback(instance_p, INTA) ;
-        FPcieIntxIrqEoi(instance_p, 2) ;
-        break;
-    case FT_PCI_INTD_IRQ_NUM:
-        FPcieIntxCallback(instance_p, INTA) ;
-        FPcieIntxIrqEoi(instance_p, 3) ;
-        break;
-    default:
-        break;
+        case FPCI_INTA_IRQ_NUM:     //如果响应的是INTA中断，则调用pcie_obj中INTA的中断处理函数
+            FPcieIntxCallback(instance_p, INTA) ;
+            FPcieIntxIrqEoi(instance_p, 0) ;
+            break;
+        case FPCI_INTB_IRQ_NUM:
+            FPcieIntxCallback(instance_p, INTA) ;
+            FPcieIntxIrqEoi(instance_p, 1) ;
+            break;
+        case FPCI_INTC_IRQ_NUM:
+            FPcieIntxCallback(instance_p, INTA) ;
+            FPcieIntxIrqEoi(instance_p, 2) ;
+            break;
+        case FPCI_INTD_IRQ_NUM:
+            FPcieIntxCallback(instance_p, INTA) ;
+            FPcieIntxIrqEoi(instance_p, 3) ;
+            break;
+        default:
+            break;
     }
 }
-
-
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.h b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.h
similarity index 82%
rename from bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.h
rename to bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.h
index d2dcbc397cf..413d2dd8396 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcir_intx.h
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_intr.h
@@ -11,19 +11,20 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: fpcir_intx.h
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:47
- * Description:  This files is for
+ * FilePath: fpcie_intr.h
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:47
+ * Description: This file is for pcie interrupt handler definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 
-#ifndef DIRVERS_PCIE_FPCIE_FPCIE_INTX_H
-#define DIRVERS_PCIE_FPCIE_FPCIE_INTX_H
+#ifndef FPCIE_INTR_H
+#define FPCIE_INTR_H
 
 /************************** Constant Definitions *****************************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_misc.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_misc.c
index 77340b588a5..cea658c0fd2 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_misc.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_misc.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: fpcie_misc.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:17
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:17
+ * Description: This file is for pcie miscellaneous interrupt operation. 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
 
@@ -43,8 +44,6 @@
 #define FPCIE_INTR_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(FPCIE_INTR_DEBUG_TAG, format, ##__VA_ARGS__)
 /************************** Function Prototypes ******************************/
 
-
-
 FError FPcieMiscSetHandler(FPcie *instance_p, u32 handler_type,
                            void *func_pointer, void *call_back_ref)
 {
@@ -55,29 +54,29 @@ FError FPcieMiscSetHandler(FPcie *instance_p, u32 handler_type,
 
     switch (handler_type)
     {
-    case FPCIE_HANDLER_DMASEND:
-        status = FT_SUCCESS;
-        instance_p->fpcie_dma_tx_cb = ((FPcieIrqCallBack)(void *)func_pointer);
-        instance_p->dma_tx_args = call_back_ref;
-        break;
-    case FPCIE_HANDLER_DMARECV:
-        status = FT_SUCCESS;
-        instance_p->fpcie_dma_rx_cb = ((FPcieIrqCallBack)(void *)func_pointer);
-        instance_p->dma_rx_args = call_back_ref;
-        break;
-    case FPCIE_HANDLER_DMASEND_ERROR:
-        status = FT_SUCCESS;
-        instance_p->fpcie_dma_tx_error_cb = ((FPcieIrqCallBack)(void *)func_pointer);
-        instance_p->dma_tx_error_args = call_back_ref;
-        break;
-    case FPCIE_HANDLER_DMARECV_ERROR:
-        status = FT_SUCCESS;
-        instance_p->fpcie_dma_rx_error_cb = ((FPcieIrqCallBack)(void *)func_pointer);
-        instance_p->dma_rx_error_args = call_back_ref;
-        break;
-    default:
-        status = FPCIE_ERR_INVALID_PARAM;
-        break;
+        case FPCIE_HANDLER_DMASEND:
+            status = FT_SUCCESS;
+            instance_p->fpcie_dma_tx_cb = ((FPcieIrqCallBack)(void *)func_pointer);
+            instance_p->dma_tx_args = call_back_ref;
+            break;
+        case FPCIE_HANDLER_DMARECV:
+            status = FT_SUCCESS;
+            instance_p->fpcie_dma_rx_cb = ((FPcieIrqCallBack)(void *)func_pointer);
+            instance_p->dma_rx_args = call_back_ref;
+            break;
+        case FPCIE_HANDLER_DMASEND_ERROR:
+            status = FT_SUCCESS;
+            instance_p->fpcie_dma_tx_error_cb = ((FPcieIrqCallBack)(void *)func_pointer);
+            instance_p->dma_tx_error_args = call_back_ref;
+            break;
+        case FPCIE_HANDLER_DMARECV_ERROR:
+            status = FT_SUCCESS;
+            instance_p->fpcie_dma_rx_error_cb = ((FPcieIrqCallBack)(void *)func_pointer);
+            instance_p->dma_rx_error_args = call_back_ref;
+            break;
+        default:
+            status = FPCIE_ERR_INVALID_PARAM;
+            break;
     }
     return status;
 }
@@ -121,8 +120,8 @@ void FPcieMiscIrq(s32 vector, void *args)
         control_address = instance_p->config.control_c5_address;
     }
 
-    FPCIE_INTR_DEBUG_I("pcie misc irq!");
-    FPCIE_INTR_DEBUG_I("pcie dma irq status : 0x%08lx", FPCIE_READREG(control_address, FPCIE_REG_DMA_INT_STATUS_OFFSET));
+    FPCIE_INTR_DEBUG_I("Pcie misc irq!");
+    FPCIE_INTR_DEBUG_I("Pcie dma irq status : 0x%08lx", FPCIE_READREG(control_address, FPCIE_REG_DMA_INT_STATUS_OFFSET));
 
     reg_value = FPCIE_READREG(control_address, FPCIE_REG_DMA_INT_STATUS_OFFSET);
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_sinit.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_sinit.c
index f972582888d..102f1e0d129 100644
--- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie_sinit.c
@@ -12,20 +12,20 @@
  *
  *
  * FilePath: fpcie_sinit.c
- * Date: 2022-02-10 14:55:11
- * LastEditTime: 2022-02-18 08:59:22
- * Description:  This files is for
+ * Date: 2022-08-10 14:55:11
+ * LastEditTime: 2022-08-18 08:59:22
+ * Description: This file is for pcie static variables implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe  2022/8/18   init commit
  */
 
-
 #include "fpcie.h"
 #include "fparameters.h"
 
-extern FPcieConfig FPcieConfigTable[FT_PCIE_NUM];
+extern FPcieConfig FPcieConfigTable[FPCIE_NUM];
 
 
 FPcieConfig *FPcieLookupConfig(u32 instance_id)
@@ -33,7 +33,7 @@ FPcieConfig *FPcieLookupConfig(u32 instance_id)
     FPcieConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FT_PCIE_NUM; index++)
+    for (index = 0; index < (u32)FPCIE_NUM; index++)
     {
         if (FPcieConfigTable[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/Kconfig b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/Kconfig
index 0d8106298ff..02c30d70d60 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/Kconfig
@@ -3,5 +3,5 @@ config ENABLE_FGPIO
     bool
     prompt "Use FGPIO"
     default n
-
-
+    
+    
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c
index 37b5eab09ce..5bb2edbdcae 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c
@@ -19,7 +19,8 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
@@ -59,7 +60,7 @@ FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config
 
     if (0 == config->base_addr)
     {
-        FGPIO_ERROR("invalid base address !!!");
+        FGPIO_ERROR("Invalid base address !!!");
         return FGPIO_ERR_INVALID_PARA;
     }
 
@@ -68,6 +69,9 @@ FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config
         instance->config = *config;
     }
 
+    /* mask interrupt for all pins */
+    FGpioWriteReg32(instance->config.base_addr, FGPIO_INTMASK_OFFSET, FGPIO_INTR_PORTA_MASKALL);
+
     instance->is_ready = FT_COMPONENT_IS_READY;
     return FGPIO_SUCCESS;
 }
@@ -113,12 +117,12 @@ FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin_instance,
                           const FGpioPinId index)
 {
     FASSERT(instance && pin_instance);
-    FASSERT_MSG(index.port < FGPIO_PORT_NUM, "invalid gpio port %d", index);
-    FASSERT_MSG(index.pin < FGPIO_PIN_NUM, "invalid gpio pin %d", index);
+    FASSERT_MSG(index.port < FGPIO_PORT_NUM, "Invalid gpio port %d", index);
+    FASSERT_MSG(index.pin < FGPIO_PIN_NUM, "Invalid gpio pin %d", index);
 
     if (FT_COMPONENT_IS_READY != instance->is_ready)
     {
-        FGPIO_ERROR("gpio instance not yet init !!!");
+        FGPIO_ERROR("gpio instance is not yet inited !!!");
         return FGPIO_ERR_NOT_INIT;
     }
 
@@ -151,14 +155,16 @@ void FGpioPinDeInitialize(FGpioPin *const pin)
     FGpio *const instance = pin->instance;
 
     if ((NULL == instance) || (FT_COMPONENT_IS_READY != instance->is_ready) ||
-            (FT_COMPONENT_IS_READY != pin->is_ready))
+        (FT_COMPONENT_IS_READY != pin->is_ready))
     {
-        FGPIO_ERROR("gpio instance not yet init !!!");
+        FGPIO_ERROR("gpio instance is not yet inited !!!");
         return;
     }
 
     if (FGPIO_DIR_INPUT == FGpioGetDirection(pin))
-        FGpioSetInterruptMask(pin, FALSE); /* 关闭引脚中断 */
+    {
+        FGpioSetInterruptMask(pin, FALSE);    /* 关闭引脚中断 */
+    }
 
     FGpioPinId index = pin->index;
     FASSERT_MSG(instance->pins[index.port][index.pin] == pin, "invalid pin instance");
@@ -269,7 +275,7 @@ void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir)
     FASSERT(pin);
     FGpio *const instance = pin->instance;
     FASSERT(instance);
-    FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not yet init !!!");
+    FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!");
     u32 reg_val;
     FGpioPinId index = pin->index;
     uintptr base_addr = instance->config.base_addr;
@@ -384,7 +390,7 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output)
     FASSERT(pin);
     FGpio *const instance = pin->instance;
     FASSERT(instance);
-    FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not yet init !!!");
+    FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance is not yet inited !!!");
 
     FGpioPinId index = pin->index;
     u32 base_addr = instance->config.base_addr;
@@ -392,7 +398,7 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output)
 
     if (FGPIO_DIR_OUTPUT != FGpioGetDirection(pin))
     {
-        FGPIO_ERROR("need to set GPIO direction as OUTPUT first !!!");
+        FGPIO_ERROR("Need to set GPIO direction as OUTPUT first !!!");
         return FGPIO_ERR_INVALID_STATE;
     }
 
@@ -411,9 +417,9 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output)
         FASSERT(0);
     }
 
-    FGPIO_INFO("output val 0x%x", reg_val);
+    FGPIO_INFO("Output val 0x%x", reg_val);
     FGpioWriteRegVal(base_addr, index.port, reg_val);
-    FGPIO_INFO("output val 0x%x", FGpioReadRegVal(base_addr, index.port));
+    FGPIO_INFO("Output val 0x%x", FGpioReadRegVal(base_addr, index.port));
     return FGPIO_SUCCESS;
 }
 
@@ -436,7 +442,7 @@ FGpioPinVal FGpioGetInputValue(FGpioPin *const pin)
 
     if (FGPIO_DIR_INPUT != FGpioGetDirection(pin))
     {
-        FGPIO_ERROR("need to set GPIO direction as INPUT first !!!");
+        FGPIO_ERROR("Need to set GPIO direction as INPUT first !!!");
         return FGPIO_PIN_LOW;
     }
 
@@ -455,6 +461,6 @@ FGpioPinVal FGpioGetInputValue(FGpioPin *const pin)
         FASSERT(0);
     }
 
-    FGPIO_INFO("input val: 0x%x", reg_val);
+    FGPIO_INFO("Input val: 0x%x.", reg_val);
     return (BIT(index.pin) & reg_val) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h
index f41f80aaf2f..8d190b70085 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h
@@ -19,24 +19,25 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
-#ifndef  DRIVERS_FGPIO_H
-#define  DRIVERS_FGPIO_H
+#ifndef  FGPIO_H
+#define  FGPIO_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-/***************************** Include Files *********************************/
+#include "fparameters.h"
 #include "ftypes.h"
 #include "fassert.h"
 #include "ferror_code.h"
 #include "sdkconfig.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 #define FGPIO_SUCCESS            FT_SUCCESS
 #define FGPIO_ERR_INVALID_PARA   FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x0)
@@ -48,6 +49,8 @@ extern "C"
 #define FGPIO_VERSION_1 /* 用于FT2000/4和D2000平台的GPIO 0 ~ 1 */
 #elif defined(CONFIG_TARGET_E2000)
 #define FGPIO_VERSION_2 /* 用于E2000平台的GPIO 3 ~ 5 */
+#elif defined(TARDIGRADE)
+
 #else
 #error "Invalid target board !!!"
 #endif
@@ -72,7 +75,7 @@ typedef enum
     FGPIO_PIN_5,
     FGPIO_PIN_6,
     FGPIO_PIN_7,
-#if defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
+#if defined(FGPIO_VERSION_2) || defined(TARDIGRADE)/* E2000 GPIO 0 ~ 5 */
     FGPIO_PIN_8,
     FGPIO_PIN_9,
     FGPIO_PIN_10,
@@ -130,10 +133,10 @@ typedef struct
 {
     u32 instance_id; /* GPIO实例ID */
     uintptr base_addr; /* GPIO控制器基地址 */
-#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+#if defined(FGPIO_VERSION_1) || defined(TARDIGRADE)  /* FT2000-4, D2000 */
     u32 irq_num; /* GPIO控制器中断号 */
 #elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
-    u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号 */
+    u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号，如果是控制器中断，则数组所有值一致 */
 #endif
     u32 irq_priority; /* 中断优先级 */
 } FGpioConfig; /* GPIO控制器配置 */
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_g.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_g.c
index 1c41a6665db..0b05494f9b1 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_g.c
@@ -19,7 +19,8 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
@@ -43,59 +44,92 @@
 #if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
 const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
 {
-    [FGPIO_ID_0] =
+    [FGPIO0_ID] =
     {
-        .instance_id = FGPIO_ID_0,
-        .base_addr = FGPIO_0_BASE_ADDR,
-        .irq_num = FGPIO_0_IRQ_NUM,
+        .instance_id = FGPIO0_ID,
+        .base_addr = FGPIO0_BASE_ADDR,
+        .irq_num = FGPIO0_IRQ_NUM,
         .irq_priority = 0
     },
-    [FGPIO_ID_1] =
+    [FGPIO1_ID] =
     {
-        .instance_id = FGPIO_ID_1,
-        .base_addr = FGPIO_1_BASE_ADDR,
-        .irq_num = FGPIO_1_IRQ_NUM,
+        .instance_id = FGPIO1_ID,
+        .base_addr = FGPIO1_BASE_ADDR,
+        .irq_num = FGPIO1_IRQ_NUM,
         .irq_priority = 0
     }
 };
 #elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
 FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
 {
-    [FGPIO_ID_0] =
+    [FGPIO0_ID] =
     {
-        .instance_id = FGPIO_ID_0,
-        .base_addr = FGPIO_0_BASE_ADDR,
+        .instance_id = FGPIO0_ID,
+        .base_addr = FGPIO0_BASE_ADDR,
         .irq_priority = 0
     },
-    [FGPIO_ID_1] =
+    [FGPIO1_ID] =
     {
-        .instance_id = FGPIO_ID_1,
-        .base_addr = FGPIO_1_BASE_ADDR,
+        .instance_id = FGPIO1_ID,
+        .base_addr = FGPIO1_BASE_ADDR,
         .irq_priority = 0
     },
-    [FGPIO_ID_2] =
+    [FGPIO2_ID] =
     {
-        .instance_id = FGPIO_ID_2,
-        .base_addr = FGPIO_2_BASE_ADDR,
+        .instance_id = FGPIO2_ID,
+        .base_addr = FGPIO2_BASE_ADDR,
         .irq_priority = 0
     },
-    [FGPIO_ID_3] =
+    [FGPIO3_ID] =
     {
-        .instance_id = FGPIO_ID_3,
-        .base_addr = FGPIO_3_BASE_ADDR,
+        .instance_id = FGPIO3_ID,
+        .base_addr = FGPIO3_BASE_ADDR,
         .irq_priority = 0
     },
-    [FGPIO_ID_4] =
+    [FGPIO4_ID] =
     {
-        .instance_id = FGPIO_ID_4,
-        .base_addr = FGPIO_4_BASE_ADDR,
+        .instance_id = FGPIO4_ID,
+        .base_addr = FGPIO4_BASE_ADDR,
         .irq_priority = 0
     },
-    [FGPIO_ID_5] =
+    [FGPIO5_ID] =
     {
-        .instance_id = FGPIO_ID_5,
-        .base_addr = FGPIO_5_BASE_ADDR,
+        .instance_id = FGPIO5_ID,
+        .base_addr = FGPIO5_BASE_ADDR,
         .irq_priority = 0
     },
 };
+#elif defined(TARDIGRADE) /* TARDIGRADE */
+const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
+{
+    [FGPIO0_ID] =
+    {
+        .instance_id = FGPIO0_ID,
+        .base_addr = FGPIO0_BASE_ADDR,
+        .irq_num = FGPIO0_IRQ_NUM,
+        .irq_priority = 0
+    },
+    [FGPIO1_ID] =
+    {
+        .instance_id = FGPIO1_ID,
+        .base_addr = FGPIO1_BASE_ADDR,
+        .irq_num = FGPIO1_IRQ_NUM,
+        .irq_priority = 0
+    },
+    [FGPIO2_ID] =
+    {
+        .instance_id = FGPIO2_ID,
+        .base_addr = FGPIO2_BASE_ADDR,
+        .irq_num = FGPIO2_IRQ_NUM,
+        .irq_priority = 0
+    },
+    [FGPIO3_ID] =
+    {
+        .instance_id = FGPIO3_ID,
+        .base_addr = FGPIO3_BASE_ADDR,
+        .irq_num = FGPIO3_IRQ_NUM,
+        .irq_priority = 0
+    }
+
+};
 #endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_hw.h b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_hw.h
index 9acad53bf0a..150e04ab8aa 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_hw.h
@@ -19,22 +19,26 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
-#ifndef  DRIVERS_FGPIO_HW_H
-#define  DRIVERS_FGPIO_HW_H
+#ifndef  FGPIO_HW_H
+#define  FGPIO_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#include "fio.h"
+#include "fkernel.h"
 
 /***************************** Include Files *********************************/
 #include "fio.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 /** @name Register Map
  *
@@ -101,6 +105,7 @@ extern "C"
 /** @name FGPIO_INTMASK_OFFSET Register
  */
 #define FGPIO_INTR_PORTA_MASK(n)          BIT(n) /* 1: disable the intr of n-th port in group-a */
+#define FGPIO_INTR_PORTA_MASKALL          GENMASK(15, 0)
 
 /** @name FGPIO_INTTYPE_LEVEL_OFFSET Register
  */
@@ -152,9 +157,13 @@ static inline void FGpioWriteReg32(uintptr base_addr, uintptr reg_off, const u32
 static inline void FGpioSetBit32(uintptr base_addr, uintptr reg_off, u32 bit)
 {
     if (0 == bit)
+    {
         FtClearBit32(base_addr + reg_off, bit);
+    }
     else if (1 == bit)
+    {
         FtSetBit32(base_addr + reg_off, bit);
+    }
 }
 
 /************************** Function Prototypes ******************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_intr.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_intr.c
index b453ecdb7e5..a4fc9bf2eca 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_intr.c
@@ -19,7 +19,8 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
@@ -121,6 +122,7 @@ void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable)
 
     FGpioWriteReg32(base_addr, FGPIO_INTMASK_OFFSET, mask_bits);
     FGpioWriteReg32(base_addr, FGPIO_INTEN_OFFSET, enable_bits);
+
     return;
 }
 
@@ -183,24 +185,24 @@ void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type)
 
     switch (type)
     {
-    case FGPIO_IRQ_TYPE_EDGE_FALLING:
-        level |= BIT(index.pin); /* 边沿敏感型 */
-        polarity &= ~BIT(index.pin); /* 下降沿或低电平 */
-        break;
-    case FGPIO_IRQ_TYPE_EDGE_RISING:
-        level |= BIT(index.pin); /* 边沿敏感型 */
-        polarity |= BIT(index.pin); /* 上升沿或高电平 */
-        break;
-    case FGPIO_IRQ_TYPE_LEVEL_LOW:
-        level &= ~BIT(index.pin); /* 电平敏感型 */
-        polarity &= ~BIT(index.pin); /* 下降沿或低电平 */
-        break;
-    case FGPIO_IRQ_TYPE_LEVEL_HIGH:
-        level &= ~BIT(index.pin); /* 电平敏感型 */
-        polarity |= BIT(index.pin); /* 上升沿或高电平 */
-        break;
-    default:
-        break;
+        case FGPIO_IRQ_TYPE_EDGE_FALLING:
+            level |= BIT(index.pin); /* 边沿敏感型 */
+            polarity &= ~BIT(index.pin); /* 下降沿或低电平 */
+            break;
+        case FGPIO_IRQ_TYPE_EDGE_RISING:
+            level |= BIT(index.pin); /* 边沿敏感型 */
+            polarity |= BIT(index.pin); /* 上升沿或高电平 */
+            break;
+        case FGPIO_IRQ_TYPE_LEVEL_LOW:
+            level &= ~BIT(index.pin); /* 电平敏感型 */
+            polarity &= ~BIT(index.pin); /* 下降沿或低电平 */
+            break;
+        case FGPIO_IRQ_TYPE_LEVEL_HIGH:
+            level &= ~BIT(index.pin); /* 电平敏感型 */
+            polarity |= BIT(index.pin); /* 上升沿或高电平 */
+            break;
+        default:
+            break;
     }
 
     FGpioWriteReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET, level);
@@ -228,17 +230,19 @@ void FGpioInterruptHandler(s32 vector, void *param)
     u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET);
 
 #if defined(FGPIO_VERSION_2) /* E2000 gpio 3 ~ 5 */
-    FASSERT_MSG(FGPIO_WITH_PIN_IRQ < instance->config.instance_id, "handle interrupt through pin !!!")
+    FASSERT_MSG(FGPIO_WITH_PIN_IRQ < instance->config.instance_id, "Handle interrupt through pin !!!")
 #endif
 
-    FGPIO_INFO("status: 0x%x, raw_status: 0x%x", status, raw_status);
+    FGPIO_INFO("status: 0x%x, raw_status: 0x%x.", status, raw_status);
     for (loop = FGPIO_PIN_0; loop < FGPIO_PIN_NUM; loop++)
     {
         if (status & BIT(loop))
         {
             pin = instance->pins[FGPIO_PORT_A][loop];
             if (NULL == pin)
+            {
                 continue;
+            }
 
             if (pin->irq_cb)
             {
@@ -252,7 +256,7 @@ void FGpioInterruptHandler(s32 vector, void *param)
             }
             else
             {
-                FGPIO_WARN("no irq handler callback for GPIO-%d-A-%d",
+                FGPIO_WARN("No irq handler callback for GPIO-%d-A-%d.",
                            instance->config.instance_id,
                            loop);
             }
@@ -283,7 +287,7 @@ void FGpioPinInterruptHandler(s32 vector, void *param)
     u32 status = FGpioReadReg32(base_addr, FGPIO_INTSTATUS_OFFSET);
     u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET);
 
-    FGPIO_INFO("status: 0x%x, raw_status: 0x%x", status, raw_status);
+    FGPIO_INFO("status: 0x%x, raw_status: 0x%x.", status, raw_status);
     if (pin->irq_cb)
     {
         pin->irq_cb(0U, pin->irq_cb_params);
@@ -296,7 +300,7 @@ void FGpioPinInterruptHandler(s32 vector, void *param)
     }
     else
     {
-        FGPIO_WARN("no irq handler callback for GPIO-%d-A-%d",
+        FGPIO_WARN("No irq handler callback for GPIO-%d-A-%d.",
                    pin->index.ctrl,
                    pin->index.pin);
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_selftest.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_selftest.c
index 8cc5ed81e00..b8ebdf2518e 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_selftest.c
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_selftest.c
@@ -14,11 +14,13 @@
  * FilePath: fgpio_selftest.c
  * Date: 2022-06-17 14:32:12
  * LastEditTime: 2022-06-17 14:32:12
- * Description:  This files is for
+ * Description:  This files is for dumping gpio register info 
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 /***************************** Include Files *********************************/
 #include "fdebug.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_sinit.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_sinit.c
index 27008990023..dff107acc01 100644
--- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio_sinit.c
@@ -14,12 +14,13 @@
  * FilePath: fgpio_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 08:25:29
- * Description:  This files is for GPIO static variables
+ * Description:  This files is for GPIO static variables implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2022-3-1     init commit
+ * 1.0   zhugengyu  2022/3/1     init commit
+ * 2.0   zhugengyu  2022/7/1     support e2000
  */
 
 
@@ -38,15 +39,15 @@
 /************************** Function Prototypes ******************************/
 
 /************************** Variable Definitions *****************************/
-#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
-    extern const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
+#if defined(FGPIO_VERSION_1)|| defined(TARDIGRADE) /* FT2000-4, D2000 */
+extern const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
 #elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */
-    extern FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
+extern FGpioConfig fgpio_cfg_tbl[FGPIO_NUM];
 #endif
 
 /*****************************************************************************/
 
-#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */
+#if defined(FGPIO_VERSION_1) || defined(TARDIGRADE) /* FT2000-4, D2000 */
 /**
  * @name: FGpioLookupConfig
  * @msg: 获取GPIO控制器的默认配置
@@ -92,15 +93,15 @@ static void FGpioSetIrqNum(u32 instance_id, FGpioConfig *ptr)
     }
     else
     {
-        if (FGPIO_ID_3 == instance_id)
+        if (FGPIO3_ID == instance_id)
         {
             irq_num = FGPIO_3_IRQ_NUM;
         }
-        else if (FGPIO_4_IRQ_NUM == instance_id)
+        else if (FGPIO4_ID == instance_id)
         {
             irq_num = FGPIO_4_IRQ_NUM;
         }
-        else if (FGPIO_5_IRQ_NUM == instance_id)
+        else if (FGPIO5_ID == instance_id)
         {
             irq_num = FGPIO_5_IRQ_NUM;
         }
@@ -147,4 +148,5 @@ const FGpioConfig *FGpioLookupConfig(u32 instance_id)
 
     return ptr;
 }
+
 #endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/Kconfig b/bsp/phytium/libraries/standalone/drivers/pwm/Kconfig
index 992039d544c..5a6185cf4e7 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/Kconfig
@@ -3,7 +3,7 @@ menu "FPWM Configuration"
         bool
         prompt "Use FPWM"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.c b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.c
index 7c1dace19e1..4d2022b53c0 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.c
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.c
@@ -13,13 +13,15 @@
  *
  * FilePath: fpwm.c
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * LastEditTime: 2022-04-15 11:45:05
+ * Description:  This file is for the minimum required function implementations for this driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
+
 #include <string.h>
 #include "fkernel.h"
 #include "ftypes.h"
@@ -65,7 +67,7 @@ FError FPwmReset(FPwmCtrl *pctrl, u32 channel)
 
     if (0 >= timeout)
     {
-        FPWM_ERROR("timeout when wait pwm reset complete");
+        FPWM_ERROR("Time out while waiting for pwm reset to complete");
         return FPWM_ERR_TIMEOUT;
     }
     return FPWM_SUCCESS;
@@ -136,16 +138,16 @@ static void FPwmTimCtrlModeSet(FPwmCtrl *pctrl, u32 channel, FPwmTimCtrlMode mod
 
     switch (mode)
     {
-    /* modulo */
-    case FPWM_MODULO:
-        reg_val &= (~FPWM_TIM_CTRL_MODE_UD);
-        break;
-    /* up-and-down */
-    case FPWM_UP_DOWN:
-        reg_val |= FPWM_TIM_CTRL_MODE_UD;
-        break;
-    default:
-        break;
+        /* modulo */
+        case FPWM_MODULO:
+            reg_val &= (~FPWM_TIM_CTRL_MODE_UD);
+            break;
+        /* up-and-down */
+        case FPWM_UP_DOWN:
+            reg_val |= FPWM_TIM_CTRL_MODE_UD;
+            break;
+        default:
+            break;
     }
 
     FPWM_WRITE_REG32(base_addr, FPWM_TIM_CTRL_OFFSET, reg_val);
@@ -251,16 +253,16 @@ static void FPwmDutySourceSet(FPwmCtrl *pctrl, u32 channel, FPwmDutySourceMode d
     reg_val = FPWM_READ_REG32(base_addr, FPWM_CTRL_OFFSET);
     switch (duty_source)
     {
-    /* duty from PWM_CCR */
-    case FPWM_DUTY_CCR:
-        reg_val &= (~FPWM_CTRL_DUTY_SOURCE_FIFO);
-        break;
-    /* from FIFO */
-    case FPWM_DUTY_FIFO:
-        reg_val |= FPWM_CTRL_DUTY_SOURCE_FIFO;
-        break;
-    default:
-        break;
+        /* duty from PWM_CCR */
+        case FPWM_DUTY_CCR:
+            reg_val &= (~FPWM_CTRL_DUTY_SOURCE_FIFO);
+            break;
+        /* from FIFO */
+        case FPWM_DUTY_FIFO:
+            reg_val |= FPWM_CTRL_DUTY_SOURCE_FIFO;
+            break;
+        default:
+            break;
     }
 
     FPWM_WRITE_REG32(base_addr, FPWM_CTRL_OFFSET, reg_val);
@@ -289,7 +291,7 @@ FError FPwmPulseSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_ccr)
     pwm_period_ccr = (u16)FPWM_READ_REG32(base_addr, FPWM_PERIOD_OFFSET);
     if (pwm_ccr > pwm_period_ccr)
     {
-        FPWM_ERROR("pwm ccr is bigger than period");
+        FPWM_ERROR("The pwm ccr is larger than the period");
         return FPWM_ERR_INVAL_PARM;
     }
 
@@ -302,7 +304,7 @@ FError FPwmPulseSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_ccr)
         state = FPWM_READ_REG32(base_addr, FPWM_STATE_OFFSET);
         if (state & FPWM_STATE_FIFO_FULL)
         {
-            FPWM_ERROR("pwm state fifo full");
+            FPWM_ERROR("The fifo of the pwm is full");
             return FPWM_ERR_CMD_FAILED;
         }
     }
@@ -386,7 +388,7 @@ static FError FPwmDbReset(FPwmCtrl *pctrl)
 
     if (0 >= timeout)
     {
-        FPWM_ERROR("timeout when wait pwm db reset complete");
+        FPWM_ERROR("Time out while waiting for pwm db reset to complete");
         return FPWM_ERR_TIMEOUT;
     }
     return FPWM_SUCCESS;
@@ -476,14 +478,14 @@ static void FPwmDbInModeSet(FPwmCtrl *pctrl, FPwmDbInMode db_in_mode)
     reg_val = FPWM_READ_REG32(base_addr, FPWM_DB_CTRL_OFFSET);
     switch (db_in_mode)
     {
-    case FPWM_DB_IN_MODE_PWM0:
-        reg_val &= (~FPWM_DB_CTRL_IN_MODE);
-        break;
-    case FPWM_DB_IN_MODE_PWM1:
-        reg_val |= FPWM_DB_CTRL_IN_MODE;
-        break;
-    default:
-        break;
+        case FPWM_DB_IN_MODE_PWM0:
+            reg_val &= (~FPWM_DB_CTRL_IN_MODE);
+            break;
+        case FPWM_DB_IN_MODE_PWM1:
+            reg_val |= FPWM_DB_CTRL_IN_MODE;
+            break;
+        default:
+            break;
     }
 
     FPWM_WRITE_REG32(base_addr, FPWM_DB_CTRL_OFFSET, reg_val);
@@ -581,7 +583,7 @@ FError FPwmDbVariableSet(FPwmCtrl *pctrl, FPwmDbVariableConfig *db_cfg_p)
     ret = FPwmDbReset(pctrl);
     if (ret != FPWM_SUCCESS)
     {
-        FPWM_ERROR("FPwmDbVariableSet FPwmDbReset failed");
+        FPWM_ERROR("%s ,The FPwmDbReset call failed",__func__);
         return FPWM_ERR_CMD_FAILED;
     }
 
@@ -592,7 +594,7 @@ FError FPwmDbVariableSet(FPwmCtrl *pctrl, FPwmDbVariableConfig *db_cfg_p)
     ret = FPwmDbPolaritySet(pctrl, db_cfg_p->db_polarity_sel);
     if (ret != FPWM_SUCCESS)
     {
-        FPWM_ERROR("FPwmDbVariableSet FPwmDbPolaritySet failed");
+        FPWM_ERROR("%s ,The FPwmDbPolaritySet call failed",__func__);
         return FPWM_ERR_CMD_FAILED;
     }
 
@@ -654,14 +656,15 @@ FError FPwmVariableSet(FPwmCtrl *pctrl, u32 channel, FPwmVariableConfig *pwm_cfg
     FASSERT(pwm_cfg_p != NULL);
     FError ret = FPWM_SUCCESS;
 
+#if defined(FLSD_CONFIG_BASE)
     /* enable lsd pwm syn */
     FPwmLsdEnable(FLSD_CONFIG_BASE, pctrl->config.instance_id);
-
+#endif
     /* bit[0]:set pwm_tim_ctrl SW_RST */
     ret = FPwmReset(pctrl, channel);
     if (ret != FPWM_SUCCESS)
     {
-        FPWM_ERROR("FPwmVariableSet FPwmReset failed");
+        FPWM_ERROR("%s ,FPwmReset  call failed",__func__);
         return FPWM_ERR_CMD_FAILED;
     }
 
@@ -697,7 +700,7 @@ FError FPwmVariableSet(FPwmCtrl *pctrl, u32 channel, FPwmVariableConfig *pwm_cfg
     ret = FPwmPulseSet(pctrl, channel, pwm_cfg_p->pwm_pulse);
     if (ret != FPWM_SUCCESS)
     {
-        FPWM_ERROR("FPwmVariableSet FPwmPulseSet failed");
+        FPWM_ERROR("%s , FPwmPulseSet failed",__func__);
         return FPWM_ERR_CMD_FAILED;
     }
 
@@ -787,22 +790,45 @@ FError FPwmCfgInitialize(FPwmCtrl *pctrl, const FPwmConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == pctrl->is_ready)
     {
-        FPWM_WARN("device is already initialized!!!");
+        FPWM_WARN("The device has been initialized!!!");
     }
 
     /*Set default values and configuration data */
     FPwmDeInitialize(pctrl);
 
     pctrl->config = *input_config_p;
-
+#if defined(CONFIG_TARGET_E2000) 
     ret = FPwmDbReset(pctrl);
     if (ret != FPWM_SUCCESS)
     {
-        FPWM_ERROR("FPwmDbVariableSet FPwmDbReset failed");
+        FPWM_ERROR("%s ,The FPwmDbReset call failed");
         return FPWM_ERR_CMD_FAILED;
     }
-
+#endif
     pctrl->is_ready = FT_COMPONENT_IS_READY;
 
     return ret;
 }
+
+/**
+ * @name: FPwmGpioSet
+ * @msg:  Control gpio output
+ * @param {FPwmCtrl} *pctrl, instance of FPWM controller
+ * @param {u32} channel, pwm module's channel, 0/1
+ * @param {u32} output, set high or low level, 0-low, 1-high
+ * @return void
+ */
+void FPwmGpioSet(FPwmCtrl *pctrl, u32 channel, u32 output)
+{
+    FASSERT(pctrl != NULL);
+    u32 reg_val = 0;
+    uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
+
+    reg_val = FPWM_READ_REG32(base_addr, FPWM_CCR_OFFSET);
+    if(output)
+	    reg_val |= FPWM_CCR_GPIO;
+    else
+        reg_val &= (~FPWM_CCR_GPIO);        
+	FPWM_WRITE_REG32(base_addr, FPWM_CCR_OFFSET, reg_val);
+    
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.h b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.h
index 80e62ae8960..7a7ca6e9c7e 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.h
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm.h
@@ -13,21 +13,17 @@
  *
  * FilePath: fpwm.h
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * LastEditTime: 2022-04-15 11:45:05
+ * Description: This file is for detailed description of the device configuration and driver.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
-#ifndef BSP_DRIVERS_FPWM_H
-#define BSP_DRIVERS_FPWM_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FPWM_H
+#define FPWM_H
 
 #include "ftypes.h"
 #include "fdebug.h"
@@ -36,6 +32,11 @@ extern "C"
 #include "fassert.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 #define FPWM_SUCCESS          FT_SUCCESS
 #define FPWM_ERR_INVAL_PARM   FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 1)
 #define FPWM_ERR_NOT_READY    FT_MAKE_ERRCODE(ErrModBsp, ErrBspPwm, 2)
@@ -181,7 +182,7 @@ void FPwmIntrHandler(s32 vector, void *args);
 void FPwmRegisterInterruptHandler(FPwmCtrl *instance_p, FPwmIntrEventType event_type, FPwmIntrEventHandler handler, void *param);
 
 /* get pwm configs by id */
-const FPwmConfig *FPwmLookupConfig(FPwmInstance instance_id);
+const FPwmConfig *FPwmLookupConfig(u32 instance_id);
 
 /* DeInitialization function for the device instance */
 void FPwmDeInitialize(FPwmCtrl *pctrl);
@@ -213,6 +214,9 @@ void FPwmEnable(FPwmCtrl *pctrl, u32 channel);
 /* dump some pwm registers value */
 void FPwmDump(uintptr base_addr);
 
+/* control gpio output */
+void FPwmGpioSet(FPwmCtrl *pctrl, u32 channel, u32 output);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_g.c b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_g.c
index b1bcc554e76..81ba3b2ef39 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_g.c
@@ -13,117 +13,138 @@
  *
  * FilePath: fpwm_g.c
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * LastEditTime: 2022-04-16 11:45:05
+ * Description:  This file is for pwm static configuration implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/16   init commit
  */
 
 #include "fparameters.h"
 #include "fpwm.h"
 #include "fpwm_hw.h"
+#include "sdkconfig.h"
 
+#if defined(CONFIG_TARGET_E2000) 
 /* default configs of pwm ctrl */
-const FPwmConfig FPwmConfigTbl[FPWM_INSTANCE_NUM] =
+const FPwmConfig FPwmConfigTbl[FPWM_NUM] =
 {
-    [FPWM_INSTANCE_0] =
+    [FPWM0_ID] =
     {
-        .instance_id = FPWM_INSTANCE_0,
+        .instance_id = FPWM0_ID,
         .db_base_addr = FPWM0_BASE_ADR,
         .pwm_base_addr = FPWM0_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM0_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM1_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM0_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM1_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL0",
     },
-    [FPWM_INSTANCE_1] =
+    [FPWM1_ID] =
     {
-        .instance_id = FPWM_INSTANCE_1,
+        .instance_id = FPWM1_ID,
         .db_base_addr = FPWM1_BASE_ADR,
         .pwm_base_addr = FPWM1_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM2_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM3_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM2_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM3_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL1",
     },
-    [FPWM_INSTANCE_2] =
+    [FPWM2_ID] =
     {
-        .instance_id = FPWM_INSTANCE_2,
+        .instance_id = FPWM2_ID,
         .db_base_addr = FPWM2_BASE_ADR,
         .pwm_base_addr = FPWM2_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM4_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM5_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM4_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM5_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL2",
     },
-    [FPWM_INSTANCE_3] =
+    [FPWM3_ID] =
     {
-        .instance_id = FPWM_INSTANCE_3,
+        .instance_id = FPWM3_ID,
         .db_base_addr = FPWM3_BASE_ADR,
         .pwm_base_addr = FPWM3_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM6_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM7_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM6_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM7_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL3",
     },
-    [FPWM_INSTANCE_4] =
+    [FPWM4_ID] =
     {
-        .instance_id = FPWM_INSTANCE_4,
+        .instance_id = FPWM4_ID,
         .db_base_addr = FPWM4_BASE_ADR,
         .pwm_base_addr = FPWM4_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM8_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM9_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM8_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM9_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL4",
     },
-    [FPWM_INSTANCE_5] =
+    [FPWM5_ID] =
     {
-        .instance_id = FPWM_INSTANCE_5,
+        .instance_id = FPWM5_ID,
         .db_base_addr = FPWM5_BASE_ADR,
         .pwm_base_addr = FPWM5_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM10_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM11_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM10_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM11_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL5",
     },
-    [FPWM_INSTANCE_6] =
+    [FPWM6_ID] =
     {
-        .instance_id = FPWM_INSTANCE_6,
+        .instance_id = FPWM6_ID,
         .db_base_addr = FPWM6_BASE_ADR,
         .pwm_base_addr = FPWM6_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM12_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM13_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM12_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM13_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL6",
     },
-    [FPWM_INSTANCE_7] =
+    [FPWM7_ID] =
     {
-        .instance_id = FPWM_INSTANCE_7,
+        .instance_id = FPWM7_ID,
         .db_base_addr = FPWM7_BASE_ADR,
         .pwm_base_addr = FPWM7_BASE_ADR + FPWM_OFFSET,
-        .base_clk = FPWM_CLK,
-        .irq_num[FPWM_CHANNEL_0] = FPWM14_INTR_IRQ,
-        .irq_num[FPWM_CHANNEL_1] = FPWM15_INTR_IRQ,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM14_IRQ_NUM,
+        .irq_num[FPWM_CHANNEL_1] = FPWM15_IRQ_NUM,
         .irq_prority[FPWM_CHANNEL_0] = 0,
         .irq_prority[FPWM_CHANNEL_1] = 0,
         .instance_name = "PWM_CTRL7",
     },
 
 
-};
\ No newline at end of file
+};
+
+#elif defined(TARDIGRADE) 
+/* default configs of pwm ctrl */
+const FPwmConfig FPwmConfigTbl[FPWM_NUM] =
+{
+    [FPWM0_ID] = 
+    {
+        .instance_id = FPWM0_ID,
+        .pwm_base_addr = FPWM0_BASE_ADR,
+        .base_clk = FPWM_CLK_FREQ_HZ,
+        .irq_num[FPWM_CHANNEL_0] = FPWM0_IRQ_NUM,
+        .irq_prority[FPWM_CHANNEL_0] = 0,
+        .instance_name = "PWM_CTRL0",
+    },
+
+};
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.c b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.c
index 33bce2b6c1b..4a4449fe182 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.c
@@ -14,11 +14,12 @@
  * FilePath: fpwm_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * Description:  This file is for pwm register implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
 #include <stdio.h>
@@ -35,7 +36,7 @@
  */
 void FPwmLsdEnable(uintptr lsd_addr, u8 pwm_id)
 {
-    FASSERT(pwm_id < FPWM_INSTANCE_NUM);
+    FASSERT(pwm_id < FPWM_NUM);
     u32 reg_val = 0;
 
     reg_val = FPWM_READ_REG32(lsd_addr, FLSD_MIO_PWM_SYN_OFFSET);
@@ -54,7 +55,7 @@ void FPwmLsdEnable(uintptr lsd_addr, u8 pwm_id)
  */
 void FPwmLsdDisable(uintptr lsd_addr, u8 pwm_id)
 {
-    FASSERT(pwm_id < FPWM_INSTANCE_NUM);
+    FASSERT(pwm_id < FPWM_NUM);
     u32 reg_val = 0;
 
     reg_val = FPWM_READ_REG32(lsd_addr, FLSD_MIO_PWM_SYN_OFFSET);
@@ -94,10 +95,10 @@ void FPwmDump(uintptr base_addr)
     printf("Off[0x%x]: FPWM_PERIOD_OFFSET = 0x%08x\r\n", pwm_base_addr + FPWM_PERIOD_OFFSET, FPWM_READ_REG32(pwm_base_addr, FPWM_PERIOD_OFFSET));
     printf("Off[0x%x]: FPWM_CTRL_OFFSET = 0x%08x\r\n", pwm_base_addr + FPWM_CTRL_OFFSET, FPWM_READ_REG32(pwm_base_addr, FPWM_CTRL_OFFSET));
     printf("Off[0x%x]: FPWM_CCR_OFFSET  = 0x%08x\r\n", pwm_base_addr + FPWM_CCR_OFFSET, FPWM_READ_REG32(pwm_base_addr, FPWM_CCR_OFFSET));
-
-
+	
+#if defined(FLSD_CONFIG_BASE)
     printf("Off[0x%x]: FPWM_LSD_OFFSET  = 0x%08x\r\n", FLSD_CONFIG_BASE + FLSD_MIO_PWM_SYN_OFFSET, FPWM_READ_REG32(FLSD_CONFIG_BASE, FLSD_MIO_PWM_SYN_OFFSET));
-
+#endif
     printf("\r\n");
-
+   
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h
index c1efe992bd9..7050ba4a647 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h
@@ -14,28 +14,29 @@
  * FilePath: fpwm_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * Description:  This file is for pwm register definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
-#ifndef BSP_DRIVERS_FPWM_HW_H
-#define BSP_DRIVERS_FPWM_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FPWM_HW_H
+#define FPWM_HW_H
 
 #include "fkernel.h"
 #include "ftypes.h"
 #include "fio.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /* pwm register definitions */
-#define FPWM_BASE_ADR(n)        ((FPWM_CONTROL_BASE)+(n<<12)) /* 0<=n<=7 */
+#define FPWM_BASE_ADR(n)        ((FPWM_BASE_ADDR)+(n<<12)) /* 0<=n<=7 */
 
 #define FPWM0_BASE_ADR           FPWM_BASE_ADR(0)     /* PWM 0 base address */
 #define FPWM1_BASE_ADR           FPWM_BASE_ADR(1)     /* PWM 1 base address */
@@ -113,6 +114,7 @@ extern "C"
 
 /* pwm_ccr field */
 #define FPWM_CCR_MASK           GENMASK(15, 0)
+#define FPWM_CCR_GPIO	        BIT(16)
 
 /* pwm lsd cfg, lsd pwm sync control */
 #define FLSD_MIO_PWM_SYN_OFFSET 0x20
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_intr.c b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_intr.c
index 2439328f5f0..49773c9cd30 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_intr.c
@@ -13,16 +13,17 @@
  *
  * FilePath: fpwm_intr.c
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * LastEditTime: 2022-04-25 11:45:05
+ * Description:  This file is for pwm interrupt handler implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
+
 #include "fparameters.h"
 #include "fassert.h"
-#include "finterrupt.h"
 #include "fpwm.h"
 #include "fpwm_hw.h"
 
@@ -78,11 +79,15 @@ void FPwmIntrHandler(s32 vector, void *args)
 
         status = FPWM_READ_REG32(pwm_base_addr, FPWM_CTRL_OFFSET);
         if (!(status & (FPWM_CTRL_INTR_COUNTER_ENABLE | FPWM_CTRL_INTR_FIFO_EMPTY_ENABLE)))
+        {
             continue;
+        }
 
         status = FPWM_READ_REG32(pwm_base_addr, FPWM_STATE_OFFSET);
         if (0 == status)
+        {
             continue;
+        }
 
         /* Check for the type of error interrupt and Processing it */
         if (status & FPWM_STATE_OVFIF_COUNTER)
diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_sinit.c b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_sinit.c
index a4d13ec00bb..f7a9487c23f 100644
--- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_sinit.c
@@ -13,12 +13,13 @@
  *
  * FilePath: fpwm_sinit.c
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * LastEditTime: 2022-04-25 11:45:05
+ * Description:  This file is for pwm static variables implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
 
 
@@ -28,7 +29,7 @@
 #include "fparameters.h"
 #include "fassert.h"
 
-extern FPwmConfig FPwmConfigTbl[FPWM_INSTANCE_NUM];
+extern FPwmConfig FPwmConfigTbl[FPWM_NUM];
 
 /************************** Constant Definitions *****************************/
 
@@ -46,14 +47,14 @@ extern FPwmConfig FPwmConfigTbl[FPWM_INSTANCE_NUM];
  * @return {*}
  * @param {u32} instanceId, id of pwm ctrl
  */
-const FPwmConfig *FPwmLookupConfig(FPwmInstance instance_id)
+const FPwmConfig *FPwmLookupConfig(u32 instance_id)
 {
     const FPwmConfig *pconfig = NULL;
-    FASSERT(instance_id < FPWM_INSTANCE_NUM);
+    FASSERT(instance_id < FPWM_NUM);
 
     u32 index = 0;
 
-    for (index = 0; index < (u32)FPWM_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FPWM_NUM; index++)
     {
         if (FPwmConfigTbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/Kconfig b/bsp/phytium/libraries/standalone/drivers/qspi/Kconfig
index 7e7a9e54c2f..a16b375482d 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/Kconfig
@@ -2,7 +2,7 @@ menu "Qspi Configuration"
     config USE_FQSPI
         bool
         prompt "Use FQSPI"
-        default n
-
+        default n  
+    
 endmenu
 
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.c
index fc42e8535db..f28004b792f 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.c
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.c
@@ -14,13 +14,14 @@
  * FilePath: fqspi.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-03-28 09:00:41
- * Description:  This files is for
+ * Description:  This files is for the qspi specific functions implementations
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.1    wangxiaodong  2021.11.12  re-construct
- * 1.2    wangxiaodong  2022.3.27   re-construct
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
+ * 1.2   zhangyan      2022/12/7  improve functions
  */
 
 #include <string.h>
@@ -29,6 +30,7 @@
 #include "fqspi.h"
 #include "fqspi_hw.h"
 #include "fsleep.h"
+#include "fqspi_flash.h"
 
 #define FQSPI_DEBUG_TAG "FQSPI"
 #define FQSPI_ERROR(format, ...)    FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -57,7 +59,7 @@ FError FQspiCfgInitialize(FQspiCtrl *pctrl, const FQspiConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == pctrl->is_ready)
     {
-        FQSPI_WARN("device is already initialized!!!");
+        FQSPI_WARN("Device is already initialized!!!");
     }
 
     /*Set default values and configuration data */
@@ -101,30 +103,30 @@ void FQspiSetCapacityAndNum(FQspiCtrl *pctrl)
 
     switch (config_p->capacity)
     {
-    case FQSPI_FLASH_CAP_4MB:
-        pctrl->flash_size = SZ_4M;
-        break;
-    case FQSPI_FLASH_CAP_8MB:
-        pctrl->flash_size = SZ_8M;
-        break;
-    case FQSPI_FLASH_CAP_16MB:
-        pctrl->flash_size = SZ_16M;
-        break;
-    case FQSPI_FLASH_CAP_32MB:
-        pctrl->flash_size = SZ_32M;
-        break;
-    case FQSPI_FLASH_CAP_64MB:
-        pctrl->flash_size = SZ_64M;
-        break;
-    case FQSPI_FLASH_CAP_128MB:
-        pctrl->flash_size = SZ_128M;
-        break;
-    case FQSPI_FLASH_CAP_256MB:
-        pctrl->flash_size = SZ_256M;
-        break;
-    default:
-        pctrl->flash_size = SZ_4M;
-        break;
+        case FQSPI_FLASH_CAP_4MB:
+            pctrl->flash_size = SZ_4M;
+            break;
+        case FQSPI_FLASH_CAP_8MB:
+            pctrl->flash_size = SZ_8M;
+            break;
+        case FQSPI_FLASH_CAP_16MB:
+            pctrl->flash_size = SZ_16M;
+            break;
+        case FQSPI_FLASH_CAP_32MB:
+            pctrl->flash_size = SZ_32M;
+            break;
+        case FQSPI_FLASH_CAP_64MB:
+            pctrl->flash_size = SZ_64M;
+            break;
+        case FQSPI_FLASH_CAP_128MB:
+            pctrl->flash_size = SZ_128M;
+            break;
+        case FQSPI_FLASH_CAP_256MB:
+            pctrl->flash_size = SZ_256M;
+            break;
+        default:
+            pctrl->flash_size = SZ_4M;
+            break;
     }
 
     /* Write flash capacity and numbers information to qspi Capacity register */
@@ -133,7 +135,7 @@ void FQspiSetCapacityAndNum(FQspiCtrl *pctrl)
 
     /*write value to flash capacity register 0x00 */
     FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CAP_OFFSET, reg_val);
-
+    FQSPI_INFO("The flash chip size is %ld bytes.\n",  pctrl->flash_size);
 }
 
 
@@ -184,7 +186,6 @@ FError FQspiRdCfgConfig(FQspiCtrl *pctrl)
     cmd_reg |= FQSPI_RD_CFG_SCK_SEL(rd_config.rd_sck_sel);
 
     FQSPI_WRITE_REG32(base_addr, FQSPI_REG_RD_CFG_OFFSET, cmd_reg);
-
     return ret;
 }
 
@@ -278,10 +279,10 @@ FError FQspiCommandPortConfig(FQspiCtrl *pctrl)
  * @name: FQspiChannelSet
  * @msg:  config qspi cs num
  * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
- * @param {FQspiChipCS} channel, cs number
+ * @param {u32} channel, cs number
  * @return
  */
-void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel)
+void FQspiChannelSet(FQspiCtrl *pctrl, u32 channel)
 {
     FASSERT(pctrl);
     FASSERT(channel < FQSPI_CS_NUM);
@@ -310,3 +311,5 @@ void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg)
     FQSPI_WRITE_REG32(base_addr, FQSPI_REG_CS_TIMING_SET_OFFSET, cmd_reg);
 
 }
+
+
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.h b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.h
index 407187ec26e..f8e259de952 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.h
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi.h
@@ -14,12 +14,14 @@
  * FilePath: fqspi.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:00:55
- * Description:  This files is for
+ * Description:  This files is for the qspi functions related definitions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.1    wangxiaodong  2021.11.12  re-construct
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
+ * 1.2   zhangyan      2022/12/7  improve functions
  */
 
 #ifndef BSP_DRIVERS_FQSPI_H
@@ -226,7 +228,7 @@ FError FQspiRdCfgConfig(FQspiCtrl *pctrl);
 FError FQspiWrCfgConfig(FQspiCtrl *pctrl);
 
 /* qspi cs number set */
-void FQspiChannelSet(FQspiCtrl *pctrl, FQspiChipCS channel);
+void FQspiChannelSet(FQspiCtrl *pctrl, u32 channel);
 
 /* qspi cs timing set */
 void FQspiCsTimingSet(FQspiCtrl *pctrl, FQspiCsTimingCfgDef *cs_timing_cfg);
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c
index a3e5fbf0c81..5e7e5d876c2 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c
@@ -14,11 +14,13 @@
  * FilePath: fqspi_flash.c
  * Date: 2022-07-12 15:42:55
  * LastEditTime: 2022-07-12 15:42:56
- * Description:  This file is for
+ * Description:  This file is for S25FS256, GD25Q256, GD25Q64 norflash program functions
  *
  * Modify History:
  *  Ver Who      Date        Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
  */
 
 #include <string.h>
@@ -63,38 +65,57 @@ FError FQspiFlashDetect(FQspiCtrl *pctrl)
     FError ret = FQSPI_SUCCESS;
     u8 flash_id[3] = {0};
     u8 i = 0;
-
-    /* read id to flash_id */
-    ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDID, flash_id, sizeof(flash_id));
-    if (FQSPI_SUCCESS != ret)
+    u32 index;
+    u32 cs_number = 0;
+    u32 min_detected_cs  = FQSPI_CS_NUM ; 
+    
+    for (index = 0; index < FQSPI_CS_NUM ; index++)
     {
-        FQSPI_ERROR("read flash id failed, ret 0x%x\r\n", ret);
-        return ret;
-    }
+        /* read id to flash_id */
+        pctrl->config.channel = index;
+        ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDID, flash_id, sizeof(flash_id));
+        if (FQSPI_SUCCESS != ret)
+        {
+            FQSPI_ERROR("Read flash id failed, ret 0x%x\r\n", ret);
+            return ret;
+        }
 
-    FQSPI_INFO("flash id = 0x%x, 0x%x, 0x%x\r\n", flash_id[0], flash_id[1], flash_id[2]);
+        if (flash_id[0] != 0xff)
+        {
+            FQSPI_INFO("CSN%d flash id = 0x%x, 0x%x, 0x%x\r\n", index, flash_id[0], flash_id[1], flash_id[2]);
+        }
+        else
+        {
+            FQSPI_ERROR("The Detected CSN%d flash is not matched", index);
+        }
 
-    for (i = 0; i < sizeof(flash_info_table) / sizeof(FQspiFlashInfo); i++)
-    {
-        if ((flash_info_table[i].mf_id == flash_id[0]) && (flash_info_table[i].type_id == flash_id[1])
+        for (i = 0; i < sizeof(flash_info_table) / sizeof(FQspiFlashInfo); i++)
+        {
+            if ((flash_info_table[i].mf_id == flash_id[0]) && (flash_info_table[i].type_id == flash_id[1])
                 && (flash_info_table[i].capacity_id == flash_id[2]))
+            {
+                pctrl->mf_id = flash_info_table[i].mf_id;
+                pctrl->config.capacity = flash_info_table[i].capacity;
+                cs_number++;
+                /*get the min detected flash channel*/
+                min_detected_cs = (min_detected_cs > index)?index:min_detected_cs ; 
+                FQSPI_INFO("CSN%d Find a %s flash chip.\n", index, flash_info_table[i].name);
+                break;
+            }
+        }
+        /*The default channel is the min detected flash*/
+        pctrl->config.channel = min_detected_cs;
+
+        if (i == sizeof(flash_info_table) / sizeof(FQspiFlashInfo) && flash_id[0] != 0xff)
         {
-            pctrl->mf_id = flash_info_table[i].mf_id;
-            pctrl->config.capacity = flash_info_table[i].capacity;
-            break;
+            FQSPI_ERROR("The Detected CSN%d flash not detected, id = 0x%x, 0x%x, 0x%x\r\n", index, flash_id[0], flash_id[1], flash_id[2]);
         }
-    }
 
-    if (i == sizeof(flash_info_table) / sizeof(FQspiFlashInfo))
-    {
-        FQSPI_ERROR("The Detected flash is not matched, id = 0x%x, 0x%x, 0x%x\r\n", flash_id[0], flash_id[1], flash_id[2]);
-        return FQSPI_NOT_SUPPORT;
     }
 
+    pctrl->config.dev_num = cs_number - 1;
     /* set flash num and flash capacity */
     FQspiSetCapacityAndNum(pctrl);
-    FQSPI_INFO("Find a %s flash chip. Size is %ld bytes.\n", flash_info_table[i].name, pctrl->flash_size);
-
     return ret;
 }
 
@@ -111,14 +132,14 @@ static FError FQspiFlashReset(FQspiCtrl *pctrl)
     ret = FQspiFlashWriteReg(pctrl, FQSPI_CMD_ENABLE_RESET, NULL, 0);
     if (FQSPI_SUCCESS != ret)
     {
-        FQSPI_ERROR("failed to enable reset, test result 0x%x\r\n", ret);
+        FQSPI_ERROR("Failed to enable reset, test result 0x%x\r\n", ret);
         return ret;
     }
 
     ret = FQspiFlashWriteReg(pctrl, FQSPI_CMD_RESET, NULL, 0);
     if (FQSPI_SUCCESS != ret)
     {
-        FQSPI_ERROR("failed to reset, test result 0x%x\r\n", ret);
+        FQSPI_ERROR("Failed to reset, test result 0x%x\r\n", ret);
         return ret;
     }
 
@@ -407,117 +428,138 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command)
 
     switch (command)
     {
-    case FQSPI_FLASH_CMD_READ:
-        FQspiFlashReset(pctrl);
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
-        break;
-
-    case FQSPI_FLASH_CMD_4READ:
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
-        break;
-
-    case FQSPI_FLASH_CMD_FAST_READ:
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
-        pctrl->rd_cfg.dummy = 8;
-        pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
-        break;
-
-    case FQSPI_FLASH_CMD_4FAST_READ:
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
-        pctrl->rd_cfg.dummy = 8;
-        pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
-        break;
-
-    case FQSPI_FLASH_CMD_DUAL_READ:
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_2_2;
-        pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
-
-        if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS)
-        {
-            pctrl->rd_cfg.mode_byte = 0x1;
-            pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
+        case FQSPI_FLASH_CMD_READ:
+            FQspiFlashReset(pctrl);
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
+            break;
+
+        case FQSPI_FLASH_CMD_4READ:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
+            break;
+
+        case FQSPI_FLASH_CMD_FAST_READ:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
             pctrl->rd_cfg.dummy = 8;
-        }
-        else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_GIGADEVICE)
-        {
-            pctrl->rd_cfg.dummy = 4;
-        }
-        else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_BOYA)
-        {
-            pctrl->rd_cfg.dummy = 4;
-        }
-        break;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            break;
 
-    case FQSPI_FLASH_CMD_QIOR:
-        /* set SR1V and CR1V */
-        FQspiFlashEnableWrite(pctrl);
+        case FQSPI_FLASH_CMD_4FAST_READ:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_1;
+            pctrl->rd_cfg.dummy = 8;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            break;
 
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
-        pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+        case FQSPI_FLASH_CMD_DOR:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_2;
+            pctrl->rd_cfg.dummy = 8;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            break;
 
-        if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS)
-        {
-            pctrl->rd_cfg.dummy = 10;
-            /* use wrr write config register 1 */
-            ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
-            if (FQSPI_SUCCESS != ret)
+        case FQSPI_FLASH_CMD_QOR:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_1_4;
+            pctrl->rd_cfg.dummy = 8;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            break;
+
+        case FQSPI_FLASH_CMD_QWFR:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
+            pctrl->rd_cfg.dummy = 2;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            break;
+
+        case FQSPI_FLASH_CMD_DUAL_READ:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_2_2;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+
+            if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS)
             {
-                FQSPI_ERROR("failed to write cmd wrr, test result 0x%x", ret);
-                return 0;
+                pctrl->rd_cfg.mode_byte = 0x1;
+                pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
+                pctrl->rd_cfg.dummy = 8;
             }
-        }
-        else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_GIGADEVICE)
-        {
-            pctrl->rd_cfg.dummy = 6;
-            /* use wrr write config register 1 */
-            ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
-            if (FQSPI_SUCCESS != ret)
+            else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_GIGADEVICE)
             {
-                FQSPI_ERROR("failed to write cmd wrr, test result 0x%x", ret);
-                return 0;
+                pctrl->rd_cfg.dummy = 4;
             }
-        }
-        else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_BOYA)
-        {
-            pctrl->rd_cfg.dummy = 6;
-            ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRITE_SR2, &wrr_buf[1], 1);
-            if (FQSPI_SUCCESS != ret)
+            else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_BOYA)
             {
-                FQSPI_ERROR("failed to write cmd wrr, test result 0x%x", ret);
-                return 0;
+                pctrl->rd_cfg.dummy = 4;
             }
-        }
+            break;
 
-        break;
+        case FQSPI_FLASH_CMD_QIOR:
+            /* set SR1V and CR1V */
+            FQspiFlashEnableWrite(pctrl);
 
-    case FQSPI_FLASH_CMD_4QIOR:
-        pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
-        pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
-        pctrl->rd_cfg.mode_byte = 0x1;
-        pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
-        pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
-        pctrl->rd_cfg.dummy = 8;
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
 
-        /* set SR1V and CR1V */
-        FQspiFlashEnableWrite(pctrl);
-        /* use wrr write config register 1 */
-        ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
-        if (FQSPI_SUCCESS != ret)
-        {
-            FQSPI_ERROR("failed to write cmd wrr, test result 0x%x\r\n", ret);
-            return ret;
-        }
-        break;
+            if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS)
+            {
+                pctrl->rd_cfg.dummy = 10;
+                /* use wrr write config register 1 */
+                ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
+                if (FQSPI_SUCCESS != ret)
+                {
+                    FQSPI_ERROR("Failed to write cmd wrr, test result 0x%x", ret);
+                    return 0;
+                }
+            }
+            else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_GIGADEVICE)
+            {
+                pctrl->rd_cfg.dummy = 6;
+                /* use wrr write config register 1 */
+                ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
+                if (FQSPI_SUCCESS != ret)
+                {
+                    FQSPI_ERROR("Failed to write cmd wrr, test result 0x%x", ret);
+                    return 0;
+                }
+            }
+            else if (pctrl->mf_id == FQSPI_FLASH_MF_ID_BOYA)
+            {
+                pctrl->rd_cfg.dummy = 6;
+                ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRITE_SR2, &wrr_buf[1], 1);
+                if (FQSPI_SUCCESS != ret)
+                {
+                    FQSPI_ERROR("Failed to write cmd wrr, test result 0x%x", ret);
+                    return 0;
+                }
+            }
 
-    default:
-        return FQSPI_INVAL_PARAM;
-        break;
+            break;
+
+        case FQSPI_FLASH_CMD_4QIOR:
+            pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_4;
+            pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4;
+            pctrl->rd_cfg.mode_byte = 0x1;
+            pctrl->rd_cfg.cmd_sign = FQSPI_QUAD_READ_MODE_CMD;
+            pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE;
+            pctrl->rd_cfg.dummy = 8;
+
+            /* set SR1V and CR1V */
+            FQspiFlashEnableWrite(pctrl);
+            /* use wrr write config register 1 */
+            ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, wrr_buf, sizeof(wrr_buf));
+            if (FQSPI_SUCCESS != ret)
+            {
+                FQSPI_ERROR("Failed to write cmd wrr, test result 0x%x\r\n", ret);
+                return ret;
+            }
+            break;
+
+        default:
+            return FQSPI_INVAL_PARAM;
+            break;
     }
 
     ret = FQspiRdCfgConfig(pctrl);
@@ -572,18 +614,18 @@ FError FQspiFlashWriteData(FQspiCtrl *pctrl, u8 command, u32 chip_addr, const u8
     /* set addr_sel region, FQSPI_ADDR_SEL_3 or FQSPI_ADDR_SEL_4 */
     switch (command)
     {
-    case FQSPI_FLASH_CMD_PP:
-    case FQSPI_FLASH_CMD_QPP:
-        pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3;
-        break;
-    case FQSPI_FLASH_CMD_4PP:
-    case FQSPI_FLASH_CMD_4QPP:
-        pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_4;
-        break;
-    default:
-        ret |= FQSPI_NOT_SUPPORT;
-        return ret;
-        break;
+        case FQSPI_FLASH_CMD_PP:
+        case FQSPI_FLASH_CMD_QPP:
+            pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3;
+            break;
+        case FQSPI_FLASH_CMD_4PP:
+        case FQSPI_FLASH_CMD_4QPP:
+            pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_4;
+            break;
+        default:
+            ret |= FQSPI_NOT_SUPPORT;
+            return ret;
+            break;
     }
 
     /*write wr_cfg to Write config register 0x08 */
@@ -802,41 +844,41 @@ FError FQspiFlashErase(FQspiCtrl *pctrl, u8 command, u32 offset)
 
     switch (command)
     {
-    case FQSPI_FLASH_CMD_SE:
-        /* set addr_sel region, FQSPI_ADDR_SEL_3 or FQSPI_ADDR_SEL_4 */
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
-
-        /* set cmd_addr region, by command, have addr transfer */
-        pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
-
-        /* need some execution time  */
-        pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
-
-        break;
-    case FQSPI_FLASH_CMD_4SE:
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_4;
-        pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
-        pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
-
-        break;
-    case FQSPI_FLASH_CMD_P4E:
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
-        pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
-
-        break;
-    case FQSPI_FLASH_CMD_4P4E:
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_4;
-        pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
-
-        break;
-    case FQSPI_FLASH_CMD_BE:
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
-        break;
-    case FQSPI_FLASH_CMD_4BE:
-        pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
-        break;
-    default:
-        return FQSPI_NOT_SUPPORT;
+        case FQSPI_FLASH_CMD_SE:
+            /* set addr_sel region, FQSPI_ADDR_SEL_3 or FQSPI_ADDR_SEL_4 */
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+
+            /* set cmd_addr region, by command, have addr transfer */
+            pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+
+            /* need some execution time  */
+            pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
+
+            break;
+        case FQSPI_FLASH_CMD_4SE:
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_4;
+            pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+            pctrl->cmd_def.wait = FQSPI_WAIT_ENABLE;
+
+            break;
+        case FQSPI_FLASH_CMD_P4E:
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+            pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+
+            break;
+        case FQSPI_FLASH_CMD_4P4E:
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_4;
+            pctrl->cmd_def.cmd_addr = FQSPI_CMD_ADDR_ENABLE;
+
+            break;
+        case FQSPI_FLASH_CMD_BE:
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+            break;
+        case FQSPI_FLASH_CMD_4BE:
+            pctrl->cmd_def.addr_sel = FQSPI_ADDR_SEL_3;
+            break;
+        default:
+            return FQSPI_NOT_SUPPORT;
     }
 
     /*write cmd_reg to Command port register 0x10 */
@@ -968,7 +1010,7 @@ FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t le
 
     if (len > 4)
     {
-        FQSPI_ERROR("data length exceed. commad 0x%lx, len:%d \n", command, len);
+        FQSPI_ERROR("Data length exceed. commad 0x%lx, len:%d \n", command, len);
         return FQSPI_INVAL_PARAM;
     }
     else if ((len > 0) && (buf != NULL))
@@ -1014,7 +1056,7 @@ FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl)
     ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDSR1, &sr1, sizeof(sr1));
     if (FQSPI_SUCCESS != ret)
     {
-        FQSPI_ERROR("failed to read sr1, result 0x%x\r\n", ret);
+        FQSPI_ERROR("Failed to read sr1, result 0x%x\r\n", ret);
         return ret;
     }
 
@@ -1027,7 +1069,7 @@ FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl)
 
         if (!timeout)
         {
-            FQSPI_ERROR("wait cmd timeout !!!");
+            FQSPI_ERROR("Wait cmd timeout !!!");
             ret = FQSPI_TIMEOUT;
             break;
         }
@@ -1035,5 +1077,30 @@ FError FQspiFlashWaitForCmd(FQspiCtrl *pctrl)
     }
     while (sr1 & FQSPI_NOR_FLASH_STATE_BUSY);
 
+    return ret;
+}
+
+/**
+ * @name: FQspiFlashWProtectSet
+ * @msg:  Set qspi write protection function
+ * @param {FQspiCtrl} *pctrl, instance of FQSPI controller
+ * @param {u32} Write protect function enable/disable 1:enable,0:disable
+ * @return err code information, FQSPI_SUCCESS indicates success，others indicates failed
+ */
+FError FQspiFlashWProtectSet(FQspiCtrl *pctrl, boolean wprotect, u8 channel)
+{
+    FASSERT(pctrl);
+    FError ret = FQSPI_SUCCESS;
+    u8 wp_block[2] = {FQSPI_FLASH_WP_ENABLE, FQSPI_FLASH_WP_DISABLE};
+    FQspiChannelSet(pctrl, channel);
+    ret = FQspiFlashEnableWrite(pctrl);
+    if (wprotect == TRUE)
+    {
+        ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, &wp_block[0], 1);
+    }
+    else if (wprotect == FALSE)
+    {
+        ret = FQspiFlashWriteReg(pctrl, FQSPI_FLASH_CMD_WRR, &wp_block[1], 1);
+    }
     return ret;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h
index 26712ca9b39..0c74afa5c01 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h
@@ -21,23 +21,27 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.1   wangxiaodong  2021.11.12  re-construct
- * 1.2   wangxiaodong  2022.3.27   re-construct
- * 1.3   wangxiaodong  2022.7.5    adapt to e2000
+ * 1.0   wangxiaodong  2021/11/12  first release
+ * 1.1   wangxiaodong  2022/3/29   improve functions
+ * 1.2   wangxiaodong  2022/7/5    adapt to e2000
+ * 1.3   wangxiaodong  2022/9/9    improve functions
+ * 1.4   zhangyan      2022/12/7   improve functions
  */
 
-#ifndef BSP_DRIVERS_FQSPI_FLASH_H
-#define BSP_DRIVERS_FQSPI_FLASH_H
+#ifndef FQSPI_FLASH_H
+#define FQSPI_FLASH_H
+
+#include "fkernel.h"
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fqspi.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "fkernel.h"
-#include "ftypes.h"
-#include "ferror_code.h"
-#include "fqspi.h"
 
 /* qspi flash support manufacturer JEDEC ID */
 #define FQSPI_FLASH_MF_ID_CYPRESS            0x01
@@ -45,17 +49,19 @@ extern "C"
 #define FQSPI_FLASH_MF_ID_BOYA               0x68
 
 /* qspi flash supported information table */
-#define FQSPI_FLASH_INFO_TABLE                                                              \
-{                                                                                           \
-    {"S25FS256S", FQSPI_FLASH_MF_ID_CYPRESS, 0x02, 0x19, FQSPI_FLASH_CAP_32MB},             \
-    {"GD25Q32C", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x16, FQSPI_FLASH_CAP_4MB},            \
-    {"GD25Q32E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x16, FQSPI_FLASH_CAP_4MB},            \
-    {"GD25Q64B", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x17, FQSPI_FLASH_CAP_8MB},            \
-    {"GD25LQ128E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x18, FQSPI_FLASH_CAP_16MB},         \
-    {"GD25QL256D", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x19, FQSPI_FLASH_CAP_32MB},         \
-    {"BY25Q64BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x17, FQSPI_FLASH_CAP_8MB},                 \
-    {"BY25Q32BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x16, FQSPI_FLASH_CAP_4MB}                  \
-}
+#define FQSPI_FLASH_INFO_TABLE                                                                  \
+    {                                                                                           \
+        {"S25FS256S", FQSPI_FLASH_MF_ID_CYPRESS, 0x02, 0x19, FQSPI_FLASH_CAP_32MB},             \
+        {"GD25Q32C", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x16, FQSPI_FLASH_CAP_4MB},            \
+        {"GD25Q32E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x16, FQSPI_FLASH_CAP_4MB},            \
+        {"GD25Q64B", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x17, FQSPI_FLASH_CAP_8MB},            \
+        {"GD25LQ128E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x40, 0x18, FQSPI_FLASH_CAP_16MB},         \
+    	{"GD25LQ128E", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x18, FQSPI_FLASH_CAP_16MB},         \
+        {"GD25QL256D", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x19, FQSPI_FLASH_CAP_32MB},         \
+        {"BY25Q64BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x17, FQSPI_FLASH_CAP_8MB},                 \
+        {"BY25Q128BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x18, FQSPI_FLASH_CAP_16MB},               \
+        {"BY25Q32BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x16, FQSPI_FLASH_CAP_4MB}                  \
+    }
 
 #define FQSPI_FLASH_CMD_WRR 0x01        /* Write status register */
 #define FQSPI_FLASH_CMD_PP 0x02         /* Page program */
@@ -76,7 +82,9 @@ extern "C"
 #define FQSPI_FLASH_CMD_RDCR 0x35       /* Read config register */
 #define FQSPI_FLASH_CMD_BE 0x60         /* Bulk erase */
 #define FQSPI_FLASH_CMD_RDAR 0x65       /* Read Any Register  */
+#define FQSPI_FLASH_CMD_DOR 0x3B        /* Dual read data bytes*/
 #define FQSPI_FLASH_CMD_QOR 0x6B        /* Quad read data bytes */
+#define FQSPI_FLASH_CMD_QWFR 0xE7       /* Quad word fast read data bytes */
 #define FQSPI_FLASH_CMD_4QOR 0x6C       /* Quad read data bytes */
 #define FQSPI_FLASH_CMD_WRAR 0x71       /* Write Any Register  */
 #define FQSPI_FLASH_CMD_RDID 0x9F       /* Read JEDEC ID */
@@ -90,14 +98,17 @@ extern "C"
 #define FQSPI_FLASH_CMD_SFDP 0x5A       /* Read JEDEC Serial Manu ID */
 #define FQSPI_CMD_ENABLE_RESET 0x66     /* Software Reset Enable */
 #define FQSPI_CMD_RESET 0x99            /* Software Reset */
+#define FQSPI_FLASH_CMD_RDSR3 0x15      /* Read status register 3 */
 
 /* boya flash */
 #define FQSPI_FLASH_CMD_WRITE_SR2 0x31  /* Write status register 2 */
-
+#define FQSPI_FLASH_CMD_WRITE_SR3 0x11  /* Write status register 3 */
 
 #define FQSPI_BUSY_TIMEOUT_US           1000000
 #define FQSPI_NOR_FLASH_STATE_BUSY      BIT(0)
 
+#define FQSPI_FLASH_WP_ENABLE 0x7c      /* Write status register 2 */
+#define FQSPI_FLASH_WP_DISABLE 0x00     /* Write status register 2 */
 /* Read some flash information */
 FError FQspiFlashSpecialInstruction(FQspiCtrl *pctrl, u8 cmd, u8 *buf, size_t len);
 
@@ -140,6 +151,9 @@ FError FQspiFlashPortWriteData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf,
 /* detect flash information */
 FError FQspiFlashDetect(FQspiCtrl *pctrl);
 
+/* qspi write protect set */
+FError FQspiFlashWProtectSet(FQspiCtrl *pctrl, boolean wprotect, u8 channel);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_g.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_g.c
index e152ccd9f0f..14f01cbcd00 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_g.c
@@ -14,26 +14,24 @@
  * FilePath: fqspi_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:00:41
- * Description:  
- * This file is for
- *
+ * Description:  This file is for the qspi default configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.1   wangxiaodong  2021.11.12  re-construct
- * 1.2   wangxiaodong  2022.3.27   re-construct
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
  */
 
 #include "fparameters.h"
 #include "fqspi.h"
 #include "sdkconfig.h"
 
-FQspiConfig FQspiConfigTbl[FQSPI_INSTANCE_NUM] =
+FQspiConfig FQspiConfigTbl[FQSPI_NUM] =
 {
     {
-        .instance_id = FQSPI_INSTANCE_0,
-        .base_addr = FQSPI_BASEADDR,
+        .instance_id = FQSPI0_ID,
+        .base_addr = FQSPI_BASE_ADDR,
         .mem_start = FQSPI_MEM_START_ADDR,
         .capacity = 0,
         .dev_num = 0,
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.c
index e759c661a56..a7c7ac34428 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.c
@@ -14,13 +14,12 @@
  * FilePath: fqspi_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:00:41
- * Description:  
- * This file is for
- *
- *
+ * Description:  This file is for the qspi register related functions
+ * 
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/3/29  first release
  */
 #include "ftypes.h"
 #include "ferror_code.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.h b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.h
index d80c0a13986..2d4dd650a79 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_hw.h
@@ -14,12 +14,14 @@
  * FilePath: fqspi_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:00:23
- * Description:  This files is for
+ * Description:  This files is for the qspi register related definition
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
- * 1.1    wangxiaodong  2021.11.12  re-construct
+ *  Ver   Who        Date        Changes
+ * ----- ------      --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
+ * 1.2   zhangyan      2022/12/7  improve functions
  */
 
 #ifndef BSP_DRIVERS_FQSPI_HW_H
@@ -49,22 +51,22 @@ extern "C"
 
 /* FQSPI_CAP */
 #define FQSPI_CAP_FLASH_NUM(data)   ((data) << 3) /* Flash number */
-#define FQSPI_CAP_FLASH_CAP(data)   ((data) << 0) /*  The flash capacity */
+#define FQSPI_CAP_FLASH_CAP(data)   ((data) << 0) /* The flash capacity */
 
 #define FQSPI_CAP_FLASH_NUM_MASK   GENMASK(4, 3)
 #define FQSPI_CAP_FLASH_CAP_MASK   GENMASK(2, 0)
 
 /* RD_CFG */
-#define FQSPI_RD_CFG_CMD(data)          ((data) << 24)       /* Read Command */
-#define FQSPI_RD_CFG_THROUGH(data)      ((data) << 23)   /* The programming flag in the status register */
+#define FQSPI_RD_CFG_CMD(data)          ((data) << 24)  /* Read Command */
+#define FQSPI_RD_CFG_THROUGH(data)      ((data) << 23)  /* The programming flag in the status register */
 #define FQSPI_RD_CFG_TRANSFER(data)     ((data) << 20)  /* rd_tranfer region */
 #define FQSPI_RD_CFG_ADDR_SEL(data)     ((data) << 19)  /* rd_addr_sel region*/
-#define FQSPI_RD_CFG_LATENCY(data)      ((data) << 18)   /* rd_latency region*/
-#define FQSPI_RD_CFG_MODE_BYTE(data)    ((data) << 17) /* mode byte region*/
+#define FQSPI_RD_CFG_LATENCY(data)      ((data) << 18)  /* rd_latency region*/
+#define FQSPI_RD_CFG_MODE_BYTE(data)    ((data) << 17)  /* mode byte region*/
 #define FQSPI_RD_CFG_CMD_SIGN(data)     ((data) << 9)   /* cmd_sign region*/
-#define FQSPI_RD_CFG_DUMMY(data)        ((data-1) << 4)      /* dummy region*/
+#define FQSPI_RD_CFG_DUMMY(data)        ((data-1) << 4) /* dummy region*/
 #define FQSPI_RD_CFG_D_BUFFER(data)     ((data) << 3)   /* d_buffer region*/
-#define FQSPI_RD_CFG_SCK_SEL(data)      ((data) << 0)    /* rd_sck_sel region*/
+#define FQSPI_RD_CFG_SCK_SEL(data)      ((data) << 0)   /* rd_sck_sel region*/
 
 #define FQSPI_RD_CFG_CMD_MASK        GENMASK(31, 24)
 #define FQSPI_RD_CFG_SCK_SEL_MASK    GENMASK(2, 0)
@@ -132,7 +134,6 @@ extern "C"
 #define FQSPI_QUAD_READ_MODE_DISABLE    0xF0BF /* disable FLASH XIP MODE */
 #define FQSPI_QUAD_READ_MODE_CMD        0xA0  /* FLASH XIP MODE CMD SIGN */
 
-
 typedef enum
 {
     FQSPI_CMD_READ = 0x01,
diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_sinit.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_sinit.c
index d6636990a82..b3d908bda06 100644
--- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_sinit.c
@@ -14,27 +14,28 @@
  * FilePath: fqspi_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:01:10
- * Description:  This files is for
+ * Description:  This files is for getting default configuration of specific qspi instance_id
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
- * 1.1    wangxiaodong  2021.11.12  re-construct
+ *  Ver   Who           Date        Changes
+ * -----  ------        --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/3/29  first release
+ * 1.1   wangxiaodong  2022/9/9   improve functions
  */
 
 #include "fparameters.h"
 #include "fassert.h"
 #include "fqspi.h"
 
-extern FQspiConfig FQspiConfigTbl[FQSPI_INSTANCE_NUM];
+extern FQspiConfig FQspiConfigTbl[FQSPI_NUM];
 
 const FQspiConfig *FQspiLookupConfig(u32 instance_id)
 {
-    FASSERT(instance_id < FQSPI_INSTANCE_NUM);
+    FASSERT(instance_id < FQSPI_NUM);
     const FQspiConfig *pconfig = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FQSPI_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FQSPI_NUM; index++)
     {
         if (FQspiConfigTbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/Kconfig b/bsp/phytium/libraries/standalone/drivers/rtc/Kconfig
index 9919d9d29f4..63cedcbe5c7 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/Kconfig
@@ -3,7 +3,7 @@ menu "FRTC Configuration"
         bool
         prompt "Use FRTC"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.c b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.c
index 8ee7ad34849..2936a065329 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.c
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.c
@@ -12,14 +12,14 @@
  *
  *
  * FilePath: frtc.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:02:33
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:02:33
+ * Description:  This file is for user API implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Wangxiaodong   2021/11/5   init
+ * 1.0   Wangxiaodong   2021/8/26  first commit
  */
 
 #include <string.h>
@@ -60,19 +60,21 @@ static FError FRtcCheckDateTime(const FRtcDateTime *date_time)
 
     /* 闰年2月+1天 */
     if ((w_month == 2) && (FRTC_IS_LEAP_YEAR(w_year)))
+    {
         days_of_month[w_month - 1] += 1;
+    }
 
     /* 判断月份日期是否合法 */
     if ((w_month > 12) || (w_month < 1) || (w_day > days_of_month[w_month - 1]) || (w_day < 1))
     {
-        FRTC_ERROR("invalid input date: month: %d, day: %d", w_month, w_day);
+        FRTC_ERROR("Invalid input date: month: %d, day: %d", w_month, w_day);
         return FRTC_ERR_DATE_INVALID;
     }
 
     /* 判断时分秒是否合法 */
     if ((w_hour > 23) || (w_minute > 59) || (w_second > 59))
     {
-        FRTC_ERROR("invalid input time: hour: %d, minute: %d, second: %d",
+        FRTC_ERROR("Invalid input time: hour: %d, minute: %d, second: %d",
                    w_hour, w_minute, w_second);
         return FRTC_ERR_TIME_INVALID;
     }
@@ -188,10 +190,14 @@ void FRtcReadTimeStamp(FRtcCtrl *pctrl, time_t *sec_p, time_t *msec_p)
     msec = ((tick * 1000) >> FRTC_COUNTER_HB_OFFSET);
 
     if (sec_p)
+    {
         *sec_p = sec;
+    }
 
     if (msec_p)
+    {
         *msec_p = msec;
+    }
 
     return;
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.h b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.h
index 25fdd276d68..870a8bf7b96 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.h
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc.h
@@ -12,29 +12,29 @@
  *
  *
  * FilePath: frtc.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:02:51
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:02:51
+ * Description:  This file is for user API definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Wangxiaodong 2021/8/26   init
+ * 1.0   Wangxiaodong 2021/8/26  first commit
  */
 
-#ifndef BSP_DRIVERS_FRTC_H
-#define BSP_DRIVERS_FRTC_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef DRIVERS_RTC_FRTC_H
+#define DRIVERS_RTC_FRTC_H
 
 #include <time.h>
 
 #include "ftypes.h"
 #include "ferror_code.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 typedef struct
 {
     uintptr control_base_addr; /* rtc控制寄存器基地址 */
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_g.c b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_g.c
index e3b54ab4885..e7457ccce28 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_g.c
@@ -12,14 +12,14 @@
  *
  *
  * FilePath: frtc_g.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:01:26
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:01:26
+ * Description:  This file is for rtc static configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Wangxiaodong   2021/8/25   init
+ * 1.0   Wangxiaodong   2021/8/26 first commit
  */
 
 #include "fparameters.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.c b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.c
index b7d07720965..947077908b1 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: frtc_hw.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:01:40
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:01:40
+ * Description:  This file is for rtc register read/write operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   Wangxiaodong   2021/8/26 first commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.h b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.h
index d104692667b..4f1a4ebe4ba 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_hw.h
@@ -12,28 +12,29 @@
  *
  *
  * FilePath: frtc_hw.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:01:54
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:01:54
+ * Description:  This file is for rtc register definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   wangxiaodong 2021/11/5   init
+ * 1.0   wangxiaodong 2021/8/26 first commit
  */
 
-#ifndef BSP_DRIVERS_FRTC_HW_H
-#define BSP_DRIVERS_FRTC_HW_H
+#ifndef DRIVERS_RTC_FRTC_HW_H
+#define DRIVERS_RTC_FRTC_HW_H
 
-#ifdef __cplusplus
-extern "C"
-{
-#endif
 
 #include "fkernel.h"
 #include "ftypes.h"
 #include "fio.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /* Rtc register definitions */
 
 #define FRTC_CMR                 0x04
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_intr.c b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_intr.c
index 9b7803214b6..72b63b241a2 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_intr.c
@@ -12,14 +12,14 @@
  *
  *
  * FilePath: frtc_intr.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:02:07
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:02:07
+ * Description:  This file is for rtc interrupt operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Wangxiaodong   2021/8/3   init
+ * 1.0   Wangxiaodong   2021/8/26   first commit
  */
 
 #include "fparameters.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_sinit.c b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_sinit.c
index 7ded7bdbcc7..693bdde77c4 100644
--- a/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/rtc/frtc/frtc_sinit.c
@@ -12,13 +12,14 @@
  *
  *
  * FilePath: frtc_sinit.c
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:02:24
- * Description:  This files is for
+ * Date: 2021-08-25 14:53:42
+ * LastEditTime: 2021-08-26 09:02:24
+ * Description:  This file is for rtc static initialization functionality
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   Wangxiaodong   2021/8/26   first commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/Kconfig b/bsp/phytium/libraries/standalone/drivers/sata/Kconfig
index 594bd366060..f2c51a66d42 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/sata/Kconfig
@@ -3,7 +3,7 @@ menu "FSATA Configuration"
         bool
         prompt "Use FSATA"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c
index c9fa80705bd..381eba09c98 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c
@@ -14,11 +14,14 @@
  * FilePath: fsata.c
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:05:09
- * Description:  This files is for sata ctrl function implementation
+ * Description:  This file is for sata ctrl function implementation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/9/9     improve functions
+ * 1.2   wangxiaodong  2022/10/21   improve functions
  */
 
 #include <string.h>
@@ -116,7 +119,9 @@ static FError FSataAhciLinkUp(FSataCtrl *instance_p, u8 port)
     {
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_STAT);
         if ((reg_val & FSATA_PORT_SCR_STAT_DET_MASK) == FSATA_PORT_SCR_STAT_DET_PHYRDY)
+        {
             return FSATA_SUCCESS;
+        }
         fsleep_microsec(1000);
         i++;
     }
@@ -152,7 +157,7 @@ static FError FSataAhciInquiry(FSataCtrl *instance_p, u8 port)
                           (u8 *)tmpid, FSATA_ID_WORDS * 2, FALSE, FALSE);
     if (ret != FSATA_SUCCESS)
     {
-        FSATA_ERROR("FSataAhciInquiry: command failure. ret = %#x", ret);
+        FSATA_ERROR("FSataAhciInquiry: command failure. ret = %#x.", ret);
         return FSATA_ERR_OPERATION;
     }
 
@@ -181,18 +186,24 @@ static void FSataIdentityCopy(unsigned char *dest, unsigned char *src, u32 len)
     while (start < len)
     {
         if (src[start] != 0x20)/* character is not sapce */
+        {
             break;
+        }
         start++;
     }
     end = len - 1;
     while (end > start)
     {
         if (src[end] != 0x20)/* character is not sapce */
+        {
             break;
+        }
         end--;
     }
     for (; start <= end; start++)
+    {
         *dest ++ = src[start];
+    }
     *dest = '\0';
 }
 
@@ -207,9 +218,13 @@ static u64 FSataIdToSectors(u16 *id)
     if (FSataIdHasLba(id))
     {
         if (FSataIdHasLba48(id))
+        {
             return FSATA_ID_U64(id, FSATA_ID_LBA48_SECTORS);
+        }
         else
+        {
             return (u64)(FSATA_ID_U32(id, FSATA_ID_LBA_SECTORS));
+        }
     }
     else
     {
@@ -229,7 +244,9 @@ static void FSataIdStrCopy(u16 *dest, u16 *src, int len)
 {
     int i;
     for (i = 0; i < len / 2; i++)
+    {
         dest[i] = __swab16(src[i]);
+    }
 }
 
 /**
@@ -262,7 +279,7 @@ void FSataInfoPrint(FSataInfo *dev_desc)
 
     if (dev_desc->type == FSATA_DEV_TYPE_UNKNOWN)
     {
-        FSATA_INFO("not available");
+        FSATA_INFO("Not available.");
         return;
     }
 
@@ -310,7 +327,7 @@ void FSataInfoPrint(FSataInfo *dev_desc)
     }
     else
     {
-        FSATA_INFO("Capacity: not available");
+        FSATA_INFO("Capacity: not available.");
     }
 }
 
@@ -342,7 +359,9 @@ static FError FSataAhciReadCapacity(FSataCtrl *instance_p, u8 port,
 
     u64 cap64 = FSataIdToSectors(instance_p->ataid[port]);
     if (cap64 > 0x100000000ULL)
+    {
         cap64 = 0xffffffff;
+    }
 
     *capacity = (unsigned long)(cap64);
     if (*capacity != 0xffffffff)
@@ -353,7 +372,7 @@ static FError FSataAhciReadCapacity(FSataCtrl *instance_p, u8 port,
     }
     else
     {
-        FSATA_DEBUG("should read capacity 16?");
+        FSATA_DEBUG("Should read capacity 16?");
     }
 
     return FSATA_SUCCESS;
@@ -457,7 +476,7 @@ static FError FSataAhciReset(FSataCtrl *instance_p)
 
     if (i == 0)
     {
-        FSATA_ERROR("controller reset failed (0x%x)", reg_val);
+        FSATA_ERROR("Controller reset failed (0x%x).", reg_val);
         return FSATA_ERR_TIMEOUT;
     }
 
@@ -484,7 +503,9 @@ FError FSataAhciInit(FSataCtrl *instance_p)
     /* reset host control */
     ret = FSataAhciReset(instance_p);
     if (ret != FSATA_SUCCESS)
+    {
         return ret;
+    }
 
     /* ahci enable */
     FSATA_WRITE_REG32(base_addr, FSATA_HOST_CTL, FSATA_HOST_AHCI_EN);
@@ -502,7 +523,9 @@ FError FSataAhciInit(FSataCtrl *instance_p)
     for (i = 0; i < instance_p->n_ports; i++)
     {
         if (!(instance_p->port_map & BIT(i)))
+        {
             continue;
+        }
         /* set ports base address */
         instance_p->port[i].port_base_addr = FSataAhciPortBase(base_addr, i);
         port_base_addr = instance_p->port[i].port_base_addr;
@@ -531,7 +554,7 @@ FError FSataAhciInit(FSataCtrl *instance_p)
         ret = FSataAhciLinkUp(instance_p, i);
         if (ret)
         {
-            FSATA_DEBUG("sata host %d, port %d link timeout", instance_p->config.instance_id, i);
+            FSATA_DEBUG("sata host %d, port %d link timeout.", instance_p->config.instance_id, i);
             continue;
         }
         else
@@ -542,7 +565,9 @@ FError FSataAhciInit(FSataCtrl *instance_p)
         /* Clear error status */
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_ERR);
         if (reg_val)
+        {
             FSATA_WRITE_REG32(port_base_addr, FSATA_PORT_SCR_ERR, reg_val);
+        }
 
         /* Device presence detected but Phy communication not established, retry once more */
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_STAT) & FSATA_PORT_SCR_STAT_DET_MASK;
@@ -556,12 +581,16 @@ FError FSataAhciInit(FSataCtrl *instance_p)
         /* Clear error status */
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_ERR);
         if (reg_val)
+        {
             FSATA_WRITE_REG32(port_base_addr, FSATA_PORT_SCR_ERR, reg_val);
+        }
 
         /* clear port irq status */
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_IRQ_STAT);
         if (reg_val)
+        {
             FSATA_WRITE_REG32(port_base_addr, FSATA_PORT_IRQ_STAT, reg_val);
+        }
 
         /* clear host corresponding port interrupt status register */
         FSATA_WRITE_REG32(base_addr, FSATA_HOST_IRQ_STAT, BIT(i));
@@ -569,7 +598,9 @@ FError FSataAhciInit(FSataCtrl *instance_p)
         /* register linkup ports */
         reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_STAT);
         if ((reg_val & FSATA_PORT_SCR_STAT_DET_MASK) == FSATA_PORT_SCR_STAT_DET_PHYRDY)
+        {
             instance_p->link_port_map |= BIT(i);
+        }
     }
 
     /* host interrupt enable */
@@ -642,7 +673,7 @@ FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
      */
     if (FSataWaitCmdCompleted(port_base_addr + FSATA_PORT_TFDATA, WAIT_MS_TFD, FSATA_BUSY))
     {
-        FSATA_DEBUG("timeout exit!");
+        FSATA_DEBUG("Timeout exit!");
         return FSATA_ERR_TIMEOUT;
     }
 
@@ -738,7 +769,7 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
 
     if (port >= instance_p->n_ports)
     {
-        FSATA_DEBUG("Invalid port number %d", port);
+        FSATA_DEBUG("Invalid port number %d.", port);
         return FSATA_ERR_INVAILD_PARAMETER;
     }
 
@@ -756,7 +787,7 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
     int prdt_length = FSataAhciFillCmdTablePrdt(instance_p, port, buf, buf_len);
     if (prdt_length == -1)
     {
-        FSATA_ERROR("FSataAhciFillCmdTablePrdt failed, buf_len = %d\n", buf_len);
+        FSATA_ERROR("FSataAhciFillCmdTablePrdt failed, buf_len = %d.\n", buf_len);
         return FSATA_ERR_INVAILD_PARAMETER;
     }
 
@@ -771,14 +802,16 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
 
     /* set tag bit in SACT register before write CI register when use native cmd */
     if (is_ncq == TRUE)
+    {
         FSATA_WRITE_REG32(port_base_addr, FSATA_PORT_SCR_ACT, FSATA_PORT_SCR_ACT_ENABLE);
+    }
 
     /* send cmd */
     FSATA_WRITE_REG32(port_base_addr, FSATA_PORT_CMD_ISSUE, FSATA_PORT_CMD_ISSUE_ENABLE);
 
     if (FSataWaitCmdCompleted(port_base_addr + FSATA_PORT_CMD_ISSUE, WAIT_MS_DATAIO, FSATA_PORT_CMD_ISSUE_ENABLE))
     {
-        FSATA_ERROR("timeout exit!");
+        FSATA_ERROR("Timeout exit!");
         return FSATA_ERR_TIMEOUT;
     }
 
@@ -816,9 +849,13 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
     fis[0] = FSATA_FIS_REG_HOST_TO_DEVICE;/* fis type */
     fis[1] = FSATA_FIS_REG_HOST_TO_DEVICE_C; /* C and PM Port */
     if (is_ncq == FALSE)
-        fis[2] = is_write ? FSATA_CMD_WRITE_EXT : FSATA_CMD_READ_EXT; /* Command */
+    {
+        fis[2] = is_write ? FSATA_CMD_WRITE_EXT : FSATA_CMD_READ_EXT;    /* Command */
+    }
     else
-        fis[2] = is_write ? FSATA_CMD_FPDMA_WRITE : FSATA_CMD_FPDMA_READ; /* Command */
+    {
+        fis[2] = is_write ? FSATA_CMD_FPDMA_WRITE : FSATA_CMD_FPDMA_READ;    /* Command */
+    }
 
     while (blk_cnt)
     {
@@ -867,7 +904,7 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
                               buffer, transfer_size, is_ncq, is_write);
         if (ret)
         {
-            FSATA_ERROR("scsi_ahci: SCSI command failure. ret = %#x", ret);
+            FSATA_ERROR("scsi_ahci: SCSI command failure. ret = %#x.", ret);
             return FSATA_ERR_OPERATION;
         }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h
index d901b344851..74f67ac0111 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h
@@ -14,24 +14,27 @@
  * FilePath: fsata.h
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:05:24
- * Description:  This files is for sata ctrl function definition
+ * Description:  This file is for sata ctrl function definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/9/9     improve functions
+ * 1.2   wangxiaodong  2022/10/21   improve functions
  */
 
-#ifndef BSP_DRIVERS_FSATA_H
-#define BSP_DRIVERS_FSATA_H
+#ifndef FSATA_H
+#define FSATA_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fkernel.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
-/***************************** Include Files *********************************/
-#include "ftypes.h"
-#include "ferror_code.h"
-#include "fkernel.h"
 
 #define FSATA_SUCCESS               FT_SUCCESS
 #define FSATA_ERR_INVAILD_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1)
@@ -54,7 +57,7 @@ extern "C"
 
 #define FSATA_AHCI_CMD_TABLE_SIZE       (FSATA_AHCI_CMD_TABLE_HEADER_SIZE + (FSATA_AHCI_PRTD_ITEM_NUM * FSATA_AHCI_PRTD_ITEM_SIZE))
 #define FSATA_AHCI_PORT_PRIV_DMA_SZ     (FSATA_AHCI_CMD_LIST_HEADER_SIZE * FSATA_AHCI_CMD_LIST_HEADER_NUM + \
-                                        FSATA_AHCI_CMD_TABLE_SIZE + FSATA_AHCI_RX_FIS_SZ)
+        FSATA_AHCI_CMD_TABLE_SIZE + FSATA_AHCI_RX_FIS_SZ)
 
 #define FSATA_AHCI_CMD_ATAPI        BIT(5)
 #define FSATA_AHCI_CMD_WRITE        BIT(6)
@@ -133,9 +136,13 @@ enum
 static inline int FSataIdHasLba48(const u16 *id)
 {
     if ((id[83] & 0xC000) != 0x4000)
+    {
         return 0;
+    }
     if (!FSATA_ID_U64(id, 100))
+    {
         return 0;
+    }
     return id[83] & BIT(10);
 }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_g.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_g.c
index dc90afa6368..f02f0b1060a 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_g.c
@@ -14,11 +14,13 @@
  * FilePath: fsata_g.c
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:03:08
- * Description:  This files is for static config of sata ctrl
+ * Description:  This file is for static config of sata ctrl
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/10/21   improve functions
  */
 
 #include "fparameters.h"
@@ -79,22 +81,22 @@ const FSataConfig FSataPcieConfigTbl[PLAT_AHCI_HOST_MAX_COUNT] =
 #if defined(CONFIG_TARGET_E2000)
 
 /* configs of controller ahci ctrl */
-const FSataConfig FSataControllerConfigTbl[FSATA_INSTANCE_NUM] =
+const FSataConfig FSataControllerConfigTbl[FSATA_NUM] =
 {
     [0] =
     {
-        .instance_id = FSATA_INSTANCE_0,
-        .base_addr = FSATA0_BASEADDR,
+        .instance_id = FSATA0_ID,
+        .base_addr = FSATA0_BASE_ADDR,
         .instance_name = "sata0",
-        .irq_num = FSATA0_IRQNUM     /* Irq number */
+        .irq_num = FSATA0_IRQ_NUM     /* Irq number */
 
     },
     [1] =
     {
-        .instance_id = FSATA_INSTANCE_1,
-        .base_addr = FSATA1_BASEADDR,
+        .instance_id = FSATA1_ID,
+        .base_addr = FSATA1_BASE_ADDR,
         .instance_name = "sata1",
-        .irq_num = FSATA1_IRQNUM     /* Irq number */
+        .irq_num = FSATA1_IRQ_NUM     /* Irq number */
 
     },
 
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.c
index 278636bc93f..54060db1b85 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.c
@@ -14,11 +14,12 @@
  * FilePath: fsata_hw.c
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:03:23
- * Description:  This files is for sata register function
+ * Description:  This file is for sata register function
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.h b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.h
index 39c1b8001fc..cfe76027794 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_hw.h
@@ -14,26 +14,27 @@
  * FilePath: fsata_hw.h
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:03:41
- * Description:  This files is for ctrl of sata functions
+ * Description:  This file is for ctrl of sata functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/10/21   improve functions
  */
 
-#ifndef BSP_DRIVERS_FSATA_HW_H
-#define BSP_DRIVERS_FSATA_HW_H
+#ifndef FSATA_HW_H
+#define FSATA_HW_H
+
+#include "fkernel.h"
+#include "ftypes.h"
+#include "fio.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-#include "fkernel.h"
-#include "ftypes.h"
-#include "fio.h"
-
 /************************** Constant Definitions *****************************/
 /* SATA register definitions */
 
@@ -121,7 +122,7 @@ extern "C"
 #define FSATA_PORT_IRQ_D2H_REG_FIS  BIT(0) /* D2H Register FIS rx'd */
 
 #define FSATA_PORT_IRQ_FREEZE   FSATA_PORT_IRQ_CONNECT | FSATA_PORT_IRQ_SDB_FIS | \
-                                FSATA_PORT_IRQ_D2H_REG_FIS | FSATA_PORT_IRQ_PIOS_FIS
+    FSATA_PORT_IRQ_D2H_REG_FIS | FSATA_PORT_IRQ_PIOS_FIS
 
 #define FSATA_PORT_SCR_ACT_ENABLE    BIT(0) /* Port Serial ATA Active */
 #define FSATA_PORT_CMD_ISSUE_ENABLE  BIT(0) /* Port Command Issue enable */
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_intr.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_intr.c
index 56fc9dc4012..066f54bcbdb 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_intr.c
@@ -14,18 +14,19 @@
  * FilePath: fsata_intr.c
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:03:57
- * Description:  This files is for intrrupt function of Sata ctrl
+ * Description:  This file is for intrrupt function of Sata ctrl
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/10/21   improve functions
  */
 
 #include "fassert.h"
 #include "fdebug.h"
 #include "fsata.h"
 #include "fsata_hw.h"
-#include "finterrupt.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -60,7 +61,9 @@ void FSataIrqEnable(FSataCtrl *instance_p, u32 int_mask)
     for (i = 0; i < instance_p->n_ports; i++)
     {
         if (!(port & BIT(i)))
+        {
             continue;
+        }
 
         uintptr port_base_addr = instance_p->port[i].port_base_addr;
         FSATA_SETBIT(port_base_addr, FSATA_PORT_IRQ_MASK, int_mask);
@@ -84,7 +87,9 @@ void FSataIrqDisable(FSataCtrl *instance_p, u32 int_mask)
     for (i = 0; i < instance_p->n_ports; i++)
     {
         if (!(port & BIT(i)))
+        {
             continue;
+        }
 
         uintptr port_base_addr = instance_p->port[i].port_base_addr;
 
@@ -110,29 +115,29 @@ FError FSataSetHandler(FSataCtrl *instance_p, u32 irq_type, void *func_pointer,
 
     switch (irq_type)
     {
-    case FSATA_PORT_IRQ_D2H_REG_FIS:
-        instance_p->fsata_dhrs_cb = ((FSataIrqCallBack)(void *)func_pointer);
-        instance_p->dhrs_args = call_back_ref;
-        break;
-
-    case FSATA_PORT_IRQ_SDB_FIS:
-        instance_p->fsata_sdbs_cb = ((FSataIrqCallBack)(void *)func_pointer);
-        instance_p->sdbs_args = call_back_ref;
-        break;
-
-    case FSATA_PORT_IRQ_CONNECT:
-        instance_p->fsata_pcs_cb = ((FSataIrqCallBack)(void *)func_pointer);
-        instance_p->pcs_args = call_back_ref;
-        break;
-
-    case FSATA_PORT_IRQ_PIOS_FIS:
-        instance_p->fsata_pss_cb = ((FSataIrqCallBack)(void *)func_pointer);
-        instance_p->pss_args = call_back_ref;
-        break;
-
-    default:
-        status = (FSATA_ERR_OPERATION);
-        break;
+        case FSATA_PORT_IRQ_D2H_REG_FIS:
+            instance_p->fsata_dhrs_cb = ((FSataIrqCallBack)(void *)func_pointer);
+            instance_p->dhrs_args = call_back_ref;
+            break;
+
+        case FSATA_PORT_IRQ_SDB_FIS:
+            instance_p->fsata_sdbs_cb = ((FSataIrqCallBack)(void *)func_pointer);
+            instance_p->sdbs_args = call_back_ref;
+            break;
+
+        case FSATA_PORT_IRQ_CONNECT:
+            instance_p->fsata_pcs_cb = ((FSataIrqCallBack)(void *)func_pointer);
+            instance_p->pcs_args = call_back_ref;
+            break;
+
+        case FSATA_PORT_IRQ_PIOS_FIS:
+            instance_p->fsata_pss_cb = ((FSataIrqCallBack)(void *)func_pointer);
+            instance_p->pss_args = call_back_ref;
+            break;
+
+        default:
+            status = (FSATA_ERR_OPERATION);
+            break;
     }
     return status;
 }
@@ -162,7 +167,9 @@ void FSataIrqHandler(s32 vector, void *param)
     for (i = 0; i < instance_p->n_ports; i++)
     {
         if (!(port & BIT(i)))
+        {
             continue;
+        }
 
         port_base_addr = instance_p->port[i].port_base_addr;
         irq_state = FSATA_READ_REG32(base_addr, FSATA_HOST_IRQ_STAT);
diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_sinit.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_sinit.c
index 8f0af5c686b..b9cfa41b263 100644
--- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata_sinit.c
@@ -14,11 +14,13 @@
  * FilePath: fsata_sinit.c
  * Date: 2022-02-10 14:55:11
  * LastEditTime: 2022-02-18 09:04:15
- * Description:  This files is for sata static init
+ * Description:  This file is for sata static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/2/10    first release
+ * 1.1   wangxiaodong  2022/10/21   improve functions
  */
 
 /***************************** Include Files *********************************/
@@ -41,7 +43,7 @@
 extern const FSataConfig FSataPcieConfigTbl[PLAT_AHCI_HOST_MAX_COUNT];
 
 #if defined(CONFIG_TARGET_E2000)
-    extern const FSataConfig FSataControllerConfigTbl[FSATA_INSTANCE_NUM];
+    extern const FSataConfig FSataControllerConfigTbl[FSATA_NUM];
 #endif
 
 /*****************************************************************************/
@@ -57,7 +59,7 @@ const FSataConfig *FSataLookupConfig(u32 instance_id, u8 type)
     if (type == FSATA_TYPE_CONTROLLER)
     {
 #if defined(CONFIG_TARGET_E2000)
-        FASSERT(instance_id < FSATA_INSTANCE_NUM);
+        FASSERT(instance_id < FSATA_NUM);
         pconfig = &FSataControllerConfigTbl[instance_id];
 #endif
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/Kconfig b/bsp/phytium/libraries/standalone/drivers/scmi/Kconfig
new file mode 100644
index 00000000000..040726be745
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/Kconfig
@@ -0,0 +1,7 @@
+menu "Scmi Configuration"
+    config ENABLE_SCMI_MHU
+        bool
+        prompt "Use Scmi MHU"
+        default n
+        
+endmenu
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.c
new file mode 100644
index 00000000000..6636ffb4803
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmhu.c
+ * Date: 2022-12-29 18:07:32
+ * LastEditTime: 2022-12-29 18:07:32
+ * Description:  This file is for mhu channel binding
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/04 init
+ */
+
+#include "fassert.h"
+#include "fmhu.h"
+#include "fmhu_hw.h"
+/**
+ * @name: 
+ * @msg: 
+ * @return {*}
+ * @param {FScmiMhu} *instance_p
+ * @param {int} chan
+ */
+void FMhuChanProbe(FScmiMhu *instance_p)
+{
+    FASSERT(instance_p);
+
+    instance_p->tx_complete = FALSE;
+    instance_p->msg_count = 0U;
+
+    instance_p->send_data = FMhuSendData;
+    instance_p->startup = FMhuStartup;
+    instance_p->shutdown = FMhuShutdown;
+    instance_p->last_tx_done = FMhuLastTxDone;
+
+    instance_p->mhu.is_ready = FT_COMPONENT_IS_READY;
+
+    instance_p->startup(instance_p->mhu.config.base_addr);
+    return;
+}
+
+/**
+ * @name: 
+ * @msg: 
+ * @return {*}
+ * @param {FScmiMhu} *instance_p
+ * @param {int} chan
+ */
+void FMhuChanRemove(FScmiMhu *instance_p)
+{
+    FASSERT(instance_p);
+
+    instance_p->tx_complete = TRUE;
+
+    instance_p->send_data = NULL;
+    instance_p->startup = NULL;
+    instance_p->shutdown = NULL;
+    instance_p->last_tx_done = NULL;
+
+    instance_p->mhu.is_ready = 0U;
+
+    instance_p->shutdown(instance_p->mhu.config.base_addr);
+    return;
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.h
new file mode 100644
index 00000000000..304eb0d7712
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmhu.h
+ * Date: 2022-12-29 18:07:43
+ * LastEditTime: 2022-12-29 18:07:43
+ * Description:  This file is for mhu function support and data struct
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/04 init
+ */
+#ifndef FMHU_H
+#define FMHU_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************** Constant Definitions *****************************/
+#define FMHU_SUCCESS          FT_SUCCESS
+#define FMHU_ERR_INVAL_PARM   FT_MAKE_ERRCODE(ErrModBsp, ErrBspMhu, 1)
+#define FMHU_ERR_NOT_READY    FT_MAKE_ERRCODE(ErrModBsp, ErrBspMhu, 2)
+#define FMHU_ERR_TIMEOUT      FT_MAKE_ERRCODE(ErrModBsp, ErrBspMhu, 3)
+#define FMHU_ERR_NOT_SUPPORT  FT_MAKE_ERRCODE(ErrModBsp, ErrBspMhu, 4)
+#define FMHU_ERR_INVAL_STATE  FT_MAKE_ERRCODE(ErrModBsp, ErrBspMhu, 5)
+
+#define FSCMI_MBOX_TX_QUEUE_LEN 20
+
+typedef void (*FMhuEvtHandler)(void *instance_p, void *param);
+
+typedef struct
+{
+    u32         mhu_chan_id;    /* Mhu chan id */
+    uintptr     base_addr;      /* Device base address */
+    u32         irq_num;        /* Device intrrupt id */
+    u32         irq_prority;    /* Device intrrupt priority */
+    u32         work_mode;      /* Device work mode intr or poll */
+} FMhuConfig;
+
+typedef struct
+{
+    FMhuConfig      config;     /* Current active configs */
+    u32             is_ready;   /* Device is initialized and ready */
+    volatile u32    status;     /* Mhu working or idle */
+    FMhuEvtHandler  slot_msg_recv;/* for interrupt handle */
+} FMhu;
+
+typedef struct
+{
+    FMhu            mhu;/* mbox object instance */
+    boolean         tx_complete ;
+    /* send message */
+    u32             msg_count, msg_free;
+    void            *msg_data[FSCMI_MBOX_TX_QUEUE_LEN];
+    void            *payload; /* share memory */
+    void            (*send_data)( uintptr addr , u32 chan);
+    void            (*startup)( uintptr addr );
+    void            (*shutdown)( uintptr addr );
+    u32             (*last_tx_done)( uintptr addr );
+} FScmiMhu;
+
+void FMhuGetDefConfig(FMhuConfig *config_p,u32 chan_id);
+void FMhuChanProbe(FScmiMhu *instance_p);
+void FMhuChanRemove(FScmiMhu *instance_p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_g.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_g.c
new file mode 100644
index 00000000000..355418e3649
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_g.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmhu_g.c
+ * Date: 2022-12-29 16:41:46
+ * LastEditTime: 2022-12-29 16:41:46
+ * Description:  This file is for get default configs
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2022/12/30 init
+ */
+
+#include <string.h>
+#include "ftypes.h"
+#include "fparameters.h"
+#include "fmhu.h"
+#include "fassert.h"
+
+void FMhuGetDefConfig(FMhuConfig *config_p,u32 chan_id)
+{
+    FASSERT(NULL != config_p);
+
+    memset(config_p, 0, sizeof(config_p));
+    config_p->base_addr = FSCMI_MHU_BASE_ADDR;
+    config_p->irq_num = FSCMI_MHU_IRQ_NUM;
+    config_p->mhu_chan_id = chan_id;
+    config_p->work_mode = TRUE;
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_hw.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_hw.h
new file mode 100644
index 00000000000..0e7c8c2d76c
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_hw.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmhu_hw.h
+ * Date: 2022-12-29 16:40:54
+ * LastEditTime: 2022-12-29 16:40:55
+ * Description:  This file is for mhu hardware define
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/12/30 init
+ */
+#ifndef FMHU_HW_H
+#define FMHU_HW_H
+
+#include "fio.h"
+#include "fkernel.h"
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fassert.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define AP_OS_STAT_OFFSET 	0x100
+#define AP_OS_SET_OFFSET	    0x108
+#define AP_OS_CLR_OFFSET	    0x110
+
+#define AP_OS_INT_OFFSET         0x508
+
+#define FMHU_DATA_MASK GENMASK(31, 0)
+
+#define FMHU_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
+#define FMHU_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)(reg_offset), (u32)(reg_value))
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define FMHU_READ_STAT(addr) (u32)(FMHU_DATA_MASK & FMHU_READ_REG32(addr, AP_OS_STAT_OFFSET))
+
+#define FMHU_READ_SECU(addr) (u32)((u32)(1U << 31) & FMHU_READ_REG32(addr, AP_OS_STAT_OFFSET))
+
+#define FMHU_WRITE_SET(addr, dat) FMHU_WRITE_REG32((addr), AP_OS_SET_OFFSET, (dat))
+
+#define FMHU_WRITE_CLR(addr, dat) FMHU_WRITE_REG32((addr), AP_OS_CLR_OFFSET, (dat))
+
+#define FMHU_WRITE_INT(addr, dat) FMHU_WRITE_REG32((addr), AP_OS_INT_OFFSET, (dat))
+
+/************************** Function Prototypes ******************************/
+
+/**
+ * @name: FMhuGetChanStatus
+ * @msg: Mhu get channel status
+ * @return {*}
+ * @param {uintptr} addr
+ */
+static inline u32 FMhuGetChanStatus(uintptr addr)
+{
+    FASSERT(addr);
+
+    return FMHU_READ_STAT(addr);
+}
+
+/**
+ * @name: FMhuSendData
+ * @msg: Mhu write the AP_OS_SET register to send share memory Data
+ * @return {*}
+ * @param {uintptr} addr
+ * @param {u32} chan
+ */
+static inline void FMhuSendData(uintptr addr, u32 chan)
+{
+    FASSERT(addr);
+
+    FMHU_WRITE_SET(addr, chan);
+
+    return;
+}
+
+/**
+ * @name: FMhuStartup
+ * @msg: 
+ * @return {*}
+ * @param {uintptr} addr
+ */
+static inline void FMhuStartup(uintptr addr)
+{
+    FASSERT(addr);
+
+    u32 val;
+
+    val = FMHU_READ_STAT(addr);
+    FMHU_WRITE_CLR(addr, val);
+
+    /* irq set */
+
+    return;
+}
+
+/**
+ * @name: FMhuShutdown
+ * @msg: 
+ * @return {*}
+ * @param {uintptr} addr
+ */
+static inline void FMhuShutdown(uintptr addr)
+{
+    FASSERT(addr);
+
+    FMHU_WRITE_INT(addr,1);
+
+    return;
+}
+
+/**
+ * @name: FMhuLastTxDone
+ * @msg: 
+ * @return {*}
+ * @param {uintptr} addr
+ */
+static inline u32 FMhuLastTxDone(uintptr addr)
+{
+    FASSERT(addr);
+
+    return (FMHU_READ_SECU(addr) == (u32)(1U << 31));
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/board/common/fsmp.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_intr.c
similarity index 54%
rename from bsp/phytium/libraries/standalone/board/common/fsmp.h
rename to bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_intr.c
index b0ee12f3398..8c661fd6dd4 100644
--- a/bsp/phytium/libraries/standalone/board/common/fsmp.h
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fmhu_intr.c
@@ -1,34 +1,23 @@
 /*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
  * All Rights Reserved.
- *
- * This program is OPEN SOURCE software: you can redistribute it and/or modify it
- * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
- * either version 1.0 of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
  * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
- * See the Phytium Public License for more details.
- *
- *
- * FilePath: fsmp.h
- * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-17 17:58:18
- * Description:  This files is for
- *
- * Modify History:
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fmhu_intr.c
+ * Date: 2022-12-29 16:42:08
+ * LastEditTime: 2022-12-29 16:42:08
+ * Description:  This file is for intr mode
+ * 
+ * Modify History: 
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 0.0.1 liushengming 2022/12/29 create file
  */
-
-
-#ifndef BSP_BOARD_COMMON_SMP_H
-#define BSP_BOARD_COMMON_SMP_H
-
-#include "ftypes.h"
-
-void SpinLockInit(unsigned long  global_addr);
-void SpinLock(void);
-void SpinUnlock(void);
-
-#endif // DEBUG
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.c
new file mode 100644
index 00000000000..e26af9b62d2
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.c
@@ -0,0 +1,347 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi.c
+ * Date: 2022-12-30 18:32:28
+ * LastEditTime: 2022-12-30 18:32:28
+ * Description:  This file is for scmi protocol support
+ * 
+ * Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ * 1.0 liushengming 2023/01/30 init
+ */
+#include <string.h>
+#include "fscmi.h"
+#include "fmhu_hw.h"
+#include "fio.h"
+#include "fkernel.h"
+#include "fdebug.h"
+#include "fsleep.h"
+#include "fassert.h"
+#include "fscmi_base.h"
+#include "fscmi_sensors.h"
+#include "fscmi_perf.h"
+
+#define FSCMI_DEBUG_TAG "FSCMI"
+#define FSCMI_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSCMI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_WARN(format, ...)   FT_DEBUG_PRINT_W(FSCMI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_INFO(format, ...)    FT_DEBUG_PRINT_I(FSCMI_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSCMI_DEBUG_TAG, format, ##__VA_ARGS__)
+
+#define MSG_ID_MASK		GENMASK(7, 0)
+#define MSG_TYPE_MASK		GENMASK(9, 8)
+#define MSG_PROTOCOL_ID_MASK	GENMASK(17, 10)
+#define MSG_TOKEN_ID_MASK	GENMASK(27, 18)
+
+
+FError FScmiDoTransport(FScmi *instance_p,struct FScmiTransferInfo *info, u32 protocol_index)
+{
+    FError ret;
+    u32 tx_done = 0;
+    u32 chan_status = 0;
+    u32 delay_out = 0;
+    FMhuConfig *mhu_config = &instance_p->scmi_mhu.mhu.config;
+
+    /* write data to share buffer */
+    ret = FScmiProtocolTxPrepare(instance_p,protocol_index);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("%s,FScmiProtocolTxPrepare is error", __FUNCTION__);
+        return ret;
+    }
+
+    if(instance_p->scmi_mhu.send_data)
+    {
+        instance_p->scmi_mhu.send_data(mhu_config->base_addr,mhu_config->mhu_chan_id);
+    }
+    chan_status = FMhuGetChanStatus(mhu_config->base_addr);
+    /* 等待发送完成 */
+    while (tx_done == 0)
+    {   
+        tx_done = instance_p->scmi_mhu.last_tx_done(mhu_config->base_addr);
+        if (tx_done == 1)
+        {
+            break;
+        }
+        else
+        {
+            fsleep_millisec(10);
+            delay_out++;
+            if (delay_out == 10)
+            {
+                FSCMI_ERROR("Send error,addr:0x%x,last_tx_done:0x%x",mhu_config->base_addr,tx_done);
+                return FSCMI_ERROR_WAIT_MBOX_TIMEOUT;
+            }
+        }
+    }
+
+    /* 等待数据接收完成 */
+    /* poll way */
+
+    if(info->poll_completion)
+    {
+        while(FScmiProtocolPollDone(instance_p,protocol_index) != TRUE);
+        /* get data */
+        ret = FScmiFetchResponse(instance_p,protocol_index);
+        if(ret != FT_SUCCESS)
+        {
+            return FSCMI_ERROR_FETCH_RESPONSE;
+        }
+    }
+    else
+    {
+        /* interrupt way */
+    }
+
+    return FT_SUCCESS;
+}
+/**
+ * @name: 
+ * @msg: 
+ * @return {*}
+ * @param {u8} pro_id
+ * @param {u32} *protocol_index
+ */
+static FError FScmiProtocolMapping(const u8 pro_id,u32 *protocol_index)
+{
+    switch (pro_id)
+    {
+        case SCMI_PROTOCOL_BASE:
+        {
+            *protocol_index = BASE_PROTOCOL_INDEX;
+            return FT_SUCCESS;
+        }
+        case SCMI_PROTOCOL_PERF:
+        {
+            *protocol_index = PERF_DOMAIN_INDEX;
+            return FT_SUCCESS;
+        }
+        case SCMI_PROTOCOL_SENSOR:
+        {
+            *protocol_index = SENSOR_MANAGEMENT_INDEX;
+            return FT_SUCCESS;
+        }
+        default:
+        return FSCMI_ERROR_NOT_FOUND;
+    }
+    return FT_SUCCESS;
+}
+
+struct FScmiTransferInfo *FScmiGetInfo(FScmi *instance_p, u8 pro_id)
+{
+    u32 index_id = 0;
+    FError ret;
+    ret = FScmiProtocolMapping(pro_id, &index_id);
+    if (ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("%s,Protocol mapping error", __FUNCTION__);
+        return NULL;
+    }
+
+    return  &instance_p->info[index_id]; 
+}
+
+FError FScmiFetchResponse(FScmi *instance_p, u8 pro_id)
+{
+    struct FScmiSharedMem *mem =(struct FScmiSharedMem *) instance_p->config.share_mem;
+    struct FScmiTransferInfo *trans_info;
+    u32 index_id = 0;
+    FError ret;
+    ret = FScmiProtocolMapping(pro_id, &index_id);
+    if (ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("%s,Protocol mapping error", __FUNCTION__);
+        return ret;
+    }
+    trans_info = &instance_p->info[index_id];
+    trans_info->hdr.status = FtIn32((uintptr)mem->msg_payload);
+    /* Skip the length of header and statues in payload area i.e 8 bytes*/
+    trans_info->rx.len = min(trans_info->rx.len, FtIn32((uintptr)(&mem->length)) - 8);
+
+    /* Take a copy to the rx buffer.. */
+
+    if(trans_info->rx.len)
+    {
+        for (u32 i = 0; i < trans_info->rx.len; i++)
+        {
+            trans_info->rx.buf[i] = mem->msg_payload[i+4];
+        }
+    }
+
+    return FT_SUCCESS;
+}
+
+FError FScmiProtocolPollDone(FScmi *instance_p,u8 pro_id)
+{
+    struct FScmiSharedMem  *mem =(struct FScmiSharedMem *) instance_p->config.share_mem;
+    u32 index_id = 0;
+    FError ret;
+    ret = FScmiProtocolMapping(pro_id, &index_id);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("%s,Protocol mapping error",__FUNCTION__);
+        return FALSE;
+    }
+
+    return FtIn32((uintptr)(&mem->channel_status)) &
+        (SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR |
+        SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE);
+}
+
+
+static u32 FScmiPackHeader(struct FScmiMsgHdr *hdr_p)
+{
+
+    return FIELD_PREP(MSG_ID_MASK, hdr_p->id) |
+        FIELD_PREP(MSG_TOKEN_ID_MASK, hdr_p->seq) |
+        FIELD_PREP(MSG_PROTOCOL_ID_MASK, hdr_p->protocol_id);
+}
+
+FError FScmiProtocolTxPrepare(FScmi *instance_p,u8 pro_id)
+{
+    struct FScmiSharedMem  *mem =(struct FScmiSharedMem *) instance_p->config.share_mem;
+    struct FScmiTransferInfo *trans_info;
+    u32 index_id = 0;
+    u32 time_out;
+    FError ret;
+    static int is_init = 0;
+    ret = FScmiProtocolMapping(pro_id, &index_id);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("Protocol mapping error");
+        return ret;
+    }
+    trans_info = &instance_p->info[index_id];
+    if(!is_init)
+    {
+        FtOut32((uintptr)&mem->channel_status,SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE);
+        is_init = 1;
+    }
+
+    while (0 == (FtIn32((uintptr)&mem->channel_status) &SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE))
+    {
+        time_out++;
+        fsleep_millisec(10);
+        if (time_out == 10)
+        {
+            FSCMI_ERROR("Memory of scmi status error,please check mhu channel set or memory addrs...");
+            return FSCMI_ERROR_WAIT_MEM_TIMEOUT;
+        }
+    }
+
+    FtOut32((uintptr)&mem->channel_status,0);
+    FtOut32((uintptr)&mem->flags, 0);
+    FtOut32((uintptr)&mem->length, sizeof(mem->msg_header) + trans_info->tx.len);
+    FtOut32((uintptr)&mem->msg_header,FScmiPackHeader(&trans_info->hdr));
+
+    if(trans_info->tx.len)
+    {
+        for (u32 i = 0; i < trans_info->tx.len; i++)
+        {
+            mem->msg_payload[i] = trans_info->tx.buf[i];
+        }
+    }
+
+    return FT_SUCCESS;
+}
+
+FError FScmiMessageInit(FScmi *instance_p,u8 msg_id,u8 pro_id,u32 tx_size,u32 rx_size,u8 *tx_buffer)
+{
+    u32 index_id = 0;
+    FError ret;
+    struct FScmiTransferInfo *trans_info;
+
+    ret = FScmiProtocolMapping(pro_id, &index_id);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("Protocol mapping error");
+        return ret;
+    }
+    trans_info = &instance_p->info[index_id];
+
+    /* 检查 tx_size / rx_size 的长度*/
+    if(tx_size > FSCMI_MSG_SIZE || rx_size > FSCMI_MSG_SIZE)
+    {
+        return FSCMI_ERROR_RANGE;
+    }
+
+    if(tx_size > 0 && tx_buffer == NULL)
+    {
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* init hdr */
+    trans_info->hdr.seq = pro_id + msg_id ;
+    trans_info->hdr.id = msg_id;
+    trans_info->hdr.protocol_id = pro_id;
+
+    /* init buffer */
+    trans_info->tx.len = tx_size;
+    if(tx_size && tx_buffer)
+    {
+        memcpy(trans_info->tx.buf, tx_buffer, tx_size);
+    }
+
+    trans_info->rx.len = rx_size ?  :FSCMI_MSG_SIZE;/*  */
+    trans_info->poll_completion = TRUE;
+
+    return FT_SUCCESS;
+    
+}
+
+
+FError FScmiCfgInitialize(FScmi *instance_p, const struct FScmiConfig *config)
+{
+    /* first init  */
+    instance_p->config = *config;
+    
+    FError ret;
+    
+    /*  Second choice is the mbox driver */
+    if (instance_p->config.mbox_type == FSCMI_MBOX_MHU_TYPE)
+    {
+        FMhuChanProbe(&instance_p->scmi_mhu);
+    }
+    else
+    {
+        return FSCMI_ERROR_TYPE;
+    }
+    
+    instance_p->config.share_mem = config->share_mem;
+
+    /* The third initializes the base protocol */
+    ret = FScmiBaseInit(instance_p);
+    if (instance_p->revision.version != FSCMI_VERSION)
+    {
+        return FSCMI_ERROR_VERSION;
+    }
+    
+    ret = FScmiSensorInit(instance_p);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("FScmiSensorInit init error.Error code:0x%x.",ret);
+        return FSCMI_ERROR_INIT;
+    }
+    
+    ret = FScmiPerfInit(instance_p);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_ERROR("FScmiPerfInit init error.Error code:0x%x.",ret);
+        return FSCMI_ERROR_INIT;
+    }
+    /* Finally confirm the completion status */
+    instance_p->is_ready = FT_COMPONENT_IS_READY;
+
+    return FT_SUCCESS;
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.h
new file mode 100644
index 00000000000..8e3e65f1bda
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi.h
+ * scmi.h
+ * Date: 2022-12-30 18:32:33
+ * LastEditTime: 2022-12-30 18:32:33
+ * Description:  This file is for scmi protocol struct and application interface
+ * 
+ * Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ * 1.0 liushengming 2023/01/31 init
+ */
+
+
+#ifndef FSCMI_H
+#define FSCMI_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fmhu.h"
+#include "fparameters.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* error code */
+
+#define FSCMI_ERROR_TYPE				FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x1u)
+#define FSCMI_ERROR_RANGE				FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x2u)
+#define FSCMI_ERROR_NOT_FOUND			FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x3u)
+#define FSCMI_ERROR_NULL_POINTER		FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x4u)
+#define FSCMI_ERROR_WAIT_MBOX_TIMEOUT	FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x5u)
+#define FSCMI_ERROR_WAIT_MEM_TIMEOUT	FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x6u)
+#define FSCMI_ERROR_FETCH_RESPONSE		FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x7u)
+#define FSCMI_ERROR_REQUEST				FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x8u)
+#define FSCMI_ERROR_VERSION				FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0x9u)
+#define FSCMI_ERROR_INIT				FT_CODE_ERR(ErrModBsp, ErrBspScmi, 0xau)
+
+#define FSCMI_MBOX_MHU_TYPE 0
+#define FSCMI_VERSION		0x20000
+/*
+ * SCMI specification requires all parameters, message headers, return
+ * arguments or any protocol data to be expressed in little endian
+ * format only.
+ */
+struct FScmiSharedMem {
+	u32 reserved;
+	u32 channel_status;
+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_ERROR	BIT(1)
+#define SCMI_SHMEM_CHAN_STAT_CHANNEL_FREE	BIT(0)
+	u32 reserved1[2];
+	u32 flags;
+#define SCMI_SHMEM_FLAG_INTR_ENABLED	BIT(0)
+	u32 length;
+	u32 msg_header;
+	u8 msg_payload[0];
+};
+
+enum FScmiStdProtocol {
+	SCMI_PROTOCOL_BASE = 0x10,
+	SCMI_PROTOCOL_POWER = 0x11,
+	SCMI_PROTOCOL_SYSTEM = 0x12,
+	SCMI_PROTOCOL_PERF = 0x13,
+	SCMI_PROTOCOL_CLOCK = 0x14,
+	SCMI_PROTOCOL_SENSOR = 0x15,
+};
+
+enum FScmiProtocolIndex
+{
+    BASE_PROTOCOL_INDEX ,
+	PERF_DOMAIN_INDEX ,
+    SENSOR_MANAGEMENT_INDEX ,
+    FSCMI_SUPPORT_PROTOCOL_NUM ,
+};
+
+/* base protocol */
+struct FScmiRevisionInfo 
+{
+    u32 version;
+    u16 major_ver;
+    u16 minor_ver;
+	u8 num_protocols;
+	u8 num_agents;
+	u32 impl_ver;
+	char vendor_id[FSCMI_MAX_STR_SIZE];
+	char sub_vendor_id[FSCMI_MAX_STR_SIZE];
+};
+
+/* Sensor protocol  */
+struct FScmiSensorInfo {
+	u32 id;
+	u8 type;
+	char name[FSCMI_MAX_STR_SIZE];
+};
+
+struct FScmiSensorsInfo {
+	u32 version;
+	u16 major_ver;
+    u16 minor_ver;
+	u32 num_sensors;
+	u32 max_requests;
+	u64 reg_addr;
+	u32 reg_size;
+	struct FScmiSensorInfo sensor_info[FSCMI_MAX_NUM_SENSOR];/* TS0 TS1 */
+};
+
+/* Performance domain protocol */
+
+struct FScmiOpp {
+	u32 perf_val;
+	u32 power;
+	u32 trans_latency_us;
+};
+
+struct FPerfDomInfo {
+	boolean set_limits;
+	boolean set_perf;
+	boolean perf_limit_notify;
+	boolean perf_level_notify;
+	u32 opp_count;
+	u32 sustained_freq_khz;
+	u32 sustained_perf_level;
+	u32 mult_factor;
+	char name[FSCMI_MAX_STR_SIZE];
+	struct FScmiOpp opp[FSCMI_MAX_OPPS];
+};
+
+struct FScmiPerfInfo {
+	u32 version;
+    u16 major_ver;
+    u16 minor_ver;
+	u32 num_domains;
+	boolean power_scale_mw;
+	u64 stats_addr;
+	u32 stats_size;
+	struct FPerfDomInfo dom_info[FSCMI_MAX_PERF_DOMAINS];
+};
+
+/* Scmi massage package */
+struct FScmiMsgHdr 
+{
+	u8 id;              /* message id   */
+	u8 protocol_id;     /* protocol id */
+	u16 seq;            /* message token */ 
+	u32 status;         /* protocal status */
+};
+
+struct FScmiMsg
+{
+	u8 buf[FSCMI_MSG_SIZE];          /* buffer in normal memory */
+	u32 len;        /* buffer length */
+};
+
+struct FScmiTransferInfo 
+{
+    struct FScmiMsgHdr hdr ; /* Message(Tx/Rx) header */
+    struct FScmiMsg tx ;
+    struct FScmiMsg rx ;
+    boolean poll_completion;
+};
+
+/* Scmi protocol struct */
+struct FScmiConfig
+{
+	uintptr share_mem;	/* Chan transport protocol shared memory */
+	u32 mbox_type;      /* select mbox driver */
+};
+
+typedef struct
+{
+    u32 is_ready; /* Device is ininitialized and ready*/
+    struct FScmiConfig config;
+    struct FScmiRevisionInfo revision;
+	struct FScmiSensorsInfo sensors;
+	struct FScmiPerfInfo perf;
+	struct FScmiTransferInfo info[FSCMI_SUPPORT_PROTOCOL_NUM];
+	u8 protocols_imp[FSCMI_MAX_PROTOCOLS_IMP];/* List of protocols implemented, currently maximum of FSCMI_MAX_PROTOCOLS_IMP elements allocated by the base protocol */
+	FScmiMhu scmi_mhu;
+} FScmi;
+
+/* Base protocol function */
+FError FScmiCfgInitialize(FScmi *instance_p, const struct FScmiConfig *config);
+FError FScmiMessageInit(FScmi *instance_p, u8 msg_id, u8 pro_id, u32 tx_size, u32 rx_size, u8 *tx_buffer);
+FError FScmiProtocolTxPrepare(FScmi *instance_p, u8 pro_id);
+FError FScmiProtocolPollDone(FScmi *instance_p, u8 pro_id);
+FError FScmiFetchResponse(FScmi *instance_p, u8 pro_id);
+struct FScmiTransferInfo *FScmiGetInfo(FScmi *instance_p, u8 pro_id);
+FError FScmiDoTransport(FScmi *instance_p, struct FScmiTransferInfo *info, u32 protocol_index);
+/* Sensor protocol function */
+FError FScmiSensorGetTemp(FScmi *instance_p, u32 sensor_id,s64 *temp);
+/* Performance domain function */
+FError FScmiDvfsFreqSet(FScmi *instance_p, u32 domain, u64 freq, boolean poll);
+FError FScmiDvfsFreqGet(FScmi *instance_p, u32 domain, u64 *freq, boolean poll);
+u64 FScmiPerfGetOppFreq(FScmi *instance_p, u32 domain, u32 opp_num);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.c
new file mode 100644
index 00000000000..75e7e9168c6
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_base.c
+ * Date: 2022-12-31 21:38:31
+ * LastEditTime: 2022-12-31 21:47:30
+ * Description:  This file is for base protocol
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/12 init
+ */
+
+#include <string.h>
+#include "fscmi.h"
+#include "fscmi_base.h"
+#include "fio.h"
+#include "fdebug.h"
+#include "fsleep.h"
+#include "ftypes.h"
+#include "fswap.h"
+#include "fkernel.h"
+
+#define FSCMI_BASE_DEBUG_TAG "FSCMI_BASE"
+#define FSCMI_BASE_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSCMI_BASE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_BASE_WARN(format, ...)   FT_DEBUG_PRINT_W(FSCMI_BASE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_BASE_INFO(format, ...)    FT_DEBUG_PRINT_I(FSCMI_BASE_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_BASE_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSCMI_BASE_DEBUG_TAG, format, ##__VA_ARGS__)
+
+struct FScmiBaseAttributes {
+	u8 num_protocols;
+	u8 num_agents;
+	u16 reserved;
+};
+
+static FError FScmiBaseGetVersion(FScmi *instance_p,u32  *rev_info)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, FSCMI_BASE_PROTOCOL_VERSION, SCMI_PROTOCOL_BASE, 0, sizeof(*rev_info),info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Transport package error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    *rev_info = FtIn32((uintptr)info->rx.buf);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiBaseGetVendor(FScmi *instance_p,boolean sub_vendor)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    u8 cmd;
+    char *vendor_id;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    if (sub_vendor) {
+		cmd = FSCMI_BASE_PROTOCOL_DISCOVER_SUB_VENDOR;
+		vendor_id = instance_p->revision.sub_vendor_id;
+	} else {
+		cmd = FSCMI_BASE_PROTOCOL_DISCOVER_VENDOR;
+		vendor_id = instance_p->revision.vendor_id;
+	}
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, cmd, SCMI_PROTOCOL_BASE, 0, FSCMI_MAX_STR_SIZE,info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Transport package error error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    memcpy(vendor_id,info->rx.buf,FSCMI_MAX_STR_SIZE);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiBaseGetAttributes(FScmi *instance_p, u8 *num_protocols, u8 *num_agents)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiBaseAttributes *attr_info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, FSCMI_BASE_PROTOCOL_ATTRIBUTES, SCMI_PROTOCOL_BASE, 0, sizeof(*attr_info),info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Transport package error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    attr_info = (struct FScmiBaseAttributes *)info->rx.buf;
+    instance_p->revision.num_protocols = attr_info->num_protocols;
+	instance_p->revision.num_agents = attr_info->num_agents;
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiBaseGetImplementVersion(FScmi *instance_p, u32 *impl_ver)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiBaseAttributes *attr_info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, FSCMI_BASE_PROTOCOL_DISCOVER_IMPLEMENTATION_VERSION, SCMI_PROTOCOL_BASE, 0, sizeof(*impl_ver),info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Transport package error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    *impl_ver = FtIn32((uintptr)info->rx.buf);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiBaseGetImplementList(FScmi *instance_p , u8 *protocols_imp)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiBaseAttributes *attr_info;
+
+    u32 *num_skip, *num_ret;
+    u8 *list;
+    u32 tot_num_ret = 0, loop_num_ret;
+    u32 loop;
+    
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, FSCMI_BASE_PROTOCOL_DISCOVER_LIST_PROTOCOLS, SCMI_PROTOCOL_BASE, sizeof(*num_skip), 0,info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    num_skip = (u32 *)info->tx.buf;
+	num_ret = (u32 *)info->rx.buf;
+    list = info->rx.buf + sizeof(num_ret);
+
+    do {
+		/* Set the number of protocols to be skipped/already read */
+		*num_skip = tot_num_ret;
+
+		ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+        if(ret != FT_SUCCESS)
+        {
+            FSCMI_BASE_ERROR("Transport package error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+            return ret;
+        }
+
+		loop_num_ret = (*num_ret);
+
+        if (tot_num_ret + loop_num_ret > FSCMI_MAX_PROTOCOLS_IMP)
+        {
+            FSCMI_BASE_ERROR("No. of Protocol > MAX_PROTOCOLS_IMP");
+			break;
+        }
+
+        for (loop = 0; loop < loop_num_ret; loop++)
+			protocols_imp[tot_num_ret + loop] = *(list + loop);
+
+		tot_num_ret += loop_num_ret;
+	} while (loop_num_ret);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiBaseGetAgent(FScmi *instance_p,int id,char *name)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiBaseAttributes *attr_info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
+    if (info == NULL)
+    {
+        FSCMI_BASE_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, FSCMI_BASE_PROTOCOL_DISCOVER_AGENT, SCMI_PROTOCOL_BASE, sizeof(u32), FSCMI_MAX_STR_SIZE,info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    *info->tx.buf = id;
+    
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_BASE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Transport package error ,protocol id is %d",SCMI_PROTOCOL_BASE);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    memcpy(name, info->rx.buf, FSCMI_MAX_STR_SIZE);
+
+    return FT_SUCCESS;
+}
+
+/**
+ * @name: FScmiBaseInit
+ * @msg: Base protocol get SCMI support information
+ * @return {FError}             返回值
+ * @param {FScmi} *instance_p   scmi协议实例
+ */
+FError FScmiBaseInit(FScmi *instance_p)
+{
+    FError ret;
+    char name[FSCMI_MAX_STR_SIZE];
+    int id;
+
+    /* first get PROTOCOL_VERSION FSCMI_BASE_PROTOCOL_VERSION*/
+    ret = FScmiBaseGetVersion(instance_p,&instance_p->revision.version);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    /* FSCMI_BASE_PROTOCOL_ATTRIBUTES */
+    ret = FScmiBaseGetAttributes(instance_p,&instance_p->revision.num_protocols,&instance_p->revision.num_agents);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get num_protocols,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    /* FSCMI_BASE_PROTOCOL_DISCOVER_VENDOR and FSCMI_BASE_PROTOCOL_DISCOVER_SUB_VENDOR */
+    ret = FScmiBaseGetVendor(instance_p,FALSE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get major_ver,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    ret = FScmiBaseGetVendor(instance_p,TRUE);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get major_ver,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    /* FSCMI_BASE_PROTOCOL_DISCOVER_IMPLEMENTATION_VERSION */
+    ret = FScmiBaseGetImplementVersion(instance_p,&instance_p->revision.impl_ver);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get impl_ver,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    /* FSCMI_BASE_PROTOCOL_DISCOVER_LIST_PROTOCOLS */
+    ret = FScmiBaseGetImplementList(instance_p,instance_p->protocols_imp);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_BASE_ERROR("Can't get vendor_id,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+
+    instance_p->revision.major_ver = (instance_p->revision.version >> 16);
+    instance_p->revision.minor_ver = (instance_p->revision.version & 0xffff);
+
+    FSCMI_BASE_INFO("SCMI Protocol v%d.%d '%s:%s' Firmware version 0x%x\n", instance_p->revision.major_ver,
+                                                                            instance_p->revision.minor_ver,
+                                                                            instance_p->revision.vendor_id,
+                                                                            instance_p->revision.sub_vendor_id,
+                                                                            instance_p->revision.impl_ver);
+
+    FSCMI_BASE_INFO("Found %d protocol(s) %d agent(s)\n",instance_p->revision.num_protocols,instance_p->revision.num_agents);
+
+    /* FSCMI_BASE_PROTOCOL_DISCOVER_AGENT */
+    for ( id = 0; id < instance_p->revision.num_agents; id++)
+    {
+        ret = FScmiBaseGetAgent(instance_p,id,name);
+        if(ret != FT_SUCCESS)
+        {
+            FSCMI_BASE_ERROR("Can't get sub_vendor_id,please check mem_address or chan_id.Error code:0x%x.",ret);
+            return FSCMI_ERROR_REQUEST;
+        }
+        FSCMI_BASE_INFO("Agent %d:%s\n",id,name);
+    }
+
+    return FT_SUCCESS;
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.h
new file mode 100644
index 00000000000..1ae4d46f2da
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_base.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_base.h
+ * Date: 2022-12-31 21:38:51
+ * LastEditTime: 2022-12-31 21:38:51
+ * Description:  This file is for base protocol message
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/04 init
+ */
+
+
+
+#ifndef FSCMI_BASE_PROTOCOL_H
+#define FSCMI_BASE_PROTOCOL_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fparameters.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#define FSCMI_BASE_PROTOCOL_VERSION                            0x0
+#define FSCMI_BASE_PROTOCOL_ATTRIBUTES                         0x1
+#define FSCMI_BASE_PROTOCOL_MESSAGE_ATTRIBUTES                 0x2
+#define FSCMI_BASE_PROTOCOL_DISCOVER_VENDOR                    0x3
+#define FSCMI_BASE_PROTOCOL_DISCOVER_SUB_VENDOR                0x4
+#define FSCMI_BASE_PROTOCOL_DISCOVER_IMPLEMENTATION_VERSION    0x5
+#define FSCMI_BASE_PROTOCOL_DISCOVER_LIST_PROTOCOLS            0x6
+#define FSCMI_BASE_PROTOCOL_DISCOVER_AGENT                     0x7
+#define FSCMI_BASE_PROTOCOL_NOTIFY_ERRORS                      0x8
+#define FSCMI_BASE_PROTOCOL_SET_DEVICE_PERMISSIONS             0x9
+#define FSCMI_BASE_PROTOCOL_SET_PROTOCOL_PERMISSIONS           0xa
+#define FSCMI_BASE_PROTOCOL_RESET_AGENT_CONFIGURATION          0xb
+
+FError FScmiBaseInit(FScmi *instance_p);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
+
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.c
new file mode 100644
index 00000000000..29620e8fc95
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.c
@@ -0,0 +1,543 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_perf.c
+ * Date: 2023-01-18 15:38:15
+ * LastEditTime: 2023-01-18 15:38:17
+ * Description:  This file is for performance domain control
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/31 init
+ */
+
+#include "fscmi_perf.h"
+#include <string.h>
+#include "fscmi.h"
+#include "fscmi_base.h"
+#include "fio.h"
+#include "fdebug.h"
+#include "ftypes.h"
+#include "fswap.h"
+#include "fkernel.h"
+#include "fassert.h"
+
+#define FSCMI_PERF_DEBUG_TAG "FSCMI_PERF"
+#define FSCMI_PERF_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSCMI_PERF_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_PERF_WARN(format, ...)   FT_DEBUG_PRINT_W(FSCMI_PERF_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_PERF_INFO(format, ...)    FT_DEBUG_PRINT_I(FSCMI_PERF_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_PERF_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSCMI_PERF_DEBUG_TAG, format, ##__VA_ARGS__)
+
+static FError FScmiPerfGetVersion(FScmi *instance_p,u32  *rev_info)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_VERSION_GET, SCMI_PROTOCOL_PERF, 0, sizeof(*rev_info),info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    *rev_info = FtIn32((uintptr)info->rx.buf);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfAttributesGet(FScmi *instance_p,struct FScmiPerfInfo *pinfo)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiMsgRespPerfAttributes *attr;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_ATTRIBUTES_GET, SCMI_PROTOCOL_PERF, 0, sizeof(*attr),info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    attr = (struct FScmiMsgRespPerfAttributes *)info->rx.buf;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    u16 flags = attr->flags;
+    pinfo->num_domains = attr->num_domains;
+    pinfo->power_scale_mw = POWER_SCALE_IN_MILLIWATT(flags);
+    pinfo->stats_addr = (u32)attr->stats_addr_low | ((u64)(attr->stats_addr_high) << 32);
+    pinfo->stats_size = attr->stats_size;
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfDomainAttributesGet(FScmi *instance_p, u32 domain, struct FPerfDomInfo *dom_info)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiMsgRespPerfDomainAttributes *attr;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_DOMAIN_ATTRIBUTES, SCMI_PROTOCOL_PERF, sizeof(domain), sizeof(*attr),info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    *(u32 *)info->tx.buf = domain;
+    attr = (struct FScmiMsgRespPerfDomainAttributes *)info->rx.buf;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    u32 flags = attr->flags;
+    
+    dom_info->set_limits = SUPPORTS_SET_LIMITS(flags);
+    dom_info->set_perf = SUPPORTS_SET_PERF_LVL(flags);
+    dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags);
+    dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags);
+    dom_info->sustained_freq_khz = attr->sustained_freq_khz;
+    dom_info->sustained_perf_level = attr->sustained_perf_level;
+    if (!dom_info->sustained_freq_khz ||
+        !dom_info->sustained_perf_level)
+        /* CPUFreq converts to kHz, hence default 1000 */
+        dom_info->mult_factor =	1000;
+    else
+        dom_info->mult_factor =
+                (dom_info->sustained_freq_khz * 1000) /
+                dom_info->sustained_perf_level;
+    strlcpy(dom_info->name, attr->name, FSCMI_MAX_STR_SIZE);
+    
+    return FT_SUCCESS;
+}
+
+static int opp_cmp_func(const void *opp1, const void *opp2)
+{
+	const struct FScmiOpp *t1 = opp1, *t2 = opp2;
+
+	return t1->perf_val - t2->perf_val;
+}
+
+static FError FScmiPerfDescribeLevelsGet(FScmi *instance_p, u32 domain, struct FPerfDomInfo *perf_dom)
+{
+    FError ret;
+    u32 cnt;
+    struct FScmiTransferInfo *info;
+    u32 tot_opp_cnt = 0;
+	u16 num_returned, num_remaining;
+	struct FScmiOpp *opp;
+	struct FScmiMsgPerfDescribeLevels *dom_info;
+	struct FScmiMsgRespPerfDescribeLevels *level_info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_DESCRIBE_LEVELS, SCMI_PROTOCOL_PERF, sizeof(*dom_info), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    dom_info = (struct FScmiMsgPerfDescribeLevels*)info->tx.buf;
+	level_info = (struct FScmiMsgRespPerfDescribeLevels *)info->rx.buf;
+
+    do
+    {
+        dom_info->domain = domain;
+		/* Set the number of OPPs to be skipped/already read */
+		dom_info->level_index = tot_opp_cnt;
+
+		ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+        if(ret != FT_SUCCESS)
+        {
+            FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+            return ret;
+        }
+
+		num_returned = level_info->num_returned;
+		num_remaining = level_info->num_remaining;
+		if (tot_opp_cnt + num_returned > FSCMI_MAX_OPPS) 
+        {
+			FSCMI_PERF_ERROR("No. of OPPs exceeded MAX_OPPS");
+			break;
+		}
+
+		opp = &perf_dom->opp[tot_opp_cnt];
+		for (cnt = 0; cnt < num_returned; cnt++, opp++) {
+			opp->perf_val = level_info->opp[cnt].perf_val;
+			opp->power = level_info->opp[cnt].power;
+			opp->trans_latency_us = level_info->opp[cnt].transition_latency_us;
+
+			FSCMI_PERF_INFO("Level %d: %d KHz Power cost%d Latency %dus\n", cnt, opp->perf_val, opp->power, opp->trans_latency_us);
+		}
+
+		tot_opp_cnt += num_returned;
+		/*
+		 * check for both returned and remaining to avoid infinite
+		 * loop due to buggy firmware
+		 */
+    } while (num_returned && num_remaining);
+
+    perf_dom->opp_count = tot_opp_cnt;
+    //sort(perf_dom->opp, tot_opp_cnt, sizeof(*opp), opp_cmp_func, NULL);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfLimitsSet(FScmi *instance_p, u32 domain, u32 max_perf, u32 min_perf)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiPerfSetLimits *limits;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_LIMITS_SET, SCMI_PROTOCOL_PERF, sizeof(*limits), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    limits = (struct FScmiPerfSetLimits *)info->tx.buf;
+    limits->domain = domain;
+    limits->max_level = max_perf;
+    limits->min_level = min_perf;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    FSCMI_PERF_INFO("FScmiPerfLimitsSet domain:%d max_level:%d KHz, min_level:%d KHz.",limits->domain,limits->max_level,limits->min_level);
+    //FSCMI_PERF_INFO("FScmiPerfLimitsSet status:%d.",(int)instance_p->info->hdr.status);
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfLimitsGet(FScmi *instance_p, u32 domain, u32 *max_perf, u32 *min_perf)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(max_perf != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    s32 status;
+    struct FScmiTransferInfo *info;
+    struct FScmiPerfGetLimits *limits;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_LIMITS_GET, SCMI_PROTOCOL_PERF, sizeof(u32), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    *(u32 *)info->tx.buf = domain;
+    
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+    limits = (struct FScmiPerfGetLimits *)info->rx.buf;
+    //status = limits->status;
+    *max_perf = limits->max_level;
+    *min_perf = limits->min_level;
+    FSCMI_PERF_INFO("FScmiPerfLimitsGet domain:%d, max_level:%d KHz, min_level:%d KHz.",domain,*max_perf,*min_perf);
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfLevelSet(FScmi *instance_p, u32 domain, u32 level, boolean poll)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FScmiPerfSetLevel *lvl;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_LEVEL_SET, SCMI_PROTOCOL_PERF, sizeof(*lvl), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    info->poll_completion = poll;
+    lvl = (struct FScmiPerfSetLevel *)info->tx.buf;
+    lvl->domain = domain;
+    lvl->level = level;
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+    FSCMI_PERF_INFO("FScmiPerfLevelSet domain:%d level:%d KHz.",lvl->domain,lvl->level);
+    return FT_SUCCESS;
+}
+
+static FError FScmiPerfLevelGet(FScmi *instance_p, u32 domain, u32 *level, boolean poll)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(level != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    struct FScmiTransferInfo *info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_PERF);
+    if (info == NULL)
+    {
+        FSCMI_PERF_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, PERF_LEVEL_GET, SCMI_PROTOCOL_PERF, sizeof(u32), sizeof(u32),info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    info->poll_completion = poll;
+    *(u32 *)info->tx.buf = domain;
+    
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_PERF);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+
+    *level = *(u32 *)info->rx.buf;
+    FSCMI_PERF_INFO("FScmiPerfLevelGet domain:%d level:%d KHz.",domain,*level);
+    return FT_SUCCESS;
+}
+
+/**
+ * @name: FScmiDvfsFreqSet
+ * @msg: Dynamic frequency scaling set
+ * @return {FError}             返回值
+ * @param {FScmi} *instance_p   scmi协议实例
+ * @param {u32} domain          性能域id
+ * @param {u64} freq            频率值Hz,依据初始化获得的level对应的值写入，不支持任意调频
+ * @param {boolean} poll        写入模式
+ */
+FError FScmiDvfsFreqSet(FScmi *instance_p, u32 domain, u64 freq_Hz, boolean poll)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    struct FScmiPerfInfo *pi = &instance_p->perf;
+	struct FPerfDomInfo *dom = pi->dom_info + domain;
+
+    ret = FScmiPerfLevelSet(instance_p, domain, freq_Hz / dom->mult_factor, poll);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("FScmiPerfLevelSet error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+    return FT_SUCCESS;
+}
+
+/**
+ * @name: FScmiDvfsFreqGet
+ * @msg: Dynamic frequency scaling get
+ * @return {FError}             返回值
+ * @param {FScmi} *instance_p   scmi协议实例
+ * @param {u32} domain          性能域id
+ * @param {u64} *freq           当前性能域的频率值
+ * @param {boolean} poll        写入模式
+ */
+FError FScmiDvfsFreqGet(FScmi *instance_p, u32 domain, u64 *freq, boolean poll)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(freq != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    FError ret;
+    u32 level;
+	struct FScmiPerfInfo *pi = &instance_p->perf;
+	struct FPerfDomInfo *dom = pi->dom_info + domain;
+
+    ret = FScmiPerfLevelGet(instance_p, domain, &level, poll);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("FScmiPerfLevelGet error ,protocol id is %d",SCMI_PROTOCOL_PERF);
+        return ret;
+    }
+    *freq = level * dom->mult_factor;
+    return FT_SUCCESS;
+}
+
+u64 FScmiPerfGetOppFreq(FScmi *instance_p,u32 domain,u32 opp_num)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+    FASSERT(domain < instance_p->perf.num_domains);
+
+    struct FPerfDomInfo *dom = &instance_p->perf.dom_info[domain];
+    
+    if (opp_num > dom->opp_count)
+    {
+        FSCMI_PERF_ERROR("Can't find opp_num,please check.");
+        return FSCMI_ERROR_REQUEST;
+    }
+
+    return dom->opp[opp_num].perf_val * dom->mult_factor;
+}
+
+/**
+ * @name: FScmiPerfInit
+ * @msg: Performance domain initialization
+ * @return {FError} 返回值
+ * @param {FScmi} *instance_p scmi协议实例
+ */
+FError FScmiPerfInit(FScmi *instance_p)
+{
+    FError ret;
+    struct FScmiPerfInfo *pinfo;
+    pinfo = &instance_p->perf;
+
+    ret = FScmiPerfGetVersion(instance_p,&instance_p->perf.version);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    instance_p->perf.major_ver = (instance_p->perf.version >> 16);
+    instance_p->perf.minor_ver = (instance_p->perf.version & 0xffff);
+	FSCMI_PERF_INFO("Perf Version %d.%d\n",instance_p->perf.major_ver, instance_p->perf.minor_ver);
+
+	ret = FScmiPerfAttributesGet(instance_p, pinfo);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_PERF_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+
+    FSCMI_PERF_INFO("SCMI Perf num_domains:%d,power_scale_mw:%d,stats_addr:0x%x,stats_size:0x%x.\n", instance_p->perf.num_domains,
+                                                                                      instance_p->perf.power_scale_mw,
+                                                                                      instance_p->perf.stats_addr,
+                                                                                      instance_p->perf.stats_size);
+    for (u32 i = 0; i < pinfo->num_domains; i++)
+    {
+        struct FPerfDomInfo *dom = pinfo->dom_info + i;
+        
+        ret = FScmiPerfDomainAttributesGet(instance_p, i, dom);
+        if (ret != FT_SUCCESS)
+        {
+            FSCMI_PERF_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+            return FSCMI_ERROR_REQUEST;
+        }
+        
+        ret = FScmiPerfDescribeLevelsGet(instance_p, i, dom);
+        if (ret != FT_SUCCESS)
+        {
+            FSCMI_PERF_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+            return FSCMI_ERROR_REQUEST;
+        }
+        FSCMI_PERF_INFO("SCMI Perf opp_count:%d,sustained_freq_khz:%d KHz,sustained_perf_level:%d KHz,mult_factor:%d Hz,name:%s.\n", dom->opp_count,
+                                                                                                                                dom->sustained_freq_khz,
+                                                                                                                                dom->sustained_perf_level,
+                                                                                                                                dom->mult_factor,
+                                                                                                                                dom->name);
+    }
+    
+    return FT_SUCCESS;
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.h
new file mode 100644
index 00000000000..9bd63f3d767
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_perf.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_perf.h
+ * Date: 2022-12-29 16:40:54
+ * LastEditTime: 2022-12-29 16:40:55
+ * Description:  This file is for performance message struct
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/31 init
+ */
+#ifndef FSCMI_PERF_H
+#define FSCMI_PERF_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fparameters.h"
+#include "fscmi.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+enum FScmiPerformanceProtocolCmd {
+	PERF_VERSION_GET = 0x0,
+	PERF_ATTRIBUTES_GET = 0x1,
+	PERF_DOMAIN_ATTRIBUTES = 0x3,
+	PERF_DESCRIBE_LEVELS = 0x4,
+	PERF_LIMITS_SET = 0x5,
+	PERF_LIMITS_GET = 0x6,
+	PERF_LEVEL_SET = 0x7,
+	PERF_LEVEL_GET = 0x8,
+	PERF_NOTIFY_LIMITS = 0x9,
+	PERF_NOTIFY_LEVEL = 0xa,
+};
+
+struct FScmiMsgRespPerfAttributes {
+	u16 num_domains;
+	u16 flags;
+#define POWER_SCALE_IN_MILLIWATT(x)	((x) & BIT(0))
+	u32 stats_addr_low;
+	u32 stats_addr_high;
+	u32 stats_size;
+};
+
+struct FScmiMsgRespPerfDomainAttributes {
+	u32 flags;
+#define SUPPORTS_SET_LIMITS(x)		((x) & BIT(31))
+#define SUPPORTS_SET_PERF_LVL(x)	((x) & BIT(30))
+#define SUPPORTS_PERF_LIMIT_NOTIFY(x)	((x) & BIT(29))
+#define SUPPORTS_PERF_LEVEL_NOTIFY(x)	((x) & BIT(28))
+	u32 rate_limit_us;
+	u32 sustained_freq_khz;
+	u32 sustained_perf_level;
+	u8 name[FSCMI_MAX_STR_SIZE];
+};
+
+struct FScmiMsgPerfDescribeLevels {
+	u32 domain;
+	u32 level_index;
+};
+
+struct FScmiPerfSetLimits {
+	u32 domain;
+	u32 max_level;
+	u32 min_level;
+};
+
+struct FScmiPerfGetLimits {
+	u32 max_level;
+	u32 min_level;
+};
+
+struct FScmiPerfSetLevel {
+	u32 domain;
+	u32 level;
+};
+
+struct FScmiPerfNotifyLevelOrLimits {
+	u32 domain;
+	u32 notify_enable;
+};
+
+struct FScmiMsgRespPerfDescribeLevels {
+	u16 num_returned;
+	u16 num_remaining;
+	struct {
+		u32 perf_val;/* Performance level value */
+		u32 power;/* Power cost */
+		u16 transition_latency_us;/* Worst-case transition latency in microseconds to move from any supported performance to the level indicated by this entry in the array */
+		u16 reserved;
+	} opp[0];
+};
+
+FError FScmiPerfInit(FScmi *instance_p);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.c b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.c
new file mode 100644
index 00000000000..1130528b0db
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.c
@@ -0,0 +1,365 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_sensors.c
+ * Date: 2023-01-12 20:52:41
+ * LastEditTime: 2023-01-12 20:52:42
+ * Description:  This file is for cpu sersor information
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/13 init
+ */
+
+#include "fscmi_sensors.h"
+#include <string.h>
+#include "fscmi.h"
+#include "fscmi_base.h"
+#include "fio.h"
+#include "fdebug.h"
+#include "fsleep.h"
+#include "ftypes.h"
+#include "fswap.h"
+#include "fkernel.h"
+#include "fassert.h"
+
+#define FSCMI_SENSOR_DEBUG_TAG "FSCMI_SENSOR"
+#define FSCMI_SENSOR_ERROR(format, ...)   FT_DEBUG_PRINT_E(FSCMI_SENSOR_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_SENSOR_WARN(format, ...)   FT_DEBUG_PRINT_W(FSCMI_SENSOR_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_SENSOR_INFO(format, ...)    FT_DEBUG_PRINT_I(FSCMI_SENSOR_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FSCMI_SENSOR_DEBUG(format, ...)   FT_DEBUG_PRINT_D(FSCMI_SENSOR_DEBUG_TAG, format, ##__VA_ARGS__)
+
+static FError FScmiSensorGetVersion(FScmi *instance_p,u32  *rev_info)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, SENSOR_VERSION_GET, SCMI_PROTOCOL_SENSOR, 0, sizeof(*rev_info),info->tx.buf);
+
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    *rev_info = FtIn32((uintptr)info->rx.buf);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiSensorAttributesGet(FScmi *instance_p,struct FScmiSensorsInfo *si)
+{
+	FError ret;
+	struct FScmiTransferInfo *info;
+	struct FScmiMsgRespSensorAttributes *attr;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+    
+	ret = FScmiMessageInit(instance_p, SENSOR_ATTRIBUTES_GET,SCMI_PROTOCOL_SENSOR, 0, sizeof(*attr), info->tx.buf);
+	if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    attr = (struct FScmiMsgRespSensorAttributes *)info->rx.buf;
+    
+    si->num_sensors = (int)attr->num_sensors;
+    si->max_requests = (int)attr->max_requests;
+    si->reg_addr = (u32)attr->reg_addr_low | ((u64)(attr->reg_addr_high)) << 32;
+    si->reg_size = (u32)(attr->reg_size);
+
+    return FT_SUCCESS;
+}
+
+static FError FScmiSensorDescriptionGet(FScmi *instance_p,struct FScmiSensorsInfo *si)
+{
+	int ret, cnt;
+	u32 desc_index = 0;
+	u16 num_returned, num_remaining;
+	struct FScmiTransferInfo *info;
+	struct FScmiMsgRespSensorDescription *buf;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+	ret = FScmiMessageInit(instance_p, SENSOR_DESCRIPTION_GET, SCMI_PROTOCOL_SENSOR, sizeof(u32), 0, info->tx.buf);
+	if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+	buf = (struct FScmiMsgRespSensorDescription *)info->rx.buf;
+
+    FSCMI_SENSOR_INFO("DescriptionGet:num_returned:%d,num_remaining:%d.\n",buf->num_returned,buf->num_remaining);
+	do {
+		/* Set the number of sensors to be skipped/already read */
+		*(u32 *)info->tx.buf = desc_index;
+
+        ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+        if(ret != FT_SUCCESS)
+        {
+            FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+            return ret;
+        }
+
+		num_returned = (u16)(buf->num_returned);
+		num_remaining = (u16)(buf->num_remaining);
+
+		if (desc_index + (u32)num_returned > si->num_sensors) {
+			FSCMI_SENSOR_ERROR("No. of sensors can't exceed:%d+%d > %d", desc_index, num_returned, si->num_sensors);
+			break;
+		}
+
+		for (cnt = 0; cnt < num_returned; cnt++) {
+			u32 attrh;
+			struct FScmiSensorInfo *s;
+
+			attrh = (u32)(buf->desc[cnt].attributes_high);
+			s = &si->sensor_info[desc_index + cnt];
+			s->id = (u32)(buf->desc[cnt].id);
+			s->type = SENSOR_TYPE(attrh);
+			strlcpy(s->name, buf->desc[cnt].name, FSCMI_MAX_STR_SIZE);
+            FSCMI_SENSOR_INFO("DescriptionGet:id:%d,type:%d,name:%s.\n",s->id,s->type,s->name);
+        }
+
+        desc_index += num_returned;
+		/*
+		 * check for both returned and remaining to avoid infinite
+		 * loop due to buggy firmware
+		 */
+	} while (num_returned && num_remaining);
+	return ret;
+}
+
+static int FScmiSensorsTripPointSet(FScmi *instance_p,u32 sensor_id, u8 trip_id, u64 trip_value)
+{
+    FError ret;
+    u32 evt_cntl = SENSOR_TP_BOTH;
+    struct FScmiTransferInfo *info;
+    struct FScmiMsgSetSensorTripPoint *trip;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, SENSOR_TRIP_POINT_SET, SCMI_PROTOCOL_SENSOR, sizeof(*trip), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    trip = (struct FScmiMsgSetSensorTripPoint *)info->tx.buf;
+	trip->id = sensor_id;
+	trip->event_control = evt_cntl;
+    trip->value_low = trip_value & 0xffffffff;
+    trip->value_high = trip_value >> 32;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+    
+    return FT_SUCCESS;
+}
+static FError FScmiSensorsConfigurationSet(FScmi *instance_p,u32 sensor_id)
+{
+    FError ret;
+    u32 evt_cntl = BIT(0);
+    struct FScmiTransferInfo *info;
+    struct FScmiMsgSetSensorConfig *cfg;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, SENSOR_CONFIG_SET, SCMI_PROTOCOL_SENSOR, sizeof(*cfg), 0,info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    cfg = (struct FScmiMsgSetSensorConfig *)info->tx.buf;
+	cfg->id = sensor_id;
+	cfg->event_control = evt_cntl;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+    
+    return FT_SUCCESS;
+}
+
+static FError FScmiSensorsReadingGet(FScmi *instance_p,u32 sensor_id, boolean async, s64 *value)
+{
+    FError ret;
+    struct FScmiTransferInfo *info;
+    struct FcmiMsgSensorReadingGet *sensor;
+
+    info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_SENSOR);
+    if (info == NULL)
+    {
+        FSCMI_SENSOR_ERROR("Info data structure not found ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return FSCMI_ERROR_NULL_POINTER;
+    }
+
+    /* Prepare hdr packaging */
+    ret = FScmiMessageInit(instance_p, SENSOR_READING_GET, SCMI_PROTOCOL_SENSOR, sizeof(*sensor), sizeof(u64),info->tx.buf);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Prepare hdr packaging is error ,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    sensor = (struct FcmiMsgSensorReadingGet *)info->tx.buf;
+    sensor->id = sensor_id;
+    sensor->flags = async ? SENSOR_READ_ASYNC:0;
+
+    ret = FScmiDoTransport(instance_p, info, SCMI_PROTOCOL_SENSOR);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Transport package error,protocol id is %d",SCMI_PROTOCOL_SENSOR);
+        return ret;
+    }
+
+    /* Fill in the obtained parameters */
+    u32 *pval = (u32 *)info->rx.buf;
+    *value = *pval;
+    *value |= (s64)(*(pval +1)) << 32;
+    return FT_SUCCESS;
+}
+
+/**
+ * @name: FScmiSensorGetTemp
+ * @msg: 
+ * @return {FError}             返回值
+ * @param {FScmi} *instance_p   scmi协议实例
+ * @param {u32} sensor_id       传感器ID，可以在初始化后获取
+ * @param {s64} *temp           获取对应ID传感器的温度
+ */
+FError FScmiSensorGetTemp(FScmi *instance_p, u32 sensor_id,s64 *temp)
+{
+    FASSERT(instance_p != NULL);
+    FASSERT(temp != NULL);
+    FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
+
+    FError ret;
+
+    if(instance_p->sensors.num_sensors > 0 && instance_p->sensors.num_sensors > sensor_id)
+    {
+        if (instance_p->sensors.sensor_info[sensor_id].type == DEGRESS_C)
+        {
+            FScmiSensorsReadingGet(instance_p, sensor_id, FALSE, temp);
+            FSCMI_SENSOR_INFO("FScmiSensorsReadingGet type DEGRESS_C value: %d `C.",*temp);
+        }
+    }
+    else
+    {
+        FSCMI_SENSOR_ERROR("Can't find sensor,please running function FScmiSensorInit first.");
+    }
+    return FT_SUCCESS;
+}
+
+/**
+ * @name: FScmiSensorInit
+ * @msg: Sensor initialization
+ * @return {FError}             返回值
+ * @param {FScmi} *instance_p   scmi协议实例
+ */
+FError FScmiSensorInit(FScmi *instance_p)
+{
+	u32 version;
+    FError ret;
+    struct FScmiSensorsInfo *sinfo;
+    sinfo = &instance_p->sensors;
+
+    ret = FScmiSensorGetVersion(instance_p,&instance_p->sensors.version);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    instance_p->sensors.major_ver = (instance_p->sensors.version >> 16);
+    instance_p->sensors.minor_ver = (instance_p->sensors.version & 0xffff);
+	FSCMI_SENSOR_INFO("Sensor Version %d.%d\n",instance_p->sensors.major_ver, instance_p->sensors.minor_ver);
+
+	ret = FScmiSensorAttributesGet(instance_p, sinfo);
+    if(ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+
+    FSCMI_SENSOR_INFO("SCMI Sensors num:%d,requests:%d,reg_addr:0x%x,reg_size:0x%x.\n", instance_p->sensors.num_sensors,
+                                                                                      instance_p->sensors.max_requests,
+                                                                                      instance_p->sensors.reg_addr,
+                                                                                      instance_p->sensors.reg_size);
+    ret = FScmiSensorDescriptionGet(instance_p, sinfo);
+    if (ret != FT_SUCCESS)
+    {
+        FSCMI_SENSOR_ERROR("Can't get version,please check mem_address or chan_id.Error code:0x%x.",ret);
+        return FSCMI_ERROR_REQUEST;
+    }
+    return FT_SUCCESS;
+}
+
diff --git a/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.h b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.h
new file mode 100644
index 00000000000..ee0edc39280
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/drivers/scmi/fscmi_mhu/fscmi_sensors.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: fscmi_sensors.h
+ * Date: 2023-01-12 20:53:01
+ * LastEditTime: 2023-01-12 20:53:01
+ * Description:  This file is for cpu sensor message struct
+ * 
+ * Modify History: 
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0 liushengming 2023/01/13 init
+ */
+
+#ifndef FSCMI_SENSORS_PROTOCOL_H
+#define FSCMI_SENSORS_PROTOCOL_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+#include "fparameters.h"
+#include "fscmi.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/* Sensor Type Enumerations */
+enum FScmiSensorType
+{
+	NONE=0x0,
+	UNSPECIFIED,
+	DEGRESS_C,
+	DEGRESS_F,
+	DEGRESS_K,
+};
+
+enum FScmiSensorProtocolCmd {
+    SENSOR_VERSION_GET = 0x0,
+    SENSOR_ATTRIBUTES_GET = 0x1,
+	SENSOR_DESCRIPTION_GET = 0x3,
+	SENSOR_CONFIG_SET = 0x4,
+	SENSOR_TRIP_POINT_SET = 0x5,
+	SENSOR_READING_GET = 0x6,
+};
+
+struct FScmiMsgRespSensorAttributes {
+	u16 num_sensors;
+	u8 max_requests;
+	u8 reserved;
+	u32 reg_addr_low;
+	u32 reg_addr_high;
+	u32 reg_size;
+};
+
+struct FScmiMsgRespSensorDescription {
+	u16 num_returned;
+	u16 num_remaining;
+	struct {
+		u32 id;
+		u32 attributes_low;
+#define SUPPORTS_ASYNC_READ(x)	((x) & BIT(31))
+#define NUM_TRIP_POINTS(x)	((x) & 0xff)
+		u32 attributes_high;
+#define SENSOR_TYPE(x)		((x) & 0xff)
+#define SENSOR_SCALE(x)		(((x) >> 11) & 0x1f)
+#define SENSOR_UPDATE_SCALE(x)	(((x) >> 22) & 0x1f)
+#define SENSOR_UPDATE_BASE(x)	(((x) >> 27) & 0x1f)
+		u8 name[FSCMI_MAX_STR_SIZE];
+	} desc[0];
+};
+
+struct FScmiMsgSetSensorConfig {
+	u32 id;
+	u32 event_control;
+};
+
+struct FScmiMsgSetSensorTripPoint {
+	u32 id;
+	u32 event_control;
+#define SENSOR_TP_EVENT_MASK	(0x3)
+#define SENSOR_TP_DISABLED	0x0
+#define SENSOR_TP_POSITIVE	0x1
+#define SENSOR_TP_NEGATIVE	0x2
+#define SENSOR_TP_BOTH		0x3
+#define SENSOR_TP_ID(x)		(((x) & 0xff) << 4)
+	u32 value_low;
+	u32 value_high;
+};
+
+struct FcmiMsgSensorReadingGet {
+	u32 id;
+	u32 flags;
+#define SENSOR_READ_ASYNC	BIT(0)
+};
+
+FError FScmiSensorInit(FScmi *instance_p);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/Kconfig b/bsp/phytium/libraries/standalone/drivers/serial/Kconfig
index d01d698f984..e84c41301c1 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/serial/Kconfig
@@ -4,7 +4,7 @@ menu "Usart Configuration"
         bool
         prompt "Use Pl011 uart"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.c
index f7023b1b2f3..6aabf5e803c 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.c
@@ -12,17 +12,18 @@
  *
  *
  * FilePath: fpl011.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:07:24
- * Description:  This files is for uart functions
+ * Description:  This file is for uart functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  fix bug
  */
 
 /***************************** Include Files ********************************/
-
 #include "fpl011.h"
 #include "fio.h"
 #include "ferror_code.h"
@@ -136,7 +137,7 @@ static void FPl011StubHandler(void *args, u32 event,
 
 /**
  * @name: FPl011SendBuffer
- * @msg: send data buffer through uart
+ * @msg: send data buffer through uart,if you close FIFO and open interrupt,recommend use FPl011BlockSend
  * @return {*}
  * @param  uart_p
  */
@@ -156,16 +157,14 @@ u32 FPl011SendBuffer(FPl011 *uart_p)
      * Otherwise put bytes into the TX FIFO unil it is full, or all of the
      * data has been put into the FIFO.
      */
-    while ((!FUART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > sent_count))
+    while ((!FUART_ISTRANSMITFULL(uart_p->config.base_address)) && (uart_p->send_buffer.remaining_bytes > 0))
     {
+        sent_count = uart_p->send_buffer.requested_bytes - uart_p->send_buffer.remaining_bytes;
+        uart_p->send_buffer.remaining_bytes--;
+
         FUART_WRITEREG32(uart_p->config.base_address, FPL011DR_OFFSET, (u32)uart_p->send_buffer.byte_p[sent_count]);
-        sent_count++;
     }
-    /* Update the buffer to reflect the bytes that were sent from it */
-    uart_p->send_buffer.byte_p += sent_count;
-    uart_p->send_buffer.remaining_bytes -= sent_count;
-
-    return sent_count;
+    return uart_p->send_buffer.requested_bytes - uart_p->send_buffer.remaining_bytes;
 }
 
 /**
@@ -203,7 +202,7 @@ u32 FPl011ReceiveBuffer(FPl011 *uart_p)
     u32 event_data;
     u32 byte_value;
 
-    while ((received_count < uart_p->receive_buffer.remaining_bytes) && !FUART_ISRECEIVEDATA(uart_p->config.base_address))
+    while ((received_count < uart_p->receive_buffer.remaining_bytes) && !FUART_RECEIVEDATAEMPTY(uart_p->config.base_address))
     {
         byte_value = FUART_READREG32(uart_p->config.base_address, FPL011DR_OFFSET);
 
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h
index 349b6a352ef..354743d4606 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h
@@ -12,17 +12,24 @@
  *
  *
  * FilePath: fpl011.h
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:07:38
- * Description:  This files is for uart functions
+ * Description:  This file is for uart functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  fix bug
  */
 
-#ifndef BSP_DRIVERS_SERIAL_PL011_UART_H
-#define BSP_DRIVERS_SERIAL_PL011_UART_H
+#ifndef FPL011_H
+#define FPL011_H
+
+#include "ftypes.h"
+#include "fassert.h"
+#include "fpl011_hw.h"
+#include "sdkconfig.h"
 
 
 #ifdef __cplusplus
@@ -30,12 +37,6 @@ extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-
-#include "ftypes.h"
-#include "fassert.h"
-#include "fpl011_hw.h"
-#include "sdkconfig.h"
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -93,7 +94,7 @@ extern "C"
 #define FPL011_EVENT_RECV_ERROR 4U      /* A receive error detected */
 #define FPL011_EVENT_MODEM 5U           /* Modem status changed */
 #define FPL011_EVENT_PARE_FRAME_BRKE 6U /* A receive parity, frame, break \
-                                        *   error detected */
+*   error detected */
 #define FPL011_EVENT_RECV_ORERR 7U      /* A receive overrun error detected */
 
 
@@ -114,7 +115,7 @@ typedef struct
 typedef struct
 {
     u32 instance_id; /* Id of device*/
-    u32 base_address;
+    uintptr base_address;
     u32 ref_clock_hz;
     u32 irq_num;
     u32 baudrate;
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_g.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_g.c
index 27171019888..87483e4e9de 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_g.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fpl011_g.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:05:41
- * Description:  This files is for uart config
+ * Description:  This file is for uart static configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18 add configs
  */
 
 /***************************** Include Files *********************************/
@@ -53,6 +55,7 @@ const FPl011Config FPl011ConfigTable[FUART_NUM] =
         .irq_num = FUART1_IRQ_NUM,
         .baudrate = 115200
     },
+#ifndef TARDIGRADE
     {
         .instance_id = FUART2_ID,
         .base_address = FUART2_BASE_ADDR,
@@ -67,4 +70,6 @@ const FPl011Config FPl011ConfigTable[FUART_NUM] =
         .irq_num = FUART3_IRQ_NUM,
         .baudrate = 115200
     }
+#endif // !TARDIGRADE 
+
 };
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.c
index 9b468f24397..83bdfa6068a 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fpl011_hw.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:05:56
- * Description:  This files is for uart register function
+ * Description:  This file is for uart register function
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18 add file head 
  */
 
 /***************************** Include Files *********************************/
@@ -43,7 +45,7 @@
  * @param  addr contains the base address of the device.
  * @param  Byte contains the byte to be sent.
  */
-void FPl011SendByte(u32 addr, u8 byte)
+void FPl011SendByte(uintptr addr, u8 byte)
 {
 
     while (FUART_ISTRANSMITFULL(addr))
@@ -59,11 +61,11 @@ void FPl011SendByte(u32 addr, u8 byte)
  * and blocks until a byte has received.
  * @param  addr contains the base address of the device.
  */
-u8 FPl011RecvByte(u32 addr)
+u8 FPl011RecvByte(uintptr addr)
 {
     u32 recieved_byte;
 
-    while (FUART_ISRECEIVEDATA(addr))
+    while (FUART_RECEIVEDATAEMPTY(addr))
     {
         ;
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.h b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.h
index cec10c1fa04..1dcb5280c1b 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_hw.h
@@ -12,26 +12,31 @@
  *
  *
  * FilePath: fpl011_hw.h
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:06:10
- * Description:  This files is for definition of uart register
+ * Description:  This file is for definition of uart register
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  modified some defines
  */
 
-#ifndef BSP_DRIVERS_SERIAL_PL011_UART_HW_H
-#define BSP_DRIVERS_SERIAL_PL011_UART_HW_H
+#ifndef FPL011_HW_H
+#define FPL011_HW_H
+
+#include "ftypes.h"
+#include "fassert.h"
+#include "fio.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "fassert.h"
-#include "fio.h"
+
 
 /************************** Constant Definitions *****************************/
 
@@ -218,13 +223,13 @@ extern "C"
 #define FUART_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value)
 
 /**
- * @name: FUART_ISRECEIVEDATA
+ * @name: FUART_RECEIVEDATAEMPTY
  * @msg:  Used to confirm whether data has been received
  * @param addr contains the base address of the device.
- * @return {bool} true 是存在数据 ， false 是不存在数据
+ * @return {bool} true 是不存在数据 ， false 是存在数据
  *
  */
-#define FUART_ISRECEIVEDATA(addr) (FtIn32(addr + FPL011FTR_OFFSET) & FPL011FTR_RXFE)
+#define FUART_RECEIVEDATAEMPTY(addr) (FtIn32(addr + FPL011FTR_OFFSET) & FPL011FTR_RXFE)
 
 /**
  * @name: FUART_ISTRANSMITFULL
@@ -245,8 +250,8 @@ extern "C"
 
 /************************** Function Prototypes ******************************/
 
-void FPl011SendByte(u32 addr, u8 byte);
-u8 FPl011RecvByte(u32 addr);
+void FPl011SendByte(uintptr addr, u8 byte);
+u8 FPl011RecvByte(uintptr addr);
 
 #ifdef __cplusplus
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c
index de69f982ae8..6a263dd6566 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fpl011_intr.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:06:30
- * Description:  This files is for uart irq functions
+ * Description:  This file is for uart irq functions
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  fix bugs
  */
 
 
@@ -187,7 +189,6 @@ static void FPl011ReceiveDataHandler(FPl011 *uart_p)
     {
         (void)FPl011ReceiveBuffer(uart_p);
     }
-
     if ((u32)0 == uart_p->receive_buffer.remaining_bytes)
     {
         if (uart_p->handler)
@@ -205,7 +206,6 @@ static void FPl011ReceiveTimeoutHandler(FPl011 *uart_p)
     {
         (void)FPl011ReceiveBuffer(uart_p);
     }
-
     if ((u32)0 == uart_p->receive_buffer.remaining_bytes)
     {
         event = FPL011_EVENT_RECV_TOUT;
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_options.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_options.c
index 4e4584d0770..d94df0db0d1 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_options.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_options.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fpl011_options.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:06:45
- * Description:  This files is for uart option setting
+ * Description:  This file is for uart option setting
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  fix bug
  */
 
 
@@ -108,7 +110,9 @@ void FPl011SetSpecificOptions(FPl011 *uart_p, u32 options)
     for (index = 0; index < FUART_NUM_OPITIONS; index++)
     {
         if ((options & option_table[index].option) == (u32)(0))
+        {
             continue;
+        }
         reg_value = FUART_READREG32(uart_p->config.base_address, option_table[index].register_offset);
 
         /* set specific options */
@@ -118,7 +122,7 @@ void FPl011SetSpecificOptions(FPl011 *uart_p, u32 options)
 }
 
 /**
- * @name: FPl011SetSpecificOptions
+ * @name: FPl011ClearSpecificOptions
  * @msg:  Clear the options for the specified driver instance.
  * @param uart_p is a pointer to the uart instance.
  * @param options contains the options to be set which are bit masks
@@ -133,7 +137,9 @@ void FPl011ClearSpecificOptions(FPl011 *uart_p, u32 options)
     for (index = 0; index < FUART_NUM_OPITIONS; index++)
     {
         if ((options & option_table[index].option) == (u32)(0))
+        {
             continue;
+        }
         reg_value = FUART_READREG32(uart_p->config.base_address, option_table[index].register_offset);
 
         /* remove specific options */
@@ -166,8 +172,8 @@ FError FPl011SetDataFormat(FPl011 *uart_p, FPl011Format *format_p)
     config_p = &uart_p->config;
 
     if ((format_p->data_bits > ((u32)(FPL011_FORMAT_WORDLENGTH_8BIT))) ||
-            (format_p->parity > ((u32)(FPL011_FORMAT_PARITY_MASK))) ||
-            (format_p->stopbits > ((u32)(FPL011_FORMAT_PARITY_MASK)))
+        (format_p->parity > ((u32)(FPL011_FORMAT_PARITY_MASK))) ||
+        (format_p->stopbits > ((u32)(FPL011_FORMAT_PARITY_MASK)))
        )
     {
         return FPL011_ERROR_PARAM ;
@@ -299,7 +305,7 @@ void FPl011SetTxFifoThreadHold(FPl011 *uart_p, u8 trigger_level)
     fifo_trig_reg = FUART_READREG32(config_p->base_address,
                                     FPL011IFLS_OFFSET);
 
-    fifo_trig_reg &= ~(FPL011IFLS_TXIFLSEL_MASK | FPL011IFLS_RXIFLSEL_MASK);
+    fifo_trig_reg &= ~(FPL011IFLS_TXIFLSEL_MASK);
 
     fifo_trig_reg |= (u32)trigger_level;
 
@@ -467,14 +473,14 @@ void FPl011SetOperMode(FPl011 *uart_p, u8 operation_mode)
 
     switch (operation_mode)
     {
-    case FPL011_OPER_MODE_NORMAL:
-        ctrl_reg |= FPL011CR_MODE_NORMAL;
-        break;
-    case FPL011_OPER_MODE_LOCAL_LOOP:
-        ctrl_reg |= FPL011CR_LBE;
-        break;
-    default:
-        break;
+        case FPL011_OPER_MODE_NORMAL:
+            ctrl_reg |= FPL011CR_MODE_NORMAL;
+            break;
+        case FPL011_OPER_MODE_LOCAL_LOOP:
+            ctrl_reg |= FPL011CR_LBE;
+            break;
+        default:
+            break;
     }
 
     /* Setup the Control Register with the passed argument.*/
diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_sinit.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_sinit.c
index ae9f4834e75..382c9ace4b3 100644
--- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_sinit.c
@@ -12,13 +12,15 @@
  *
  *
  * FilePath: fpl011_sinit.c
- * Date: 2022-02-10 14:53:42
+ * Date: 2021-11-02 14:53:42
  * LastEditTime: 2022-02-18 09:07:00
- * Description:  This files is for uart static init
+ * Description:  This file is for uart static init
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  huanghe 2021/11/2  first commit
+ * 1.1  liushengming 2022/02/18  add file head 
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/Kconfig b/bsp/phytium/libraries/standalone/drivers/spi/Kconfig
index 2133ced9fbc..1d17ec511ca 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/spi/Kconfig
@@ -4,8 +4,7 @@ config USE_FSPIM
     prompt "Use FSPIM"
     default n
     depends on USE_SPI
-    depends on TARGET_F2000_4 || TARGET_D2000 || TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q
     help
         Select FSPIM driver component
-
-
+	
+	
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.c
index b2694483ad0..0fc6f4bc6ec 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.c
@@ -14,14 +14,15 @@
  * FilePath: fspim.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:32
- * Description:  This files is for spim api implementation
+ * Description:  This file is for spim api implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
- * 1.2   zhugengyu  2022-5-13   support spi dma
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
+ * 1.2   zhugengyu  2022/5/13   support spi dma
+ * 1.3 liqiaozhong 2022/12/30 add check func and spim option func
  */
 
 
@@ -52,14 +53,14 @@ FError FSpimReset(FSpim *instance_p);
 /************************** Variable Definitions *****************************/
 static const char *FSPIM_ERROR_CODE_MSG[FSPIM_NUM_OF_ERR_CODE] =
 {
-    "FSPIM_SUCCESS : fspim success",
-    "FSPIM_ERR_INVAL_STATE : fspim invalid state",
-    "FSPIM_ERR_NOT_READY : fspim driver not ready",
-    "FSPIM_ERR_INVAL_PARAM : fspim invalid input parameters",
-    "FSPIM_ERR_BUS_BUSY : fspim bus is busy",
-    "FSPIM_ERR_NOT_SUPPORT : fspim not support operation",
-    "FSPIM_ERR_TIMEOUT : fspim wait timeout",
-    "FSPIM_ERR_TRANS_FAIL : fspim data transfer failed",
+    "FSPIM_SUCCESS : The fspim was successful",
+    "FSPIM_ERR_INVAL_STATE : The fspim invalid state",
+    "FSPIM_ERR_NOT_READY : The fspim driver is not ready",
+    "FSPIM_ERR_INVAL_PARAM : The fspim input parameter is invalid",
+    "FSPIM_ERR_BUS_BUSY : The fspim bus is busy",
+    "FSPIM_ERR_NOT_SUPPORT : Operations are not supported by fspim",
+    "FSPIM_ERR_TIMEOUT : The fspim waits for a timeout",
+    "FSPIM_ERR_TRANS_FAIL : The fspim data transmission failed",
 };
 
 
@@ -92,7 +93,7 @@ FError FSpimCfgInitialize(FSpim *instance_p, const FSpimConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == instance_p->is_ready)
     {
-        FSPIM_WARN("device is already initialized!!!");
+        FSPIM_WARN("The device has been initialized!!!");
     }
 
     /*
@@ -103,9 +104,7 @@ FError FSpimCfgInitialize(FSpim *instance_p, const FSpimConfig *input_config_p)
     FSpimDeInitialize(instance_p);
     instance_p->config = *input_config_p;
 
-    /*
-    * Reset the device.
-    */
+    /* Reset the device. */
     ret = FSpimReset(instance_p);
     if (FSPIM_SUCCESS == ret)
     {
@@ -133,7 +132,7 @@ void FSpimDeInitialize(FSpim *instance_p)
 
 /**
  * @name: FSpimReset
- * @msg: 重置FSPIM控制器
+ * @msg: Reset FSPIM controller
  * @return {FError} FSPIM_SUCCESS表示重置成功，其它返回值表示重置失败
  * @param {FSpim} *instance_p
  */
@@ -167,7 +166,7 @@ FError FSpimReset(FSpim *instance_p)
     /* 选择串行时钟极性和相位 */
     FSpimSetCpha(base_addr, instance_p->config.cpha);
     FSpimSetCpol(base_addr, instance_p->config.cpol);
-
+    
     /* 设置传输模式 */
     FSpimSetTransMode(base_addr, FSPIM_TRANS_MODE_RX_TX);
 
@@ -183,14 +182,14 @@ FError FSpimReset(FSpim *instance_p)
     {
         fifo = FSpimGetTxFifoDepth(base_addr);
         instance_p->tx_fifo_len = ((fifo == 1) ? 0 : fifo);
-        FSPIM_INFO("fifo depth %d tx_fifo_len %d", fifo, instance_p->tx_fifo_len);
+        FSPIM_INFO("The fifo depth is %d ,tx effective length bits %d", fifo, instance_p->tx_fifo_len);
     }
 
     if (0 == instance_p->rx_fifo_len)
     {
         fifo = FSpimGetRxFifoDepth(base_addr);
         instance_p->rx_fifo_len = ((fifo == 1) ? 0 : fifo);
-        FSPIM_INFO("fifo depth %d tx_fifo_len %d", fifo, instance_p->tx_fifo_len);
+        FSPIM_INFO("The fifo depth is %d ,rx effective length bits %d", fifo, instance_p->rx_fifo_len);
     }
 
     FSPIM_WRITE_REG32(base_addr, FSPIM_DMA_CR_OFFSET, 0x0); /* disable ddma */
@@ -221,16 +220,129 @@ FError FSpimReset(FSpim *instance_p)
 
     ret = FSpimSetSpeed(base_addr, instance_p->config.max_freq_hz);
     if (FSPIM_SUCCESS != ret)
+    {
         return ret;
+    }
 
     FSPIM_WRITE_REG32(base_addr, FSPIM_RX_SAMPLE_DLY_OFFSET, FSPIM_DEFAULT_RSD);
 
-    /* 使能SPI控制器 */
-    FSpimSetEnable(base_addr, TRUE);
+    return ret;
+}
+
+/*
+ * @name: FSpimSetOption
+ * @msg:  Give user a way to set speed and polarity etc.
+ * @param {FSpim} *instance_p FSPIM驱动控制数据
+ * @param {u32} option FSPIM操作标识数
+ * @param {u32} value FSPIM用户自定参数
+ * @return 驱动初始化的错误码信息，FSPIM_SUCCESS 表示设置成功，其它返回值表示设置失败
+ */
+FError FSpimSetOption(FSpim *instance_p, u32 option, u32 value)
+{
+    FASSERT(instance_p);
+    uintptr base_addr = instance_p->config.base_addr;
+    FError ret = FSPIM_SUCCESS;
+    boolean enabled = FSpimGetEnable(base_addr);
+
+    if (FT_COMPONENT_IS_READY != instance_p->is_ready)
+    {
+        FSPIM_ERROR("The device is not initialized!!!");
+        return FSPIM_ERR_NOT_READY;
+    }
+
+    FSpimSetEnable(base_addr, FALSE);
+    
+    if (option == FSPIM_CPOLTYPE_OPTION)
+    {
+        if (value == FSPIM_CPOL_HIGH || value == FSPIM_CPOL_LOW)
+        {
+            FSpimSetCpol(base_addr, value);
+            instance_p->config.cpol = value;
+            FSPIM_INFO("Set cpol to %d", value);
+        }
+        else
+        {
+            FSPIM_ERROR("Input error, CPOL value should be 0 or 1.");
+            return FSPIM_ERR_INVAL_PARAM;
+        }
+    }
+
+    if (option == FSPIM_CPHATYPE_OPTION)
+    {
+        if (value == FSPIM_CPHA_2_EDGE || value == FSPIM_CPHA_1_EDGE)
+        {
+            FSpimSetCpha(base_addr, value);
+            instance_p->config.cpha = value;
+            FSPIM_INFO("Set cpha to %d", value);
+        }
+        else
+        {
+            FSPIM_ERROR("Input error, CPHA value should be 0 or 1.");
+            return FSPIM_ERR_INVAL_PARAM;
+        }
+    }
+
+    if (option == FSPIM_FREQUENCY_OPTION)
+    {
+        if (value <= (FSPI_CLK_FREQ_HZ / FSPIM_BAUD_R_SCKDV_MIN))
+        {
+            ret = FSpimSetSpeed(base_addr, value);
+            if (FSPIM_SUCCESS != ret)
+            {
+                return ret;
+            }
+            instance_p->config.max_freq_hz = value;
+            FSPIM_INFO("Set spim freqency to %d", value);
+        }
+        else
+        {
+            FSPIM_ERROR("Input error, spim freqency value should be less than 24M.");
+            return FSPIM_ERR_INVAL_PARAM;
+        }
+    }
+
+    if (enabled)
+    {
+        FSpimSetEnable(base_addr, TRUE);
+    }
 
     return ret;
 }
 
+/*
+ * @name: FSpimGetOption
+ * @msg:  Give user a way to get speed and polarity etc.
+ * @param {FSpim} *instance_p FSPIM驱动控制数据
+ * @param {u32} option FSPIM操作标识数
+ * @return {u32} 获取到的参数值
+ */
+u32 FSpimGetOption(FSpim *instance_p, u32 option)
+{
+    FASSERT(instance_p);
+    uintptr base_addr = instance_p->config.base_addr;
+    u32 value;
+
+    if (option == FSPIM_CPOLTYPE_OPTION)
+    {
+        value = FSpimGetCpol(base_addr);
+        FSPIM_INFO("Get cpol value: %d", value);
+        return value;
+    }
+
+    if (option == FSPIM_CPHATYPE_OPTION)
+    {
+        value = FSpimGetCpha(base_addr);
+        FSPIM_INFO("Get cpha value: %d", value);
+        return value;
+    }
+
+    if (option == FSPIM_FREQUENCY_OPTION)
+    {
+        value = FSpimGetSpeed(base_addr);
+        FSPIM_INFO("Get freq_clock value: 0x%x, %d", value, value);
+        return value;
+    }
+}
 /**
  * @name: FSpimGetTxRound
  * @msg: 计算当前FIFO支持的发送字节数
@@ -393,7 +505,7 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSPIM_ERROR("device is already initialized!!!");
+        FSPIM_ERROR("The device is not initialized!!!");
         return FSPIM_ERR_NOT_READY;
     }
 
@@ -406,11 +518,17 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
 
     reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
     if (tx_buf && rx_buf)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
     else if (rx_buf)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_ONLY);
+    }
     else
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 
@@ -439,8 +557,8 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
 
 /**
  * @name: FSpimTransferByInterrupt
- * @msg: 先发送后接收数据 (中断处理)，利用Fifo进行处理
- * @return {FError} FSPIM_SUCCESS表示处理成功，其它返回值表示处理失败
+ * @msg: 配置并打开spim中断传输，利用Fifo进行处理
+ * @return {FError} FSPIM_SUCCESS表示成功打开中断，其它返回值表示失败
  * @param {FSpim} *instance_p 驱动控制数据
  * @param {void} *tx_buf 写缓冲区
  * @param {void} *rx_buf 读缓冲区
@@ -456,7 +574,7 @@ FError FSpimTransferByInterrupt(FSpim *instance_p, const void *tx_buf, void *rx_
 
     if (FT_COMPONENT_IS_READY != instance_p->is_ready)
     {
-        FSPIM_ERROR("device is already initialized!!!");
+        FSPIM_ERROR("The device is not initialized!!!");
         return FSPIM_ERR_NOT_READY;
     }
 
@@ -469,11 +587,17 @@ FError FSpimTransferByInterrupt(FSpim *instance_p, const void *tx_buf, void *rx_
 
     reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
     if (tx_buf && rx_buf)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
     else if (rx_buf)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_ONLY);
+    }
     else
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 
@@ -495,7 +619,7 @@ FError FSpimTransferByInterrupt(FSpim *instance_p, const void *tx_buf, void *rx_
     return FSPIM_SUCCESS;
 }
 
-#ifdef FSPIM_VERSION_2 /* E2000 */
+#if defined(FSPIM_VERSION_2) /* E2000 */
 
 /**
  * @name: FSpimTransferDMA
@@ -527,11 +651,17 @@ FError FSpimTransferDMA(FSpim *instance_p, boolean tx, boolean rx)
 
     reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK;
     if (tx && rx)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
     else if (rx)
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_ONLY);
+    }
     else
+    {
         reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 
@@ -542,14 +672,22 @@ FError FSpimTransferDMA(FSpim *instance_p, boolean tx, boolean rx)
     /* enable DMA tx / rx */
     reg_val = FSPIM_READ_REG32(base_addr, FSPIM_DMA_CR_OFFSET);
     if (tx)
+    {
         reg_val |= FSPIM_DMA_CR_TDMAE;
+    }
     else
+    {
         reg_val &= ~FSPIM_DMA_CR_TDMAE;
+    }
 
     if (rx)
+    {
         reg_val |= FSPIM_DMA_CR_RDMAE;
+    }
     else
+    {
         reg_val &= ~FSPIM_DMA_CR_RDMAE;
+    }
     FSPIM_WRITE_REG32(base_addr, FSPIM_DMA_CR_OFFSET, reg_val);
 
     FSpimSelSlaveDev(base_addr, instance_p->config.slave_dev_id);
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.h b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.h
index cb3ffb346e6..7783ceb520d 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.h
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim.h
@@ -14,14 +14,15 @@
  * FilePath: fspim.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:38
- * Description:  This files is for
+ * Description:  This file is for providing spim basic api func and predefined variables.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
- * 1.2   zhugengyu  2022-5-13   support spi dma
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
+ * 1.2   zhugengyu  2022/5/13   support spi dma
+ * 1.3 liqiaozhong 2022/12/30 add check func and spim option func
  */
 
 
@@ -34,7 +35,7 @@ extern "C"
 #endif
 
 /***************************** Include Files *********************************/
-
+#include "fparameters.h"
 #include "ftypes.h"
 #include "ferror_code.h"
 #include "fassert.h"
@@ -52,10 +53,15 @@ extern "C"
 #define FSPIM_ERR_TRANS_FAIL    FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 6)
 #define FSPIM_ERR_DMA_INIT      FT_MAKE_ERRCODE(ErrModBsp, ErrBspSpi, 6)
 
-#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000)
-#define FSPIM_VERSION_1 /* 用于FT2000/4和D2000平台的SPIM */
+#define FSPIM_CPOLTYPE_OPTION  0
+#define FSPIM_CPHATYPE_OPTION  1
+#define FSPIM_FREQUENCY_OPTION  2
+
+#if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000) || defined(TARDIGRADE)
+#define FSPIM_VERSION_1 /* SPIM for FT2000/4 and D2000 */
 #elif defined(CONFIG_TARGET_E2000)
-#define FSPIM_VERSION_2 /* 用于E2000平台的SPIM */
+#define FSPIM_VERSION_2 /* SPIM for E2000 */
+
 #else
 #error "Invalid target board !!!"
 #endif
@@ -64,6 +70,11 @@ extern "C"
 #define FSPIM_ERR_CODE_PREFIX  FSPIM_ERR_TRANS_FAIL & (FT_ERRCODE_SYS_MODULE_MASK | FT_ERRCODE_SUB_MODULE_MASK)
 #define FSPIM_NUM_OF_ERR_CODE  8
 
+typedef enum
+{
+    FSPIM_DEV_MASTER_MODE = 0 /* only support master mode */
+} FSpimWorkMode;
+
 typedef enum
 {
     FSPIM_SLAVE_DEV_0 = 0,
@@ -113,10 +124,10 @@ typedef enum
 
 typedef enum
 {
-    FSPIM_INTR_EVT_RX_DONE = 0, /* 接收完成事件 */
-    FSPIM_INTR_EVT_TX_OVERFLOW, /* 发送FIFO上溢事件 */
-    FSPIM_INTR_EVT_RX_UNDERFLOW, /* 接收FIFO下溢事件 */
-    FSPIM_INTR_EVT_RX_OVERFLOW, /* 接收FIFO上溢事件 */
+    FSPIM_INTR_EVT_RX_DONE = 0, /*  receive complete event */
+    FSPIM_INTR_EVT_TX_OVERFLOW, /* send FIFO overflow event */
+    FSPIM_INTR_EVT_RX_UNDERFLOW, /* receive FIFO underflow event */
+    FSPIM_INTR_EVT_RX_OVERFLOW, /* receive FIFO overflow event */
 
     FSPIM_INTR_EVT_NUM
 } FSpimIntrEvtType;
@@ -132,6 +143,7 @@ typedef struct
     uintptr              base_addr;    /* Device base address */
     u32                  irq_num;      /* Device intrrupt id */
     u32                  irq_prority;  /* Device intrrupt priority */
+    FSpimWorkMode        work_mode;    /* Device work mode */
     FSpimSlaveDevice     slave_dev_id; /* Slave device id */
     u32                  max_freq_hz;  /* Clock frequency in Hz */
     FSpimTransByte       n_bytes;      /* Bytes in transfer */
@@ -179,10 +191,17 @@ FError FSpimCfgInitialize(FSpim *instance_p, const FSpimConfig *cofig_p);
 /* 完成I2C驱动实例去使能，清零实例数据 */
 void FSpimDeInitialize(FSpim *instance_p);
 
+/* FSPIM临时修改参数操作 */
+FError FSpimSetOption(FSpim *instance_p, u32 option, u32 value);
+
+/* FSPIM获取某些参数 */
+u32 FSpimGetOption(FSpim *instance_p, u32 option);
+
 /* 先发送后接收数据 (阻塞处理)，利用Fifo进行处理 */
 FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf, fsize_t len);
 
-#ifdef FSPIM_VERSION_2 /* E2000 */
+#if defined(FSPIM_VERSION_2)/* E2000 */
+
 /* 启动SPIM DMA数据传输 */
 FError FSpimTransferDMA(FSpim *instance_p, boolean tx, boolean rx);
 
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_g.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_g.c
index 5094ff58eaa..d61e966e354 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_g.c
@@ -14,13 +14,13 @@
  * FilePath: fspim_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:07:55
- * Description:  This files is for
+ * Description:  This file is for providing spim basic information.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
  */
 
 /***************************** Include Files *********************************/
@@ -42,14 +42,15 @@
 
 /************************** Variable Definitions *****************************/
 
-const FSpimConfig FSPIM_CONFIG_TBL[FSPI_DEVICE_NUM] =
+const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
 {
     [FSPI0_ID] =
     {
         .instance_id  = FSPI0_ID, /* Id of device*/
-        .base_addr = FSPI0_BASE,
+        .base_addr = FSPI0_BASE_ADDR,
         .irq_num = FSPI0_IRQ_NUM,
         .irq_prority = 0,
+        .work_mode = FSPIM_DEV_MASTER_MODE,
         .slave_dev_id = FSPIM_SLAVE_DEV_0,
         .max_freq_hz  = 4000000,
         .n_bytes      = 1,
@@ -59,22 +60,24 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_DEVICE_NUM] =
     [FSPI1_ID] =
     {
         .instance_id  = FSPI1_ID, /* Id of device*/
-        .base_addr = FSPI1_BASE,
+        .base_addr = FSPI1_BASE_ADDR,
         .irq_num = FSPI1_IRQ_NUM,
         .irq_prority = 0,
+        .work_mode = FSPIM_DEV_MASTER_MODE,
         .slave_dev_id = FSPIM_SLAVE_DEV_0,
         .max_freq_hz  = 4000000,
         .n_bytes      = 1,
         .en_test = FALSE,
         .en_dma  = FALSE
     },
-#if defined(CONFIG_TARGET_E2000S) || defined(CONFIG_TARGET_E2000D) || defined(CONFIG_TARGET_E2000Q)
+#if defined(CONFIG_TARGET_E2000)
     [FSPI2_ID] =
     {
         .instance_id  = FSPI2_ID, /* Id of device*/
         .base_addr = FSPI2_BASE,
         .irq_num = FSPI2_IRQ_NUM,
         .irq_prority = 0,
+        .work_mode = FSPIM_DEV_MASTER_MODE,
         .slave_dev_id = FSPIM_SLAVE_DEV_0,
         .max_freq_hz  = 4000000,
         .n_bytes      = 1,
@@ -87,6 +90,7 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_DEVICE_NUM] =
         .base_addr = FSPI3_BASE,
         .irq_num = FSPI3_IRQ_NUM,
         .irq_prority = 0,
+        .work_mode = FSPIM_DEV_MASTER_MODE,
         .slave_dev_id = FSPIM_SLAVE_DEV_0,
         .max_freq_hz  = 4000000,
         .n_bytes      = 1,
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.c
index c1004bea238..406c3b6ad13 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.c
@@ -14,13 +14,14 @@
  * FilePath: fspim_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:00
- * Description:  This files is for
+ * Description:  This file is for providing spim Hardware interaction func.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
+ * 1.2  liqiaozhong 2023/1/4    add data get func
  */
 
 
@@ -60,7 +61,7 @@ u32 FSpimGetTxFifoDepth(uintptr base_addr)
         FSpimSetTxFifoThreshold(base_addr, fifo_depth);
         if (fifo_depth != FSpimGetTxFifoThreshold(base_addr))
         {
-            FSPIM_INFO("Tx fifo threshold is %d", fifo_depth);
+            FSPIM_INFO("The Tx fifo threshold is %d", fifo_depth);
             break;
         }
     }
@@ -83,7 +84,7 @@ u32 FSpimGetRxFifoDepth(uintptr base_addr)
         FSpimSetRxFifoThreshold(base_addr, fifo_depth);
         if (fifo_depth != FSpimGetRxFifoThreshold(base_addr))
         {
-            FSPIM_INFO("Rx fifo threshold is %d", fifo_depth);
+            FSPIM_INFO("The Rx fifo threshold is %d", fifo_depth);
             break;
         }
 
@@ -118,23 +119,48 @@ void FSpimSelSlaveDev(uintptr base_addr, u32 slave_dev_id)
  * @param {u32} speed, SPI传输速度设置
  */
 FError FSpimSetSpeed(uintptr base_addr, u32 speed)
-{
+{   
+    FASSERT(speed != 0);
     u32 clk_div;
     boolean enabled = FSpimGetEnable(base_addr);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, FALSE);
+    }
 
-    clk_div = FSPI_FREQ / speed;
-    FSPIM_INFO("set clk div as %d", clk_div);
+    clk_div = FSPI_CLK_FREQ_HZ / speed;
+    if (clk_div < FSPIM_BAUD_R_SCKDV_MIN || clk_div > FSPIM_BAUD_R_SCKDV_MAX)
+    {
+        FSPIM_ERROR("Clk div is %d => do not support, this parameter should be set as an even from 2 to 65534.", clk_div);
+        return FSPIM_ERR_NOT_SUPPORT;
+    }
+    FSPIM_INFO("Set clk div as %d", clk_div);
     FSPIM_WRITE_REG32(base_addr, FSPIM_BAUD_R_OFFSET, clk_div);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, TRUE);
+    }
 
     return FSPIM_SUCCESS;
 }
 
+/**
+ * @name: FSpimGetSpeed
+ * @msg: 获取SPI传输速度
+ * @return {u32}FSPIM传输频率
+ * @param {uintptr} base_addr, SPI控制器基地址
+ * @param {u32} speed, SPI传输速度设置
+ */
+u32 FSpimGetSpeed(uintptr base_addr)
+{
+    u32 clk_div;
+    u32 spim_speed;
+    
+    return FSPIM_READ_REG32(base_addr, FSPIM_BAUD_R_OFFSET);
+}
+
 /**
  * @name: FSpimSetTransMode
  * @msg: 设置SPI传输模式
@@ -149,33 +175,37 @@ void FSpimSetTransMode(uintptr base_addr, u32 trans_mode)
     boolean enabled = FSpimGetEnable(base_addr);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, FALSE);
+    }
 
     reg_val = FSpimGetCtrlR0(base_addr);
     reg_val &= ~FSPIM_CTRL_R0_TMOD_MASK; /* clear trans mode bits */
     switch (trans_mode)
     {
-    case FSPIM_TRANS_MODE_RX_TX:
-        reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
-        break;
-    case FSPIM_TRANS_MODE_TX_ONLY:
-        reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_TX_ONLY);
-        break;
-    case FSPIM_TRANS_MODE_RX_ONLY:
-        reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_ONLY);
-        break;
-    case FSPIM_TRANS_MODE_READ_EEPROM:
-        reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RD_EEPROM);
-        break;
-    default:
-        FASSERT(0);
-        break;
+        case FSPIM_TRANS_MODE_RX_TX:
+            reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_TX);
+            break;
+        case FSPIM_TRANS_MODE_TX_ONLY:
+            reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_TX_ONLY);
+            break;
+        case FSPIM_TRANS_MODE_RX_ONLY:
+            reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RX_ONLY);
+            break;
+        case FSPIM_TRANS_MODE_READ_EEPROM:
+            reg_val |= FSPIM_CTRL_R0_TMOD(FSPIM_TMOD_RD_EEPROM);
+            break;
+        default:
+            FASSERT(0);
+            break;
     }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, TRUE);
+    }
 
     return;
 }
@@ -193,15 +223,41 @@ void FSpimSetCpha(uintptr base_addr, u32 cpha_mode)
 
     reg_val &= ~FSPIM_CTRL_R0_SCPHA_MASK; /* clear bits */
     if (FSPIM_CPHA_1_EDGE == cpha_mode)
+    {
         reg_val |= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_MID);
+    }
     else if (FSPIM_CPHA_2_EDGE == cpha_mode)
+    {
         reg_val |= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_BEG);
+    }
     else
+    {
         FASSERT(0);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 }
 
+/**
+ * @name: FSpimGetCpha
+ * @msg: 获取串行时钟相位
+ * @return {FSpimCphaType}串行时钟相位
+ * @param {uintptr} base_addr, SPI控制器基地址
+ */
+FSpimCphaType FSpimGetCpha(uintptr base_addr)
+{
+    u32 reg_val = FSpimGetCtrlR0(base_addr);
+
+    if (reg_val &= FSPIM_CTRL_R0_SCPHA(FSPIM_SCPHA_SWITCH_DATA_BEG))
+    {
+        return FSPIM_CPHA_2_EDGE;
+    }
+    else 
+    {
+        return FSPIM_CPHA_1_EDGE;
+    }
+}
+
 /**
  * @name: FSpimSetCpol
  * @msg: 设置串行时钟极性
@@ -215,15 +271,41 @@ void FSpimSetCpol(uintptr base_addr, u32 cpol_mode)
 
     reg_val &= ~FSPIM_CTRL_R0_SCPOL_MASK; /* clear bits */
     if (FSPIM_CPOL_LOW == cpol_mode)
+    {
         reg_val |= FSPIM_CTRL_R0_SCPOL(FSPIM_SCPOL_INACTIVE_LOW);
+    }
     else if (FSPIM_CPOL_HIGH == cpol_mode)
+    {
         reg_val |= FSPIM_CTRL_R0_SCPOL(FSPIM_SCPOL_INACTIVE_HIGH);
+    }
     else
+    {
         FASSERT(0);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 }
 
+/**
+ * @name: FSpimGetCpol
+ * @msg: 获取串行时钟极性
+ * @return {无}
+ * @param {uintptr} base_addr, SPI控制器基地址
+ */
+FSpimCpolType FSpimGetCpol(uintptr base_addr)
+{
+    u32 reg_val = FSpimGetCtrlR0(base_addr);
+
+    if (reg_val &= FSPIM_CTRL_R0_SCPOL(FSPIM_SCPOL_INACTIVE_HIGH))
+    {
+        return FSPIM_CPOL_HIGH;
+    }
+    else
+    {
+        return FSPIM_CPOL_LOW;
+    }
+}
+
 /**
  * @name: FSpimSetSlaveEnable
  * @msg: 使能/去使能和从设备的连接
@@ -237,20 +319,28 @@ void FSpimSetSlaveEnable(uintptr base_addr, boolean enable)
     boolean enabled = FSpimGetEnable(base_addr);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, FALSE);
+    }
 
     reg_val = FSpimGetCtrlR0(base_addr);
 
     reg_val &= ~FSPIM_CTRL_R0_SLV_OE_MASK;
     if (enable)
+    {
         reg_val |= FSPIM_CTRL_R0_SLV_OE(FSPIM_SLAVE_TX_ENABLE);
+    }
     else
+    {
         reg_val |= FSPIM_CTRL_R0_SLV_OE(FSPIM_SLAVE_TX_DISALE);
+    }
 
     FSpimSetCtrlR0(base_addr, reg_val);
 
     if (enabled)
+    {
         FSpimSetEnable(base_addr, TRUE);
+    }
 
     return;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.h b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.h
index d66f3bfa306..7519a493c89 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_hw.h
@@ -14,14 +14,16 @@
  * FilePath: fspim_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:05
- * Description:  This files is for
+ * Description:  This file is for providing spim Hardware interaction api 
+ *               and some predefined variables.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
- * 1.2   zhugengyu  2022-5-13   support spi dma
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
+ * 1.2   zhugengyu  2022/5/13   support spi dma
+ * 1.3  liqiaozhong 2023/1/4    add data get func
  */
 
 
@@ -38,6 +40,7 @@ extern "C"
 #include "fkernel.h"
 #include "fio.h"
 #include "ftypes.h"
+#include "fspim.h"
 
 /************************** Constant Definitions *****************************/
 /** @name Register Map
@@ -165,8 +168,8 @@ enum
 /** @name FSPIM_BAUD_R_OFFSET Register
  */
 #define FSPIM_BAUD_R_SCKDV(x)        (GENMASK(15, 0) & ((x) << 0)) /* SCKDV 为 2 ~ 65534 之间的任何偶数值 */
-#define FSPIM_BAUD_R_SCKDV_MIN       2
-#define FSPIM_BAUD_R_SCKDV_MAX       65534
+#define FSPIM_BAUD_R_SCKDV_MIN       2U
+#define FSPIM_BAUD_R_SCKDV_MAX       65534U
 #define FSPIM_BAUD_R_SCKDV_IS_VALID(x)  (0 == (x) % 2)
 
 /** @name FSPIM_TXFTL_R_OFFSET Register
@@ -286,7 +289,6 @@ enum
 
 #define FSPIM_TX_DMA_LEVEL             0x10
 #define FSPIM_RX_DMA_LEVEL             0xf
-
 /**************************** Type Definitions *******************************/
 
 /************************** Variable Definitions *****************************/
@@ -466,9 +468,13 @@ static inline boolean FSpimGetEnable(uintptr base_addr)
 static inline void FSpimSetEnable(uintptr base_addr, boolean enable)
 {
     if (enable)
+    {
         FSPIM_WRITE_REG32(base_addr, FSPIM_SSIENR_OFFSET, FSPIM_SSIENR_SSI_EN(1));
+    }
     else
+    {
         FSPIM_WRITE_REG32(base_addr, FSPIM_SSIENR_OFFSET, FSPIM_SSIENR_SSI_EN(0));
+    }
 }
 
 /**
@@ -572,15 +578,24 @@ void FSpimSelSlaveDev(uintptr base_addr, u32 slave_dev_id);
 /* 设置SPI传输速度 */
 FError FSpimSetSpeed(uintptr base_addr, u32 speed);
 
+/* 读取SPI传输速度 */
+u32 FSpimGetSpeed(uintptr base_addr);
+
 /* 设置SPI传输模式 */
 void FSpimSetTransMode(uintptr base_addr, u32 trans_mode);
 
 /* 设置串行时钟相位 */
 void FSpimSetCpha(uintptr base_addr, u32 cpha_mode);
 
-/* 设置串行时钟极性 */
+/* 设置串行时钟相位 */
 void FSpimSetCpol(uintptr base_addr, u32 cpol_mode);
 
+/* 读取串行时钟相位 */
+FSpimCphaType FSpimGetCpha(uintptr base_addr);
+
+/* 读取串行时钟极性 */
+FSpimCpolType FSpimGetCpol(uintptr base_addr);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_intr.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_intr.c
index 6d1e85df4dc..c1b29451170 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_intr.c
@@ -14,13 +14,13 @@
  * FilePath: fspim_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:10
- * Description:  This files is for
+ * Description:  This file is for providing spim interrupt func.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_selftest.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_selftest.c
index 1040178d777..c54b8df7dd5 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_selftest.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_selftest.c
@@ -14,11 +14,13 @@
  * FilePath: fspim_selftest.c
  * Date: 2022-07-21 13:21:43
  * LastEditTime: 2022-07-21 13:21:44
- * Description:  This files is for
+ * Description:  This file is for providing spim self test func.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
  */
 /***************************** Include Files *********************************/
 #include "fio.h"
diff --git a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_sinit.c b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_sinit.c
index 13b2d176660..fd3c85fc7f8 100644
--- a/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/spi/fspim/fspim_sinit.c
@@ -14,13 +14,13 @@
  * FilePath: fspim_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:08:24
- * Description:  This files is for
+ * Description:  This file is for providing spim init basic func.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   zhugengyu  2021-12-3   init commit
- * 1.1   zhugengyu  2022-4-15   support test mode
+ * 1.0   zhugengyu  2021/12/3   init commit
+ * 1.1   zhugengyu  2022/4/15   support test mode
  */
 
 /***************************** Include Files *********************************/
@@ -37,7 +37,7 @@
 
 /************************** Variable Definitions *****************************/
 
-extern const FSpimConfig FSPIM_CONFIG_TBL[FSPI_DEVICE_NUM];
+extern const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM];
 
 /************************** Function Prototypes ******************************/
 /**
@@ -51,7 +51,7 @@ const FSpimConfig *FSpimLookupConfig(u32 instance_id)
     const FSpimConfig *ptr = NULL;
     u32 index;
 
-    for (index = 0; index < (u32)FSPI_DEVICE_NUM; index++)
+    for (index = 0; index < (u32)FSPI_NUM; index++)
     {
         if (FSPIM_CONFIG_TBL[index].instance_id == instance_id)
         {
@@ -61,4 +61,4 @@ const FSpimConfig *FSpimLookupConfig(u32 instance_id)
     }
 
     return (const FSpimConfig *)ptr;
-}
\ No newline at end of file
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftacho.c b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftacho.c
index 87087e6caa6..b7a69c99652 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftacho.c
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftacho.c
@@ -14,11 +14,12 @@
  * FilePath: ftacho.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-05-20 09:08:52
- * Description:  This files is for
+ * Description:  This file is for user tacho API implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/05/20    first commit
  */
 
 /***************************** Include Files *********************************/
@@ -47,7 +48,7 @@ FError FTachoInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
 
     if (instance_p->isready == FT_COMPONENT_IS_READY)
     {
-        FTIMER_INFO("device is already initialized.!!!\r\n");
+        FTIMER_INFO("Device is already initialized !!!\r\n");
         return FTIMER_TACHO_ERR_IS_READ;
     }
 
@@ -69,7 +70,7 @@ FError FTachoInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTACHO_ERROR("not support work_mode.");
+        FTACHO_ERROR("Not support work_mode.");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -84,7 +85,7 @@ FError FTachoInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTACHO_ERROR("invalid input 32/64bits.");
+        FTACHO_ERROR("Invalid input 32/64bits.");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -106,7 +107,7 @@ FError FTachoInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTACHO_ERROR("invalid input edge.");
+        FTACHO_ERROR("Invalid input edge.");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -142,7 +143,7 @@ FError FTachoGetFanRPM(FTimerTachoCtrl *instance_p, u32 *rpm)
 
     if (instance_p->isready != FT_COMPONENT_IS_READY || instance_p->config.work_mode != FTIMER_WORK_MODE_TACHO)
     {
-        FTIMER_ERROR("device is not already or not work on TACHO_MODE!!!");
+        FTIMER_ERROR("Device is not ready or not work on TACHO_MODE!!!");
         return FTIMER_TACHO_ERR_NOT_READY;
     }
 
@@ -176,7 +177,7 @@ FError FTachoGetFanRPM(FTimerTachoCtrl *instance_p, u32 *rpm)
     {
         /* calculate rpm */
         /* (60(second) * freq * tacho) / (2 * (cmp_l + 1)) cmp_l */
-        *rpm = (TIMER_CLK_FREQ_HZ * 60 * raw_dat) / (2 * (cnt_num + 1));
+        *rpm = (FTIMER_CLK_FREQ_HZ * 60 * raw_dat) / (2 * (cnt_num + 1));
     }
 
     return FTIMER_TACHO_SUCCESS;
@@ -196,7 +197,7 @@ u32 FTachoGetCaptureCnt(FTimerTachoCtrl *instance_p)
 
     if (instance_p->isready != FT_COMPONENT_IS_READY || instance_p->config.work_mode != FTIMER_WORK_MODE_CAPTURE)
     {
-        FTIMER_ERROR("device is not already or not work on CAPTURE_MODE!!!");
+        FTIMER_ERROR("Device is not ready or not work on CAPTURE_MODE!!!");
         return FTIMER_TACHO_ERR_NOT_READY;
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer.c b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer.c
index 3b10410b4cf..8bfd08c74f4 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer.c
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer.c
@@ -14,11 +14,12 @@
  * FilePath: ftimer.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:09:49
- * Description:  This files is for
+ * Description:  This file is for user timer API implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/02/18    first commit
  */
 
 /***************************** Include Files *********************************/
@@ -41,7 +42,7 @@ FError FTimerSoftwareReset(FTimerTachoCtrl *instance_p)
 
     if (instance_p->isready != FT_COMPONENT_IS_READY)
     {
-        FTIMER_ERROR("device is not already!!!");
+        FTIMER_ERROR("Device is not ready!!!");
         return FTIMER_TACHO_ERR_NOT_READY;
     }
 
@@ -149,7 +150,7 @@ static FError TimerSwithBits(FTimerTachoCtrl *instance_p)
     }
     else
     {
-        FTIMER_ERROR("invalid input");
+        FTIMER_ERROR("Invalid input");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -258,7 +259,7 @@ inline FError FTimerSetStartVal(FTimerTachoCtrl *instance_p, u32 cnt)
        otherwise the previous cmp val still work */
     TimerForceLoad(instance_p);
 
-    FTIMER_INFO("set start val 0x%x", FTIMER_STAR_READ(instance_p));
+    FTIMER_INFO("Set start val 0x%x", FTIMER_STAR_READ(instance_p));
 
     return ret;
 }
@@ -313,15 +314,15 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     u32 Ret = FTIMER_TACHO_SUCCESS;
 
     if ((FTIMER_ONCE_CMP == config_p->cmp_type) &&
-            (FTIMER_FREE_RUN != config_p->timer_mode))
+        (FTIMER_FREE_RUN != config_p->timer_mode))
     {
-        FTIMER_ERROR("time mode shall be free-run when use once timer!!");
+        FTIMER_ERROR("Time mode shall be free-run when use once timer!!");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
     if (instance_p->isready == FT_COMPONENT_IS_READY)
     {
-        FTIMER_INFO("device is already initialized.!!!\r\n");
+        FTIMER_INFO("Device is already initialized.!!!\r\n");
         return FTIMER_TACHO_ERR_IS_READ;
     }
 
@@ -331,7 +332,7 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTIMER_ERROR("not support");
+        FTIMER_ERROR("Not support");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -345,7 +346,7 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTIMER_ERROR("invalid input");
+        FTIMER_ERROR("Invalid input");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -359,7 +360,7 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTIMER_ERROR("invalid input");
+        FTIMER_ERROR("Invalid input");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -373,7 +374,7 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
     }
     else
     {
-        FTIMER_ERROR("invalid input");
+        FTIMER_ERROR("Invalid input");
         return FTIMER_TACHO_ERR_INVAL_PARM;
     }
 
@@ -428,32 +429,32 @@ FError FTimeSettingDump(const FTimerTachoCtrl *instance_p)
 
     FASSERT(FT_COMPONENT_IS_READY == instance_p->isready);
 
-    printf("ctrl: \r\n");
-    printf("===%d-bit timer\r\n", is64Bit ? 64 : 32);
-    printf("===timer enabled: %d\r\n", (CtrlReg & FTIMER_REG_ENABLE) ? 1 : 0);
-    printf("===timer mode: %d\r\n", (CtrlReg & FTIMER_REG_TACHO_MODE_TIMER) ? 1 : 0);
-    printf("===once timer: %d\r\n", (CtrlReg & FTIMER_REG_MODE_ONCE) ? 1 : 0);
-    printf("===restart mode: %d\r\n", (CtrlReg & FTIMER_REG_CNT_RESTART) ? 1 : 0);
-    printf("===in reset: %d\r\n", (CtrlReg & FTIMER_REG_TACHO_RESET) ? 1 : 0);
-    printf("===force load: %d\r\n", (CtrlReg & FTIMER_REG_TACHO_FORCE_LOAD) ? 1 : 0);
-    printf("===clear cnt: %d\r\n", (CtrlReg & FTIMER_REG_CNT_CLR) ? 1 : 0);
-
-    printf("start cnt: 0x%08x\r\n", FTIMER_STAR_READ(instance_p));
+    FTIMER_DEBUG("ctrl: ");
+    FTIMER_DEBUG("===%d-bit timer", is64Bit ? 64 : 32);
+    FTIMER_DEBUG("===timer enabled: %d", (CtrlReg & FTIMER_REG_ENABLE) ? 1 : 0);
+    FTIMER_DEBUG("===timer mode: %d", (CtrlReg & FTIMER_REG_TACHO_MODE_TIMER) ? 1 : 0);
+    FTIMER_DEBUG("===once timer: %d", (CtrlReg & FTIMER_REG_MODE_ONCE) ? 1 : 0);
+    FTIMER_DEBUG("===restart mode: %d", (CtrlReg & FTIMER_REG_CNT_RESTART) ? 1 : 0);
+    FTIMER_DEBUG("===in reset: %d", (CtrlReg & FTIMER_REG_TACHO_RESET) ? 1 : 0);
+    FTIMER_DEBUG("===force load: %d", (CtrlReg & FTIMER_REG_TACHO_FORCE_LOAD) ? 1 : 0);
+    FTIMER_DEBUG("===clear cnt: %d", (CtrlReg & FTIMER_REG_CNT_CLR) ? 1 : 0);
+
+    FTIMER_DEBUG("start cnt: 0x%08x", FTIMER_STAR_READ(instance_p));
     if (is64Bit)
     {
-        printf("cmp low: 0x%08x", FTIMER_CMPL_READ(instance_p));
-        printf("high: 0x%08x\r\n", FTIMER_CMPU_READ(instance_p));
-        printf("cur cnt: low: 0x%08x", FTIMER_CNTL_READ(instance_p));
-        printf("high: 0x%08x\r\n", FTIMER_CNTU_READ(instance_p));
+        FTIMER_DEBUG("cmp low: 0x%08x", FTIMER_CMPL_READ(instance_p));
+        FTIMER_DEBUG("high: 0x%08x", FTIMER_CMPU_READ(instance_p));
+        FTIMER_DEBUG("cur cnt: low: 0x%08x", FTIMER_CNTL_READ(instance_p));
+        FTIMER_DEBUG("high: 0x%08x", FTIMER_CNTU_READ(instance_p));
     }
     else
     {
-        printf("cmp low: 0x%08x\r\n", FTIMER_CMPL_READ(instance_p));
-        printf("cur cnt: low: 0x%08x", FTIMER_CNTL_READ(instance_p));
+        FTIMER_DEBUG("cmp low: 0x%08x", FTIMER_CMPL_READ(instance_p));
+        FTIMER_DEBUG("cur cnt: low: 0x%08x", FTIMER_CNTL_READ(instance_p));
     }
 
-    printf("intr mask: 0x%08x\r\n", FTIMER_INTR_M_READ(instance_p));
-    printf("intr status: 0x%08x\r\n", FTIMER_INTR_S_READ(instance_p));
+    FTIMER_DEBUG("intr mask: 0x%08x", FTIMER_INTR_M_READ(instance_p));
+    FTIMER_DEBUG("intr status: 0x%08x", FTIMER_INTR_S_READ(instance_p));
 
     return FTIMER_TACHO_SUCCESS;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho.h b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho.h
index 8f8b4a9edf6..7912ca3e76f 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho.h
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho.h
@@ -14,25 +14,26 @@
  * FilePath: ftimer_tacho.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:09:43
- * Description:  This files is for
+ * Description:  This file is for user ftimer_tacho API definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/02/18   first commit
  */
 
-#ifndef BSP_DRIVERS_E2000_TIMER_TACHO_H
-#define BSP_DRIVERS_E2000_TIMER_TACHO_H
+#ifndef FTIMER_TACHO_H
+#define FTIMER_TACHO_H
+
+#include "ftypes.h"
+#include "fdebug.h"
+#include "ferror_code.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
-#include "fdebug.h"
-#include "ferror_code.h"
-
 #define FTIMER_TACHO_SUCCESS          FT_SUCCESS
 #define FTIMER_TACHO_ERR_INVAL_PARM   FT_MAKE_ERRCODE(ErrModBsp, ErrBspTimer, 1)
 #define FTIMER_TACHO_ERR_NOT_READY    FT_MAKE_ERRCODE(ErrModBsp, ErrBspTimer, 2)
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_g.c b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_g.c
index 8c4868c3af0..6353f21c6e5 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_g.c
@@ -14,11 +14,12 @@
  * FilePath: ftimer_tacho_g.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:09:07
- * Description:  This files is for
+ * Description:  This file is for timer_tacho static configuration
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/02/18    first commit
  */
 
 /***************************** Include Files *********************************/
@@ -33,7 +34,7 @@
 /************************** Function Prototypes ******************************/
 void FTimerGetDefConfig(u32 timer_id, FTimerTachoConfig *config_p)
 {
-    FASSERT((timer_id < TIMER_NUM) && (NULL != config_p));
+    FASSERT((timer_id < FTIMER_NUM) && (NULL != config_p));
 
     memset(config_p, 0, sizeof(FTimerTachoConfig));
     config_p->id = timer_id;
@@ -47,7 +48,7 @@ void FTimerGetDefConfig(u32 timer_id, FTimerTachoConfig *config_p)
 
 void FTachoGetDefConfig(u32 tacho_id, FTimerTachoConfig *config_p)
 {
-    FASSERT((tacho_id < TACHO_NUM) && (NULL != config_p));
+    FASSERT((tacho_id < FTACHO_NUM) && (NULL != config_p));
 
     memset(config_p, 0, sizeof(FTimerTachoConfig));
     config_p->id = tacho_id;
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_hw.h b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_hw.h
index e9bc4d6bd10..d5d937ff8a7 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_hw.h
@@ -14,26 +14,27 @@
  * FilePath: ftimer_tacho_hw.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:09:15
- * Description:  This files is for
+ * Description:  This file is for timer_tacho register definition
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/02/18   first commit
  */
 
-#ifndef BSP_DRIVERS_E2000_TIMER_HW_H
-#define BSP_DRIVERS_E2000_TIMER_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FTIMER_TACHO_HW_H
+#define FTIMER_TACHO_HW_H
 
 #include "fio.h"
 #include "ftypes.h"
 #include "fkernel.h"
 #include "fparameters.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /* register offset */
 #define FTIMER_CTRL_REG_OFFSET (0x0)                /*Timer or Tachometer 控制寄存器*/
 #define FTACHO_RESULT_REG_OFFSET (0x4)                /*一个转速周期内的时钟周期计数结果*/
@@ -134,7 +135,7 @@ extern "C"
 
 #define FTIMER_TIMEOUT 3000     /*超时时间*/
 
-#define FTIMER_BASE_ADDR(instance_p) TIMER_TACHO_BASE_ADDR((instance_p)->config.id)        /*获取设备基地址*/
+#define FTIMER_BASE_ADDR(instance_p) FTIMER_TACHO_BASE_ADDR((instance_p)->config.id)        /*获取设备基地址*/
 /*read and write reg value*/
 #define FTIMER_CTRL_READ(instance_p) FTIMER_READ_REG32(FTIMER_BASE_ADDR(instance_p), FTIMER_CTRL_REG_OFFSET)
 #define FTIMER_CTRL_WRITE(instance_p, regVal) FTIMER_WRITE_REG32(FTIMER_BASE_ADDR(instance_p), FTIMER_CTRL_REG_OFFSET, (regVal))
diff --git a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_intr.c b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_intr.c
index 015a0799dff..c7318ede81e 100644
--- a/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/timer/ftimer_tacho/ftimer_tacho_intr.c
@@ -14,18 +14,18 @@
  * FilePath: ftimer_tacho_intr.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:09:36
- * Description:  This files is for
+ * Description:  This file is for timer_tacho interrupt operation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0  liushengming 2022/02/18    first commit
  */
 
 /***************************** Include Files *********************************/
 #include "fassert.h"
 #include "ftimer_tacho.h"
 #include "ftimer_tacho_hw.h"
-#include "finterrupt.h"
 
 /************************** Constant Definitions *****************************/
 
@@ -99,7 +99,7 @@ void FTimerTachoIntrHandler(s32 vector, void *param)
     u32 loop;
     FTimerEventHandler evtHandler;
 
-    FTIMER_INFO("intr entered cause: 0x%x.\r\n", intr_status);
+    FTIMER_INFO("Intr entered cause: 0x%x.\r\n", intr_status);
 
     /* check intr status bit by bit */
     for (loop = 0; loop < FMAX_TIMER_TACHO_EVENT; loop++)
@@ -206,6 +206,6 @@ void FTimerTachoSetIntr(FTimerTachoCtrl *instance_p)
     {
         FASSERT(0);
     }
-    FTIMER_INFO("mask:0x%x.\r\n", FTIMER_INTR_M_READ(instance_p));
+    FTIMER_INFO("Mask:0x%x.\r\n", FTIMER_INTR_M_READ(instance_p));
     return;
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/Kconfig b/bsp/phytium/libraries/standalone/drivers/usb/Kconfig
index 3ecf7c474c2..18d0f459d8b 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/usb/Kconfig
@@ -5,5 +5,5 @@ config ENABLE_USB_FXHCI
     depends on USE_USB
     help
         Select USB FUSB_HC_XHCI Host driver component
-
-
+	
+	
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb.c
index f5e0818757e..a7a2fea4b59 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb.c
@@ -14,12 +14,12 @@
  * FilePath: fusb.c
  * Date: 2022-02-11 13:33:11
  * LastEditTime: 2022-02-18 09:22:06
- * Description:  This files is for implmentation of USB user API
+ * Description:  This file is for implmentation of USB user API
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0  Zhugengyu  2022/2/8     init commit
+ * 1.0  zhugengyu  2022/2/8     init commit
  */
 
 #include <string.h>
@@ -59,13 +59,17 @@ FError FUsbCfgInitialize(FUsb *instance, const FUsbConfig *input_config)
     FError ret = FUSB_SUCCESS;
 
     if (input_config != &instance->config)
+    {
         instance->config = *input_config;
+    }
 
     instance->hc = NULL; /* non usb host attached */
 
     /* create usb hc instance, which will be add as the head of hc list */
     if (NULL == FXhciHcInit(instance, instance->config.base_addr))
+    {
         ret = FUSB_ERR_ALLOCATE_FAIL;
+    }
 
     if (FUSB_SUCCESS == ret)
     {
@@ -113,7 +117,9 @@ void FUsbPoll(FUsb *instance)
     }
 
     if (FUsbPollPrepare)
+    {
         FUsbPollPrepare(instance);
+    }
 
     FUsbHc *controller = instance->hc;
     if (controller != NULL)
@@ -148,7 +154,9 @@ void FUsbExit(FUsb *instance)
     }
 
     if (FUsbExitPrepare)
+    {
         FUsbExitPrepare(instance);
+    }
 
     FUsbHc *controller = instance->hc;
     if (controller != NULL)
@@ -232,7 +240,9 @@ void FUsbMempFreeTag(FUsb *instance, void *ptr)
 {
     FASSERT(instance);
     if (NULL != ptr)
+    {
         FMempFreeTag(&instance->memp, ptr);
+    }
 
     return;
 }
@@ -263,7 +273,9 @@ FUsbHc *FUsbAllocateHc(FUsb *instance)
 void FUsbDetachHc(FUsbHc *controller)
 {
     if (controller == NULL)
+    {
         return;
+    }
 
     FUsb *instance = controller->usb;
     FUsbDetachDev(controller, 0); /* tear down root hub tree */
@@ -289,9 +301,9 @@ static FUsbDevInitHandler FUsbFindValidInitFunc(FUsb *instance, const FUsbDevInd
     {
         func = &instance->dev_init[loop];
         if ((index->category == func->index.category) &&
-                (index->class == func->index.class) &&
-                (index->sub_class == func->index.sub_class) &&
-                (index->protocol == func->index.protocol))
+            (index->class == func->index.class) &&
+            (index->sub_class == func->index.sub_class) &&
+            (index->protocol == func->index.protocol))
         {
             handler = func->handler;
         }
@@ -312,7 +324,9 @@ FError FUsbAssignDevInitFunc(FUsb *instance, const FUsbDevIndex *index, FUsbDevI
 {
     FASSERT(instance && index && handler);
     if (FUSB_MAX_DEV_TYPE_NUM == instance->dev_init_num)
+    {
         return FUSB_ERR_INVALID_PARA;
+    }
 
     if (NULL != FUsbFindValidInitFunc(instance, index))
     {
@@ -343,13 +357,13 @@ FUsbDev *FUsbInitDevEntry(FUsbHc *controller, int slot_id)
 
     if (NULL == dev)
     {
-        FUSB_ERROR("no memory to allocate device structure ");
+        FUSB_ERROR("No memory to allocate device structure .");
         return NULL;
     }
 
     if (controller->devices[slot_id] != NULL)
     {
-        FUSB_WARN("warning: device %d reassigned? ", slot_id);
+        FUSB_WARN("Warning: device %d reassigned? ", slot_id);
     }
 
     controller->devices[slot_id] = dev;
@@ -387,7 +401,9 @@ size_t FUsbGetAllDevEntries(FUsbHc *controller, FUsbDev *devs[], size_t max_dev_
 
             /* get at most max_dev_num device entry before exit */
             if (num >= max_dev_num)
+            {
                 break;
+            }
         }
     }
 
@@ -405,43 +421,43 @@ int FUsbDecodeMaxPacketSz0(FUsbSpeed speed, u8 bMaxPacketSize0)
 {
     switch (speed)
     {
-    case FUSB_LOW_SPEED:
-        if (bMaxPacketSize0 != 8)
-        {
-            FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
-            bMaxPacketSize0 = 8;
-        }
-        return bMaxPacketSize0;
-    case FUSB_FULL_SPEED:
-        switch (bMaxPacketSize0)
-        {
-        case 8:
-        case 16:
-        case 32:
-        case 64:
+        case FUSB_LOW_SPEED:
+            if (bMaxPacketSize0 != 8)
+            {
+                FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
+                bMaxPacketSize0 = 8;
+            }
+            return bMaxPacketSize0;
+        case FUSB_FULL_SPEED:
+            switch (bMaxPacketSize0)
+            {
+                case 8:
+                case 16:
+                case 32:
+                case 64:
+                    return bMaxPacketSize0;
+                default:
+                    FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
+                    return 8;
+            }
+        case FUSB_HIGH_SPEED:
+            if (bMaxPacketSize0 != 64)
+            {
+                FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
+                bMaxPacketSize0 = 64;
+            }
             return bMaxPacketSize0;
+        case FUSB_SUPER_SPEED:
+        /* Intentional fallthrough */
+        case FUSB_SUPER_SPEED_PLUS:
+            if (bMaxPacketSize0 != 9)
+            {
+                FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
+                bMaxPacketSize0 = 9;
+            }
+            return 1 << bMaxPacketSize0;
         default:
-            FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
             return 8;
-        }
-    case FUSB_HIGH_SPEED:
-        if (bMaxPacketSize0 != 64)
-        {
-            FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
-            bMaxPacketSize0 = 64;
-        }
-        return bMaxPacketSize0;
-    case FUSB_SUPER_SPEED:
-    /* Intentional fallthrough */
-    case FUSB_SUPER_SPEED_PLUS:
-        if (bMaxPacketSize0 != 9)
-        {
-            FUSB_ERROR("Invalid MPS0: 0x%02x ", bMaxPacketSize0);
-            bMaxPacketSize0 = 9;
-        }
-        return 1 << bMaxPacketSize0;
-    default:
-        return 8;
     }
 }
 
@@ -525,7 +541,9 @@ FUsbTransCode FUsbGetDescriptor(FUsbDev *dev, int rtype, FUsbDescriptorType desc
                                        sizeof(dr), &dr, len, data);
 
         if (ret == (int)len)
+        {
             break;
+        }
 
         fsleep_microsec(10);
     }
@@ -562,7 +580,9 @@ FUsbTransCode FUsbGetStringDescriptor(FUsbDev *dev, int rtype, FUsbDescriptorTyp
 
         ret = dev->controller->control(dev, FUSB_IN, sizeof(dr), &dr, len, data);
         if (ret == (int)len)
+        {
             break;
+        }
 
         fsleep_microsec(10);
     }
@@ -624,16 +644,16 @@ int FUsbSpeedtoDefaultMaxPacketSz(FUsbSpeed speed)
 {
     switch (speed)
     {
-    case FUSB_LOW_SPEED:
-        return 8;
-    case FUSB_FULL_SPEED:
-    case FUSB_HIGH_SPEED:
-        return 64;
-    case FUSB_SUPER_SPEED:
-    /* Intentional fallthrough */
-    case FUSB_SUPER_SPEED_PLUS:
-    default:
-        return 512;
+        case FUSB_LOW_SPEED:
+            return 8;
+        case FUSB_FULL_SPEED:
+        case FUSB_HIGH_SPEED:
+            return 64;
+        case FUSB_SUPER_SPEED:
+        /* Intentional fallthrough */
+        case FUSB_SUPER_SPEED_PLUS:
+        default:
+            return 512;
     }
 }
 
@@ -651,47 +671,47 @@ static int FUsbDecodeInterval(FUsbSpeed speed, const FUsbEpType type, const unsi
 #define LOG2(a) ((sizeof(unsigned) << 3) - __builtin_clz(a) - 1)
     switch (speed)
     {
-    case FUSB_LOW_SPEED:
-        switch (type)
-        {
-        case FUSB_ISOCHRONOUS_EP:
-        case FUSB_INTERRUPT_EP:
-            return LOG2(bInterval) + 3;
-        default:
-            return 0;
-        }
-    case FUSB_FULL_SPEED:
-        switch (type)
-        {
-        case FUSB_ISOCHRONOUS_EP:
-            return (bInterval - 1) + 3;
-        case FUSB_INTERRUPT_EP:
-            return LOG2(bInterval) + 3;
-        default:
-            return 0;
-        }
-    case FUSB_HIGH_SPEED:
-        switch (type)
-        {
-        case FUSB_ISOCHRONOUS_EP:
-        case FUSB_INTERRUPT_EP:
-            return bInterval - 1;
-        default:
-            return LOG2(bInterval);
-        }
-    case FUSB_SUPER_SPEED:
-    /* Intentional fallthrough */
-    case FUSB_SUPER_SPEED_PLUS:
-        switch (type)
-        {
-        case FUSB_ISOCHRONOUS_EP:
-        case FUSB_INTERRUPT_EP:
-            return bInterval - 1;
+        case FUSB_LOW_SPEED:
+            switch (type)
+            {
+                case FUSB_ISOCHRONOUS_EP:
+                case FUSB_INTERRUPT_EP:
+                    return LOG2(bInterval) + 3;
+                default:
+                    return 0;
+            }
+        case FUSB_FULL_SPEED:
+            switch (type)
+            {
+                case FUSB_ISOCHRONOUS_EP:
+                    return (bInterval - 1) + 3;
+                case FUSB_INTERRUPT_EP:
+                    return LOG2(bInterval) + 3;
+                default:
+                    return 0;
+            }
+        case FUSB_HIGH_SPEED:
+            switch (type)
+            {
+                case FUSB_ISOCHRONOUS_EP:
+                case FUSB_INTERRUPT_EP:
+                    return bInterval - 1;
+                default:
+                    return LOG2(bInterval);
+            }
+        case FUSB_SUPER_SPEED:
+        /* Intentional fallthrough */
+        case FUSB_SUPER_SPEED_PLUS:
+            switch (type)
+            {
+                case FUSB_ISOCHRONOUS_EP:
+                case FUSB_INTERRUPT_EP:
+                    return bInterval - 1;
+                default:
+                    return 0;
+            }
         default:
             return 0;
-        }
-    default:
-        return 0;
     }
 #undef LOG2
 }
@@ -717,7 +737,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     FASSERT(instace);
     if (NULL == dev)
     {
-        FUSB_INFO("set_address failed ");
+        FUSB_INFO("Set address failed.");
         return FUSB_NO_DEV_ADDR;
     }
 
@@ -726,22 +746,22 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     if ((NULL == dev->descriptor) || FUsbGetDescriptor(dev, FUSB_DR_DESC, FUSB_DESC_TYPE_DEVICE, 0,
             dev->descriptor, sizeof(*dev->descriptor)) != sizeof(*dev->descriptor))
     {
-        FUSB_INFO("FUsbGetDescriptor(FUSB_DESC_TYPE_DEVICE) failed ");
+        FUSB_INFO("FUsbGetDescriptor(FUSB_DESC_TYPE_DEVICE) failed.");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
 
-    FUSB_INFO("* found device (0x%04x:0x%04x, USB %x.%x, MPS0: %d) ",
+    FUSB_INFO("Found device (0x%04x:0x%04x, USB %x.%x, MPS0: %d) ",
               dev->descriptor->idVendor, dev->descriptor->idProduct,
               dev->descriptor->bcdUSB >> 8, dev->descriptor->bcdUSB & 0xff,
               dev->endpoints[0].maxpacketsize);
 
-    FUSB_INFO("device has %d configurations ",
+    FUSB_INFO("Device has %d configurations.",
               dev->descriptor->bNumConfigurations);
     if (dev->descriptor->bNumConfigurations == 0)
     {
         /* device isn't usable */
-        FUSB_INFO("... no usable configuration! ");
+        FUSB_INFO("No usable configuration!");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
@@ -749,7 +769,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     u16 buf[2];
     if (FUsbGetDescriptor(dev, FUSB_DR_DESC, FUSB_DESC_TYPE_CONFIG, 0, buf, sizeof(buf)) != sizeof(buf))
     {
-        FUSB_INFO("first FUsbGetDescriptor(FUSB_DESC_TYPE_CONFIG) failed ");
+        FUSB_INFO("First FUsbGetDescriptor(FUSB_DESC_TYPE_CONFIG) failed.");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
@@ -761,7 +781,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     dev->configuration = FUSB_ALLOCATE(instace, buf[1], FUSB_DEFAULT_ALIGN);
     if (NULL == dev->configuration)
     {
-        FUSB_INFO("could not allocate %d bytes for FUSB_DESC_TYPE_CONFIG ", buf[1]);
+        FUSB_INFO("Could not allocate %d bytes for FUSB_DESC_TYPE_CONFIG.", buf[1]);
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
@@ -769,7 +789,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     if (FUsbGetDescriptor(dev, FUSB_DR_DESC, FUSB_DESC_TYPE_CONFIG, 0, dev->configuration,
                           buf[1]) != buf[1])
     {
-        FUSB_INFO("FUsbGetDescriptor(FUSB_DESC_TYPE_CONFIG) failed ");
+        FUSB_INFO("FUsbGetDescriptor(FUSB_DESC_TYPE_CONFIG) failed.");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
@@ -777,7 +797,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     FUsbConfigurationDescriptor *cd = dev->configuration;
     if (cd->wTotalLength != buf[1])
     {
-        FUSB_INFO("configuration descriptor size changed, aborting ");
+        FUSB_INFO("Configuration descriptor size changed, aborting.");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
@@ -788,7 +808,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
      * else for the time being. If you need it, see the SetInterface and
      * GetInterface functions in the USB specification and set it yourself.
      */
-    FUSB_INFO("device has %x interfaces ", cd->bNumInterfaces);
+    FUSB_INFO("Device has %x interfaces.", cd->bNumInterfaces);
 
     u8 *end = (void *)dev->configuration + cd->wTotalLength;
     FUsbInterfaceDescriptor *intf;
@@ -799,22 +819,24 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     {
         if (ptr + 2 > end || !ptr[0] || ptr + ptr[0] > end)
         {
-            FUSB_INFO("Couldn't find usable FUSB_DESC_TYPE_INTERFACE ");
+            FUSB_INFO("Couldn't find usable FUSB_DESC_TYPE_INTERFACE.");
             FUsbDetachDev(controller, dev->address);
             return FUSB_NO_DEV_ADDR;
         }
 
         if (ptr[1] != FUSB_DESC_TYPE_INTERFACE)
+        {
             continue;
+        }
 
         intf = (void *)ptr;
         if (intf->bLength != sizeof(*intf))
         {
-            FUSB_INFO("Skipping broken FUSB_DESC_TYPE_INTERFACE ");
+            FUSB_INFO("Skipping broken FUSB_DESC_TYPE_INTERFACE.");
             continue;
         }
 
-        FUSB_INFO("Interface %d: class 0x%x, sub 0x%x. proto 0x%x ",
+        FUSB_INFO("Interface %d: class 0x%x, sub 0x%x. proto 0x%x.",
                   intf->bInterfaceNumber, intf->bInterfaceClass,
                   intf->bInterfaceSubClass, intf->bInterfaceProtocol);
         ptr += sizeof(*intf);
@@ -827,11 +849,15 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     for (; ptr + 2 <= end && ptr[0] && ptr + ptr[0] <= end; ptr += ptr[0])
     {
         if (ptr[1] == FUSB_DESC_TYPE_INTERFACE || ptr[1] == FUSB_DESC_TYPE_CONFIG ||
-                (size_t)dev->num_endp >= ARRAY_SIZE(dev->endpoints))
+            (size_t)dev->num_endp >= ARRAY_SIZE(dev->endpoints))
+        {
             break;
+        }
 
         if (ptr[1] != FUSB_DESC_TYPE_ENDPOINT)
+        {
             continue;
+        }
 
         FUsbEndpointDescriptor *desc = (void *)ptr;
         static const char *transfertypes[4] =
@@ -856,47 +882,49 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     }
 
     if ((controller->finish_device_config &&
-            controller->finish_device_config(dev)) ||
-            FUsbSetConfiguration(dev) < 0)
+         controller->finish_device_config(dev)) ||
+        FUsbSetConfiguration(dev) < 0)
     {
-        FUSB_INFO("Could not finalize device configuration ");
+        FUSB_INFO("Could not finalize device configuration. ");
         FUsbDetachDev(controller, dev->address);
         return FUSB_NO_DEV_ADDR;
     }
 
     int class = dev->descriptor->bDeviceClass;
     if (class == 0)
+    {
         class = intf->bInterfaceClass;
+    }
 
     switch (class)
     {
-    case FUSB_AUDIO_DEVICE:
-        FUSB_INFO("Audio Class ");
-        break;
-    case FUSB_COMM_DEVICE:
-        FUSB_INFO("Communication Class ");
-        break;
-    case FUSB_HID_DEVICE:
-        FUSB_INFO("HID Class ");
-        break;
-    case FUSB_PHYSICAL_DEVICE:
-        FUSB_INFO("Physical Class");
-        break;
-    case FUSB_IMAGE_DEVICE:
-        FUSB_INFO("Camera Class ");
-        break;
-    case FUSB_PRINTER_DEVICE:
-        FUSB_INFO("Printer Class");
-        break;
-    case FUSB_MASS_STORAGE_DEVICE:
-        FUSB_INFO("Mass Storage Class ");
-        break;
-    case FUSB_HUB_DEVICE:
-        FUSB_INFO("Hub Class ");
-        break;
-    default:
-        FUSB_ERROR("Unsupported Class %x ", class);
-        break;
+        case FUSB_AUDIO_DEVICE:
+            FUSB_INFO("Audio Class ");
+            break;
+        case FUSB_COMM_DEVICE:
+            FUSB_INFO("Communication Class ");
+            break;
+        case FUSB_HID_DEVICE:
+            FUSB_INFO("HID Class ");
+            break;
+        case FUSB_PHYSICAL_DEVICE:
+            FUSB_INFO("Physical Class");
+            break;
+        case FUSB_IMAGE_DEVICE:
+            FUSB_INFO("Camera Class ");
+            break;
+        case FUSB_PRINTER_DEVICE:
+            FUSB_INFO("Printer Class");
+            break;
+        case FUSB_MASS_STORAGE_DEVICE:
+            FUSB_INFO("Mass Storage Class ");
+            break;
+        case FUSB_HUB_DEVICE:
+            FUSB_INFO("Hub Class ");
+            break;
+        default:
+            FUSB_ERROR("Unsupported Class %x ", class);
+            break;
     }
 
     index.category = FUSB_STANDARD_INTERFACE;
@@ -904,7 +932,7 @@ static FUsbDevAddr FUsbSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubpo
     index.sub_class = intf->bInterfaceSubClass;
     index.protocol = intf->bInterfaceProtocol;
 
-    FUSB_INFO("class: 0x%x sub-class: 0x%x, protocol: 0x%x",
+    FUSB_INFO("Class: 0x%x sub-class: 0x%x, protocol: 0x%x.",
               index.class, index.sub_class, index.protocol);
 
     init_handler = FUsbFindValidInitFunc(instace, &index);
@@ -942,7 +970,9 @@ void FUsbDetachDev(FUsbHc *controller, int devno)
         controller->devices[devno]->destroy(controller->devices[devno]);
 
         if (controller->destroy_device)
+        {
             controller->destroy_device(controller, devno);
+        }
 
         FUSB_FREE(instace, controller->devices[devno]->descriptor);
         controller->devices[devno]->descriptor = NULL;
@@ -975,7 +1005,9 @@ FUsbDevAddr FUsbAttachDev(FUsbHc *controller, int hubaddress, int port, FUsbSpee
               : "Unkonwn");
     FUsbDevAddr newdev = FUsbSetAddress(controller, speed, port, hubaddress);
     if (newdev == FUSB_NO_DEV_ADDR)
+    {
         return FUSB_NO_DEV_ADDR;
+    }
 
     FUsbDev *newdev_t = controller->devices[newdev];
 
@@ -995,7 +1027,9 @@ FUsbDevAddr FUsbAttachDev(FUsbHc *controller, int hubaddress, int port, FUsbSpee
 static void FUsbGenericDestory(FUsbDev *dev)
 {
     if (FUsbGenericRemove)
+    {
         FUsbGenericRemove(dev);
+    }
 
     return;
 }
@@ -1012,11 +1046,13 @@ void FUsbGenericDevInit(FUsbDev *dev)
     dev->destroy = FUsbGenericDestory;
 
     if (FUsbGenericCreate)
+    {
         FUsbGenericCreate(dev);
+    }
 
     if (dev->data == NULL)
     {
-        FUSB_INFO("Detaching device not used by payload ");
+        FUSB_INFO("Detaching device not used by payload.");
         FUsbDetachDev(dev->controller, dev->address);
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb.h
index 7967cb1b493..fde6391d310 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb.h
@@ -19,16 +19,11 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_FUSB_H
-#define  DRIVERS_FUSB_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FUSB_H
+#define  FUSB_H
 
 /***************************** Include Files *********************************/
 #include "ftypes.h"
@@ -36,6 +31,11 @@ extern "C"
 #include "fassert.h"
 #include "fusb_def.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 #define FUSB_SUCCESS            FT_SUCCESS
 #define FUSB_ERR_WAIT_TIMEOUT   FT_MAKE_ERRCODE(ErrModBsp, ErrUsb, 0x0)
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_debug.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_debug.c
index 7870df0f4de..ebb0c4924d5 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_debug.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_debug.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fdebug.h"
@@ -47,7 +47,9 @@ void FUsbDumpAllDescriptors(FUsbDev *dev)
 {
     FError ret = FUSB_SUCCESS;
     if ((NULL == dev) || (NULL == dev->configuration))
+    {
         return;
+    }
 
     const FUsbDeviceDescriptor *dev_desc = NULL;
     const FUsbConfigurationDescriptor *config_desc = NULL;
@@ -65,27 +67,35 @@ void FUsbDumpAllDescriptors(FUsbDev *dev)
     ret = FUsbSetupConfigParser(dev, config_desc, config_desc->wTotalLength);
     FUsbSetupStringParser(dev);
     if (FUSB_SUCCESS != ret)
+    {
         return;
+    }
 
     if (FUsbIsValidStringIndex(dev_desc->iManufacturer))
     {
         ret = FUsbSearchStringDescriptor(instance, dev, dev_desc->iManufacturer);
         if (FUSB_SUCCESS == ret)
+        {
             printf("	Manufacturer: %s\r\n", FUsbGetString(dev));
+        }
     }
 
     if (FUsbIsValidStringIndex(dev_desc->iProduct))
     {
         ret = FUsbSearchStringDescriptor(instance, dev, dev_desc->iProduct);
         if (FUSB_SUCCESS == ret)
+        {
             printf("	Product: %s\r\n", FUsbGetString(dev));
+        }
     }
 
     if (FUsbIsValidStringIndex(dev_desc->iSerialNumber))
     {
         ret = FUsbSearchStringDescriptor(instance, dev, dev_desc->iSerialNumber);
         if (FUSB_SUCCESS == ret)
+        {
             printf("	Serial No.: %s\r\n", FUsbGetString(dev));
+        }
     }
 
     while (NULL != (if_desc = (const FUsbInterfaceDescriptor *)FUsbGetDescriptorFromParser(parser, FUSB_DESC_TYPE_INTERFACE)))
@@ -105,7 +115,9 @@ void FUsbDumpAllDescriptors(FUsbDev *dev)
         {
             ret = FUsbSearchStringDescriptor(instance, dev, if_desc->iInterface);
             if (FUSB_SUCCESS == ret)
+            {
                 printf("	Interface: %s\r\n", FUsbGetString(dev));
+            }
         }
 
     }
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_def.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_def.h
index 5d66390d212..f2c453d89b8 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_def.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_def.h
@@ -19,21 +19,22 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_FUSB_DEF_H
-#define  DRIVERS_FUSB_DEF_H
+#ifndef  FUSB_DEF_H
+#define  FUSB_DEF_H
+
+/***************************** Include Files *********************************/
+
+#include "ftypes.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-
-#include "ftypes.h"
-
 /************************** Constant Definitions *****************************/
 typedef enum
 {
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_dev.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_dev.c
index 2d3fdf0dbdb..dad3877a3cd 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_dev.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_dev.c
@@ -19,13 +19,11 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include <string.h>
-
 #include "fdebug.h"
-
 #include "fusb_private.h"
 
 #define FUSB_DEBUG_TAG "FUSB-DEV"
@@ -101,43 +99,43 @@ static FError FUsbParserDescriptor(FUsbConfigParser *parser)
         alt_len = 0;
         switch (desc_type)
         {
-        case FUSB_DESC_TYPE_CONFIG:
-            if (FUSB_DESC_TYPE_NONE != last_desc_type)
-            {
-                FUSB_ERROR("Configuration descriptor must be the first !!!");
-                parser->err_pos = cur_pos;
-                ret = FUSB_ERR_DESC_PARSE_ERR;
-                goto err_handle;
-            }
-            exp_len = sizeof(FUsbConfigurationDescriptor);
-            break;
-        case FUSB_DESC_TYPE_INTERFACE:
-            if (FUSB_DESC_TYPE_NONE == last_desc_type)
-            {
-                FUSB_ERROR("Interface descriptor must not be the first !!!");
-                parser->err_pos = cur_pos;
-                ret = FUSB_ERR_DESC_PARSE_ERR;
-                goto err_handle;
-            }
-            exp_len = sizeof(FUsbInterfaceDescriptor);
-            break;
-        case FUSB_DESC_TYPE_ENDPOINT:
-            if ((FUSB_DESC_TYPE_NONE == last_desc_type) ||
+            case FUSB_DESC_TYPE_CONFIG:
+                if (FUSB_DESC_TYPE_NONE != last_desc_type)
+                {
+                    FUSB_ERROR("Configuration descriptor must be the first !!!");
+                    parser->err_pos = cur_pos;
+                    ret = FUSB_ERR_DESC_PARSE_ERR;
+                    goto err_handle;
+                }
+                exp_len = sizeof(FUsbConfigurationDescriptor);
+                break;
+            case FUSB_DESC_TYPE_INTERFACE:
+                if (FUSB_DESC_TYPE_NONE == last_desc_type)
+                {
+                    FUSB_ERROR("Interface descriptor must not be the first !!!");
+                    parser->err_pos = cur_pos;
+                    ret = FUSB_ERR_DESC_PARSE_ERR;
+                    goto err_handle;
+                }
+                exp_len = sizeof(FUsbInterfaceDescriptor);
+                break;
+            case FUSB_DESC_TYPE_ENDPOINT:
+                if ((FUSB_DESC_TYPE_NONE == last_desc_type) ||
                     (FUSB_DESC_TYPE_CONFIG == last_desc_type))
-            {
-                FUSB_ERROR("Endpoint descriptor must follow interface descriptor !!!");
-                parser->err_pos = cur_pos;
-                ret = FUSB_ERR_DESC_PARSE_ERR;
-                goto err_handle;
-            }
-            break;
-        default:
-            FUSB_DEBUG("Descriptor %d not handled !!!", desc_type);
-            break;
+                {
+                    FUSB_ERROR("Endpoint descriptor must follow interface descriptor !!!");
+                    parser->err_pos = cur_pos;
+                    ret = FUSB_ERR_DESC_PARSE_ERR;
+                    goto err_handle;
+                }
+                break;
+            default:
+                FUSB_DEBUG("Descriptor %d not handled !!!", desc_type);
+                break;
         }
 
         if (((exp_len != 0) && (desc_len != exp_len)) &&
-                ((alt_len == 0) || (desc_len != alt_len)))
+            ((alt_len == 0) || (desc_len != alt_len)))
         {
             FUSB_ERROR("Descriptor %d invalid !!!", desc_type);
             parser->err_pos = cur_pos;
@@ -198,8 +196,8 @@ FError FUsbSetupConfigParser(FUsbDev *dev, const void *buf, u32 buf_len)
     /* input buffer must start with config desc */
     config_desc = (FUsbConfigurationDescriptor *)parser->buf;
     if ((config_desc->bLength != sizeof(FUsbConfigurationDescriptor)) ||
-            (config_desc->bDescriptorType != FUSB_DESC_TYPE_CONFIG) ||
-            (config_desc->wTotalLength > parser->buf_len))
+        (config_desc->bDescriptorType != FUSB_DESC_TYPE_CONFIG) ||
+        (config_desc->wTotalLength > parser->buf_len))
     {
         FUSB_ERROR("Invalid configuration descriptor !!!");
         return FUSB_ERR_INVALID_DATA;
@@ -256,11 +254,15 @@ const FUsbDescriptor *FUsbGetDescriptorFromParser(FUsbConfigParser *parser, FUsb
 
         desc_end = FUSB_SKIP_BYTES(parser->next_pos, desc_len);
         if (desc_end > parser->end_pos)
+        {
             break;
+        }
 
         if ((FUSB_DESC_TYPE_ENDPOINT == type) &&
-                (FUSB_DESC_TYPE_INTERFACE == desc_type))
-            break; /* there is no chance to find endpoint desc after interface desc */
+            (FUSB_DESC_TYPE_INTERFACE == desc_type))
+        {
+            break;    /* there is no chance to find endpoint desc after interface desc */
+        }
 
         if (type == desc_type)
         {
@@ -352,7 +354,9 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
 
     parser->usb_str = FUSB_ALLOCATE(instance, FUSB_USBSTR_MIN_LEN, FUSB_DEFAULT_ALIGN);
     if (NULL == parser->usb_str)
+    {
         return FUSB_ERR_ALLOCATE_FAIL;
+    }
 
     /* get header of string for the full length */
     if (FUsbGetStringDescriptor(dev, FUSB_DR_DESC, FUSB_DESC_TYPE_STRING, id, FUSB_DEFAULT_LANG_ID,
@@ -365,8 +369,8 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
     /* check if string descriptor header is valid */
     total_len = parser->usb_str->len;
     if ((total_len < FUSB_DESCRIPTOR_HEADER_SIZE) ||
-            ((total_len & 1) != 0) ||
-            (parser->usb_str->type != FUSB_DESC_TYPE_STRING))
+        ((total_len & 1) != 0) ||
+        (parser->usb_str->type != FUSB_DESC_TYPE_STRING))
     {
         FUSB_ERROR("Get invalid string descriptor (len: %d) !!!", FUSB_USBSTR_MIN_LEN);
         return FUSB_ERR_DESC_PARSE_ERR;
@@ -374,7 +378,9 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
 
     /* return if no need to get more */
     if (total_len <= FUSB_USBSTR_MIN_LEN)
+    {
         return FUSB_SUCCESS;
+    }
 
     /* re-malloc usb string desc buffer with full length */
     FASSERT(parser->usb_str);
@@ -383,7 +389,9 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
 
     parser->usb_str = FUSB_ALLOCATE(instance, total_len, FUSB_DEFAULT_ALIGN);
     if (NULL == parser->usb_str)
+    {
         return FUSB_ERR_ALLOCATE_FAIL;
+    }
 
     /* get the whole string descriptor */
     if (FUsbGetStringDescriptor(dev, FUSB_DR_DESC, FUSB_DESC_TYPE_STRING, id,  FUSB_DEFAULT_LANG_ID,
@@ -394,8 +402,8 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
     }
 
     if ((parser->usb_str->len < FUSB_DESCRIPTOR_HEADER_SIZE) ||
-            ((parser->usb_str->len & 1) != 0) ||
-            (parser->usb_str->type != FUSB_DESC_TYPE_STRING))
+        ((parser->usb_str->len & 1) != 0) ||
+        (parser->usb_str->type != FUSB_DESC_TYPE_STRING))
     {
         FUSB_ERROR("Get invalid string descriptor (len: %d) !!!", total_len);
         return FUSB_ERR_DESC_PARSE_ERR;
@@ -414,7 +422,7 @@ FError FUsbSearchStringDescriptor(FUsb *instance, FUsbDev *dev, u8 id)
     {
         character = usb_str->string[i];
         if (character < ' '     /* 0x20 */
-                || character > '~') /* 0x7E */
+            || character > '~') /* 0x7E */
         {
             character = '_';
         }
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_g.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_g.c
index dd088f21bd9..a8f32188f07 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_g.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.c
index 5aa22361248..2b155803963 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fsleep.h"
@@ -38,7 +38,9 @@ void FUsbGenericHubDestory(FUsbDev *const dev)
     FUsbGenericHub *const hub = FUSB_GEN_HUB_GET(dev);
     FUsb *instace = dev->controller->usb;
     if (!hub)
+    {
         return;
+    }
 
     /* First, detach all devices behind this hub */
     int port;
@@ -46,7 +48,7 @@ void FUsbGenericHubDestory(FUsbDev *const dev)
     {
         if (hub->ports[port] >= 0)
         {
-            FUSB_INFO("generic_hub: Detachment at port %d ", port);
+            FUSB_INFO("Generic hub: Detachment at port %d ", port);
             FUsbDetachDev(dev->controller, hub->ports[port]);
             hub->ports[port] = FUSB_NO_DEV_ADDR;
         }
@@ -56,7 +58,9 @@ void FUsbGenericHubDestory(FUsbDev *const dev)
     if (hub->ops->disable_port)
     {
         for (port = 1; port <= hub->num_ports; ++port)
+        {
             hub->ops->disable_port(dev, port);
+        }
     }
 
     FUSB_FREE(instace, hub->ports); // free(hub->ports);
@@ -80,7 +84,9 @@ static int FUsbGenericHubDebounce(FUsbDev *const dev, const int port)
         const int changed = hub->ops->port_status_changed(dev, port);
         const int connected = hub->ops->port_connected(dev, port);
         if (changed < 0 || connected < 0)
+        {
             return -1;
+        }
 
         if (!changed && connected)
         {
@@ -88,14 +94,16 @@ static int FUsbGenericHubDebounce(FUsbDev *const dev, const int port)
         }
         else
         {
-            FUSB_INFO("generic_hub: Unstable connection at %d ",
+            FUSB_INFO("Generic hub: Unstable connection at %d ",
                       port);
             stable_ms = 0;
         }
         total_ms += step_ms;
     }
     if (total_ms >= timeout_ms)
-        FUSB_INFO("generic_hub: Debouncing timed out at %d ", port);
+    {
+        FUSB_INFO("Generic hub: Debouncing timed out at %d ", port);
+    }
     return 0; /* ignore timeouts, try to always go on */
 }
 
@@ -109,9 +117,13 @@ int FUsbGenericHubWaitForPort(FUsbDev *const dev, const int port,
     {
         state = port_op(dev, port);
         if (state < 0)
+        {
             return -1;
+        }
         else if (!!state == wait_for)
+        {
             return timeout_steps;
+        }
         fsleep_microsec(step_us);
         --timeout_steps;
     }
@@ -125,7 +137,9 @@ int FUsbGenericHubResetPort(FUsbDev *const dev, const int port)
     FUsbGenericHub *const hub = FUSB_GEN_HUB_GET(dev);
 
     if (hub->ops->start_port_reset(dev, port) < 0)
+    {
         return -1;
+    }
 
     /* wait for 10ms (usb20 spec 11.5.1.5: reset should take 10 to 20ms) */
     fsleep_millisec(10);
@@ -135,9 +149,13 @@ int FUsbGenericHubResetPort(FUsbDev *const dev, const int port)
                         /* time out after 120 * 100us = 12ms */
                         dev, port, 0, hub->ops->port_in_reset, 120, 100);
     if (ret < 0)
+    {
         return -1;
+    }
     else if (!ret)
-        FUSB_INFO("generic_hub: Reset timed out at port %d ", port);
+    {
+        FUSB_INFO("Generic hub: Reset timed out at port %d ", port);
+    }
 
     return 0; /* ignore timeouts, try to always go on */
 }
@@ -157,17 +175,21 @@ static int FUsbGenericHubAttachDev(FUsbDev *const dev, const int port)
     FUsbGenericHub *const hub = FUSB_GEN_HUB_GET(dev);
 
     if (FUsbGenericHubDebounce(dev, port) < 0)
+    {
         return -1;
+    }
 
     if (hub->ops->reset_port)
     {
         if (hub->ops->reset_port(dev, port) < 0)
+        {
             return -1;
+        }
 
         if (!hub->ops->port_connected(dev, port))
         {
             FUSB_INFO(
-                "generic_hub: Port %d disconnected after "
+                "Generic hub: Port %d disconnected after "
                 "reset. Possibly upgraded, rescan required. ",
                 port);
             return 0;
@@ -178,9 +200,11 @@ static int FUsbGenericHubAttachDev(FUsbDev *const dev, const int port)
                             /* time out after 1,000 * 10us = 10ms */
                             dev, port, 1, hub->ops->port_enabled, 1000, 10);
         if (ret < 0)
+        {
             return -1;
+        }
         else if (!ret)
-            FUSB_INFO("generic_hub: Port %d still "
+            FUSB_INFO("Generic hub: Port %d still "
                       "disabled after 10ms ",
                       port);
     }
@@ -188,9 +212,11 @@ static int FUsbGenericHubAttachDev(FUsbDev *const dev, const int port)
     const FUsbSpeed speed = hub->ops->port_speed(dev, port);
     if (speed >= 0)
     {
-        FUSB_DEBUG("generic_hub: Success at port %d ", port);
+        FUSB_DEBUG("Generic hub: Success at port %d ", port);
         if (hub->ops->reset_port)
-            fsleep_millisec(10); /* Reset recovery time
+        {
+            fsleep_millisec(10);
+        } /* Reset recovery time
                        (usb20 spec 7.1.7.5) */
         hub->ports[port] = FUsbAttachDev(
                                dev->controller, dev->address, port, speed);
@@ -204,15 +230,17 @@ int FUsbGenericHubScanPort(FUsbDev *const dev, const int port)
 
     if (hub->ports[port] >= 0)
     {
-        FUSB_INFO("generic_hub: Detachment at port %d ", port);
+        FUSB_INFO("Generic hub: Detachment at port %d ", port);
         const int ret = FUsbGenericHubDetachDev(dev, port);
         if (ret < 0)
+        {
             return ret;
+        }
     }
 
     if (hub->ops->port_connected(dev, port))
     {
-        FUSB_INFO("generic_hub: Attachment at port %d ", port);
+        FUSB_INFO("Generic hub: Attachment at port %d ", port);
         return FUsbGenericHubAttachDev(dev, port);
     }
 
@@ -223,10 +251,12 @@ static void FUsbGenericHubPoll(FUsbDev *const dev)
 {
     FUsbGenericHub *const hub = FUSB_GEN_HUB_GET(dev);
     if (!hub)
+    {
         return;
+    }
 
     if (hub->ops->hub_status_changed &&
-            hub->ops->hub_status_changed(dev) != FUSB_CC_SUCCESS)
+        hub->ops->hub_status_changed(dev) != FUSB_CC_SUCCESS)
     {
         return;
     }
@@ -242,9 +272,11 @@ static void FUsbGenericHubPoll(FUsbDev *const dev)
         }
         else if (ret == FUSB_CC_SUCCESS)
         {
-            FUSB_INFO("generic_hub: Port change at %d ", port);
+            FUSB_INFO("Generic hub: Port change at %d ", port);
             if (FUsbGenericHubScanPort(dev, port) < 0)
+            {
                 return;
+            }
         }
     }
 }
@@ -261,7 +293,7 @@ int FUsbGenericHubInit(FUsbDev *const dev, const int num_ports,
     dev->data = FUSB_ALLOCATE(instance, sizeof(FUsbGenericHub), FUSB_DEFAULT_ALIGN);
     if (NULL == dev->data)
     {
-        FUSB_ERROR("generic_hub: ERROR: Out of memory ");
+        FUSB_ERROR("Generic hub: Out of memory ");
         return -1;
     }
 
@@ -272,20 +304,24 @@ int FUsbGenericHubInit(FUsbDev *const dev, const int num_ports,
     hub->ops = ops;
     if (NULL == hub->ports)
     {
-        FUSB_ERROR("generic_hub: ERROR: Out of memory ");
+        FUSB_ERROR("Generic hub: Out of memory ");
         FUSB_FREE(instance, dev->data);
         dev->data = NULL;
         return -1;
     }
 
     for (port = 1; port <= num_ports; ++port)
+    {
         hub->ports[port] = FUSB_NO_DEV_ADDR;
+    }
 
     /* Enable all ports */
     if (ops->enable_port)
     {
         for (port = 1; port <= num_ports; ++port)
+        {
             ops->enable_port(dev, port);
+        }
 
         /* wait once for all ports */
         fsleep_millisec(20);
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.h
index da3bd6cc2d8..ce91d73f0b8 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_generic_hub.h
@@ -19,19 +19,19 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_FUSB_GENERIC_HUB_H
-#define  DRIVERS_FUSB_GENERIC_HUB_H
+#ifndef  FUSB_GENERIC_HUB_H
+#define  FUSB_GENERIC_HUB_H
+
+#include "fusb_private.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "fusb_private.h"
-
 typedef struct
 {
     /* negative results denote an error */
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.c
index a2df9e6e138..89d1867bfaa 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.c
@@ -14,11 +14,12 @@
  * FilePath: fusb_hid.c
  * Date: 2022-09-28 18:26:42
  * LastEditTime: 2022-09-29 14:50:09
- * Description:  This files is for
+ * Description:  This files is for usb hid class implmentation
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2022/9/28   init commit
  */
 
 #include <string.h>
@@ -93,11 +94,17 @@ static void FUsbHidDestory(FUsbDev *dev)
         for (i = 0; i <= dev->num_endp; i++)
         {
             if (dev->endpoints[i].endpoint == 0)
+            {
                 continue;
+            }
             if (dev->endpoints[i].type != FUSB_INTERRUPT_EP)
+            {
                 continue;
+            }
             if (dev->endpoints[i].direction != FUSB_IN)
+            {
                 continue;
+            }
             break;
         }
         dev->controller->destroy_intr_queue(
@@ -278,7 +285,9 @@ static void FUsbHidKeyboardQueue(int ch)
 {
     /* ignore key presses if buffer full */
     if (keycount < KEYBOARD_BUFFER_SIZE)
+    {
         keybuffer[keycount++] = ch;
+    }
 }
 
 /* handle hid received data */
@@ -292,22 +301,34 @@ static void FUsbHidProcessKeyboardEvent(FUsbHid *const inst,
     modifiers = 0;
 
     if (current->modifiers & 0x01) /* Left-Ctrl */
+    {
         modifiers |= KB_MOD_CTRL;
+    }
     if (current->modifiers & 0x02) /* Left-Shift */
+    {
         modifiers |= KB_MOD_SHIFT;
+    }
     if (current->modifiers & 0x04) /* Left-Alt */
+    {
         modifiers |= KB_MOD_ALT;
+    }
     if (current->modifiers & 0x08) /* Left-GUI */
     {
 
     }
 
     if (current->modifiers & 0x10) /* Right-Ctrl */
+    {
         modifiers |= KB_MOD_CTRL;
+    }
     if (current->modifiers & 0x20) /* Right-Shift */
+    {
         modifiers |= KB_MOD_SHIFT;
+    }
     if (current->modifiers & 0x40) /* Right-AltGr */
+    {
         modifiers |= KB_MOD_ALT;
+    }
     if (current->modifiers & 0x80) /* Right-GUI */
     {
 
@@ -321,7 +342,7 @@ static void FUsbHidProcessKeyboardEvent(FUsbHid *const inst,
 
     /* Did the event change at all? */
     if (inst->lastkeypress &&
-            !memcmp(current, previous, sizeof(*current)))
+        !memcmp(current, previous, sizeof(*current)))
     {
         /* No. Then it's a key repeat event. */
         if (inst->repeat_delay)
@@ -345,7 +366,9 @@ static void FUsbHidProcessKeyboardEvent(FUsbHid *const inst,
         int skip = 0;
         /* No more keys? skip */
         if (current->keys[i] == 0)
+        {
             return;
+        }
 
         for (j = 0; j < 6; j++)
         {
@@ -357,7 +380,9 @@ static void FUsbHidProcessKeyboardEvent(FUsbHid *const inst,
         }
 
         if (skip)
+        {
             continue;
+        }
 
         /* Mask off KB_MOD_CTRL */
         keypress = map->map[modifiers & 0x03][current->keys[i]];
@@ -366,11 +391,11 @@ static void FUsbHidProcessKeyboardEvent(FUsbHid *const inst,
         {
             switch (keypress)
             {
-            case 'a' ... 'z':
-                keypress &= 0x1f;
-                break;
-            default:
-                continue;
+                case 'a' ... 'z':
+                    keypress &= 0x1f;
+                    break;
+                default:
+                    continue;
             }
         }
 
@@ -441,7 +466,9 @@ static int FUsbHidSetLayout(const char *country)
     {
         if (strncmp(keyboard_layouts[i].country, country,
                     strlen(keyboard_layouts[i].country)))
+        {
             continue;
+        }
 
         /* Found, changing keyboard layout */
         map = &keyboard_layouts[i];
@@ -471,62 +498,68 @@ void FUsbHidInit(FUsbDev *dev)
                    boot_protos[interface->bInterfaceProtocol]);
         switch (interface->bInterfaceProtocol)
         {
-        case FUSB_HID_BOOT_PROTOCOL_KEYBOARD:
-            dev->data = FUSB_ALLOCATE(instance, sizeof(FUsbHid), FUSB_DEFAULT_ALIGN);
-            FUSB_DEBUG("  configuring...\n");
-            FUsbHidSetProtocol(dev, interface, FUSB_HID_PROTOCOL_BOOT);
-            FUsbHidSetIdle(dev, interface, KEYBOARD_REPEAT_MS);
-            FUSB_DEBUG("  activating...\n");
-
-            FUsbHidDescriptor *desc = FUSB_ALLOCATE(instance, sizeof(FUsbHidDescriptor), FUSB_DEFAULT_ALIGN);
-            if (!desc || FUsbGetDescriptor(dev, FUsbGenerateReqType(
-                                               FUSB_REQ_DEVICE_TO_HOST, FUSB_REQ_TYPE_STANDARD, FUSB_REQ_RECP_IF),
-                                           0x21, 0, desc, sizeof(*desc)) != sizeof(*desc))
-            {
-                FUSB_DEBUG("FUsbGetDescriptor(HID) failed\n");
-                FUsbDetachDev(dev->controller, dev->address);
-                return;
-            }
-            FUSB_HID_INST(dev)->descriptor = desc;
-            countrycode = desc->bCountryCode;
-            /* 35 countries defined: */
-            if (countrycode >= ARRAY_SIZE(countries))
-                countrycode = 0;
-            printf("  Keyboard has %s layout (country code %02x)\n",
-                   countries[countrycode][0], countrycode);
-
-            /* Set keyboard layout accordingly */
-            FUsbHidSetLayout(countries[countrycode][1]);
-
-            // only add here, because we only support boot-keyboard HID devices
-            dev->destroy = FUsbHidDestory;
-            dev->poll = FUsbHidPoll;
-            int i;
-            for (i = 1; i < dev->num_endp; i++)
-            {
-                if (dev->endpoints[i].type != FUSB_INTERRUPT_EP)
-                    continue;
-                if (dev->endpoints[i].direction != FUSB_IN)
-                    continue;
-                break;
-            }
+            case FUSB_HID_BOOT_PROTOCOL_KEYBOARD:
+                dev->data = FUSB_ALLOCATE(instance, sizeof(FUsbHid), FUSB_DEFAULT_ALIGN);
+                FUSB_DEBUG("  configuring...\n");
+                FUsbHidSetProtocol(dev, interface, FUSB_HID_PROTOCOL_BOOT);
+                FUsbHidSetIdle(dev, interface, KEYBOARD_REPEAT_MS);
+                FUSB_DEBUG("  activating...\n");
+
+                FUsbHidDescriptor *desc = FUSB_ALLOCATE(instance, sizeof(FUsbHidDescriptor), FUSB_DEFAULT_ALIGN);
+                if (!desc || FUsbGetDescriptor(dev, FUsbGenerateReqType(
+                                                   FUSB_REQ_DEVICE_TO_HOST, FUSB_REQ_TYPE_STANDARD, FUSB_REQ_RECP_IF),
+                                               0x21, 0, desc, sizeof(*desc)) != sizeof(*desc))
+                {
+                    FUSB_DEBUG("FUsbGetDescriptor(HID) failed\n");
+                    FUsbDetachDev(dev->controller, dev->address);
+                    return;
+                }
+                FUSB_HID_INST(dev)->descriptor = desc;
+                countrycode = desc->bCountryCode;
+                /* 35 countries defined: */
+                if (countrycode >= ARRAY_SIZE(countries))
+                {
+                    countrycode = 0;
+                }
+                FUSB_INFO("  Keyboard has %s layout (country code %02x)\n",
+                       countries[countrycode][0], countrycode);
+
+                /* Set keyboard layout accordingly */
+                FUsbHidSetLayout(countries[countrycode][1]);
+
+                // only add here, because we only support boot-keyboard HID devices
+                dev->destroy = FUsbHidDestory;
+                dev->poll = FUsbHidPoll;
+                int i;
+                for (i = 1; i < dev->num_endp; i++)
+                {
+                    if (dev->endpoints[i].type != FUSB_INTERRUPT_EP)
+                    {
+                        continue;
+                    }
+                    if (dev->endpoints[i].direction != FUSB_IN)
+                    {
+                        continue;
+                    }
+                    break;
+                }
 
-            if (i >= dev->num_endp)
-            {
-                FUSB_DEBUG("Could not find HID endpoint\n");
-                FUsbDetachDev(dev->controller, dev->address);
-                return;
-            }
+                if (i >= dev->num_endp)
+                {
+                    FUSB_DEBUG("Could not find HID endpoint\n");
+                    FUsbDetachDev(dev->controller, dev->address);
+                    return;
+                }
 
-            FUSB_DEBUG("  found endpoint %x for interrupt-in\n", i);
-            /* 20 buffers of 8 bytes, for every 10 msecs */
-            FUSB_HID_INST(dev)->queue = dev->controller->create_intr_queue(&dev->endpoints[i], 8, 20, 10);
-            keycount = 0;
-            FUSB_DEBUG("  configuration done.\n");
-            break;
-        case FUSB_HID_BOOT_PROTOCOL_MOUSE:
-            FUSB_DEBUG("NOTICE: USB mice are not supported.\n");
-            break;
+                FUSB_DEBUG("  found endpoint %x for interrupt-in\n", i);
+                /* 20 buffers of 8 bytes, for every 10 msecs */
+                FUSB_HID_INST(dev)->queue = dev->controller->create_intr_queue(&dev->endpoints[i], 8, 20, 10);
+                keycount = 0;
+                FUSB_DEBUG("  configuration done.\n");
+                break;
+            case FUSB_HID_BOOT_PROTOCOL_MOUSE:
+                FUSB_DEBUG("NOTICE: USB mice are not supported.\n");
+                break;
         }
     }
 }
@@ -544,11 +577,11 @@ int FUsbHidCheckInput(FUsbDev *dev, int times)
         {
             ret = keybuffer[0];
             memmove(keybuffer, keybuffer + 1, --keycount);
-            printf("%c", ret);
+            FUSB_INFO("%c", ret);
         }
 
         fsleep_millisec(10);
     }
 
-    printf("\r\n");
+    FUSB_INFO("\r\n");
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.h
index e4bc50e3639..da43bbeefd5 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hid.h
@@ -19,21 +19,21 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/9/28   init commit
+ * 1.0   zhugengyu  2022/9/28   init commit
  */
 
-#ifndef  DRIVERS_USB_HID_H
-#define  DRIVERS_USB_HID_H
+#ifndef  FUSB_HID_H
+#define  FUSB_HID_H
+
+/***************************** Include Files *********************************/
+
+#include "fusb.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-
-#include "fusb.h"
-
 /************************** Constant Definitions *****************************/
 /*----------------------------------------------------------------------
  *
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.c
index a18cd4e09fd..bf2bc3cc2c1 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.c
@@ -20,7 +20,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fkernel.h"
@@ -84,8 +84,10 @@ static FUsbEndpoint *FUsbHubIntrEp(FUsbDev *const dev)
     for (i = 0; i < dev->num_endp; ++i)
     {
         if (dev->endpoints[i].type == FUSB_INTERRUPT_EP &&
-                dev->endpoints[i].direction == FUSB_IN)
+            dev->endpoints[i].direction == FUSB_IN)
+        {
             return &dev->endpoints[i];
+        }
     }
 
     return NULL;
@@ -151,7 +153,9 @@ static FUsbTransCode FUsbHubPortInReset(FUsbDev *const dev, const int port)
     FUsbTransCode ret = FUsbGetStatus(dev, port, DR_PORT, sizeof(buf), buf);
 
     if (ret >= FUSB_CC_ZERO_BYTES)
+    {
         ret = buf[FUSB_HUB_PORT_STATUS] & FUSB_HUB_STATUS_PORT_RESET;
+    }
 
     return ret;
 }
@@ -170,7 +174,9 @@ static FUsbTransCode FUsbHubPortEnabled(FUsbDev *const dev, const int port)
     FUsbTransCode ret = FUsbGetStatus(dev, port, DR_PORT, sizeof(buf), buf);
 
     if (ret >= FUSB_CC_ZERO_BYTES)
+    {
         ret = buf[FUSB_HUB_PORT_STATUS] & FUSB_HUB_STATUS_PORT_ENABLE;
+    }
 
     return ret;
 }
@@ -193,7 +199,9 @@ static FUsbSpeed FUsbHubPortSpeed(FUsbDev *const dev, const int port)
     {
         /* SuperSpeed hubs can only have SuperSpeed devices. */
         if (FUsbIsSuperSpeed(dev->speed))
+        {
             return dev->speed;
+        }
 
         /*[bit] 10  9  (USB 2.0 port status word)
          *      0   0  full speed
@@ -203,7 +211,9 @@ static FUsbSpeed FUsbHubPortSpeed(FUsbDev *const dev, const int port)
          */
         speed = (buf[FUSB_HUB_PORT_STATUS] >> 9) & 0x3;
         if (speed != 0x3) /* high-speed device */
+        {
             return speed;
+        }
     }
 
     return FUSB_UNKNOWN_SPEED;
@@ -290,14 +300,18 @@ static void FUsbHubPortInit(FUsbDev *const dev, const int port)
     FUsbTransCode ret = FUsbGetStatus(dev, port, DR_PORT, sizeof(buf), buf);
 
     if (ret < FUSB_CC_ZERO_BYTES)
+    {
         return;
+    }
 
     if (buf[FUSB_HUB_PORT_CHANGE] & FUSB_HUB_STATUS_PORT_CONNECTION)
+    {
         FUsbClearFeature(dev, port, FUSB_HUB_SEL_C_PORT_CONNECTION, DR_PORT);
+    }
 
     if (buf[FUSB_HUB_PORT_STATUS] & FUSB_HUB_STATUS_PORT_CONNECTION)
     {
-        FUSB_INFO("usbhub: Port coldplug at %d ", port);
+        FUSB_INFO("Usb hub: Port coldplug at %d ", port);
         FUsbGenericHubScanPort(dev, port);
     }
 
@@ -337,7 +351,9 @@ static FUsbTransCode FUsbHubHandlePortChange(FUsbDev *const dev, const int port)
 
     ret = FUsbGetStatus(dev, port, DR_PORT, sizeof(buf), buf);
     if (ret < FUSB_CC_ZERO_BYTES)
+    {
         return ret;
+    }
 
     /*
      * Second word holds the change bits. The interrupt transfer shows
@@ -355,7 +371,9 @@ static FUsbTransCode FUsbHubHandlePortChange(FUsbDev *const dev, const int port)
     }
 
     if (buf[FUSB_HUB_PORT_CHANGE] & ~checked_bits)
+    {
         FUSB_DEBUG("Spurious change bit at port %d ", port);
+    }
 
     /* Now, handle connection changes. */
     if (buf[FUSB_HUB_PORT_CHANGE] & FUSB_HUB_STATUS_PORT_CONNECTION)
@@ -387,7 +405,9 @@ static void FUsbHubPoll(FUsbDev *const dev)
     while (NULL != (ibuf = dev->controller->poll_intr_queue(FUSB_GEN_HUB_GET(dev)->data)))
     {
         for (i = 0; (size_t)i < port_bytes; ++i)
+        {
             buf[i] |= ibuf[i];
+        }
     }
 
     for (port = 1; port <= FUSB_GEN_HUB_GET(dev)->num_ports; ++port)
@@ -396,7 +416,9 @@ static void FUsbHubPoll(FUsbDev *const dev)
         if (buf[port / 8] & (1 << (port % 8)))
         {
             if (FUsbHubHandlePortChange(dev, port) < 0)
+            {
                 return;
+            }
         }
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.h
index 5e6235a11fe..62750491d9c 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_hub.h
@@ -19,21 +19,21 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_USB_HUB_H
-#define  DRIVERS_USB_HUB_H
+#ifndef  FUSB_HUB_H
+#define  FUSB_HUB_H
+
+/***************************** Include Files *********************************/
+
+#include "fusb.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-
-#include "fusb.h"
-
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c
index 0e6a8a64efc..f48d945eb59 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include <string.h>
@@ -116,7 +116,9 @@ static void FUsbMscRemoveDisk(FUsbDev *dev)
     FASSERT(dev);
 
     if (MSC_INST(dev)->usbdisk_created && FUsbDiskRemove)
+    {
         FUsbDiskRemove(dev);
+    }
 
     return;
 }
@@ -222,12 +224,14 @@ static int FUsbMscResetTransport(FUsbDev *dev)
     dr.wLength = 0;
 
     if (MSC_INST(dev)->quirks & FUSB_MSC_QUIRK_NO_RESET)
+    {
         return MSC_COMMAND_FAIL;
+    }
 
     /* if any of these fails, detach device, as we are lost */
     if (dev->controller->control(dev, FUSB_OUT, sizeof(dr), &dr, 0, 0) < 0 ||
-            FUsbClearStall(MSC_INST(dev)->bulk_in) ||
-            FUsbClearStall(MSC_INST(dev)->bulk_out))
+        FUsbClearStall(MSC_INST(dev)->bulk_in) ||
+        FUsbClearStall(MSC_INST(dev)->bulk_out))
     {
         FUSB_INFO("Detaching unresponsive device. ");
         FUsbDetachDev(dev->controller, dev->address);
@@ -253,8 +257,8 @@ static void FUsbMscInitLuns(FUsbDev *dev)
 
     /* send class-spefic request Get Max Lun */
     if ((MSC_INST(dev)->quirks & FUSB_MSC_QUIRK_NO_LUNS) ||
-            (dev->controller->control(dev, FUSB_IN, sizeof(dr), &dr,
-                                      sizeof(msc->num_luns), &msc->num_luns) < FUSB_CC_ZERO_BYTES))
+        (dev->controller->control(dev, FUSB_IN, sizeof(dr), &dr,
+                                  sizeof(msc->num_luns), &msc->num_luns) < FUSB_CC_ZERO_BYTES))
     {
         msc->num_luns = 0; /* assume only 1 lun if req fails */
     }
@@ -298,18 +302,22 @@ static int FUsbMscGetCsw(FUsbEndpoint *ep, FUsbMscCsw *csw)
     /* Some broken sticks send a zero-length packet at the end of their data
        transfer which would show up here. Skip it to get the actual CSW. */
     if (ret == 0)
+    {
         ret = ctrlr->bulk(ep, sizeof(FUsbMscCsw), (u8 *)csw, 1);
+    }
 
     if (ret < 0)
     {
         FUsbClearStall(ep);
         ret = ctrlr->bulk(ep, sizeof(FUsbMscCsw), (u8 *)csw, 1);
         if (ret < 0)
+        {
             return FUsbMscResetTransport(ep->dev);
+        }
     }
 
     if (ret != sizeof(FUsbMscCsw) || csw->dCSWTag != tag ||
-            csw->dCSWSignature != csw_signature)
+        csw->dCSWSignature != csw_signature)
     {
         FUSB_INFO("MSC: received malformed CSW ");
         return FUsbMscResetTransport(ep->dev);
@@ -343,12 +351,16 @@ static int FUsbMscExecCmd(FUsbDev *dev, FUsbMassStorageDirection dir, const u8 *
         if (dir == FUSB_DIR_DATA_IN)
         {
             if (dev->controller->bulk(MSC_INST(dev)->bulk_in, buflen, buf, 0) < 0)
+            {
                 FUsbClearStall(MSC_INST(dev)->bulk_in);
+            }
         }
         else
         {
             if (dev->controller->bulk(MSC_INST(dev)->bulk_out, buflen, buf, 0) < 0)
+            {
                 FUsbClearStall(MSC_INST(dev)->bulk_out);
+            }
         }
     }
 
@@ -372,21 +384,29 @@ static int FUsbMscExecCmd(FUsbDev *dev, FUsbMassStorageDirection dir, const u8 *
     {
         if ((csw.dCSWDataResidue == 0) || residue_ok)
             /* no error, exit */
+        {
             return MSC_COMMAND_OK;
+        }
         else
             /* missed some bytes */
+        {
             return MSC_COMMAND_FAIL;
+        }
     }
     else
     {
         if (cb[0] == 0x03)
             /* requesting sense failed, that's bad */
+        {
             return MSC_COMMAND_FAIL;
+        }
         else if (cb[0] == 0)
             /* If command was TEST UNIT READY determine if the
              * device is of removable type indicating no media
              * found. */
+        {
             return FUsbMscRequestNoMedia(dev);
+        }
         /* error "check condition" or reserved error */
         ret = FUsbMscRequestSense(dev);
         /* return fail or the status of FUsbMscRequestSense if it's worse */
@@ -510,7 +530,9 @@ static int FUsbMscRwBlks(FUsbDev *dev, int start, int n, FUsbMassStorageDirectio
         if (FUsbMscRwChunk(dev, start + (chunk * chunk_size),
                            chunk_size, dir,
                            buf + (chunk * MAX_CHUNK_BYTES)) != MSC_COMMAND_OK)
+        {
             return 1;
+        }
     }
 
     /* Read any remaining partial chunk at the end. */
@@ -519,7 +541,9 @@ static int FUsbMscRwBlks(FUsbDev *dev, int start, int n, FUsbMassStorageDirectio
         if (FUsbMscRwChunk(dev, start + (chunk * chunk_size),
                            n % chunk_size, dir,
                            buf + (chunk * MAX_CHUNK_BYTES)) != MSC_COMMAND_OK)
+        {
             return 1;
+        }
     }
 
     return 0;
@@ -553,15 +577,21 @@ static int FUsbMscRequestNoMedia(FUsbDev *dev)
                          sizeof(cb), buf, sizeof(buf), 1);
 
     if (ret)
+    {
         return ret;
+    }
 
     /* Check if sense key is set to NOT READY. */
     if ((buf[2] & 0xf) != 2)
+    {
         return MSC_COMMAND_FAIL;
+    }
 
     /* Check if additional sense code is 0x3a. */
     if (buf[12] != 0x3a)
+    {
         return MSC_COMMAND_FAIL;
+    }
 
     /* No media is present. Return MSC_COMMAND_OK while marking the disk
      * not ready. */
@@ -604,19 +634,19 @@ static int FUsbMscReadCapcity(FUsbDev *dev)
         switch (ret = FUsbMscExecCmd(dev, FUSB_DIR_DATA_IN, (u8 *)&cb,
                                      sizeof(cb), (u8 *)buf, 8, 0))
         {
-        case MSC_COMMAND_OK:
-            break;
-        case MSC_COMMAND_FAIL:
-            continue;
-        default: /* if it's worse return */
-            return ret;
+            case MSC_COMMAND_OK:
+                break;
+            case MSC_COMMAND_FAIL:
+                continue;
+            default: /* if it's worse return */
+                return ret;
         }
         break;
     }
     if (count >= 20)
     {
         /* still not successful, assume 2tb in 512byte sectors, which is just the same garbage as any other number, but probably more usable. */
-        FUSB_WARN("  assuming 2 TB with 512-byte sectors as READ CAPACITY didn't answer. ");
+        FUSB_WARN("Assuming 2 TB with 512-byte sectors as read capacity didn't answer. ");
         MSC_INST(dev)->numblocks = 0xffffffff;
         MSC_INST(dev)->blocksize = 512;
     }
@@ -655,15 +685,15 @@ static int FUsbMscWaitReady(FUsbDev *dev)
     {
         switch (FUsbMscCheckIfReady(dev))
         {
-        case MSC_COMMAND_OK:
-            break;
-        case MSC_COMMAND_FAIL:
-            fsleep_millisec(100);
-            FUSB_INFO(".");
-            continue;
-        default:
-            /* Device detached, return immediately */
-            return FUSB_MSC_DETACHED;
+            case MSC_COMMAND_OK:
+                break;
+            case MSC_COMMAND_FAIL:
+                fsleep_millisec(100);
+                FUSB_INFO(".");
+                continue;
+            default:
+                /* Device detached, return immediately */
+                return FUSB_MSC_DETACHED;
         }
         break;
     }
@@ -671,7 +701,7 @@ static int FUsbMscWaitReady(FUsbDev *dev)
 
     if (FUsbMscTimeout(start_tick, timeout_tick))
     {
-        FUSB_INFO("timeout. Device not ready. ");
+        FUSB_INFO("Timeout. Device not ready. ");
         MSC_INST(dev)->ready = FUSB_MSC_NOT_READY;
     }
 
@@ -679,28 +709,32 @@ static int FUsbMscWaitReady(FUsbDev *dev)
      * ready. This can happen when empty card readers are present.
      * Polling will pick it back up if readiness changes. */
     if (!MSC_INST(dev)->ready)
+    {
         return MSC_INST(dev)->ready;
+    }
 
     for (i = 0; i < 30; i++)
     {
         FUSB_INFO(".");
         switch (FUsbMscSpinUp(dev))
         {
-        case MSC_COMMAND_OK:
-            FUSB_INFO(" OK.");
-            break;
-        case MSC_COMMAND_FAIL:
-            fsleep_millisec(100);
-            continue;
-        default:
-            /* Device detached, return immediately */
-            return FUSB_MSC_DETACHED;
+            case MSC_COMMAND_OK:
+                FUSB_INFO(" OK.");
+                break;
+            case MSC_COMMAND_FAIL:
+                fsleep_millisec(100);
+                continue;
+            default:
+                /* Device detached, return immediately */
+                return FUSB_MSC_DETACHED;
         }
         break;
     }
 
     if (FUsbMscReadCapcity(dev) == MSC_COMMAND_DETACHED)
+    {
         return FUSB_MSC_DETACHED;
+    }
 
     return MSC_INST(dev)->ready;
 }
@@ -739,8 +773,8 @@ void FUsbMassStorageInit(FUsbDev *dev)
     }
 
     if ((interface->bInterfaceSubClass != FUSB_MSC_SUBCLASS_ATAPI_8020) && /* ATAPI 8020 */
-            (interface->bInterfaceSubClass != FUSB_MSC_SUBCLASS_ATAPI_8070) && /* ATAPI 8070 */
-            (interface->bInterfaceSubClass != FUSB_MSC_SUBCLASS_SCSI))
+        (interface->bInterfaceSubClass != FUSB_MSC_SUBCLASS_ATAPI_8070) && /* ATAPI 8070 */
+        (interface->bInterfaceSubClass != FUSB_MSC_SUBCLASS_SCSI))
     {
         /* SCSI */
         /* Other protocols, such as ATAPI don't seem to be very popular. looks like ATAPI would be really easy to add, if necessary. */
@@ -784,19 +818,27 @@ static void FUsbMassStorageForceInit(FUsbDev *dev, u32 quirks)
     for (i = 1; i <= dev->num_endp; i++)
     {
         if (dev->endpoints[i].endpoint == 0)
+        {
             continue;
+        }
         if (dev->endpoints[i].type != FUSB_BULK_EP)
+        {
             continue;
+        }
         if ((dev->endpoints[i].direction == FUSB_IN) && (MSC_INST(dev)->bulk_in == 0))
+        {
             MSC_INST(dev)->bulk_in = &dev->endpoints[i];
+        }
         if ((dev->endpoints[i].direction == FUSB_OUT) && (MSC_INST(dev)->bulk_out == 0))
+        {
             MSC_INST(dev)->bulk_out = &dev->endpoints[i];
+        }
     }
 
     /* check if non bulk-in ep */
     if (MSC_INST(dev)->bulk_in == NULL)
     {
-        FUSB_ERROR("couldn't find bulk-in endpoint. ");
+        FUSB_ERROR("Couldn't find bulk-in endpoint.");
         FUsbDetachDev(dev->controller, dev->address);
         return;
     }
@@ -804,12 +846,12 @@ static void FUsbMassStorageForceInit(FUsbDev *dev, u32 quirks)
     /* check if non bulk-out ep */
     if (MSC_INST(dev)->bulk_out == NULL)
     {
-        FUSB_ERROR("couldn't find bulk-out endpoint. ");
+        FUSB_ERROR("Couldn't find bulk-out endpoint.");
         FUsbDetachDev(dev->controller, dev->address);
         return;
     }
 
-    FUSB_INFO("using endpoint %x as in, %x as out ",
+    FUSB_INFO("Using endpoint %x as in, %x as out.",
               MSC_INST(dev)->bulk_in->endpoint,
               MSC_INST(dev)->bulk_out->endpoint);
 
@@ -817,11 +859,13 @@ static void FUsbMassStorageForceInit(FUsbDev *dev, u32 quirks)
     fsleep_microsec(50);
 
     FUsbMscInitLuns(dev);
-    FUSB_INFO("  has %d luns ", MSC_INST(dev)->num_luns);
+    FUSB_INFO("Has %d luns.", MSC_INST(dev)->num_luns);
 
     /* Test if msc is ready (nothing to do if it isn't). */
     if (FUsbMscWaitReady(dev) != FUSB_MSC_READY)
+    {
         return;
+    }
 
     /* Create the disk. */
     FUsbMscCreateDisk(dev);
@@ -835,7 +879,9 @@ static void FUsbMscPoll(FUsbDev *dev)
     int prev_ready = msc->ready;
 
     if (FUsbMscWaitReady(dev) == FUSB_MSC_DETACHED)
+    {
         return;
+    }
 
     if (!prev_ready && msc->ready)
     {
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.h
index bc0a1989b95..0e9d7c2eef8 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.h
@@ -19,21 +19,21 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_USB_MSC_H
-#define  DRIVERS_USB_MSC_H
+#ifndef  FUSB_MSC_H
+#define  FUSB_MSC_H
+
+/***************************** Include Files *********************************/
+
+#include "fusb.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-
-#include "fusb.h"
-
 /************************** Constant Definitions *****************************/
 /* Possible values for quirks field. */
 enum
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h
index b1db5215070..859db19a090 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h
@@ -19,10 +19,11 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#pragma once
+#ifndef  FUSB_PRIVATE_H
+#define  FUSB_PRIVATE_H
 
 /***************************** Include Files *********************************/
 #ifdef __aarch64__
@@ -36,6 +37,11 @@
 #include "fassert.h"
 #include "fusb.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -101,4 +107,10 @@ void FUsbDumpConfigDescriptor(const FUsbConfigurationDescriptor *descriptor);
 void FUsbDumpInterfaceDescriptor(const FUsbInterfaceDescriptor *descriptor);
 
 /* 打印端点描述符信息 */
-void FUsbDumpEndpointDescriptor(const FUsbEndpointDescriptor *descriptor);
\ No newline at end of file
+void FUsbDumpEndpointDescriptor(const FUsbEndpointDescriptor *descriptor);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_sinit.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_sinit.c
index cf5af243e10..fe4f5e6283d 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_sinit.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/8    init version
+ * 1.0   zhugengyu  2022/2/8    init version
  */
 
 /***************************** Include Files *********************************/
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.c
index 17b5538d475..ce112381731 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include <string.h>
@@ -73,12 +73,18 @@ void *FXhciAlign(FXhci *const xhci, const size_t min_align, const size_t size)
     FUsb *instance = xhci->usb;
 
     if (!(size & (size - 1)))
-        align = size; /* It's a power of 2 */
+    {
+        align = size;    /* It's a power of 2 */
+    }
     else
+    {
         align = 1 << ((sizeof(unsigned) << 3) - __builtin_clz(size));
+    }
 
     if (align < min_align)
+    {
         align = min_align;
+    }
 
     return FUSB_ALLOCATE(instance, size, align);
 }
@@ -91,12 +97,18 @@ void *FXhciAlignTag(FXhci *const xhci, const size_t min_align, const size_t size
     FUsb *instance = xhci->usb;
 
     if (!(size & (size - 1)))
-        align = size; /* It's a power of 2 */
+    {
+        align = size;    /* It's a power of 2 */
+    }
     else
+    {
         align = 1 << ((sizeof(unsigned) << 3) - __builtin_clz(size));
+    }
 
     if (align < min_align)
+    {
         align = min_align;
+    }
 
     return FUsbMempAllocateTag(instance, size, align, file, line, msg);
 }
@@ -163,12 +175,12 @@ static FError FXhciHandShake(FXhci *xhci, FXhciHandShakeType type, uintptr reg_o
 
     switch (type)
     {
-    case FXHCI_OP_REG:
-        ret = FXhciWaitOper32(&xhci->mmio, reg_off, mask, wait_for, timeout);
-        break;
-    default:
-        FASSERT(0);
-        break;
+        case FXHCI_OP_REG:
+            ret = FXhciWaitOper32(&xhci->mmio, reg_off, mask, wait_for, timeout);
+            break;
+        default:
+            FASSERT(0);
+            break;
     }
 
     return ret;
@@ -183,13 +195,17 @@ static FError FXhciHandShake(FXhci *xhci, FXhciHandShakeType type, uintptr reg_o
 static FError FXhciWaitReady(FXhci *const xhci)
 {
     FASSERT(xhci);
-    FUSB_INFO("Waiting for controller to be ready... ");
+    FUSB_INFO("Waiting for controller to be ready.");
     FError ret = FXhciHandShake(xhci, FXHCI_OP_REG, FXHCI_REG_OP_USBSTS, FXHCI_REG_OP_USBSTS_CNR, 0, FXHCI_TIMEOUT);
 
     if (FUSB_SUCCESS == ret)
-        FUSB_INFO("ok");
+    {
+        FUSB_INFO("Waiting for controller success.");
+    }
     else
-        FUSB_ERROR("timeout.");
+    {
+        FUSB_ERROR("Waiting for controller timeout.");
+    }
 
     return ret;
 }
@@ -210,12 +226,12 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     u16 hc_version;
     uintptr xhci_base_addr =  base_addr + FUSB3_XHCI_OFFSET;
 
-    FUSB_DEBUG("xhci base addr: 0x%x", xhci_base_addr);
+    FUSB_DEBUG("Xhci base addr: 0x%x.", xhci_base_addr);
     /* First, allocate and initialize static controller structures */
     FUsbHc *const controller = FUsbAllocateHc(instance);
     if (NULL == controller)
     {
-        FUSB_ERROR("Out of memory ");
+        FUSB_ERROR("Out of memory.");
         return NULL;
     }
 
@@ -241,7 +257,7 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     controller->instance = FUSB_ALLOCATE(instance, sizeof(FXhci), FUSB_DEFAULT_ALIGN);
     if (NULL == controller->instance)
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         goto _free_controller;
     }
 
@@ -261,9 +277,9 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     xhci->er.ring = FXHCI_ALIGN(xhci, 64, FXHCI_EVENT_RING_SIZE * sizeof(FXhciTrb));
     xhci->ev_ring_table = FXHCI_ALIGN(xhci, 64, sizeof(FXhciErstEntry));
     if ((NULL == xhci->roothub) || (NULL == xhci->cr.ring) ||
-            (NULL == xhci->er.ring) || (NULL == xhci->ev_ring_table))
+        (NULL == xhci->er.ring) || (NULL == xhci->ev_ring_table))
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         goto _free_xhci;
     }
 
@@ -275,7 +291,7 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     hc_version = FXhciReadHcVersion(mmio);
     if (hc_version < FXHCI_HC_VERSION_MIN || hc_version > FXHCI_HC_VERSION_MAX)
     {
-        FUSB_ERROR("xHCI version 0x%x not support", hc_version);
+        FUSB_ERROR("Xhci version 0x%x not support.", hc_version);
         goto _free_xhci;
     }
 
@@ -304,7 +320,7 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     xhci->dev = FUSB_ALLOCATE(instance, (xhci->max_slots_en + 1) * sizeof(*xhci->dev), FUSB_DEFAULT_ALIGN);
     if ((NULL == xhci->dcbaa) || (NULL == xhci->dev))
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         goto _free_xhci;
     }
 
@@ -314,17 +330,17 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
      */
     reg_val = FXhciReadCap32(&xhci->mmio, FXHCI_REG_CAP_HCSPARAMS2);
     const size_t max_sp_bufs = FXHCI_REG_CAP_HCSPARAMS2_MAX_SCRATCHPAD_BUFS_GET(reg_val);
-    FUSB_INFO("max scratchpad bufs: 0x%lx reg_val : 0x%x", max_sp_bufs, reg_val);
+    FUSB_INFO("Max scratchpad bufs: 0x%lx reg_val : 0x%x.", max_sp_bufs, reg_val);
     if (0 < max_sp_bufs)
     {
-        FUSB_INFO("allocate sp_ptrs");
+        FUSB_INFO("Allocate sp_ptrs.");
         const size_t sp_ptrs_size = max_sp_bufs * sizeof(u64);
         /* allocate scratchpad bufs entry to preserve pointers of scratchpad buf */
         FASSERT(NULL == xhci->sp_ptrs);
         xhci->sp_ptrs = FXHCI_ALIGN(xhci, 64, sp_ptrs_size);
         if (NULL == xhci->sp_ptrs)
         {
-            FUSB_INFO("Out of memory ");
+            FUSB_INFO("Out of memory.");
             goto _free_xhci_structs;
         }
 
@@ -334,7 +350,7 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
             void *const page = FUSB_ALLOCATE(instance, pagesize, pagesize);
             if (NULL == page)
             {
-                FUSB_INFO("Out of memory ");
+                FUSB_INFO("Out of memory.");
                 goto _free_xhci_structs;
             }
 
@@ -346,7 +362,9 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
 
     /* Now start working on the hardware */
     if (FUSB_SUCCESS != FXhciWaitReady(xhci))
+    {
         goto _free_xhci_structs;
+    }
 
     /* TODO: Check if BIOS claims ownership (and hand over) */
 
@@ -362,7 +380,7 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
     xhci->roothub->init = FXhciRootHubInit;
     xhci->roothub->init(xhci->roothub);
 
-    FUSB_INFO("init xHc@%p success", controller);
+    FUSB_INFO("Init xhc@%p success.", controller);
     return controller;
 
 _free_xhci_structs:
@@ -371,7 +389,9 @@ FUsbHc *FXhciHcInit(FUsb *instance, uintptr base_addr)
         for (i = 0; (size_t)i < max_sp_bufs; ++i)
         {
             if (xhci->sp_ptrs[i])
+            {
                 FUSB_FREE(instance, (void *)(uintptr)(xhci->sp_ptrs[i]));
+            }
         }
     }
     FUSB_FREE(instance, xhci->sp_ptrs);
@@ -439,7 +459,9 @@ static void FXhciReinit(FUsbHc *controller)
 
     /* wait xhci ready */
     if (FUSB_SUCCESS != FXhciWaitReady(xhci))
+    {
         return;
+    }
 
     /* Enable all available slots */
     reg_val = FXhciReadOper32(&xhci->mmio, FXHCI_REG_OP_CONFIG);
@@ -496,10 +518,10 @@ static void FXhciReinit(FUsbHc *controller)
     /* run Cmd Nop to test if command ring okay */
     for (int i = 0; i < 3; ++i)
     {
-        FUSB_INFO("NOOP run #%d ", i);
+        FUSB_INFO("Noop run #%d .", i);
         if (FXHCI_CC_SUCCESS != FXhciCmdNop(xhci))
         {
-            FUSB_ERROR("noop command failed. ");
+            FUSB_ERROR("Noop command failed. ");
             break;
         }
     }
@@ -519,7 +541,9 @@ static void FXhciShutdown(FUsbHc *const controller)
     u32 reg_val;
 
     if (controller == NULL)
+    {
         return;
+    }
 
     /* detach the Hc instance */
     FUsbDetachHc(controller);
@@ -537,7 +561,9 @@ static void FXhciShutdown(FUsbHc *const controller)
         for (i = 0; (size_t)i < max_sp_bufs; ++i)
         {
             if (NULL != (void *)(uintptr)xhci->sp_ptrs[i])
+            {
                 FUSB_FREE(instance, (void *)(uintptr)(xhci->sp_ptrs[i]));
+            }
         }
     }
 
@@ -630,7 +656,7 @@ static FError FXhciResetEp(FUsbDev *const dev, FUsbEndpoint *const ep)
         const FXhciTransCode cc = FXhciCmdResetEp(xhci, slot_id, ep_id);
         if (cc != FXHCI_CC_SUCCESS)
         {
-            FUSB_INFO("Reset Endpoint Command failed: %d ", cc);
+            FUSB_INFO("Reset endpoint command failed: %d .", cc);
             return FUSB_ERR_TRANS_FAIL;
         }
     }
@@ -638,7 +664,7 @@ static FError FXhciResetEp(FUsbDev *const dev, FUsbEndpoint *const ep)
     /* Clear TT buffer for bulk and control endpoints behind a TT */
     const int hub = dev->hub;
     if (hub && dev->speed < FUSB_HIGH_SPEED &&
-            dev->controller->devices[hub]->speed == FUSB_HIGH_SPEED)
+        dev->controller->devices[hub]->speed == FUSB_HIGH_SPEED)
     {
         /* TODO */;
     }
@@ -653,7 +679,7 @@ static FError FXhciResetEp(FUsbDev *const dev, FUsbEndpoint *const ep)
                                   tr->ring, 1);
         if (cc != FXHCI_CC_SUCCESS)
         {
-            FUSB_INFO("Set TR Dequeue Command failed: %d ", cc);
+            FUSB_INFO("Set TR dequeue command failed: %d .", cc);
             return FUSB_ERR_TRANS_FAIL;
         }
 
@@ -682,7 +708,7 @@ static void FXhciEnqueueTrb(FXhciTransRing *const tr)
 
     while (FXHCI_TRB_GET(TT, tr->cur) == FXHCI_TRB_LINK)
     {
-        FUSB_DEBUG("Handling LINK pointer ");
+        FUSB_DEBUG("Handling link pointer. ");
 
         const int tc = FXHCI_TRB_GET(TC, tr->cur);
         FXHCI_TRB_SET(CH, tr->cur, chain); /* Chain Bit */
@@ -694,7 +720,9 @@ static void FXhciEnqueueTrb(FXhciTransRing *const tr)
 
         /* toggle cycle state */
         if (tc)
+        {
             tr->pcs ^= 1;
+        }
     }
 
     return;
@@ -955,7 +983,7 @@ static FXhciTransCode FXhciBulk(FUsbEndpoint *const ep, const int size, u8 *cons
     const size_t off = (size_t)data & 0xffff;
     if ((off + size) > ((FXHCI_TRANSFER_RING_SIZE - 2) << 16))
     {
-        FUSB_INFO("Unsupported transfer size ");
+        FUSB_INFO("Unsupported transfer size .");
         return FXHCI_CC_GENERAL_ERROR;
     }
 
@@ -964,7 +992,9 @@ static FXhciTransCode FXhciBulk(FUsbEndpoint *const ep, const int size, u8 *cons
     if (ep_state > FXHCI_EC_STATE_RUNNING)
     {
         if (FUSB_SUCCESS != FXhciResetEp(ep->dev, ep))
+        {
             return FXHCI_CC_GENERAL_ERROR;
+        }
     }
 
     FCacheDCacheInvalidateRange((uintptr)data, size);
@@ -1014,7 +1044,9 @@ static FXhciTrb *FXhciNextTrb(FXhciTrb *cur, int *const pcs)
     while (FXHCI_TRB_GET(TT, cur) == FXHCI_TRB_LINK)
     {
         if (pcs && FXHCI_TRB_GET(TC, cur))
+        {
             *pcs ^= 1;
+        }
 
         cur = (void *)(uintptr)(cur->ptr_low);
     }
@@ -1047,20 +1079,20 @@ static void *FXhciCreateIntrQueue(FUsbEndpoint *const ep, const int reqsize, con
 
     if (reqcount > (FXHCI_TRANSFER_RING_SIZE - 2))
     {
-        FUSB_INFO("reqcount is too high, at most %d supported ",
+        FUSB_INFO("Reqcount is too high, at most %d supported .",
                   FXHCI_TRANSFER_RING_SIZE - 2);
         return NULL;
     }
 
     if (reqsize > 0x10000)
     {
-        FUSB_INFO("reqsize is too large, at most 64KiB supported ");
+        FUSB_INFO("Reqsize is too large, at most 64KiB supported .");
         return NULL;
     }
 
     if (xhci->dev[slot_id].interrupt_queues[ep_id])
     {
-        FUSB_INFO("Only one interrupt queue per endpoint supported ");
+        FUSB_INFO("Only one interrupt queue per endpoint supported .");
         return NULL;
     }
 
@@ -1068,7 +1100,7 @@ static void *FXhciCreateIntrQueue(FUsbEndpoint *const ep, const int reqsize, con
     FXhciIntrQ *const intrq = FUSB_ALLOCATE(instance, sizeof(*intrq), FUSB_DEFAULT_ALIGN);
     if (NULL == intrq)
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         return NULL;
     }
 
@@ -1079,7 +1111,7 @@ static void *FXhciCreateIntrQueue(FUsbEndpoint *const ep, const int reqsize, con
     {
         if (FXHCI_TRB_GET(C, cur) == (unsigned int)pcs)
         {
-            FUSB_INFO("Not enough empty TRBs ");
+            FUSB_INFO("Not enough empty TRBs .");
             goto _free_return;
         }
 
@@ -1087,7 +1119,7 @@ static void *FXhciCreateIntrQueue(FUsbEndpoint *const ep, const int reqsize, con
         void *const reqdata = FXHCI_ALIGN(xhci, 1, reqsize);
         if (NULL == reqdata)
         {
-            FUSB_INFO("Out of memory ");
+            FUSB_INFO("Out of memory.");
             goto _free_return;
         }
 
@@ -1112,7 +1144,9 @@ static void *FXhciCreateIntrQueue(FUsbEndpoint *const ep, const int reqsize, con
     /* Now enqueue all the prepared TRBs but the last
        and ring the doorbell. */
     for (i = 0; i < (reqcount - 1); ++i)
+    {
         FXhciEnqueueTrb(tr);
+    }
 
     FXhciRingDoorbell(ep);
     return intrq;
@@ -1152,7 +1186,9 @@ static void FXhciDestoryIntrQueue(FUsbEndpoint *const ep, void *const q)
     {
         const FXhciTransCode cc = FXhciCmdStopEp(xhci, slot_id, ep_id);
         if (cc != FXHCI_CC_SUCCESS)
-            FUSB_INFO("Warning: Failed to stop endpoint ");
+        {
+            FUSB_INFO("Warning: Failed to stop endpoint .");
+        }
     }
 
     /* Process all remaining transfer events */
@@ -1188,7 +1224,9 @@ static void FXhciDestoryIntrQueue(FUsbEndpoint *const ep, void *const q)
 static u8 *FXhciPollIntrQueue(void *const q)
 {
     if (NULL == q)
+    {
         return NULL;
+    }
 
     FXhciIntrQ *const intrq = (FXhciIntrQ *)q;
     FUsbEndpoint *const ep = intrq->ep;
@@ -1224,15 +1262,21 @@ static u8 *FXhciPollIntrQueue(void *const q)
         /* Check if anything was transferred */
         const size_t read = FXHCI_TRB_GET(TL, intrq->next);
         if (!read)
+        {
             reqdata = NULL;
+        }
         else if (read < intrq->size)
             /* At least zero it, poll interface is rather limited */
+        {
             memset(reqdata + read, 0x00, intrq->size - read);
+        }
 
         /* Advance the interrupt queue */
         if (intrq->ready == intrq->next)
             /* This was last TRB being ready */
+        {
             intrq->ready = NULL;
+        }
         intrq->next = FXhciNextTrb(intrq->next, NULL);
     }
 
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.h b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.h
index b23ebd05a18..9221bb352be 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci.h
@@ -19,20 +19,21 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_USB_FXHCI_H
-#define  DRIVERS_USB_FXHCI_H
+#ifndef  FXHCI_H
+#define  FXHCI_H
+
+/***************************** Include Files *********************************/
+#include "fusb.h"
+
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-/***************************** Include Files *********************************/
-#include "fusb.h"
-
 /************************** Constant Definitions *****************************/
 #define FXHCI_EVENT_RING_SIZE    64
 #define FXHCI_TRANSFER_RING_SIZE 32 /* Never raise this above 256 to prevent transfer event length overflow! */
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_cmd.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_cmd.c
index dbfb2780daf..a25961bf662 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_cmd.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_cmd.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fdebug.h"
@@ -39,7 +39,7 @@ FXhciTrb *FXhciNextCmdTrb(FXhci *const xhci)
 
 void FXhciPostCmd(FXhci *const xhci)
 {
-    FUSB_INFO("Command %d (@%p) ", FXHCI_TRB_GET(TT, xhci->cr.cur), xhci->cr.cur);
+    FUSB_INFO("Command %d (@%p).", FXHCI_TRB_GET(TT, xhci->cr.cur), xhci->cr.cur);
 
     FXHCI_TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); /* Cycle Bit */
     ++xhci->cr.cur;
@@ -52,12 +52,14 @@ void FXhciPostCmd(FXhci *const xhci)
 
     while (FXHCI_TRB_GET(TT, xhci->cr.cur) == FXHCI_TRB_LINK)
     {
-        FUSB_DEBUG("Handling LINK pointer (@%p) ", xhci->cr.cur);
+        FUSB_DEBUG("Handling link pointer (@%p).", xhci->cr.cur);
         const int tc = FXHCI_TRB_GET(TC, xhci->cr.cur); /* Completion Code */
         FXHCI_TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); /* Cycle Bit */
         xhci->cr.cur = (void *)(uintptr)(xhci->cr.cur->ptr_low);
         if (tc)
+        {
             xhci->cr.pcs ^= 1;
+        }
     }
 }
 
@@ -70,10 +72,12 @@ static FXhciTransCode FXhciWaitForCmd(FXhci *const xhci,
 
     cc = FXhciWaitForCmdDone(xhci, cmd_trb, clear_event);
     if (cc != FXHCI_CC_TIMEOUT)
+    {
         return cc;
+    }
 
     /* Abort command on timeout */
-    FUSB_ERROR("Aborting command (@%p), CRCR: 0x%x ", cmd_trb, FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR));
+    FUSB_ERROR("Aborting command (@%p), CRCR: 0x%x.", cmd_trb, FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR));
 
     /*
      * Ref. xHCI Specification Revision 1.2, May 2019.
@@ -88,7 +92,9 @@ static FXhciTransCode FXhciWaitForCmd(FXhci *const xhci,
     cc = FXhciWaitForCmdAborted(xhci, cmd_trb);
 
     if ((FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR) & FXHCI_REG_OP_CRCR_CRR))
-        FUSB_ERROR("xhci_wait_for_command: Command ring still running");
+    {
+        FUSB_ERROR("FXhciWaitForCmd: Command ring still running.");
+    }
 
     return cc;
 }
@@ -103,12 +109,14 @@ FXhciTransCode FXhciCmdNop(FXhci *const xhci)
     /* wait for result in event ring */
     FXhciTransCode cc = FXhciWaitForCmdDone(xhci, cmd, 1);
 
-    FUSB_INFO("Command ring is %srunning: cc: %d",
+    FUSB_INFO("Command ring is %srunning: cc: %d.",
               (FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR) & FXHCI_REG_OP_CRCR_CRR) ? "" : "not ", /* check if cmd ring is running */
               cc);
 
     if (cc != FXHCI_CC_SUCCESS)
-        FUSB_ERROR("noop command failed. ");
+    {
+        FUSB_ERROR("Noop command failed.");
+    }
 
     return cc;
 }
@@ -131,7 +139,9 @@ FXhciTransCode FXhciCmdEnableSlot(FXhci *const xhci, int *const slot_id)
         {
             *slot_id = FXHCI_TRB_GET(ID, xhci->er.cur);
             if (*slot_id > xhci->max_slots_en)
+            {
                 cc = FXHCI_CC_CONTROLLER_ERROR;
+            }
         }
 
         FXhciAdvanceEvtRing(xhci);
@@ -178,7 +188,9 @@ FXhciTransCode FXhciCmdConfigureEp(FXhci *const xhci,
     cmd->ptr_low = (uintptr)(ic->raw);
 
     if (config_id == 0)
-        FXHCI_TRB_SET(DC, cmd, 1); /* Deconfigure */
+    {
+        FXHCI_TRB_SET(DC, cmd, 1);    /* Deconfigure */
+    }
 
     FXhciPostCmd(xhci);
 
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_debug.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_debug.c
index 027a7f43906..13663444ec1 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_debug.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_debug.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include <inttypes.h>
@@ -77,12 +77,16 @@ void FXhciDumpDevCtx(const FXhciDevCtx *const dc, const u32 ctx_mask)
     unsigned int i;
 
     if (ctx_mask & 1)
+    {
         FXhciDumpSlotCtx(dc->slot);
+    }
 
     for (i = 1; i <= FXHCI_SC_GET(CTXENT, dc->slot); ++i)
     {
         if (ctx_mask & (1 << i))
+        {
             FXhciDumpEpCtx(dc->ep[i]);
+        }
     }
 }
 
@@ -114,9 +118,13 @@ void FXhciDumpTransferTrb(const FXhciTrb *const cur)
 static const FXhciTrb *FXhciNextTrb(const FXhciTrb *const cur)
 {
     if (FXHCI_TRB_GET(TT, cur) == FXHCI_TRB_LINK)
+    {
         return (!cur->ptr_low) ? NULL : (void *)(uintptr)(cur->ptr_low);
+    }
     else
+    {
         return cur + 1;
+    }
 }
 
 void FXhciDumpTransferTrbs(const FXhciTrb *const first, const FXhciTrb *const last)
@@ -126,6 +134,8 @@ void FXhciDumpTransferTrbs(const FXhciTrb *const first, const FXhciTrb *const la
     {
         FXhciDumpTransferTrb(cur);
         if (cur == last)
+        {
             break;
+        }
     }
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_dev.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_dev.c
index 3d1b868c855..e284bf6bdc9 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_dev.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_dev.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include <string.h>
@@ -39,7 +39,9 @@ static u32 FXhciGenRounte(FXhci *const xhci, const int hubport, const int hubadd
 {
     FASSERT(xhci);
     if (!hubaddr)
+    {
         return 0;
+    }
 
     u32 route_string = FXHCI_SC_GET(ROUTE, xhci->dev[hubaddr].ctx.slot);
     int i;
@@ -60,7 +62,9 @@ static int FXhciGetRoothubPort(FXhci *const xhci, const int hubport, const int h
 {
     FASSERT(xhci);
     if (!hubaddr)
+    {
         return hubport;
+    }
 
     return FXHCI_SC_GET(RHPORT, xhci->dev[hubaddr].ctx.slot);
 }
@@ -71,7 +75,9 @@ static int FXhciGetTT(FXhci *const xhci, const FUsbSpeed speed,
 {
     FASSERT(xhci);
     if (!hubaddr)
+    {
         return 0;
+    }
 
     const FXhciSlotCtx *const slot = xhci->dev[hubaddr].ctx.slot;
 
@@ -95,21 +101,31 @@ static void FXhciReapSlots(FXhci *const xhci, int skip_slot)
     int i;
     FUsb *instance = xhci->usb;
 
-    FUSB_INFO("xHC resource shortage, trying to reap old slots... ");
+    FUSB_INFO("Xhci resource shortage, trying to reap old slots.");
     for (i = 1; i <= xhci->max_slots_en; i++)
     {
         if (i == skip_slot)
-            continue; /* don't reap slot we were working on */
+        {
+            continue;    /* don't reap slot we were working on */
+        }
         if (xhci->dev[i].transfer_rings[1])
-            continue; /* slot still in use */
+        {
+            continue;    /* slot still in use */
+        }
         if (NULL == xhci->dev[i].ctx.raw)
-            continue; /* slot already disabled */
+        {
+            continue;    /* slot already disabled */
+        }
 
         const FXhciTransCode cc = FXhciCmdDisableSlot(xhci, i);
         if (cc != FXHCI_CC_SUCCESS)
-            FUSB_INFO("Failed to disable slot %d: %d ", i, cc);
+        {
+            FUSB_INFO("Failed to disable slot %d: %d.", i, cc);
+        }
         else
-            FUSB_INFO("Successfully reaped slot %d ", i);
+        {
+            FUSB_INFO("Successfully reaped slot %d.", i);
+        }
         xhci->dcbaa[i] = 0;
 
         FUSB_FREE(instance, xhci->dev[i].ctx.raw);
@@ -138,7 +154,9 @@ static FXhciInputCtx *FXhciMakeInputCtx(FXhci *xhci, const size_t ctxsize)
     ic->add = dma_buffer + 4;
     dma_buffer += ctxsize;
     for (i = 0; i < FXHCI_NUM_EPS; i++, dma_buffer += ctxsize)
+    {
         ic->dev.ep[i] = dma_buffer;
+    }
 
     return ic;
 }
@@ -173,7 +191,7 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
 
     if ((NULL == ic) || (NULL == tr) || (NULL == tr->ring))
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         goto _free_return;
     }
 
@@ -188,22 +206,26 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
 
     if (cc != FXHCI_CC_SUCCESS)
     {
-        FUSB_INFO("Enable slot failed: %d ", cc);
+        FUSB_INFO("Enable slot failed: %d.", cc);
         goto _free_return;
     }
     else
     {
-        FUSB_INFO("Enabled slot %d ", slot_id);
+        FUSB_INFO("Enabled slot %d.", slot_id);
     }
 
     di = &xhci->dev[slot_id];
     void *dma_buffer = FUSB_ALLOCATE(instance, FXHCI_NUM_EPS * ctxsize, 64);
     if (NULL == dma_buffer)
+    {
         goto _disable_return;
+    }
 
     memset(dma_buffer, 0, FXHCI_NUM_EPS * ctxsize);
     for (i = 0; i < FXHCI_NUM_EPS; i++, dma_buffer += ctxsize)
+    {
         di->ctx.ep[i] = dma_buffer;
+    }
 
     *ic->add = (1 << 0) /* Slot Context */ | (1 << 1) /* EP0 Context */;
 
@@ -215,7 +237,7 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
     int tt, tt_port;
     if (FXhciGetTT(xhci, speed, hubport, hubaddr, &tt, &tt_port))
     {
-        FUSB_INFO("TT for %d: %d[%d] ", slot_id, tt, tt_port);
+        FUSB_INFO("TT for %d: %d[%d].", slot_id, tt, tt_port);
         FXHCI_SC_SET(MTT, ic->dev.slot, FXHCI_SC_GET(MTT, xhci->dev[tt].ctx.slot));
         FXHCI_SC_SET(TTID, ic->dev.slot, tt);
         FXHCI_SC_SET(TTPORT, ic->dev.slot, tt_port);
@@ -245,12 +267,12 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
 
     if (cc != FXHCI_CC_SUCCESS)
     {
-        FUSB_INFO("Address device failed: %d ", cc);
+        FUSB_INFO("Address device failed: %d.", cc);
         goto _disable_return;
     }
     else
     {
-        FUSB_INFO("Addressed device %d (USB: %d) ",
+        FUSB_INFO("Addressed device %d (USB: %d).",
                   slot_id, FXHCI_SC_GET(UADDR, di->ctx.slot));
     }
 
@@ -258,7 +280,9 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
 
     dev = FUsbInitDevEntry(controller, slot_id);
     if (!dev)
+    {
         goto _disable_return;
+    }
 
     dev->address = slot_id;
     dev->hub = hubaddr;
@@ -273,7 +297,7 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
     u8 buf[8];
     if (FUsbGetDescriptor(dev, FUsbGenerateReqType(FUSB_REQ_DEVICE_TO_HOST, FUSB_REQ_TYPE_STANDARD, FUSB_REQ_RECP_DEV), FUSB_DESC_TYPE_DEVICE, 0, buf, sizeof(buf)) != sizeof(buf))
     {
-        FUSB_INFO("first FUsbGetDescriptor(FUSB_DESC_TYPE_DEVICE) failed ");
+        FUSB_INFO("First FUsbGetDescriptor(FUSB_DESC_TYPE_DEVICE) failed.");
         goto _disable_return;
     }
 
@@ -295,7 +319,7 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
         }
         if (cc != FXHCI_CC_SUCCESS)
         {
-            FUSB_INFO("Context evaluation failed: %d ", cc);
+            FUSB_INFO("Context evaluation failed: %d.", cc);
             goto _disable_return;
         }
     }
@@ -309,7 +333,9 @@ FUsbDev *FXhciSetAddress(FUsbHc *controller, FUsbSpeed speed, int hubport, int h
     dev = NULL;
 _free_return:
     if (tr)
+    {
         FUSB_FREE(instance, (void *)tr->ring);
+    }
     FUSB_FREE(instance, tr);
     if (di)
     {
@@ -332,7 +358,7 @@ static int FXhciFinishHubConfig(FUsbDev *const dev, FXhciInputCtx *const ic)
 
     if (FUsbGetDescriptor(dev, FUsbGenerateReqType(FUSB_REQ_DEVICE_TO_HOST, FUSB_REQ_TYPE_CLASS, FUSB_REQ_RECP_DEV), type, 0, &desc, sizeof(desc)) != sizeof(desc))
     {
-        FUSB_INFO("Failed to fetch hub descriptor ");
+        FUSB_INFO("Failed to fetch hub descriptor.");
         return FXHCI_CC_COMMUNICATION_ERROR;
     }
 
@@ -350,26 +376,38 @@ static int FXhciFinishHubConfig(FUsbDev *const dev, FXhciInputCtx *const ic)
 static size_t FXhciBoundInterval(const FUsbEndpoint *const ep)
 {
     if ((ep->dev->speed == FUSB_LOW_SPEED &&
-            (ep->type == FUSB_ISOCHRONOUS_EP ||
-             ep->type == FUSB_INTERRUPT_EP)) ||
-            (ep->dev->speed == FUSB_FULL_SPEED &&
-             ep->type == FUSB_INTERRUPT_EP))
+         (ep->type == FUSB_ISOCHRONOUS_EP ||
+          ep->type == FUSB_INTERRUPT_EP)) ||
+        (ep->dev->speed == FUSB_FULL_SPEED &&
+         ep->type == FUSB_INTERRUPT_EP))
     {
         if (ep->interval < 3)
+        {
             return 3;
+        }
         else if (ep->interval > 11)
+        {
             return 11;
+        }
         else
+        {
             return ep->interval;
+        }
     }
     else
     {
         if (ep->interval < 0)
+        {
             return 0;
+        }
         else if (ep->interval > 15)
+        {
             return 15;
+        }
         else
+        {
             return ep->interval;
+        }
     }
 }
 
@@ -379,10 +417,12 @@ static int FXhciFinishEpConfig(const FUsbEndpoint *const ep, FXhciInputCtx *cons
     FASSERT(xhci);
     FUsb *instance = xhci->usb;
     const int ep_id = FXhciEpId(ep);
-    FUSB_INFO("ep_id: %d ", ep_id);
+    FUSB_INFO("ep_id: %d.", ep_id);
 
     if (ep_id <= 1 || 32 <= ep_id)
+    {
         return FXHCI_CC_DRIVER_ERROR;
+    }
 
     FXhciTransRing *const tr = FUSB_ALLOCATE(instance, sizeof(*tr), FUSB_DEFAULT_ALIGN);
     if (NULL != tr)
@@ -394,7 +434,7 @@ static int FXhciFinishEpConfig(const FUsbEndpoint *const ep, FXhciInputCtx *cons
     if ((NULL == tr) || (NULL == tr->ring))
     {
         FUSB_FREE(instance, tr);
-        FUSB_ERROR("Out of memory ");
+        FUSB_ERROR("Out of memory.");
         return FXHCI_CC_OUT_OF_MEMORY;
     }
 
@@ -403,11 +443,13 @@ static int FXhciFinishEpConfig(const FUsbEndpoint *const ep, FXhciInputCtx *cons
 
     *ic->add |= (1 << ep_id);
     if ((int)FXHCI_SC_GET(CTXENT, ic->dev.slot) < ep_id)
+    {
         FXHCI_SC_SET(CTXENT, ic->dev.slot, ep_id);
+    }
 
     FXhciEpCtx *const epctx = ic->dev.ep[ep_id];
 
-    FUSB_DEBUG("Filling epctx (@%p) ", epctx);
+    FUSB_DEBUG("Filling epctx (@%p).", epctx);
     epctx->tr_dq_low = (uintptr)(tr->ring);
     epctx->tr_dq_high = 0;
 
@@ -420,16 +462,16 @@ static int FXhciFinishEpConfig(const FUsbEndpoint *const ep, FXhciInputCtx *cons
     size_t avrtrb;
     switch (ep->type)
     {
-    case FUSB_BULK_EP:
-    case FUSB_ISOCHRONOUS_EP:
-        avrtrb = 3 * 1024;
-        break;
-    case FUSB_INTERRUPT_EP:
-        avrtrb = 1024;
-        break;
-    default:
-        avrtrb = 8;
-        break;
+        case FUSB_BULK_EP:
+        case FUSB_ISOCHRONOUS_EP:
+            avrtrb = 3 * 1024;
+            break;
+        case FUSB_INTERRUPT_EP:
+            avrtrb = 1024;
+            break;
+        default:
+            avrtrb = 8;
+            break;
     }
     FXHCI_EC_SET(AVRTRB, epctx, avrtrb);
     FXHCI_EC_SET(MXESIT, epctx, FXHCI_EC_GET(MPS, epctx) * FXHCI_EC_GET(MBS, epctx));
@@ -457,7 +499,7 @@ FXhciTransCode FXhciFinishDevConfig(FUsbDev *const dev)
     FXhciInputCtx *const ic = FXhciMakeInputCtx(xhci, FXhciGetCtxSize(&xhci->mmio));
     if (!ic)
     {
-        FUSB_INFO("Out of memory ");
+        FUSB_INFO("Out of memory.");
         return FXHCI_CC_OUT_OF_MEMORY;
     }
 
@@ -474,14 +516,18 @@ FXhciTransCode FXhciFinishDevConfig(FUsbDev *const dev)
     {
         ret = FXhciFinishHubConfig(dev, ic);
         if (ret)
+        {
             goto _free_return;
+        }
     }
 
     for (i = 1; i < dev->num_endp; ++i)
     {
         ret = FXhciFinishEpConfig(&dev->endpoints[i], ic);
         if (ret)
+        {
             goto _free_ep_ctx_return;
+        }
     }
 
     const int config_id = dev->configuration->bConfigurationValue;
@@ -496,13 +542,13 @@ FXhciTransCode FXhciFinishDevConfig(FUsbDev *const dev)
 
     if (cc != FXHCI_CC_SUCCESS)
     {
-        FUSB_INFO("Configure endpoint failed: %d ", cc);
+        FUSB_INFO("Configure endpoint failed: %d.", cc);
         ret = FXHCI_CC_CONTROLLER_ERROR;
         goto _free_ep_ctx_return;
     }
     else
     {
-        FUSB_INFO("Endpoints configured ");
+        FUSB_INFO("Endpoints configured.");
     }
 
     goto _free_return;
@@ -540,7 +586,9 @@ void FXhciDestoryDev(FUsbHc *const controller, const int slot_id)
     FUsb *instance = xhci->usb;
 
     if (slot_id <= 0 || slot_id > xhci->max_slots_en)
+    {
         return;
+    }
 
     FXhciInputCtx *const ic = FXhciMakeInputCtx(xhci, FXhciGetCtxSize(&xhci->mmio));
     if (NULL == ic)
@@ -565,11 +613,15 @@ void FXhciDestoryDev(FUsbHc *const controller, const int slot_id)
     }
 
     if (cc != FXHCI_CC_SUCCESS)
-        FUSB_INFO("Failed to quiesce slot %d: %d ", slot_id, cc);
+    {
+        FUSB_INFO("Failed to quiesce slot %d: %d.", slot_id, cc);
+    }
 
     cc = FXhciCmdStopEp(xhci, slot_id, FXHCI_EP0_ID);
     if (cc != FXHCI_CC_SUCCESS)
-        FUSB_INFO("Failed to stop EP0 on slot %d: %d ", slot_id, cc);
+    {
+        FUSB_INFO("Failed to stop EP0 on slot %d: %d.", slot_id, cc);
+    }
 
     int i;
     FXhciDevInfo *const di = &xhci->dev[slot_id];
@@ -590,7 +642,7 @@ void FXhciDestoryDev(FUsbHc *const controller, const int slot_id)
         di->ctx.raw = NULL;
     }
 
-    FUSB_INFO("Stopped slot %d, but not disabling it yet. ", slot_id);
+    FUSB_INFO("Stopped slot %d, but not disabling it yet.", slot_id);
     di->transfer_rings[1] = NULL;
 
     return;
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_evt.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_evt.c
index cfa984ed6a6..0995b6eeef1 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_evt.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_evt.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fsleep.h"
@@ -43,7 +43,9 @@ void FXhciResetEvtRing(FXhciEvtRing *const er)
 {
     int i;
     for (i = 0; i < FXHCI_EVENT_RING_SIZE; ++i)
+    {
         er->ring[i].control &= ~FXHCI_TRB_CYCLE;
+    }
     er->cur = er->ring;
     er->last = er->ring + FXHCI_EVENT_RING_SIZE;
     er->ccs = 1;
@@ -59,7 +61,7 @@ void FXhciUpdateEvtDQ(FXhci *const xhci)
 {
     if (xhci->er.adv)
     {
-        FUSB_DEBUG("Updating dq ptr: @0x%lx -> %p",
+        FUSB_DEBUG("Updating dq ptr: @0x%lx -> %p.",
                    FXhciReadRt64(&xhci->mmio, 0, FXHCI_REG_RT_IR_ERDP),
                    xhci->er.cur);
         FXhciWriteRt64(&xhci->mmio, 0, FXHCI_REG_RT_IR_ERDP, FXHCI_REG_RT_IR_ERDP_MASK & ((u64)(uintptr)xhci->er.cur));
@@ -73,7 +75,7 @@ void FXhciAdvanceEvtRing(FXhci *const xhci)
     xhci->er.adv = 1;
     if (xhci->er.cur == xhci->er.last)
     {
-        FUSB_DEBUG("Roll over in event ring ");
+        FUSB_DEBUG("Roll over in event ring.");
         xhci->er.cur = xhci->er.ring;
         xhci->er.ccs ^= 1;
         FXhciUpdateEvtDQ(xhci);
@@ -91,7 +93,7 @@ static void FXhciHandleTransferEvt(FXhci *const xhci)
     FXhciIntrQ *intrq;
 
     if (id && id <= xhci->max_slots_en &&
-            (intrq = xhci->dev[id].interrupt_queues[ep]))
+        (intrq = xhci->dev[id].interrupt_queues[ep]))
     {
         /* It's a running interrupt endpoint */
         intrq->ready = (void *)(uintptr)(ev->ptr_low);
@@ -102,7 +104,7 @@ static void FXhciHandleTransferEvt(FXhci *const xhci)
         }
         else
         {
-            FUSB_INFO("Interrupt Transfer failed: %d ", cc);
+            FUSB_INFO("Interrupt transfer failed: %d.", cc);
             FXHCI_TRB_SET(TL, intrq->ready, 0); /* Transfer Length */
         }
     }
@@ -146,22 +148,22 @@ static void FXhciHandleHostCtrlEvt(FXhci *const xhci)
     const FXhciTransCode cc = FXHCI_TRB_GET(CC, ev);
     switch (cc)
     {
-    case FXHCI_CC_EVENT_RING_FULL_ERROR:
-        FUSB_INFO("Event ring full! (@%p) ", xhci->er.cur);
-        /*
-         * If we get here, we have processed the whole queue:
-         * xHC pushes this event, when it sees the ring full,
-         * full of other events.
-         * IMO it's save and necessary to update the dequeue
-         * pointer here.
-         */
-        FXhciAdvanceEvtRing(xhci);
-        FXhciUpdateEvtDQ(xhci);
-        break;
-    default:
-        FUSB_INFO("Warning: Spurious host controller event: %d ", cc);
-        FXhciAdvanceEvtRing(xhci);
-        break;
+        case FXHCI_CC_EVENT_RING_FULL_ERROR:
+            FUSB_INFO("Event ring full! (@%p).", xhci->er.cur);
+            /*
+             * If we get here, we have processed the whole queue:
+             * xHC pushes this event, when it sees the ring full,
+             * full of other events.
+             * IMO it's save and necessary to update the dequeue
+             * pointer here.
+             */
+            FXhciAdvanceEvtRing(xhci);
+            FXhciUpdateEvtDQ(xhci);
+            break;
+        default:
+            FUSB_INFO("Warning: spurious host controller event: %d.", cc);
+            FXhciAdvanceEvtRing(xhci);
+            break;
     }
 }
 
@@ -178,35 +180,37 @@ static void FXhciHandleEvt(FXhci *const xhci)
     const int trb_type = FXHCI_TRB_GET(TT, ev);
     switch (trb_type)
     {
-    /* Either pass along the event or advance event ring */
-    case FXHCI_TRB_EV_TRANSFER:
-        FXhciHandleTransferEvt(xhci);
-        break;
-    case FXHCI_TRB_EV_CMD_CMPL:
-        FXhciHandleCmdCompletionEvt(xhci);
-        break;
-    case FXHCI_TRB_EV_PORTSC:
-        FUSB_INFO("Port Status Change Event for %d: %d ",
-                  FXHCI_TRB_GET(PORT, ev), FXHCI_TRB_GET(CC, ev));
-        /* We ignore the event as we look for the PORTSC
-           registers instead, at a time when it suits _us_. */
-        FXhciAdvanceEvtRing(xhci);
-        break;
-    case FXHCI_TRB_EV_HOST:
-        FXhciHandleHostCtrlEvt(xhci);
-        break;
-    default:
-        FUSB_INFO("Warning: Spurious event: %d, Completion Code: %d ",
-                  trb_type, FXHCI_TRB_GET(CC, ev));
-        FXhciAdvanceEvtRing(xhci);
-        break;
+        /* Either pass along the event or advance event ring */
+        case FXHCI_TRB_EV_TRANSFER:
+            FXhciHandleTransferEvt(xhci);
+            break;
+        case FXHCI_TRB_EV_CMD_CMPL:
+            FXhciHandleCmdCompletionEvt(xhci);
+            break;
+        case FXHCI_TRB_EV_PORTSC:
+            FUSB_INFO("Port status change event for %d: %d. ",
+                      FXHCI_TRB_GET(PORT, ev), FXHCI_TRB_GET(CC, ev));
+            /* We ignore the event as we look for the PORTSC
+               registers instead, at a time when it suits _us_. */
+            FXhciAdvanceEvtRing(xhci);
+            break;
+        case FXHCI_TRB_EV_HOST:
+            FXhciHandleHostCtrlEvt(xhci);
+            break;
+        default:
+            FUSB_INFO("Warning: spurious event: %d, completion code: %d.",
+                      trb_type, FXHCI_TRB_GET(CC, ev));
+            FXhciAdvanceEvtRing(xhci);
+            break;
     }
 }
 
 void FXhciHandleEvts(FXhci *const xhci)
 {
     while (FXhciEvtReady(&xhci->er))
+    {
         FXhciHandleEvt(xhci);
+    }
 
     FXhciUpdateEvtDQ(xhci);
     return;
@@ -230,7 +234,9 @@ static unsigned long FXhciWaitForEvtType(FXhci *const xhci,
     while (FXhciWaitForEvt(&xhci->er, timeout_us))
     {
         if (FXHCI_TRB_GET(TT, xhci->er.cur) == (unsigned int)trb_type)
+        {
             break;
+        }
 
         FXhciHandleEvt(xhci);
     }
@@ -265,7 +271,7 @@ FXhciTransCode FXhciWaitForCmdAborted(FXhci *const xhci, const FXhciTrb *const a
     while (FXhciWaitForEvtType(xhci, FXHCI_TRB_EV_CMD_CMPL, &timeout_us))
     {
         if ((xhci->er.cur->ptr_low == (uintptr)(address)) &&
-                (xhci->er.cur->ptr_high == 0))
+            (xhci->er.cur->ptr_high == 0))
         {
             cc = FXHCI_TRB_GET(CC, xhci->er.cur);
             FXhciAdvanceEvtRing(xhci);
@@ -276,8 +282,7 @@ FXhciTransCode FXhciWaitForCmdAborted(FXhci *const xhci, const FXhciTrb *const a
     }
     if (timeout_us == 0)
     {
-        FUSB_INFO("Warning: Timed out waiting for "
-                  "COMMAND_ABORTED or COMMAND_RING_STOPPED. ");
+        FUSB_INFO("Warning: timeout waiting COMMAND_ABORTED or COMMAND_RING_STOPPED.");
         goto update_and_return;
     }
     if (cc == FXHCI_CC_COMMAND_RING_STOPPED)
@@ -299,8 +304,7 @@ FXhciTransCode FXhciWaitForCmdAborted(FXhci *const xhci, const FXhciTrb *const a
         FXhciHandleCmdCompletionEvt(xhci);
     }
     if (timeout_us == 0)
-        FUSB_INFO("Warning: Timed out "
-                  "waiting for COMMAND_RING_STOPPED. ");
+        FUSB_INFO("Warning: timeout waiting for COMMAND_RING_STOPPED.");
 
 update_and_return:
     FXhciUpdateEvtDQ(xhci);
@@ -321,7 +325,7 @@ FXhciTransCode FXhciWaitForCmdDone(FXhci *const xhci,
     while (FXhciWaitForEvtType(xhci, FXHCI_TRB_EV_CMD_CMPL, &timeout_us))
     {
         if ((xhci->er.cur->ptr_low == (uintptr)(address)) &&
-                (xhci->er.cur->ptr_high == 0))
+            (xhci->er.cur->ptr_high == 0))
         {
             cc = FXHCI_TRB_GET(CC, xhci->er.cur);
             break;
@@ -332,7 +336,7 @@ FXhciTransCode FXhciWaitForCmdDone(FXhci *const xhci,
 
     if (!timeout_us)
     {
-        FUSB_INFO("Warning: Timed out waiting for FXHCI_TRB_EV_CMD_CMPL. ");
+        FUSB_INFO("Warning: timeout waiting for FXHCI_TRB_EV_CMD_CMPL.");
     }
     else if (clear_event)
     {
@@ -352,11 +356,13 @@ FXhciTransCode FXhciWaitForTransfer(FXhci *const xhci, const int slot_id, const
     while (FXhciWaitForEvtType(xhci, FXHCI_TRB_EV_TRANSFER, &timeout_us))
     {
         if (FXHCI_TRB_GET(ID, xhci->er.cur) == (unsigned int)slot_id &&
-                FXHCI_TRB_GET(EP, xhci->er.cur) == (unsigned int)ep_id)
+            FXHCI_TRB_GET(EP, xhci->er.cur) == (unsigned int)ep_id)
         {
             ret = -FXHCI_TRB_GET(CC, xhci->er.cur);
             if (ret == -FXHCI_CC_SUCCESS || ret == -FXHCI_CC_SHORT_PACKET)
+            {
                 ret = FXHCI_TRB_GET(EVTL, xhci->er.cur);
+            }
             FXhciAdvanceEvtRing(xhci);
             break;
         }
@@ -364,7 +370,9 @@ FXhciTransCode FXhciWaitForTransfer(FXhci *const xhci, const int slot_id, const
         FXhciHandleTransferEvt(xhci);
     }
     if (!timeout_us)
-        FUSB_INFO("Warning: Timed out waiting for FXHCI_TRB_EV_TRANSFER. ");
+    {
+        FUSB_INFO("Warning: timeout waiting for FXHCI_TRB_EV_TRANSFER. ");
+    }
 
     FXhciUpdateEvtDQ(xhci);
     return ret;
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.c
index 3af4ad49681..aa06b6e48f9 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 /***************************** Include Files *********************************/
@@ -87,77 +87,81 @@ static void FXhciParseExtCap(FXhciMMIO *mmio, const uintptr offset, const u32 ca
 
     switch (cap_id)
     {
-    case FXHCI_EXT_CAP_ID_USB_LEGACY_SUPPORT:
-        reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBLEGSUP_OFFSET);
-        FUSB_INFO(" BIOS owned %d OS owned %d",
-                  FXHCI_USBLEGSUP_BIOS_OWNED_SEMAPHORE & reg_val,
-                  FXHCI_USBLEGSUP_OS_OWNED_SEMAPHORE & reg_val);
-
-        reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBLEGCTLSTS_OFFSET);
-        FUSB_INFO(" SMI ctrl/status 0x%x", reg_val);
-        break;
-    case FXHCI_EXT_CAP_ID_SUPPORT_PROTOCOL:
-        reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCFDEF_OFFSET);
-        FUSB_INFO(" Name: %c%c%c%c",
-                  *((char *)&reg_val),  *((char *)&reg_val + 1),
-                  *((char *)&reg_val + 2),  *((char *)&reg_val + 3));
-
-        reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCF_OFFSET);
-        major_ver = FXHCI_USBSPCF_MAJOR_REVERSION_GET(reg_val);
-        minor_ver = FXHCI_USBSPCF_MINOR_REVERSION_GET(reg_val);
-        FUSB_INFO(" Version: %d.%d", major_ver, minor_ver);
-
-        reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCFDEF2_OFFSET);
-        FUSB_INFO(" Compatible ports: [%d-%d]",
-                  FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val),
-                  FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1);
-
-        if (FXHCI_MAJOR_REVERSION_USB2 == major_ver)
-        {
-            mmio->usb2_ports.port_beg = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val);
-            mmio->usb2_ports.port_end = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1;
-
-            FUSB_INFO(" High-speed only: %d, Integrated hub: %d, Hardware LMP: %d",
-                      FXHCI_USBSPCFDEF2_USB2_HIGH_SPEED_ONLY & reg_val,
-                      FXHCI_USBSPCFDEF2_USB2_INTERGRATED_HUB & reg_val,
-                      FXHCI_USBSPCFDEF2_USB2_HW_LMP_CAP & reg_val);
-        }
-        else if (FXHCI_MAJOR_REVERSION_USB3 == major_ver)
-        {
-            mmio->usb3_ports.port_beg = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val);
-            mmio->usb3_ports.port_end = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1;
-        }
-
-        psic = FXHCI_USBSPCFDEF2_PROTOCOL_SPEED_ID_CNT_GET(reg_val);
-        FUSB_INFO(" PSIC: 0x%x", psic);
-
-        if (0 != psic)
-        {
-            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_PROTOCOL_SPEED_ID_OFFSET(psic));
-
-            FUSB_INFO(" Protocol speed-id: %d^%d",
-                      FXHCI_PROTOCOL_SPEED_ID_VALUE_GET(reg_val),
-                      FXHCI_PROTOCOL_SPEED_ID_EXPONENT_GET(reg_val));
-            FUSB_INFO(" PSI type: %d, PSI full-duplex: %d,  Mantissa: 0x%x",
-                      FXHCI_PROTOCOL_SPEED_ID_PSI_TYPE_GET(reg_val),
-                      (FXHCI_PROTOCOL_SPEED_ID_PSI_FULL_DUPLEX & reg_val == FXHCI_PROTOCOL_SPEED_ID_PSI_FULL_DUPLEX),
-                      FXHCI_PROTOCOL_SPEED_ID_MANTISSA_GET(reg_val));
-        }
-        else
-        {
-            if (FXHCI_MAJOR_REVERSION_USB3 == major_ver)
-                FUSB_INFO("For USB3, only the default SuperSpeed bit rate is supported !!!");
-            else if (FXHCI_MAJOR_REVERSION_USB2 == major_ver)
-                FUSB_INFO("For USB2, default Full-speed, Low-speed and High-speed bit rate supported !!!");
-        }
+        case FXHCI_EXT_CAP_ID_USB_LEGACY_SUPPORT:
+            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBLEGSUP_OFFSET);
+            FUSB_INFO(" BIOS owned %d OS owned %d",
+                      FXHCI_USBLEGSUP_BIOS_OWNED_SEMAPHORE & reg_val,
+                      FXHCI_USBLEGSUP_OS_OWNED_SEMAPHORE & reg_val);
+
+            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBLEGCTLSTS_OFFSET);
+            FUSB_INFO(" SMI ctrl/status 0x%x", reg_val);
+            break;
+        case FXHCI_EXT_CAP_ID_SUPPORT_PROTOCOL:
+            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCFDEF_OFFSET);
+            FUSB_INFO(" Name: %c%c%c%c",
+                      *((char *)&reg_val),  *((char *)&reg_val + 1),
+                      *((char *)&reg_val + 2),  *((char *)&reg_val + 3));
+
+            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCF_OFFSET);
+            major_ver = FXHCI_USBSPCF_MAJOR_REVERSION_GET(reg_val);
+            minor_ver = FXHCI_USBSPCF_MINOR_REVERSION_GET(reg_val);
+            FUSB_INFO(" Version: %d.%d", major_ver, minor_ver);
+
+            reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_EXT_CAP_USBSPCFDEF2_OFFSET);
+            FUSB_INFO(" Compatible ports: [%d-%d]",
+                      FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val),
+                      FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1);
+
+            if (FXHCI_MAJOR_REVERSION_USB2 == major_ver)
+            {
+                mmio->usb2_ports.port_beg = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val);
+                mmio->usb2_ports.port_end = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1;
+
+                FUSB_INFO(" High-speed only: %d, Integrated hub: %d, Hardware LMP: %d",
+                          FXHCI_USBSPCFDEF2_USB2_HIGH_SPEED_ONLY & reg_val,
+                          FXHCI_USBSPCFDEF2_USB2_INTERGRATED_HUB & reg_val,
+                          FXHCI_USBSPCFDEF2_USB2_HW_LMP_CAP & reg_val);
+            }
+            else if (FXHCI_MAJOR_REVERSION_USB3 == major_ver)
+            {
+                mmio->usb3_ports.port_beg = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val);
+                mmio->usb3_ports.port_end = FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_OFF_GET(reg_val) + FXHCI_USBSPCFDEF2_COMPATIBLE_PORT_CNT_GET(reg_val) - 1;
+            }
+
+            psic = FXHCI_USBSPCFDEF2_PROTOCOL_SPEED_ID_CNT_GET(reg_val);
+            FUSB_INFO(" PSIC: 0x%x", psic);
+
+            if (0 != psic)
+            {
+                reg_val = FXhciReadExtCap32(mmio, offset + FXHCI_REG_PROTOCOL_SPEED_ID_OFFSET(psic));
+
+                FUSB_INFO(" Protocol speed-id: %d^%d",
+                          FXHCI_PROTOCOL_SPEED_ID_VALUE_GET(reg_val),
+                          FXHCI_PROTOCOL_SPEED_ID_EXPONENT_GET(reg_val));
+                FUSB_INFO(" PSI type: %d, PSI full-duplex: %d,  Mantissa: 0x%x",
+                          FXHCI_PROTOCOL_SPEED_ID_PSI_TYPE_GET(reg_val),
+                          (FXHCI_PROTOCOL_SPEED_ID_PSI_FULL_DUPLEX & reg_val == FXHCI_PROTOCOL_SPEED_ID_PSI_FULL_DUPLEX),
+                          FXHCI_PROTOCOL_SPEED_ID_MANTISSA_GET(reg_val));
+            }
+            else
+            {
+                if (FXHCI_MAJOR_REVERSION_USB3 == major_ver)
+                {
+                    FUSB_INFO("For USB3, only the default super speed bit rate is supported !!!");
+                }
+                else if (FXHCI_MAJOR_REVERSION_USB2 == major_ver)
+                {
+                    FUSB_INFO("For USB2, default full speed, low speed and high speed bit rate supported !!!");
+                }
+            }
 
-        break;
-    case FXHCI_EXT_CAP_ID_USB_DEBUG_CAPABILITY:
+            break;
+        case FXHCI_EXT_CAP_ID_USB_DEBUG_CAPABILITY:
 
-        break;
-    default:
-        FUSB_WARN("Unhandled extend capabilities %d", cap_id);
-        break;
+            break;
+        default:
+            FUSB_WARN("Unhandled extend capabilities %d", cap_id);
+            break;
     }
 
     return;
@@ -181,7 +185,7 @@ void FXhciListExtCap(FXhciMMIO *mmio)
         cap_id = FXHCI_REG_EXT_CAP_CAP_ID_GET(reg_val);
         FXhciParseExtCap(mmio, ext_cap_offset, cap_id);
 
-        FUSB_INFO("==== Capability ID: %d, Next Capability Pointer: 0x%x",
+        FUSB_INFO("Capability ID: %d, Next Capability Pointer: 0x%x",
                   cap_id, next_ext_cap_offset);
         ext_cap_offset += next_ext_cap_offset;
     }
@@ -210,7 +214,7 @@ FError FXhciWaitOper32(FXhciMMIO *mmio, u32 offset, u32 mask, u32 exp_val, u32 t
 
     if (FUSB_SUCCESS != ret)
     {
-        FUSB_ERROR("wait status 0x%x timeout, current 0x%x, tick: %ld", exp_val, mask, tick);
+        FUSB_ERROR("Waitting status 0x%x timeout, current 0x%x, tick: %ld", exp_val, mask, tick);
     }
 
     return ret;
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.h b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.h
index 6c780e6a965..c3e3605014f 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_hw.h
@@ -19,22 +19,21 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_USB_FXHCI_HW_H
-#define  DRIVERS_USB_FXHCI_HW_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FXHCI_HW_H
+#define  FXHCI_HW_H
 
 /***************************** Include Files *********************************/
 #include "fio.h"
 #include "fassert.h"
 #include "fkernel.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 /************************** Constant Definitions *****************************/
 /** @name Register Map
@@ -244,8 +243,8 @@ enum
 #define FXHCI_REG_OP_PORTS_PORTSC_DR  (1 << 30)      /* Device Removable, 0: Device is removable. 1:  Device is non-removable */
 #define FXHCI_REG_OP_PORTS_PORTSC_WPR (1 << 31)      /* Warm Port Reset 1: follow Warm Reset sequence */
 #define FXHCI_REG_OP_PORTS_PORTSC_RW_MASK (FXHCI_REG_OP_PORTS_PORTSC_PR | FXHCI_REG_OP_PORTS_PORTSC_PLS_MASK | FXHCI_REG_OP_PORTS_PORTSC_PP \
-                                        | FXHCI_REG_OP_PORTS_PORTSC_PIC_MASK | FXHCI_REG_OP_PORTS_PORTSC_LWS | FXHCI_REG_OP_PORTS_PORTSC_WCE \
-                                        | FXHCI_REG_OP_PORTS_PORTSC_WDE | FXHCI_REG_OP_PORTS_PORTSC_WOE)
+        | FXHCI_REG_OP_PORTS_PORTSC_PIC_MASK | FXHCI_REG_OP_PORTS_PORTSC_LWS | FXHCI_REG_OP_PORTS_PORTSC_WCE \
+        | FXHCI_REG_OP_PORTS_PORTSC_WDE | FXHCI_REG_OP_PORTS_PORTSC_WOE)
 
 /***************** Host Controller Runtime Registers ***********************/
 
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_private.h b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_private.h
index 818b5f25203..e181a7b999f 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_private.h
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_private.h
@@ -19,22 +19,22 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
-#ifndef  DRIVERS_USB_FXHCI_PRIVATE_H
-#define  DRIVERS_USB_FXHCI_PRIVATE_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef  FXHCI_PRIVATE_H
+#define  FXHCI_PRIVATE_H
 
 /***************************** Include Files *********************************/
 #include "fusb_private.h"
 #include "fxhci_hw.h"
 #include "fxhci.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 /************************** Constant Definitions *****************************/
 typedef enum
 {
@@ -284,10 +284,10 @@ typedef struct
 #define FXHCI_TRB_ID_LEN        8
 #define FXHCI_TRB_MASK(tok)     FXHCI_MASK(FXHCI_TRB_##tok##_START, FXHCI_TRB_##tok##_LEN)
 #define FXHCI_TRB_GET(tok, trb) (((trb)->FXHCI_TRB_##tok##_FIELD & FXHCI_TRB_MASK(tok)) \
-                                >> FXHCI_TRB_##tok##_START)
+                                 >> FXHCI_TRB_##tok##_START)
 #define FXHCI_TRB_SET(tok, trb, to) (trb)->FXHCI_TRB_##tok##_FIELD = \
-                                    (((trb)->FXHCI_TRB_##tok##_FIELD & ~FXHCI_TRB_MASK(tok)) | \
-                                    (((to) << FXHCI_TRB_##tok##_START) & FXHCI_TRB_MASK(tok)))
+        (((trb)->FXHCI_TRB_##tok##_FIELD & ~FXHCI_TRB_MASK(tok)) | \
+         (((to) << FXHCI_TRB_##tok##_START) & FXHCI_TRB_MASK(tok)))
 #define FXHCI_TRB_DUMP(dumper, tok, trb)    dumper(" "#tok"\t0x%04x ", FXHCI_TRB_GET(tok, trb))
 
 #define FXHCI_TRB_CYCLE     (1 << 0)
@@ -331,10 +331,10 @@ typedef struct
 #define FXHCI_SC_STATE_LEN          5
 #define FXHCI_SC_MASK(tok)          FXHCI_MASK(FXHCI_SC_##tok##_START, FXHCI_SC_##tok##_LEN)
 #define FXHCI_SC_GET(tok, sc)       (((sc)->FXHCI_SC_##tok##_FIELD & FXHCI_SC_MASK(tok)) \
-                                    >> FXHCI_SC_##tok##_START)
+                                     >> FXHCI_SC_##tok##_START)
 #define FXHCI_SC_SET(tok, sc, to)   (sc)->FXHCI_SC_##tok##_FIELD = \
-                                    (((sc)->FXHCI_SC_##tok##_FIELD & ~FXHCI_SC_MASK(tok)) | \
-                                    (((to) << FXHCI_SC_##tok##_START) & FXHCI_SC_MASK(tok)))
+        (((sc)->FXHCI_SC_##tok##_FIELD & ~FXHCI_SC_MASK(tok)) | \
+         (((to) << FXHCI_SC_##tok##_START) & FXHCI_SC_MASK(tok)))
 #define FXHCI_SC_DUMP(dumper, tok, sc)  dumper(" "#tok"\t0x%04x ", FXHCI_SC_GET(tok, sc))
 
 /* shortcut to access endpoint context */
@@ -374,10 +374,10 @@ typedef struct
 
 #define FXHCI_EC_MASK(tok)          FXHCI_MASK(FXHCI_EC_##tok##_START, FXHCI_EC_##tok##_LEN)
 #define FXHCI_EC_GET(tok, ec)       (((ec)->FXHCI_EC_##tok##_FIELD & FXHCI_EC_MASK(tok)) \
-                                    >> FXHCI_EC_##tok##_START)
+                                     >> FXHCI_EC_##tok##_START)
 #define FXHCI_EC_SET(tok, ec, to)   (ec)->FXHCI_EC_##tok##_FIELD = \
-                                    (((ec)->FXHCI_EC_##tok##_FIELD & ~FXHCI_EC_MASK(tok)) | \
-                                    (((to) << FXHCI_EC_##tok##_START) & FXHCI_EC_MASK(tok)))
+        (((ec)->FXHCI_EC_##tok##_FIELD & ~FXHCI_EC_MASK(tok)) | \
+         (((to) << FXHCI_EC_##tok##_START) & FXHCI_EC_MASK(tok)))
 #define FXHCI_EC_DUMP(dumper, tok, ec)  dumper(" "#tok"\t0x%04x ", FXHCI_EC_GET(tok, ec))
 
 /* the current operational state of the endpoint. */
diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_roothub.c b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_roothub.c
index 56619be4982..83b545be0a9 100644
--- a/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_roothub.c
+++ b/bsp/phytium/libraries/standalone/drivers/usb/fxhci/fxhci_roothub.c
@@ -19,7 +19,7 @@
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   Zhugengyu  2022/2/7    init commit
+ * 1.0   zhugengyu  2022/2/7    init commit
  */
 
 #include "fdebug.h"
@@ -122,7 +122,7 @@ static int FXhciRootHubResetPort(FUsbDev *const dev, const int port)
     if (FUsbGenericHubWaitForPort(dev, port, 0, FXhciRootHubPortInReset,
                                   150, 1000) == 0)
     {
-        FUSB_INFO("xhci_rh: Reset timed out at port %d ", port);
+        FUSB_INFO("Xhci root hub: Reset timed out at port %d ", port);
     }
     else
     {
@@ -189,5 +189,5 @@ void FXhciRootHubInit(FUsbDev *dev)
 
     FUsbGenericHubInit(dev, num_ports, &FXHCI_ROOTHUB_OPS);
 
-    FUSB_INFO("xHCI: root hub init done ");
+    FUSB_INFO("Xhci: root hub init done. ");
 }
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/Kconfig b/bsp/phytium/libraries/standalone/drivers/watchdog/Kconfig
index 5d2860d27b3..5da173ab680 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/Kconfig
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/Kconfig
@@ -4,7 +4,7 @@ menu "FWDT Configuration"
         bool
         prompt "Use FWDT"
         default n
-
+        
 endmenu
 
 
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c
index 68b0db3f157..0fc9c907fd9 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c
@@ -13,7 +13,7 @@
  * FilePath: fwdt.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-07-15 17:05:09
- * Description:  This files is for wdt ctrl function implementation.
+ * Description:  This file is for wdt ctrl function implementation.
  * Users can operate as a single stage watchdog or a two stages watchdog.
  * In the single stage mode, when the timeout is reached, your system will
  * be reset by WS1. The first signal (WS0) is ignored.
@@ -56,7 +56,7 @@
 #include "fwdt.h"
 #include "fwdt_hw.h"
 
-#define FWDT_DEBUG_TAG "WDT"
+#define FWDT_DEBUG_TAG "FWDT"
 #define FWDT_ERROR(format, ...)   FT_DEBUG_PRINT_E(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FWDT_WARN(format, ...)   FT_DEBUG_PRINT_W(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
 #define FWDT_INFO(format, ...) FT_DEBUG_PRINT_I(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
@@ -82,7 +82,7 @@ FError FWdtCfgInitialize(FWdtCtrl *pctrl, const FWdtConfig *input_config_p)
     */
     if (FT_COMPONENT_IS_READY == pctrl->is_ready)
     {
-        FWDT_WARN("device is already initialized!!!");
+        FWDT_WARN("Device is already initialized!!!");
     }
 
     /*Set default values and configuration data */
@@ -126,17 +126,17 @@ FError FWdtSetTimeout(FWdtCtrl *pctrl, u32 timeout)
     FASSERT(pctrl != NULL);
     if (pctrl->is_ready != FT_COMPONENT_IS_READY)
     {
-        FWDT_ERROR("device is not already!!!");
+        FWDT_ERROR("Device is not ready!!!");
         return FWDT_NOT_READY;
     }
     if (timeout > FWDT_MAX_TIMEOUT)
     {
-        FWDT_ERROR("timeout value is invalid");
+        FWDT_ERROR("Timeout value is invalid.");
         return FWDT_ERR_INVAL_PARM;
     }
     uintptr base_addr = pctrl->config.control_base_addr;
 
-    FWDT_WRITE_REG32(base_addr, FWDT_GWDT_WOR, (u32)(FWDT_CLK * timeout));
+    FWDT_WRITE_REG32(base_addr, FWDT_GWDT_WOR, (u32)(FWDT_CLK_FREQ_HZ * timeout));
 
     return FWDT_SUCCESS;
 }
@@ -156,7 +156,9 @@ u32 FWdtGetTimeleft(FWdtCtrl *pctrl)
 
     /* if the ws0 bit of register WCS is zero，indicates that there is one more timeout opportunity */
     if (!(FWdtReadWCS(base_addr) & FWDT_GWDT_WCS_WS0))
+    {
         timeleft += FWdtReadWOR(base_addr);
+    }
 
     u32 wcvh = (u32)FWdtReadWCVH(base_addr);
     u32 wcvl = (u32)FWdtReadWCVL(base_addr);
@@ -164,9 +166,9 @@ u32 FWdtGetTimeleft(FWdtCtrl *pctrl)
 
     timeleft += (wcv - GenericTimerRead());
 
-    // f_printk("------wcvh=%llx, wcvl=%llx, wcv=%llx, timeleft=%llx\n", wcvh, wcvl, wcv, timeleft);
+    FWDT_DEBUG("wcvh=%llx, wcvl=%llx, wcv=%llx, timeleft=%llx\n", wcvh, wcvl, wcv, timeleft);
 
-    do_div(timeleft, FWDT_CLK);
+    do_div(timeleft, FWDT_CLK_FREQ_HZ);
 
     return (u32)timeleft;
 }
@@ -182,7 +184,7 @@ FError FWdtRefresh(FWdtCtrl *pctrl)
     FASSERT(pctrl != NULL);
     if (pctrl->is_ready != FT_COMPONENT_IS_READY)
     {
-        FWDT_ERROR("device is not already!!!");
+        FWDT_ERROR("Device is not ready!!!");
         return FWDT_NOT_READY;
     }
     uintptr base_addr = pctrl->config.refresh_base_addr;
@@ -201,7 +203,7 @@ FError FWdtStart(FWdtCtrl *pctrl)
     FASSERT(pctrl != NULL);
     if (pctrl->is_ready != FT_COMPONENT_IS_READY)
     {
-        FWDT_ERROR("device is not already!!!");
+        FWDT_ERROR("Device is not ready!!!");
         return FWDT_NOT_READY;
     }
 
@@ -239,13 +241,13 @@ FError FWdtReadFWdtReadWIIDR(FWdtCtrl *pctrl, FWdtIdentifier *wdt_identify)
 
     if (pctrl->is_ready != FT_COMPONENT_IS_READY)
     {
-        FWDT_ERROR("device is not already!!!");
+        FWDT_ERROR("Device is not ready!!!");
         return FWDT_NOT_READY;
     }
 
     u32 reg_val = 0;
     uintptr base_addr = pctrl->config.refresh_base_addr;
-    reg_val =  FWDT_READ_REG32(base_addr, FWDT_GWDT_W_IIDR);
+    reg_val =  FWDT_READ_REG32(base_addr, FWDT_GWDT_W_IIR);
 
     wdt_identify->version = (u16)((reg_val & FWDT_VERSION_MASK) >> 16);
     wdt_identify->continuation_code = (u8)((reg_val & FWDT_CONTINUATION_CODE_MASK) >> 8);
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.h b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.h
index e1fcc103900..3710f1051b2 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.h
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.h
@@ -14,7 +14,7 @@
  * FilePath: fwdt.h
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:24:34
- * Description:  This files is for wdt ctrl function definition
+ * Description:  This file is for wdt ctrl function definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
@@ -23,13 +23,8 @@
  * 1.1   Wangxiaodong 2021/11/5    restruct
  */
 
-#ifndef BSP_DRIVERS_FWDT_H
-#define BSP_DRIVERS_FWDT_H
-
-#ifdef __cplusplus
-extern "C"
-{
-#endif
+#ifndef FWDT_H
+#define FWDT_H
 
 #include "ftypes.h"
 #include "fdebug.h"
@@ -37,6 +32,11 @@ extern "C"
 #include "fkernel.h"
 #include "fassert.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 #define FWDT_SUCCESS           FT_SUCCESS
 #define FWDT_ERR_INVAL_PARM    FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 1)
 #define FWDT_NOT_READY         FT_MAKE_ERRCODE(ErrModBsp, ErrBspWdt, 2)
@@ -58,8 +58,10 @@ typedef struct
     u32 instance_id;/* wdt id */
     uintptr refresh_base_addr;/* wdt refresh base addr */
     uintptr control_base_addr;/* wdt control base addr */
-    u32 irq_num;    /* wdt ir num */
+    u32 irq_num;    /* wdt irq num */
     u32 irq_prority;/* wdt irq priority */
+    u32 irq_twice_num;    /* wdt twice irq num */
+    u32 irq_twice_prority;/* wdt twice irq priority */
     const char *instance_name;/* instance name */
 } FWdtConfig; /* wdt config */
 
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_g.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_g.c
index 21bc05458b3..b1a16e0caf7 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_g.c
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_g.c
@@ -13,36 +13,115 @@
  *
  * FilePath: fwdt_g.c
  * Date: 2022-02-10 14:53:42
- * LastEditTime: 2022-02-18 09:22:49
- * Description:  This files is for static config of wdt ctrl
+ * LastEditTime: 2022-06-18 09:22:49
+ * Description:  This file is for static config of wdt device.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
  * 1.0   Wangxiaodong   2021/8/25   init
+ * 1.1   Wangxiaodong   2022/6/25   adapt to e2000
  */
 
 #include "fparameters.h"
 #include "fwdt.h"
 
 /* default configs of wdt ctrl */
-const FWdtConfig FWdtConfigTbl[FWDT_INSTANCE_NUM] =
+const FWdtConfig FWdtConfigTbl[FWDT_NUM] =
 {
+    [FWDT0_ID] =
     {
-        .instance_id = FWDT_INSTANCE_0,
-        .refresh_base_addr = FWDT0_REFRESH_BASE,
-        .control_base_addr = FWDT0_CONTROL_BASE,
-        .irq_num = FWDT0_INTR_IRQ,
+        .instance_id = FWDT0_ID,
+        .refresh_base_addr = FWDT0_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT0_REFRESH_BASE_ADDR),
+        .irq_num = FWDT0_IRQ_NUM,
         .irq_prority = 0,
+        #if defined(TARDIGRADE)
+        .irq_twice_num = FWDT0_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        #endif
         .instance_name = "WDT-0"
     },
-
+    [FWDT1_ID] =
     {
-        .instance_id = FWDT_INSTANCE_1,
-        .refresh_base_addr = FWDT1_REFRESH_BASE,
-        .control_base_addr = FWDT1_CONTROL_BASE,
-        .irq_num = FWDT1_INTR_IRQ,
+        .instance_id = FWDT1_ID,
+        .refresh_base_addr = FWDT1_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT1_REFRESH_BASE_ADDR),
+        .irq_num = FWDT1_IRQ_NUM,
         .irq_prority = 0,
+        #if defined(TARDIGRADE)
+        .irq_twice_num = FWDT1_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        #endif
         .instance_name = "WDT-1"
-    }
+    },
+
+    #if defined(TARDIGRADE)
+    [FWDT2_ID] =
+    {
+        .instance_id = FWDT2_ID,
+        .refresh_base_addr = FWDT2_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT2_REFRESH_BASE_ADDR),
+        .irq_num = FWDT2_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT2_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-2"
+    },
+    [FWDT3_ID] =
+    {
+        .instance_id = FWDT3_ID,
+        .refresh_base_addr = FWDT3_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT3_REFRESH_BASE_ADDR),
+        .irq_num = FWDT3_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT3_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-3"
+    },
+    [FWDT4_ID] =
+    {
+        .instance_id = FWDT4_ID,
+        .refresh_base_addr = FWDT4_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT4_REFRESH_BASE_ADDR),
+        .irq_num = FWDT4_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT4_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-4"
+    },
+    [FWDT5_ID] =
+    {
+        .instance_id = FWDT5_ID,
+        .refresh_base_addr = FWDT5_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT5_REFRESH_BASE_ADDR),
+        .irq_num = FWDT5_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT5_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-5"
+    },
+    [FWDT6_ID] =
+    {
+        .instance_id = FWDT6_ID,
+        .refresh_base_addr = FWDT6_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT6_REFRESH_BASE_ADDR),
+        .irq_num = FWDT6_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT6_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-6"
+    },
+    [FWDT7_ID] =
+    {
+        .instance_id = FWDT7_ID,
+        .refresh_base_addr = FWDT7_REFRESH_BASE_ADDR,
+        .control_base_addr = FWDT_CONTROL_BASE_ADDR(FWDT7_REFRESH_BASE_ADDR),
+        .irq_num = FWDT7_IRQ_NUM,
+        .irq_prority = 0,
+        .irq_twice_num = FWDT7_TWICE_IRQ_NUM,
+        .irq_twice_prority = 0,
+        .instance_name = "WDT-7"
+    },
+    #endif // TARDIGRADE
 };
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.c
index d81b945332c..d31383ef8ca 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.c
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.c
@@ -14,16 +14,19 @@
  * FilePath: fwdt_hw.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-18 09:23:08
- * Description:  This files is for wdt register function
+ * Description:  This file is for wdt register implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
 /***************************** Include Files *********************************/
-
+#include <stdio.h>
+#include "fparameters.h"
 #include "fwdt_hw.h"
+#include "fdebug.h"
 
 
 /************************** Constant Definitions *****************************/
@@ -35,3 +38,30 @@
 /***************** Macros (Inline Functions) Definitions *********************/
 
 /************************** Function Prototypes ******************************/
+
+#define FWDT_DEBUG_TAG "FWDT_HW"
+#define FWDT_ERROR(format, ...)   FT_DEBUG_PRINT_E(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FWDT_WARN(format, ...)   FT_DEBUG_PRINT_W(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FWDT_INFO(format, ...) FT_DEBUG_PRINT_I(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
+#define FWDT_DEBUG(format, ...) FT_DEBUG_PRINT_D(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
+
+/**
+ * @name: FWdtDump
+ * @msg: debug register value for wdt.
+ * @param {uintptr} base_addr, base address of FWDT controller
+ * @return {*}
+ */
+void FWdtDump(uintptr base_addr)
+{
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_WRR, FWDT_READ_REG32(base_addr, FWDT_GWDT_WRR));
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_W_IIR, FWDT_READ_REG32(base_addr, FWDT_GWDT_W_IIR));
+
+    base_addr = FWDT_CONTROL_BASE_ADDR(base_addr);
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_WCS, FWDT_READ_REG32(base_addr, FWDT_GWDT_WCS));
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_WOR, FWDT_READ_REG32(base_addr, FWDT_GWDT_WOR));
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_WCVL, FWDT_READ_REG32(base_addr, FWDT_GWDT_WCVL));
+	FWDT_DEBUG("Off[0x%x]: = 0x%08x\r\n", base_addr + FWDT_GWDT_WCVH, FWDT_READ_REG32(base_addr, FWDT_GWDT_WCVH));
+
+	FWDT_DEBUG("\r\n");
+   
+}
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.h b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.h
index ede7d813735..f1d7ab9821e 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.h
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_hw.h
@@ -14,29 +14,30 @@
  * FilePath: fwdt_hw.h
  * Date: 2021-08-25 10:27:42
  * LastEditTime: 2022-02-25 11:44:33
- * Description:  This files is for ctrl of watchdog timer functions
+ * Description:  This file is for wdt register definition.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
- * 1.0   wangxiaodong 2021/8/25   init
+ * 1.0   wangxiaodong  2022/4/15   init commit
  */
 
-#ifndef BSP_DRIVERS_FWDT_HW_H
-#define BSP_DRIVERS_FWDT_HW_H
+#ifndef FWDT_HW_H
+#define FWDT_HW_H
+
+#include "fkernel.h"
+#include "fio.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "fkernel.h"
-#include "fio.h"
-
 /* Watchdog register definitions */
 
 /* refresh frame */
 #define FWDT_GWDT_WRR       0x000
+#define FWDT_GWDT_W_IIR     0xfcc
 
 /* control frame */
 #define FWDT_GWDT_WCS       0x000  /* WCS register */
@@ -44,10 +45,6 @@ extern "C"
 #define FWDT_GWDT_WCVL      0x010
 #define FWDT_GWDT_WCVH      0x014
 
-/* refresh/control frame */
-#define FWDT_GWDT_W_IIDR    0xfcc
-#define FWDT_GWDT_IDR       0xfd0
-
 /* Watchdog Control and Status Register */
 #define FWDT_GWDT_WCS_WDT_EN    BIT(0)
 #define FWDT_GWDT_WCS_WS0       BIT(1)
@@ -124,6 +121,8 @@ static inline u32 FWdtReadWCS(uintptr addr)
     return FWDT_READ_REG32(addr, FWDT_GWDT_WCS);
 }
 
+void FWdtDump(uintptr base_addr);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_intr.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_intr.c
index 39972e27a03..b10a4cde2c9 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_intr.c
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_intr.c
@@ -14,9 +14,10 @@
  * FilePath: fwdt_intr.c
  * Date: 2021-11-05 10:01:59
  * LastEditTime: 2022-02-25 11:44:02
- * Description:  This files is for intrrupt function of wdt ctrl
+ * Description:  This file is for wdt interrupt handler implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_sinit.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_sinit.c
index 69498558e44..89250d8438d 100644
--- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_sinit.c
+++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt_sinit.c
@@ -14,11 +14,12 @@
  * FilePath: fwdt_sinit.c
  * Date: 2022-02-10 14:53:42
  * LastEditTime: 2022-02-25 11:45:05
- * Description:  This files is for
+ * Description:  This file is for wdt static variables implementation.
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   wangxiaodong  2022/4/25   init commit
  */
 
 
@@ -34,7 +35,7 @@
 #define FWDT_DEBUG(format, ...) FT_DEBUG_PRINT_D(FWDT_DEBUG_TAG, format, ##__VA_ARGS__)
 
 
-extern FWdtConfig FWdtConfigTbl[FWDT_INSTANCE_NUM];
+extern FWdtConfig FWdtConfigTbl[FWDT_NUM];
 /************************** Constant Definitions *****************************/
 
 /**************************** Type Definitions *******************************/
@@ -56,13 +57,13 @@ const FWdtConfig *FWdtLookupConfig(u32 instance_id)
     const FWdtConfig *pconfig = NULL;
     u32 index;
 
-    if (instance_id >= FWDT_INSTANCE_NUM)
+    if (instance_id >= FWDT_NUM)
     {
         FWDT_ERROR("wdt id is not invalid.");
         return NULL;
     }
 
-    for (index = 0; index < (u32)FWDT_INSTANCE_NUM; index++)
+    for (index = 0; index < (u32)FWDT_NUM; index++)
     {
         if (FWdtConfigTbl[index].instance_id == instance_id)
         {
diff --git a/bsp/phytium/libraries/standalone/gitinfo b/bsp/phytium/libraries/standalone/gitinfo
index 4cb410e5a67..e6334ebcefe 100644
--- a/bsp/phytium/libraries/standalone/gitinfo
+++ b/bsp/phytium/libraries/standalone/gitinfo
@@ -1,4 +1,3 @@
-[commit-id]:
-ccf728ed578713cae89a5472f7dfb6fbd01e7a70
-[branch]:
-new_master
+[commit-id]: 41da10704f28d248120e389ae889e92f43f49a98
+[branch]: pin_example_reconsitution
+[date]: 2023-03-09 14:58:04
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcache.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcache.c
new file mode 100644
index 00000000000..ed999cdfc7e
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcache.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fcache.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for aarch32 cache functions port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include <cp15.h>
+#include "fassert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern void rt_hw_cpu_dcache_invalidate(void *addr, int size);
+extern void rt_hw_cpu_dcache_clean(void *addr, int size);
+
+/************************** Function *****************************************/
+void FCacheDCacheInvalidate(void)
+{
+    /* there is no dcache invalidate implmentation for contrex-a aarch32, use flush instead */
+    rt_cpu_dcache_clean_flush();
+}
+
+void FCacheDCacheInvalidateRange(intptr adr, intptr len)
+{
+    rt_hw_cpu_dcache_invalidate((void *)adr, (int)len);
+}
+
+void FCacheDCacheFlushRange(intptr adr, intptr len)
+{
+    rt_hw_cpu_dcache_clean((void *)adr, (int)len);
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c
new file mode 100644
index 00000000000..e2945ede4b6
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fcp15.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for cp15 function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include "fassert.h"
+#include "fcp15.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.h
new file mode 100644
index 00000000000..b2221399ab1
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fcp15.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for cp15 function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+#ifndef FDRV_AARCH32_H
+#define FDRV_AARCH32_H
+
+/***************************** Include Files *********************************/
+#include <stddef.h>
+#include "ftypes.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+static inline void WMB(void)
+{
+    __asm__ __volatile__("dsb" \
+                            :     \
+                            :     \
+                            : "memory");
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c
new file mode 100644
index 00000000000..8512d868565
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fgeneric_timer.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for generic timer function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include <gtimer.h>
+
+#include "fkernel.h"
+#include "fassert.h"
+#include "fgeneric_timer.h"
+
+/************************** Constant Definitions *****************************/
+#define CNTP_CTL_ENABLE     (1U << 0)    /* Enables the timer */
+#define CNTP_CTL_IMASK      (1U << 1)    /* Timer interrupt mask bit */
+#define CNTP_CTL_ISTATUS    (1U << 2)    /* The status of the timer */
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+u64 GenericTimerRead(void)
+{
+    return (u64)gtimer_get_current_value();
+}
+
+void GenericTimerStart(void)
+{
+    u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */
+
+    if (!(ctrl & CNTP_CTL_ENABLE))
+    {
+        ctrl |= CNTP_CTL_ENABLE; /* enable gtimer if off */
+        gtimer_set_control(ctrl); /* set CNTP_CTL */
+    }
+}
+
+void GenericTimerStop(void)
+{
+    u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */
+    if ((ctrl & CNTP_CTL_ENABLE))
+    {
+        ctrl &= ~CNTP_CTL_ENABLE; /* disable gtimer if on */
+        gtimer_set_control(ctrl); /* set CNTP_CTL */
+    }
+}
+
+u32 GenericTimerFrequecy(void)
+{
+    u32 rate = gtimer_get_counter_frequency(); /* get CNTFRQ bit[31:0] freq of system counter */
+    FASSERT_MSG((rate > 1000000), "invalid freqency %ud", rate);
+    return rate;
+}
+
+void GenericTimerCompare(u32 interval)
+{
+    /* set CNTP_CVAL, set compare value for physical timer */
+    gtimer_set_load_value((rt_uint64_t)interval);
+}
+
+void GenericTimerInterruptEnable(void)
+{
+    u64 ctrl = gtimer_get_control();
+    if (ctrl & CNTP_CTL_IMASK)
+    {
+        ctrl &= ~CNTP_CTL_IMASK;
+        gtimer_set_control(ctrl);
+    }
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c
similarity index 93%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.c
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c
index 2c2e298b230..19dc830d38a 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.c
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c
@@ -11,14 +11,15 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: psci.c
+ * FilePath: fpsci.c
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:30:35
- * Description:  This files is for
+ * Description:  This file is for cpu energy management
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
  */
 
 
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h
similarity index 86%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.h
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h
index d79f0ba548b..195a787ffd7 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fpsci.h
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h
@@ -14,16 +14,17 @@
  * FilePath: fpsci.h
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:30:40
- * Description:  This files is for
+ * Description:  This file is for cpu energy management
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
  */
 
 
-#ifndef BSP_ARCH_ARMV8_AARCH32_PSCI_H
-#define BSP_ARCH_ARMV8_AARCH32_PSCI_H
+#ifndef ARCH_ARMV8_AARCH32_PSCI_H
+#define ARCH_ARMV8_AARCH32_PSCI_H
 
 #ifdef __cplusplus
 extern "C"
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c
new file mode 100644
index 00000000000..165b599c52f
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fsleep.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for sleep function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include "fassert.h"
+#include "fsleep.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+u32 fsleep_seconds(u32 seconds)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+}
+
+u32 fsleep_millisec(u32 mseconds)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+}
+
+u32 fsleep_microsec(u32 useconds)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+}
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h
new file mode 100644
index 00000000000..445ba4813c0
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h
@@ -0,0 +1,76 @@
+/*
+ * @Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * @FilePath: fsmc.h
+ * @Date: 2023-04-19 10:14:11
+ * @LastEditTime: 2023-04-19 10:14:12
+ * @Description:  This file is for 
+ * 
+ * @Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fsmc.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:30:49
+ * Description:  This file is for Non-secure SMC Call
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
+ */
+
+
+#ifndef ARCH_ARMV8_AARCH32_SMC_H
+#define ARCH_ARMV8_AARCH32_SMC_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include "ftypes.h"
+
+typedef struct
+{
+    /* data */
+    u32 function_identifier;
+    u32 a1;
+    u32 a2;
+    u32 a3;
+    u32 a4;
+    u32 a5;
+    u32 a6;
+
+} FSmc_Data_t;
+
+void FSmcCall(FSmc_Data_t *Input, FSmc_Data_t *Output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !FT_SMC_H
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/gcc/fsmccc_call.S b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S
similarity index 95%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch32/gcc/fsmccc_call.S
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S
index 16b14b209e9..7845646194c 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/gcc/fsmccc_call.S
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S
@@ -14,11 +14,12 @@
  * FilePath: smccc-call.S
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:28:10
- * Description:  This files is for 
+ * Description:  This file is for initiating SMC call
  * 
  * Modify History: 
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
  */
 
 
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h
new file mode 100644
index 00000000000..3379577aa6b
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: sdkopts.h
+ * Date: 2022-09-16 13:54:28
+ * LastEditTime: 2022-09-16 13:54:28
+ * Description:  This file is for configure sdkconfig in non-Kconfig way
+ * 
+ * Modify History: 
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0  liuzhihong     2022/10/20            first release
+ */
+
+#ifndef SDK_OPTS_H
+#define SDK_OPTS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************Control Options*******************/
+/* cpu aarch 32/64 */
+#define CPU_AARCH     32
+#define TARGET_NAME   "e2000d_baremetal_a32"
+
+/* e2000d e2000q e2000s d2000 ft2004 */
+#define CPU_TYPE_E2000D      0
+#define CPU_TYPE_E2000Q      1
+#define CPU_TYPE_E2000S      2
+#define CPU_TYPE_D2000       3
+#define CPU_TYPE_FT2004      4
+#define CPU_TYPE             CPU_TYPE_E2000D
+
+/* log type */
+#define LOG_TYPE_VERBOS      0
+#define LOG_TYPE_DEBUG       1
+#define LOG_TYPE_INFO        2
+#define LOG_TYPE_WARN        3
+#define LOG_TYPE_ERROR       4
+#define LOG_TYPE_NONE        5
+#define LOG_TYPE             LOG_TYPE_ERROR
+
+/*******************SDK Configures*******************/
+#include "sdkopts.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDK_OPTS_H */
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c
new file mode 100644
index 00000000000..88906b1e2df
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: faarch64.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for aarch64 function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include "fassert.h"
+#include "faarch64.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.h
new file mode 100644
index 00000000000..9c0c9ee4fe0
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: faarch64.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for aarch64 function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+#ifndef FDRV_AARCH64_H
+#define FDRV_AARCH64_H
+
+/***************************** Include Files *********************************/
+#include <stddef.h>
+#include "ftypes.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+void WMB(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/farm_smccc.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/farm_smccc.h
similarity index 93%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch64/farm_smccc.h
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/farm_smccc.h
index c682d385333..670d4bf993f 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/farm_smccc.h
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/farm_smccc.h
@@ -14,15 +14,23 @@
  * FilePath: farm_smccc.h
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:32:15
- * Description:  This files is for
+ * Description:  This file is for initiating SMC call
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe   2022/6/13    first release
  */
 
-#ifndef __LINUX_ARM_SMCCC_H
-#define __LINUX_ARM_SMCCC_H
+#ifndef FARM_SMCCC_H
+#define FARM_SMCCC_H
+
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
 
 /*
  * This file provides common defines for ARM SMC Calling Convention as
@@ -72,7 +80,6 @@
 
 #ifndef __ASSEMBLY__
 
-#include <stdio.h>
 /**
  * struct arm_smccc_res - Result from SMC/HVC call
  * @a0-a3 result values from registers 0 to 3
@@ -117,9 +124,14 @@ void __arm_smccc_smc(unsigned long a0, unsigned long a1,
                      unsigned long a5, unsigned long a6, unsigned long a7,
                      struct arm_smccc_res *res, struct arm_smccc_quirk *quirk);
 
-#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL)
+#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__)
 
 #define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__)
 
 #endif /*__ASSEMBLY__*/
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /*__LINUX_ARM_SMCCC_H*/
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fcache.c_x b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fcache.c_x
new file mode 100644
index 00000000000..cfda8c9404c
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fcache.c_x
@@ -0,0 +1,52 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fcache.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for aarch64 cache function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include "fassert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+void FCacheDCacheInvalidate(void)
+{
+    rt_hw_dcache_invalidate_all();
+}
+
+void FCacheDCacheInvalidateRange(intptr adr, intptr len)
+{
+    rt_hw_dcache_invalidate_range((unsigned long)adr, (unsigned long)len);
+}
+
+void FCacheDCacheFlushRange(intptr adr, intptr len)
+{
+    rt_hw_dcache_flush_range((unsigned long)adr, (unsigned long)len);
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c
new file mode 100644
index 00000000000..ead65027be6
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fgeneric_timer.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for generic timer function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include "fassert.h"
+#include "fgeneric_timer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fgeneric_timer.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for generic timer function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include <gtimer.h>
+
+#include "fassert.h"
+#include "fgeneric_timer.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+u64 GenericTimerRead(void)
+{
+    return (u64)rt_hw_get_gtimer_val();
+}
+
+void GenericTimerStart(void)
+{
+    /* shall not be called in rtt */
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+}
+
+void GenericTimerStop(void)
+{
+    /* shall not be called in rtt */
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+}
+
+u32 GenericTimerFrequecy(void)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);
+    return 0U;    
+}
+
+void GenericTimerCompare(u32 interval)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);    
+}
+
+void GenericTimerInterruptEnable(void)
+{
+    FASSERT_MSG(0, "%s not implment !!!", __func__);      
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c
similarity index 75%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.c
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c
index fb5f8ec6868..36b373683bc 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/fpsci.c
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c
@@ -11,14 +11,15 @@
  * See the Phytium Public License for more details.
  *
  *
- * FilePath: psci.c
+ * FilePath: fpsci.c
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:33:51
- * Description:  This files is for
+ * Description:  This file is for cpu energy management
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
  */
 
 #include "fpsci.h"
@@ -26,22 +27,25 @@
 #include "ftypes.h"
 #include "fcpu_info.h"
 #include "ferror_code.h"
+#include "fprintk.h"
 
 FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr)
 {
     FError ret ;
     u64 cluster = 0;
+    struct arm_smccc_res res;
+    struct arm_smccc_quirk quirk;
     ret = GetCpuAffinityByMask(cpu_id_mask, &cluster);
     if (ret != ERR_SUCCESS)
     {
-        printf("GetCpuAffinity is failed \r\n") ;
+        f_printk("GetCpuAffinity is failed \r\n") ;
         return ret ;
     }
-    arm_smccc_smc(0xc4000003, cluster, bootaddr, 0, 0, 0, 0, 0, 0);
+    __arm_smccc_smc(0xc4000003, cluster, bootaddr, 0, 0, 0, 0, 0,&res, &quirk);
     return ERR_SUCCESS ;
 }
 void PsciCpuReset(void)
 {
     struct arm_smccc_res res;
-    arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
+    __arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res,NULL);
 }
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h
new file mode 100644
index 00000000000..c672a45bbd8
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h
@@ -0,0 +1,66 @@
+/*
+ * @Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * @FilePath: fpsci.h
+ * @Date: 2023-04-21 15:39:57
+ * @LastEditTime: 2023-04-21 15:39:57
+ * @Description:  This file is for 
+ * 
+ * @Modify History: 
+ *  Ver   Who  Date   Changes
+ * ----- ------  -------- --------------------------------------
+ */
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fpsci.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:34:06
+ * Description:  This file is for cpu energy management
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
+ */
+
+
+#ifndef FPSCI_H
+#define FPSCI_H
+
+#include "ftypes.h"
+#include "ferror_code.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+void PsciCpuReset(void);
+FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FPSCI_H
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsleep.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsleep.c
new file mode 100644
index 00000000000..d6ce7e00712
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsleep.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fsleep.c
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for sleep function port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+
+/***************************** Include Files *********************************/
+#include <gtimer.h>
+
+#include "fassert.h"
+#include "fsleep.h"
+#include "fkernel.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+static u32 fsleep_general(u32 ticks, u32 div)
+{
+    u64 end_time;
+    u64 cur_time;
+    cur_time = rt_hw_get_gtimer_val();
+    end_time = cur_time + ((u64)ticks * rt_hw_get_gtimer_frq() / div);
+
+    do
+    {
+        cur_time = rt_hw_get_gtimer_val();
+    }
+    while (cur_time < end_time);
+
+    return 0;
+}
+
+u32 fsleep_seconds(u32 seconds)
+{
+    return fsleep_general(seconds, 1);
+}
+
+u32 fsleep_millisec(u32 mseconds)
+{
+    return fsleep_general(mseconds, NANO_TO_MICRO);
+}
+
+u32 fsleep_microsec(u32 useconds)
+{
+    return fsleep_general(useconds, NANO_TO_KILO);
+}
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/gcc/fsmccc_call.S b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmccc_call.S
similarity index 91%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch64/gcc/fsmccc_call.S
rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmccc_call.S
index 78464c59bf4..27e8e61f26c 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch64/gcc/fsmccc_call.S
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmccc_call.S
@@ -11,14 +11,15 @@
  * See the Phytium Public License for more details. 
  *  
  * 
- * FilePath: smccc-call.S
+ * FilePath: fsmccc-call.S
  * Date: 2022-02-10 14:53:41
  * LastEditTime: 2022-02-17 17:31:23
- * Description:  This files is for 
+ * Description:  This file is for initiating SMC call 
  * 
  * Modify History: 
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   huanghe     2021/7/3     first release
  */
 
 .macro SMCCC instr
diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h
new file mode 100644
index 00000000000..e86224eb82a
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: sdkopts.h
+ * Date: 2022-09-16 13:54:28
+ * LastEditTime: 2022-09-16 13:54:28
+ * Description:  This file is for configure sdkconfig in non-Kconfig way
+ * 
+ * Modify History: 
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0    zhugengyu    2023/03/03            first release
+ */
+
+#ifndef SDK_OPTS_H
+#define SDK_OPTS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************Control Options*******************/
+/* cpu aarch 32/64 */
+#define CPU_AARCH     64
+#define TARGET_NAME   "e2000d_baremetal_a64"
+
+/* e2000d e2000q e2000s d2000 ft2004 */
+#define CPU_TYPE_E2000D      0
+#define CPU_TYPE_E2000Q      1
+#define CPU_TYPE_E2000S      2
+#define CPU_TYPE_D2000       3
+#define CPU_TYPE_FT2004      4
+#define CPU_TYPE             CPU_TYPE_E2000D
+
+/* log type */
+#define LOG_TYPE_VERBOS      0
+#define LOG_TYPE_DEBUG       1
+#define LOG_TYPE_INFO        2
+#define LOG_TYPE_WARN        3
+#define LOG_TYPE_ERROR       4
+#define LOG_TYPE_NONE        5
+#define LOG_TYPE             LOG_TYPE_ERROR
+
+/*******************SDK Configures*******************/
+#include "sdkopts.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDK_OPTS_H */
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/arch/fcache.h b/bsp/phytium/libraries/standalone/port/arch/fcache.h
new file mode 100644
index 00000000000..4e1d9d268eb
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/arch/fcache.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
+ * All Rights Reserved.
+ *
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
+ * either version 1.0 of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details.
+ *
+ *
+ * FilePath: fcache.h
+ * Date: 2022-02-10 14:53:41
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for aarch32 cache functions port for driver
+ *
+ * Modify History:
+ *  Ver   Who        Date         Changes
+ * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
+ */
+#ifndef FDRV_CACHE_AARCH32_H
+#define FDRV_CACHE_AARCH32_H
+
+/***************************** Include Files *********************************/
+#include <stddef.h>
+#include "ftypes.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+void FCacheDCacheInvalidate(void);
+void FCacheDCacheInvalidateRange(intptr adr, intptr len);
+void FCacheDCacheFlushRange(intptr adr, intptr len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.h b/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h
similarity index 54%
rename from bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.h
rename to bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h
index 5a247c3fbd8..19e6edefae5 100644
--- a/bsp/phytium/libraries/standalone/arch/armv8/aarch32/fgeneric_timer.h
+++ b/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h
@@ -1,5 +1,5 @@
 /*
- * Copyright : (C) 2022 Phytium Information Technology, Inc.
+ * Copyright : (C) 2023 Phytium Information Technology, Inc.
  * All Rights Reserved.
  *
  * This program is OPEN SOURCE software: you can redistribute it and/or modify it
@@ -13,39 +13,46 @@
  *
  * FilePath: fgeneric_timer.h
  * Date: 2022-02-10 14:53:41
- * LastEditTime: 2022-02-17 17:30:13
- * Description:  This files is for
+ * LastEditTime: 2022-02-17 17:36:17
+ * Description:  This file is for generic timer function port for driver
  *
  * Modify History:
  *  Ver   Who        Date         Changes
  * ----- ------     --------    --------------------------------------
+ * 1.0   zhugengyu  2023/2/28   first release
  */
+#ifndef FDRV_GENERIC_TIMER_AARCH32_H
+#define FDRV_GENERIC_TIMER_AARCH32_H
 
-
-#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H
-#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H
+/***************************** Include Files *********************************/
+#include <stddef.h>
+#include "ftypes.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
-#include "ftypes.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Variable Definitions *****************************/
 
-typedef void (* GenericTimerTickHandler)();
+/***************** Macros (Inline Functions) Definitions *********************/
 
+/************************** Function Prototypes ******************************/
+
+/************************** Function *****************************************/
+u64 GenericTimerRead(void);
 void GenericTimerStart(void);
 void GenericTimerStop(void);
-void GenericTimerInterruptEnable(void);
-void GenericTimerInterruptDisable(void);
 u32 GenericTimerFrequecy(void);
-u64 GenericTimerRead(void);
 void GenericTimerCompare(u32 interval);
-void GenericTimerSetupSystick(u32 tickRateHz, GenericTimerTickHandler tickHandler, u32 intrPrority);
-u32 GenericGetTick(void);
+void GenericTimerInterruptEnable(void);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif // !
\ No newline at end of file
+#endif
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/common/fsleep.h b/bsp/phytium/libraries/standalone/port/arch/fsleep.h
similarity index 71%
rename from bsp/phytium/libraries/standalone/common/fsleep.h
rename to bsp/phytium/libraries/standalone/port/arch/fsleep.h
index f9d29c201ed..b0e78fa80fd 100644
--- a/bsp/phytium/libraries/standalone/common/fsleep.h
+++ b/bsp/phytium/libraries/standalone/port/arch/fsleep.h
@@ -14,21 +14,32 @@
  * FilePath: fsleep.h
  * Date: 2021-05-28 08:48:40
  * LastEditTime: 2022-02-17 18:02:51
- * Description:  This files is for
+ * Description:  This file is for sleep function port for driver
  *
  * Modify History:
- *  Ver   Who        Date         Changes
- * ----- ------     --------    --------------------------------------
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0   zhugengyu  2023/2/28              first release
  */
 
 
-#ifndef _BSP_ARCH_ARMV8_FSLEEP_H
-#define _BSP_ARCH_ARMV8_FSLEEP_H
+#ifndef FDRV_FSLEEP_H
+#define FDRV_FSLEEP_H
 
 #include "ftypes.h"
 
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
 u32 fsleep_seconds(u32 seconds); /* 按秒延迟 */
 u32 fsleep_millisec(u32 mseconds); /* 按毫秒延迟 */
 u32 fsleep_microsec(u32 useconds); /* 按微秒延迟 */
 
+#ifdef __cplusplus
+}
+#endif
+
+
 #endif // !
\ No newline at end of file
diff --git a/bsp/phytium/libraries/standalone/port/sdkconfig.h b/bsp/phytium/libraries/standalone/port/sdkconfig.h
new file mode 100644
index 00000000000..6be880137e0
--- /dev/null
+++ b/bsp/phytium/libraries/standalone/port/sdkconfig.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright : (C) 2022 Phytium Information Technology, Inc. 
+ * All Rights Reserved.
+ *  
+ * This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+ * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+ * either version 1.0 of the License, or (at your option) any later version. 
+ *  
+ * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+ * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the Phytium Public License for more details. 
+ *  
+ * 
+ * FilePath: sdkopts.h
+ * Date: 2022-09-16 13:54:28
+ * LastEditTime: 2022-09-16 13:54:28
+ * Description:  This file is for configure sdkconfig in non-Kconfig way
+ * 
+ * Modify History: 
+ *  Ver     Who           Date                  Changes
+ * -----   ------       --------     --------------------------------------
+ *  1.0   zhugengyu    2023/03/01            first release
+ */
+
+#ifndef SDK_CONFIG_H
+#define SDK_CONFIG_H
+
+#include "rtconfig.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(TARGET_ARMV8_AARCH32)
+#define CONFIG_TARGET_ARMV8_AARCH32
+#elif defined(TARGET_ARMV8_AARCH64)
+#define CONFIG_TARGET_ARMV8_AARCH64
+#endif
+
+#if defined(TARGET_E2000D)
+#define CONFIG_TARGET_E2000
+#define CONFIG_TARGET_E2000D
+#elif defined(TARGET_E2000Q)
+#define CONFIG_TARGET_E2000
+#define CONFIG_TARGET_E2000Q
+#elif defined(TARGET_E2000S)
+#define CONFIG_TARGET_E2000
+#define CONFIG_TARGET_E2000S
+#elif defined(TARGET_D2000)
+#define CONFIG_TARGET_D2000
+#elif defined(TARGET_F2000_4)
+#define CONFIG_TARGET_F2000_4
+#endif
+
+#if defined(LOG_VERBOS)
+#define CONFIG_LOG_VERBOS
+#elif defined(LOG_DEBUG)
+#define CONFIG_LOG_DEBUG
+#elif defined(LOG_INFO)
+#define CONFIG_LOG_INFO
+#elif defined(LOG_WARN)
+#define CONFIG_LOG_WARN
+#elif defined(LOG_ERROR)
+#define CONFIG_LOG_ERROR
+#elif defined(LOG_NONE)
+#define CONFIG_LOG_NONE
+#endif
+
+#if defined(BSP_USING_UART)
+#define CONFIG_USE_SERIAL
+#define CONFIG_ENABLE_Pl011_UART
+#endif
+
+#if defined(BSP_USING_CAN)
+#define CONFIG_USE_CAN
+#define CONFIG_USE_FCAN
+#define CONFIG_FCAN_USE_CANFD
+#endif
+
+#if defined(BSP_USING_QSPI)
+#define CONFIG_USE_QSPI
+#define CONFIG_USE_FQSPI
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SDK_CONFIG_H */
\ No newline at end of file
diff --git a/bsp/phytium/tools/figures/commit_id.png b/bsp/phytium/tools/figures/commit_id.png
new file mode 100644
index 00000000000..bf296bd1d63
Binary files /dev/null and b/bsp/phytium/tools/figures/commit_id.png differ
diff --git a/bsp/phytium/tools/figures/commit_reduce.png b/bsp/phytium/tools/figures/commit_reduce.png
new file mode 100644
index 00000000000..9012cebf985
Binary files /dev/null and b/bsp/phytium/tools/figures/commit_reduce.png differ
diff --git a/bsp/phytium/tools/figures/rebase_commit.png b/bsp/phytium/tools/figures/rebase_commit.png
new file mode 100644
index 00000000000..92fef40975c
Binary files /dev/null and b/bsp/phytium/tools/figures/rebase_commit.png differ
diff --git a/bsp/phytium/tools/figures/rebase_done.png b/bsp/phytium/tools/figures/rebase_done.png
new file mode 100644
index 00000000000..99847b3cd7a
Binary files /dev/null and b/bsp/phytium/tools/figures/rebase_done.png differ
diff --git a/bsp/phytium/tools/figures/reduce_rtt.png b/bsp/phytium/tools/figures/reduce_rtt.png
new file mode 100644
index 00000000000..e7cd74a810d
Binary files /dev/null and b/bsp/phytium/tools/figures/reduce_rtt.png differ
diff --git a/bsp/phytium/tools/lite_tools.md b/bsp/phytium/tools/lite_tools.md
new file mode 100644
index 00000000000..0f807e2d28a
--- /dev/null
+++ b/bsp/phytium/tools/lite_tools.md
@@ -0,0 +1,44 @@
+# 背景
+
+- RT-Thread 中有大量代码平常是不需要使用的，这里使用脚本将不使用的代码临时删除，后面又提供了一种方法在需要时恢复
+
+# 精简 RT-Thread 代码
+
+- 首先运行 reduce_rtt_code.py 脚本，用 -i 指定 RT-Thread 完整版代码路径，用 -o 指定输出
+
+```
+./reduce_rtt_code.py -i=/mnt/d/proj/rt-thread/rt-thread-base -o=/mnt/d/proj/rt-thread/rt-thread-lite
+```
+
+![](./figures/reduce_rtt.png)
+
+- 进入 rt-thread-lite 目录，然后提交删除动作，记录删除动作前一个 commit 号 
+
+```
+git add .
+git commit -m 'reduce rtt code tree'
+```
+
+![](./figures/commit_reduce.png)
+
+![](./figures/commit_id.png)
+
+# 恢复 RT-Thread 代码
+
+- 需要同步 RT-Thread 基线仓库时，可能需要完整版的代码
+- 用 git rebase 撤销删除动作，在交互界面里将 pick 修改为 d，表示删除指定 commit, 然后保存修改
+
+```
+git rebase -i <commit-id>
+```
+
+![](./figures/rebase_commit.png)
+
+- 等待一段时间可以看到原来删除的文件都恢复了
+
+![](./figures/rebase_done.png)
+
+
+# 删除 tools 文件夹
+
+- lite 工具所在的文件夹在上传社区的时候可能不需要，要收到删除本文件夹
\ No newline at end of file
diff --git a/bsp/phytium/tools/reduce_rtt_code.py b/bsp/phytium/tools/reduce_rtt_code.py
new file mode 100644
index 00000000000..e2c1ec5d62e
--- /dev/null
+++ b/bsp/phytium/tools/reduce_rtt_code.py
@@ -0,0 +1,130 @@
+#!/usr/bin/env python3
+# Copyright : (C) 2022 Phytium Information Technology, Inc. 
+# All Rights Reserved.
+ 
+# This program is OPEN SOURCE software: you can redistribute it and/or modify it  
+# under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,  
+# either version 1.0 of the License, or (at your option) any later version. 
+ 
+# This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;  
+# without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+# See the Phytium Public License for more details. 
+ 
+# FilePath: reduce_rtt_cde.py
+# Date: 2021-10-14 08:19:30
+# LastEditTime: 2022-02-18 09:26:24
+# Description:  This files is for install phytiunm standalone sdk
+
+# Modify History: 
+#  Ver   Who        Date         Changes
+# ----- ------     --------    --------------------------------------
+# 1.0   zhugengyu  2023/1/12   init commit
+
+#
+# ./reduce_rtt_code.py -i=/mnt/d/proj/rt-thread/rt-thread-base -o=/mnt/d/proj/rt-thread/rt-thread-lite
+#
+
+
+import sys
+import os
+import argparse
+import shutil
+
+src_path = []
+dst_path = []
+
+dry_run = False #True
+
+def append_path(path):
+    src_path.append(os.path.abspath(path))
+
+parser = argparse.ArgumentParser()
+parser.description='please enter two parameters <input-PATH> and <export-PATH> ...'
+parser.add_argument("-i", "--input", help="input PATH of RTT", type=str, default="./rt-thread")
+parser.add_argument("-o", "--output", help="export PATH for RTT",  type=str, default="./rt-thread-lite")
+args = parser.parse_args()
+
+rtt_src_dir = os.path.abspath(args.input)
+rtt_dst_dir = os.path.abspath(args.output)
+
+os.chdir(rtt_src_dir) # change to rt-thread folder
+
+# append path and files need to reserve
+
+## root
+append_path(r'./.git')
+append_path(r'./.gitee')
+append_path(r'./.github')
+append_path(r'./.gitattributes')
+append_path(r'./.gitignore')
+append_path(r'./ChangeLog.md')
+append_path(r'./Kconfig')
+append_path(r'./LICENSE')
+append_path(r'./README.md')
+append_path(r'./README_de.md')
+append_path(r'./README_es.md')
+append_path(r'./README_zh.md')
+
+## bsp
+append_path(r'./bsp/phytium')
+
+## components
+append_path(r'./components')
+
+## examples
+append_path(r'./examples')
+
+## include
+append_path(r'./include')
+
+## libcpu
+append_path(r'./libcpu/Kconfig')
+append_path(r'./libcpu/SConscript')
+append_path(r'./libcpu/aarch64')
+append_path(r'./libcpu/arm')
+
+## src
+append_path(r'./src')
+
+## tools
+append_path(r'./tools')
+
+print('Source path ======')
+for path in src_path:
+    print(path)
+print('====================')
+
+for path in src_path:
+    dst_path.append(path.replace(rtt_src_dir, rtt_dst_dir))
+
+print('Destination path ======')
+for path in dst_path:
+    print(path)
+print('====================')
+
+print('Total {} items'.format(len(src_path)))
+print('Current dir: {}'.format(os.getcwd()))
+
+if dry_run:
+    for i in range(len(src_path)):
+        print('copy {} to {}'.format(src_path[i], dst_path[i]))           
+else:
+    root_dir = r'.' + rtt_dst_dir
+    if os.path.exists(root_dir):
+        shutil.rmtree(root_dir)
+
+    for i in range(len(src_path)):
+        if os.path.exists(dst_path[i]):
+            continue
+
+        # do real copy !!!!
+        if os.path.isdir(src_path[i]):
+            shutil.copytree(src_path[i], dst_path[i])
+        else:
+            file_dir = os.path.dirname(dst_path[i])
+            if not os.path.exists(file_dir):
+                os.mkdir(file_dir)
+            shutil.copyfile(src_path[i], dst_path[i])
+
+
+    os.chdir(rtt_dst_dir) # change to rt-thread folder
diff --git a/libcpu/aarch64/common/context_gcc.S b/libcpu/aarch64/common/context_gcc.S
index 0a611cbf483..6afc676ae36 100644
--- a/libcpu/aarch64/common/context_gcc.S
+++ b/libcpu/aarch64/common/context_gcc.S
@@ -24,7 +24,7 @@ rt_hw_cpu_id_set:
 /*
 int rt_hw_cpu_id(void)
 */
-.global rt_hw_cpu_id
+.weak rt_hw_cpu_id
 .type rt_hw_cpu_id, @function
 rt_hw_cpu_id:
    mrs x0, tpidr_el1           /* MPIDR_EL1: Multi-Processor Affinity Register */
diff --git a/libcpu/aarch64/common/gicv3.c b/libcpu/aarch64/common/gicv3.c
index 18fdcddc7f1..35864fea2fb 100644
--- a/libcpu/aarch64/common/gicv3.c
+++ b/libcpu/aarch64/common/gicv3.c
@@ -45,9 +45,9 @@ extern rt_uint64_t rt_cpu_mpidr_early[];
 struct arm_gic
 {
     rt_uint64_t offset;                     /* the first interrupt index in the vector table */
-    rt_uint64_t redist_hw_base[RT_CPUS_NR]; /* the pointer of the gic redistributor */
+    rt_uint64_t redist_hw_base[ARM_GIC_CPU_NUM]; /* the pointer of the gic redistributor */
     rt_uint64_t dist_hw_base;               /* the base address of the gic distributor */
-    rt_uint64_t cpu_hw_base[RT_CPUS_NR];    /* the base address of the gic cpu interface */
+    rt_uint64_t cpu_hw_base[ARM_GIC_CPU_NUM];    /* the base address of the gic cpu interface */
 };
 
 /* 'ARM_GIC_MAX_NR' is the number of cores */
@@ -737,7 +737,7 @@ int arm_gic_redist_init(rt_uint64_t index, rt_uint64_t redist_base)
 
     if (master_cpu_id < 0)
     {
-        master_cpu_id = cpu_id;
+        master_cpu_id = 0;
         rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, &master_cpu_id, sizeof(master_cpu_id));
     }
 
diff --git a/libcpu/aarch64/common/gicv3.h b/libcpu/aarch64/common/gicv3.h
index cdc7720b376..fbcf3fb4d92 100644
--- a/libcpu/aarch64/common/gicv3.h
+++ b/libcpu/aarch64/common/gicv3.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,6 +18,11 @@
 
 #if defined(BSP_USING_GIC) && defined(BSP_USING_GICV3)
 
+
+#ifndef ARM_GIC_CPU_NUM
+#define ARM_GIC_CPU_NUM RT_CPUS_NR
+#endif
+
 #define GICV3_ROUTED_TO_ALL   1UL
 #define GICV3_ROUTED_TO_SPEC  0UL
 
diff --git a/libcpu/aarch64/common/interrupt.c b/libcpu/aarch64/common/interrupt.c
index e30223a6969..dc142dd9e83 100644
--- a/libcpu/aarch64/common/interrupt.c
+++ b/libcpu/aarch64/common/interrupt.c
@@ -109,11 +109,11 @@ void rt_hw_interrupt_init(void)
 
     /* initialize ARM GIC */
 #ifdef RT_USING_SMART
-    gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000);
+    gic_dist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x40000);
     gic_cpu_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
 #ifdef BSP_USING_GICV3
     gic_rdist_base = (rt_uint64_t)rt_ioremap((void*)platform_get_gic_redist_base(),
-            RT_CPUS_NR * (2 << 16));
+            ARM_GIC_CPU_NUM * (2 << 16));
 #endif
 #else
     gic_dist_base = platform_get_gic_dist_base();
diff --git a/libcpu/aarch64/cortex-a/entry_point.S b/libcpu/aarch64/cortex-a/entry_point.S
index c1f14c28b03..112987c88d1 100644
--- a/libcpu/aarch64/cortex-a/entry_point.S
+++ b/libcpu/aarch64/cortex-a/entry_point.S
@@ -120,7 +120,7 @@ __start:
     adr x1, __start         /* install early page table */
     ldr x0, =~0x1fffff
     and x0, x1, x0
-    add x1, x0, #0x1000
+    add x1, x0, #0x1000     
 
     msr ttbr0_el1, x0
     msr ttbr1_el1, x1
@@ -130,7 +130,10 @@ __start:
     ldr     x2, =__start
     GET_PHY x3, __start
     sub     x3, x3, x2
+#else
+    mov     x3,0
 #endif
+    
     ldr x2, =0x40000000     /* map 1G memory for kernel space */
     bl rt_hw_mem_setup_early
 
diff --git a/libcpu/arm/cortex-a/cpuport.c b/libcpu/arm/cortex-a/cpuport.c
index e3ce568243e..ec523f2aa7b 100644
--- a/libcpu/arm/cortex-a/cpuport.c
+++ b/libcpu/arm/cortex-a/cpuport.c
@@ -13,7 +13,7 @@
 #include <rtthread.h>
 #include <board.h>
 
-int rt_hw_cpu_id(void)
+rt_weak int rt_hw_cpu_id(void)
 {
     int cpu_id;
     __asm__ volatile (
diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c
index bfb3b271707..6fd74aaf76f 100644
--- a/libcpu/arm/cortex-a/interrupt.c
+++ b/libcpu/arm/cortex-a/interrupt.c
@@ -100,8 +100,7 @@ void rt_hw_interrupt_init(void)
 
     /* initialize ARM GIC */
 #ifdef RT_USING_SMART
-    gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x2000);
-    gic_cpu_base = (uint32_t)rt_ioremap((void*)platform_get_gic_cpu_base(), 0x1000);
+    gic_dist_base = (uint32_t)rt_ioremap((void*)platform_get_gic_dist_base(), 0x10000);
 #else
     gic_dist_base = platform_get_gic_dist_base();
 #endif
diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S
index 658ff5a6492..1283686439f 100644
--- a/libcpu/arm/cortex-a/start_gcc.S
+++ b/libcpu/arm/cortex-a/start_gcc.S
@@ -208,13 +208,22 @@ bss_loop:
 _rtthread_startup:
     .word rtthread_startup
 
+.weak rt_asm_cpu_id 
+rt_asm_cpu_id:
+    mov r9, lr
+    mrc p15, 0, r0, c0, c0, 5
+    and r0, r0, #0xf
+    mov lr, r9
+
 stack_setup:
 
 #ifdef RT_USING_SMP
     /* cpu id */
-    mrc p15, 0, r0, c0, c0, 5
-    and r0, r0, #0xf
+    mov r10, lr
+    bl rt_asm_cpu_id
+    mov lr, r10
     add r0, r0, #1
+    
 #else
     mov r0, #1
 #endif
@@ -300,6 +309,50 @@ _halt:
     wfe
     b _halt
 
+#ifdef RT_USING_SMP
+
+.global rt_secondary_cpu_entry
+rt_secondary_cpu_entry:
+#ifdef RT_USING_SMART
+    ldr     r0, =_reset
+    adr     r5, _reset
+    sub     r5, r5, r0
+
+    ldr     lr, =after_enable_mmu_n
+    ldr     r0, =init_mtbl
+    add     r0, r5
+    b       enable_mmu
+
+after_enable_mmu_n:
+    ldr     r0, =MMUTable
+    add     r0, r5
+    bl      rt_hw_mmu_switch
+#endif
+
+#ifdef RT_USING_FPU
+    mov r4, #0xfffffff
+    mcr p15, 0, r4, c1, c0, 2
+#endif
+
+    mrc p15, 0, r1, c1, c0, 1
+    mov r0, #(1<<6)
+    orr r1, r0
+    mcr p15, 0, r1, c1, c0, 1    /* enable smp */
+
+    mrc p15, 0, r0, c1, c0, 0
+    bic r0, #(1<<13)
+    mcr p15, 0, r0, c1, c0, 0
+
+    bl stack_setup
+
+    /* initialize the mmu table and enable mmu */
+#ifndef RT_USING_SMART
+    bl rt_hw_mmu_init
+#endif
+
+    b rt_hw_secondary_cpu_bsp_start
+#endif
+
 /* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
 .section .text.isr, "ax"
     .align  5
@@ -616,50 +669,6 @@ rt_hw_clz:
     clz r0, r0
     bx lr
 
-#ifdef RT_USING_SMP
-
-.global rt_secondary_cpu_entry
-rt_secondary_cpu_entry:
-#ifdef RT_USING_SMART
-    ldr     r0, =_reset
-    adr     r5, _reset
-    sub     r5, r5, r0
-
-    ldr     lr, =after_enable_mmu_n
-    ldr     r0, =init_mtbl
-    add     r0, r5
-    b       enable_mmu
-
-after_enable_mmu_n:
-    ldr     r0, =MMUTable
-    add     r0, r5
-    bl      rt_hw_mmu_switch
-#endif
-
-#ifdef RT_USING_FPU
-    mov r4, #0xfffffff
-    mcr p15, 0, r4, c1, c0, 2
-#endif
-
-    mrc p15, 0, r1, c1, c0, 1
-    mov r0, #(1<<6)
-    orr r1, r0
-    mcr p15, 0, r1, c1, c0, 1    /* enable smp */
-
-    mrc p15, 0, r0, c1, c0, 0
-    bic r0, #(1<<13)
-    mcr p15, 0, r0, c1, c0, 0
-
-    bl stack_setup
-
-    /* initialize the mmu table and enable mmu */
-#ifndef RT_USING_SMART
-    bl rt_hw_mmu_init
-#endif
-
-    b rt_hw_secondary_cpu_bsp_start
-#endif
-
 #ifndef RT_CPUS_NR
 #define RT_CPUS_NR 1
 #endif
diff --git a/src/mem.c b/src/mem.c
index 79affcaa9bd..6beede9f6e3 100644
--- a/src/mem.c
+++ b/src/mem.c
@@ -91,7 +91,8 @@ struct rt_small_mem
 #define MIN_SIZE 12
 #endif /* ARCH_CPU_64BIT */
 
-#define MEM_MASK             0xfffffffe
+#define MEM_MASK ((~(rt_size_t)0) - 1)
+
 #define MEM_USED()         ((((rt_base_t)(small_mem)) & MEM_MASK) | 0x1)
 #define MEM_FREED()        ((((rt_base_t)(small_mem)) & MEM_MASK) | 0x0)
 #define MEM_ISUSED(_mem)   \