drivers: clock control: some stm32f4 have no div-q on there plli2s

Check that the plli2s has a DIV-Q output or not. That depends
on the PLLi2S of some stm32F4xx devices

(cherry picked from commit bba13ae)

Original-Signed-off-by: Francois Ramu <[email protected]>
GitOrigin-RevId: bba13ae
Cr-Build-Id: 8724184635785024145
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8724184635785024145
Copybot-Job-Name: zephyr-main-copybot-downstream
Change-Id: I35bd320b511e29b4ac22098de900399b855435d8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/zephyr/+/6222351
Tested-by: ChromeOS Prod (Robot) <[email protected]>
Bot-Commit: ChromeOS Prod (Robot) <[email protected]>
Commit-Queue: ChromeOS Prod (Robot) <[email protected]>

Author: Francois Ramu

drivers/clock_control/clock_stm32_ll_common.c

@@ -432,7 +432,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 					      STM32_PLL_R_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_Q_ENABLED & STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,