drivers: clock control of some stm32f4x has no 48MHz from PLL i2s

Remove the LL_RCC_PLLI2S_ConfigDomain_48M for the stm32f4
w/o Q divider on the PLLI2S to configure the PLL48CK

Signed-off-by: Francois Ramu <[email protected]>

Author: FRASTM

drivers/clock_control/clock_stm32f2_f4_f7.c

@@ -157,7 +157,7 @@ void config_plli2s(void)
 				       STM32_PLLI2S_N_MULTIPLIER,
 				       plli2sr(STM32_PLLI2S_R_DIVISOR));
 
-#if STM32_PLLI2S_Q_ENABLED
+#if STM32_PLLI2S_Q_ENABLED && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
 	/* There is a Q divider on the PLLI2S to configure the PLL48CK */
 	LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
 				       plli2sm(STM32_PLLI2S_M_DIVISOR),