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[AArch64] Fix spillfill-sve.mir with expensive checks.
This fixes an issue introduced by PR llvm#70679. Using constrainRegClass() is not strong enough to actually force the use of a register to be a PPR register class. It will need an actual COPY to do the conversion. The downside is that this introduces an extra register, which is an issue we may want to fix at a later point using a custom copy operation where the register allocator uses the same register when it can.
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2 files changed

+22
-9
lines changed

2 files changed

+22
-9
lines changed

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 14 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4773,9 +4773,13 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
47734773
} else if (AArch64::PNRRegClass.hasSubClassEq(RC)) {
47744774
assert((Subtarget.hasSVE2p1() || Subtarget.hasSME2()) &&
47754775
"Unexpected register store without SVE2p1 or SME2");
4776-
if (SrcReg.isVirtual())
4777-
MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::PPRRegClass);
4778-
else
4776+
if (SrcReg.isVirtual()) {
4777+
auto NewSrcReg =
4778+
MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
4779+
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), NewSrcReg)
4780+
.addReg(SrcReg);
4781+
SrcReg = NewSrcReg;
4782+
} else
47794783
SrcReg = (SrcReg - AArch64::PN0) + AArch64::P0;
47804784
Opc = AArch64::STR_PXI;
47814785
StackID = TargetStackID::ScalableVector;
@@ -4931,7 +4935,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
49314935
unsigned Opc = 0;
49324936
bool Offset = true;
49334937
unsigned StackID = TargetStackID::Default;
4934-
MCRegister PNRReg = MCRegister::NoRegister;
4938+
Register PNRReg = MCRegister::NoRegister;
49354939
switch (TRI->getSpillSize(*RC)) {
49364940
case 1:
49374941
if (AArch64::FPR8RegClass.hasSubClassEq(RC))
@@ -4950,7 +4954,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
49504954
"Unexpected register load without SVE2p1 or SME2");
49514955
PNRReg = DestReg;
49524956
if (DestReg.isVirtual())
4953-
MF.getRegInfo().constrainRegClass(DestReg, &AArch64::PPRRegClass);
4957+
DestReg = MF.getRegInfo().createVirtualRegister(&AArch64::PPRRegClass);
49544958
else
49554959
DestReg = (DestReg - AArch64::PN0) + AArch64::P0;
49564960
Opc = AArch64::LDR_PXI;
@@ -5061,9 +5065,13 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
50615065
.addFrameIndex(FI);
50625066
if (Offset)
50635067
MI.addImm(0);
5064-
if (PNRReg.isValid())
5068+
if (PNRReg.isValid() && !PNRReg.isVirtual())
50655069
MI.addDef(PNRReg, RegState::Implicit);
50665070
MI.addMemOperand(MMO);
5071+
5072+
if (PNRReg.isValid() && PNRReg.isVirtual())
5073+
BuildMI(MBB, MBBI, DebugLoc(), get(TargetOpcode::COPY), PNRReg)
5074+
.addReg(DestReg);
50675075
}
50685076

50695077
bool llvm::isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,

llvm/test/CodeGen/AArch64/spillfill-sve.mir

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -121,8 +121,13 @@ body: |
121121
122122
; EXPAND-LABEL: name: spills_fills_stack_id_virtreg_pnr
123123
; EXPAND: renamable $pn8 = WHILEGE_CXX_B
124-
; EXPAND: STR_PXI killed renamable $pn8, $sp, 7
125-
; EXPAND: $p0 = LDR_PXI $sp, 7, implicit-def $pn0
124+
; EXPAND: $p0 = ORR_PPzPP $p8, $p8, killed $p8
125+
; EXPAND: STR_PXI killed renamable $p0, $sp, 7
126+
;
127+
; EXPAND: renamable $p0 = LDR_PXI $sp, 7
128+
; EXPAND: $p8 = ORR_PPzPP $p0, $p0, killed $p0, implicit-def $pn8
129+
; EXPAND: $p0 = PEXT_PCI_B killed renamable $pn8, 0
130+
126131
127132
%0:pnr_p8to15 = WHILEGE_CXX_B undef $x0, undef $x0, 0, implicit-def dead $nzcv
128133
@@ -143,7 +148,7 @@ body: |
143148
$pn14 = IMPLICIT_DEF
144149
$pn15 = IMPLICIT_DEF
145150
146-
$pn0 = COPY %0
151+
$p0 = PEXT_PCI_B %0, 0
147152
RET_ReallyLR
148153
...
149154
---

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