LDUR (#295)

* LDUR

* Fix up immediate masking

* Consume operands directly

* Consistency and cleanup

* More consistency and entrypoints

* Cleaner syntax for masks

* Cleaner shifting for encodings

Author: kddnewton

yjit/src/asm/arm64/inst/branches_and_system.rs

@@ -1,8 +1,4 @@
-use super::{
-    super::opnd::*,
-    family::Family,
-    sf::Sf
-};
+use super::family::Family;
 
 /// The struct that represents an A64 branches and system instruction that can
 /// be encoded.
@@ -14,36 +10,32 @@ use super::{
 /// |                                                                             rn.............. rm.............. |
 /// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 ///
-struct BranchesAndSystem {
+pub struct BranchesAndSystem {
     /// The register holding the address to be branched to.
     rn: u8
 }
 
 impl BranchesAndSystem {
     /// RET
     /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/RET--Return-from-subroutine-?lang=en
-    pub fn ret(rn: &A64Opnd) -> Self {
-        match rn {
-            A64Opnd::None => BranchesAndSystem { rn: 30 },
-            A64Opnd::Reg(reg) => BranchesAndSystem { rn: reg.reg_no },
-            _ => panic!("Invalid operand for RET")
-        }
+    pub fn ret(rn: u8) -> Self {
+        Self { rn }
     }
 }
 
 impl From<BranchesAndSystem> for u32 {
-    /// Convert a data processing instruction into a 32-bit value.
+    /// Convert an instruction into a 32-bit value.
     fn from(inst: BranchesAndSystem) -> Self {
         0
         | (0b11 << 30)
-        | (Family::BranchesAndSystem as u32).wrapping_shl(25)
+        | ((Family::BranchesAndSystem as u32) << 25)
         | (0b1001011111 << 16)
-        | (inst.rn as u32).wrapping_shl(5)
+        | ((inst.rn as u32) << 5)
     }
 }
 
 impl From<BranchesAndSystem> for [u8; 4] {
-    /// Convert a data processing instruction into a 4 byte array.
+    /// Convert an instruction into a 4 byte array.
     fn from(inst: BranchesAndSystem) -> [u8; 4] {
         let result: u32 = inst.into();
         result.to_le_bytes()
@@ -56,14 +48,14 @@ mod tests {
 
     #[test]
     fn test_ret() {
-        let inst = BranchesAndSystem::ret(&A64Opnd::None);
+        let inst = BranchesAndSystem::ret(30);
         let result: u32 = inst.into();
         assert_eq!(0xd65f03C0, result);
     }
 
     #[test]
     fn test_ret_rn() {
-        let inst = BranchesAndSystem::ret(&X20);
+        let inst = BranchesAndSystem::ret(20);
         let result: u32 = inst.into();
         assert_eq!(0xd65f0280, result);
     }

yjit/src/asm/arm64/inst/data_processing_immediate.rs

@@ -1,8 +1,4 @@
-use super::{
-    super::opnd::*,
-    family::Family,
-    sf::Sf
-};
+use super::{family::Family, sf::Sf};
 
 /// The operation being performed by this instruction.
 enum Op {
@@ -33,127 +29,106 @@ enum Shift {
 /// +-------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
 ///
 pub struct DataProcessingImmediate {
-    /// Whether or not this instruction is operating on 64-bit operands.
-    sf: Sf,
+    /// The register number of the destination register.
+    rd: u8,
 
-    /// The opcode for this instruction.
-    op: Op,
+    /// The register number of the first operand register.
+    rn: u8,
 
-    /// Whether or not to update the flags when this instruction is performed.
-    s: S,
+    /// The value of the immediate.
+    imm12: u16,
 
     /// How much to shift the immediate by.
     shift: Shift,
 
-    /// The value of the immediate.
-    imm12: u16,
+    /// Whether or not to update the flags when this instruction is performed.
+    s: S,
 
-    /// The register number of the first operand register.
-    rn: u8,
+    /// The opcode for this instruction.
+    op: Op,
 
-    /// The register number of the destination register.
-    rd: u8
+    /// Whether or not this instruction is operating on 64-bit operands.
+    sf: Sf
 }
 
 impl DataProcessingImmediate {
     /// ADD (immediate)
     /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADD--immediate---Add--immediate--?lang=en
-    pub fn add(rd: &A64Opnd, rn: &A64Opnd, imm12: &A64Opnd) -> Self {
-        let (rd, rn, imm12) = Self::unwrap(rd, rn, imm12);
-
+    pub fn add(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
         Self {
-            sf: rd.num_bits.into(),
-            op: Op::Add,
-            s: S::LeaveFlags,
+            rd,
+            rn,
+            imm12,
             shift: Shift::LSL0,
-            imm12: imm12.value as u16,
-            rn: rn.reg_no,
-            rd: rd.reg_no
+            s: S::LeaveFlags,
+            op: Op::Add,
+            sf: num_bits.into()
         }
     }
 
     /// ADDS (immediate, set flags)
     /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/ADDS--immediate---Add--immediate---setting-flags-?lang=en
-    pub fn adds(rd: &A64Opnd, rn: &A64Opnd, imm12: &A64Opnd) -> Self {
-        let (rd, rn, imm12) = Self::unwrap(rd, rn, imm12);
-
+    pub fn adds(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
         Self {
-            sf: rd.num_bits.into(),
-            op: Op::Add,
-            s: S::UpdateFlags,
+            rd,
+            rn,
+            imm12,
             shift: Shift::LSL0,
-            imm12: imm12.value as u16,
-            rn: rn.reg_no,
-            rd: rd.reg_no
+            s: S::UpdateFlags,
+            op: Op::Add,
+            sf: num_bits.into()
         }
     }
 
     /// SUB (immediate)
     /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUB--immediate---Subtract--immediate--?lang=en
-    pub fn sub(rd: &A64Opnd, rn: &A64Opnd, imm12: &A64Opnd) -> Self {
-        let (rd, rn, imm12) = Self::unwrap(rd, rn, imm12);
-
+    pub fn sub(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
         Self {
-            sf: rd.num_bits.into(),
-            op: Op::Sub,
-            s: S::LeaveFlags,
+            rd,
+            rn,
+            imm12,
             shift: Shift::LSL0,
-            imm12: imm12.value as u16,
-            rn: rn.reg_no,
-            rd: rd.reg_no
+            s: S::LeaveFlags,
+            op: Op::Sub,
+            sf: num_bits.into()
         }
     }
 
     /// SUBS (immediate, set flags)
     /// https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/SUBS--immediate---Subtract--immediate---setting-flags-?lang=en
-    pub fn subs(rd: &A64Opnd, rn: &A64Opnd, imm12: &A64Opnd) -> Self {
-        let (rd, rn, imm12) = Self::unwrap(rd, rn, imm12);
-
+    pub fn subs(rd: u8, rn: u8, imm12: u16, num_bits: u8) -> Self {
         Self {
-            sf: rd.num_bits.into(),
-            op: Op::Sub,
-            s: S::UpdateFlags,
+            rd,
+            rn,
+            imm12,
             shift: Shift::LSL0,
-            imm12: imm12.value as u16,
-            rn: rn.reg_no,
-            rd: rd.reg_no
-        }
-    }
-
-    /// Extract out two registers and an immediate from the given operands.
-    /// Panic if any of the operands do not match the expected type or size.
-    fn unwrap<'a>(rd: &'a A64Opnd, rn: &'a A64Opnd, imm12: &'a A64Opnd) -> (&'a A64Reg, &'a A64Reg, &'a A64UImm) {
-        match (rd, rn, imm12) {
-            (A64Opnd::Reg(rd), A64Opnd::Reg(rn), A64Opnd::UImm(imm12)) => {
-                assert!(rd.num_bits == rn.num_bits, "Both rd and rn operands to a data processing immediate instruction must be of the same size.");
-                assert!(imm12.num_bits <= 12, "The immediate operand to a data processing immediate instruction must be 12 bits or less.");
-                (rd, rn, imm12)
-            },
-            _ => {
-                panic!("Expected 2 register operands and an immediate operand for a data processing immediate instruction.");
-            }
+            s: S::UpdateFlags,
+            op: Op::Sub,
+            sf: num_bits.into()
         }
     }
 }
 
 impl From<DataProcessingImmediate> for u32 {
-    /// Convert a data processing instruction into a 32-bit value.
+    /// Convert an instruction into a 32-bit value.
     fn from(inst: DataProcessingImmediate) -> Self {
+        let imm12 = (inst.imm12 as u32) & ((1 << 12) - 1);
+
         0
-        | (inst.sf as u32).wrapping_shl(31)
-        | (inst.op as u32).wrapping_shl(30)
-        | (inst.s as u32).wrapping_shl(29)
-        | (Family::DataProcessingImmediate as u32).wrapping_shl(25)
-        | (0b1 << 24)
-        | (inst.shift as u32).wrapping_shl(22)
-        | (inst.imm12 as u32).wrapping_shl(10)
-        | (inst.rn as u32).wrapping_shl(5)
+        | ((inst.sf as u32) << 31)
+        | ((inst.op as u32) << 30)
+        | ((inst.s as u32) << 29)
+        | ((Family::DataProcessingImmediate as u32) << 25)
+        | (1 << 24)
+        | ((inst.shift as u32) << 22)
+        | (imm12 << 10)
+        | ((inst.rn as u32) << 5)
         | inst.rd as u32
     }
 }
 
 impl From<DataProcessingImmediate> for [u8; 4] {
-    /// Convert a data processing instruction into a 4 byte array.
+    /// Convert an instruction into a 4 byte array.
     fn from(inst: DataProcessingImmediate) -> [u8; 4] {
         let result: u32 = inst.into();
         result.to_le_bytes()
@@ -166,32 +141,28 @@ mod tests {
 
     #[test]
     fn test_add() {
-        let uimm12 = A64Opnd::new_uimm(7);
-        let inst = DataProcessingImmediate::add(&X0, &X1, &uimm12);
+        let inst = DataProcessingImmediate::add(0, 1, 7, 64);
         let result: u32 = inst.into();
         assert_eq!(0x91001c20, result);
     }
 
     #[test]
     fn test_adds() {
-        let uimm12 = A64Opnd::new_uimm(7);
-        let inst = DataProcessingImmediate::adds(&X0, &X1, &uimm12);
+        let inst = DataProcessingImmediate::adds(0, 1, 7, 64);
         let result: u32 = inst.into();
         assert_eq!(0xb1001c20, result);
     }
 
     #[test]
     fn test_sub() {
-        let uimm12 = A64Opnd::new_uimm(7);
-        let inst = DataProcessingImmediate::sub(&X0, &X1, &uimm12);
+        let inst = DataProcessingImmediate::sub(0, 1, 7, 64);
         let result: u32 = inst.into();
         assert_eq!(0xd1001c20, result);
     }
 
     #[test]
     fn test_subs() {
-        let uimm12 = A64Opnd::new_uimm(7);
-        let inst = DataProcessingImmediate::subs(&X0, &X1, &uimm12);
+        let inst = DataProcessingImmediate::subs(0, 1, 7, 64);
         let result: u32 = inst.into();
         assert_eq!(0xf1001c20, result);
     }