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Specify text format for SIMD (#336)
* Specify text format for SIMD * Reword description of SIMD memory instructions Co-authored-by: Ben Smith <[email protected]>
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‎document/core/exec/numerics.rst

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@@ -126,6 +126,7 @@ When a number is stored into :ref:`memory <syntax-mem>`, it is converted into a
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.. math::
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\begin{array}{lll@{\qquad}l}
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\bytes_t(i^\ast) &=& (\bytes_t(i))^\ast \\[1ex]
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\bytes_t(i) &=& \littleendian(\bits_t(i)) \\[1ex]
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\littleendian(\epsilon) &=& \epsilon \\
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\littleendian(d^8~{d'}^\ast~) &=& \littleendian({d'}^\ast)~\ibits_8^{-1}(d^8) \\

‎document/core/syntax/instructions.rst

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@@ -308,6 +308,8 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
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\K{max} \\
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\end{array}
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.. _syntax-simd-shape:
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SIMD instructions have a naming convention involving a prefix that
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determines how their operands will be interpreted.
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This prefix describes the *shape* of the operand,

‎document/core/text/conventions.rst

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@@ -67,7 +67,8 @@ In order to distinguish symbols of the textual syntax from symbols of the abstra
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\text{i32} &\Rightarrow& \I32 \\ &&|&
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\text{i64} &\Rightarrow& \I64 \\ &&|&
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\text{f32} &\Rightarrow& \F32 \\ &&|&
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\text{f64} &\Rightarrow& \F64 \\
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\text{f64} &\Rightarrow& \F64 \\ &&|&
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\text{v128} &\Rightarrow& \V128 \\
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\end{array}
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The :ref:`textual grammar <text-limits>` for :ref:`limits <syntax-limits>` is defined as follows:

‎document/core/text/instructions.rst

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@@ -447,6 +447,304 @@ Numeric Instructions
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\end{array}
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.. index:: simd instruction
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pair: text format; instruction
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.. _text-instr-simd:
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SIMD Instructions
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~~~~~~~~~~~~~~~~~~~~
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SIMD memory instructions have optional offset and alignment immediates, like the :ref:`memory instructions <text-memarg>`.
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.. math::
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\begin{array}{llclll}
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\production{instruction} & \Tplaininstr_I &::=& \dots \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\ &&|&
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\text{v128.load}~~m{:}\Tmemarg_{16} &\Rightarrow& \V128.\LOAD~m \\ &&|&
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\text{i16x8.load8x8\_s}~~m{:}\Tmemarg_8 &\Rightarrow& \I16X8.\LOAD\K{8x8\_s}~m \\ &&|&
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\text{i16x8.load8x8\_u}~~m{:}\Tmemarg_8 &\Rightarrow& \I16X8.\LOAD\K{8x8\_u}~m \\ &&|&
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\text{i32x4.load16x4\_s}~~m{:}\Tmemarg_8 &\Rightarrow& \I32X4.\LOAD\K{16x4\_s}~m \\ &&|&
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\text{i32x4.load16x4\_u}~~m{:}\Tmemarg_8 &\Rightarrow& \I32X4.\LOAD\K{16x4\_u}~m \\ &&|&
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\text{i64x2.load32x2\_s}~~m{:}\Tmemarg_8 &\Rightarrow& \I64X2.\LOAD\K{32x2\_s}~m \\ &&|&
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\text{i64x2.load32x2\_u}~~m{:}\Tmemarg_8 &\Rightarrow& \I64X2.\LOAD\K{32x2\_u}~m \\ &&|&
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\text{i8x16.load\_splat}~~m{:}\Tmemarg_1 &\Rightarrow& \I8X16.\LOAD\K{\_splat}~m \\ &&|&
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\text{i16x8.load\_splat}~~m{:}\Tmemarg_2 &\Rightarrow& \I16X8.\LOAD\K{\_splat}~m \\ &&|&
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\text{i32x4.load\_splat}~~m{:}\Tmemarg_4 &\Rightarrow& \I32X4.\LOAD\K{\_splat}~m \\ &&|&
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\text{i64x2.load\_splat}~~m{:}\Tmemarg_8 &\Rightarrow& \I64X2.\LOAD\K{\_splat}~m \\ &&|&
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\text{v128.store}~~m{:}\Tmemarg_{16} &\Rightarrow& \V128.\STORE~m \\
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\end{array}
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SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descriptor, which determines how the following values are parsed.
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{v128.const}~~\text{i8x16}~~(n{:}\Ti8)^{16} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{i8}(n^{16})) \\ &&|&
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\text{v128.const}~~\text{i16x8}~~(n{:}\Ti16)^{8} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{i16}(n^8)) \\ &&|&
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\text{v128.const}~~\text{i32x4}~~(n{:}\Ti32)^{4} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{i32}(n^4)) \\ &&|&
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\text{v128.const}~~\text{i64x2}~~(n{:}\Ti64)^{2} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{i64}(n^2)) \\ &&|&
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\text{v128.const}~~\text{f32x4}~~(z{:}\Tf32)^{4} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{f32}(z^4)) \\ &&|&
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\text{v128.const}~~\text{f64x2}~~(z{:}\Tf64)^{2} &\Rightarrow& \V128.\VCONST~\bytes_{i128}^{-1}(\bytes_{f64}(z^2)) \\ &&|&
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\text{i8x16.shuffle}~~(laneidx{:}\Tu8)^{16} &\Rightarrow& \I8X16.\SHUFFLE~laneidx^{16} \\ &&|&
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\text{i8x16.swizzle} &\Rightarrow& \I8X16.\SWIZZLE\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i8x16.splat} &\Rightarrow& \I8X16.\SPLAT\\ &&|&
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\text{i16x8.splat} &\Rightarrow& \I16X8.\SPLAT\\ &&|&
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\text{i32x4.splat} &\Rightarrow& \I32X4.\SPLAT\\ &&|&
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\text{i64x2.splat} &\Rightarrow& \I64X2.\SPLAT\\ &&|&
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\text{f32x4.splat} &\Rightarrow& \F32X4.\SPLAT\\ &&|&
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\text{f64x2.splat} &\Rightarrow& \F64X2.\SPLAT\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i8x16.extract\_lane\_s}~~laneidx{:}\Tu8 &\Rightarrow& \I8X16.\EXTRACTLANE\K{\_s}~laneidx \\ &&|&
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\text{i8x16.extract\_lane\_u}~~laneidx{:}\Tu8 &\Rightarrow& \I8X16.\EXTRACTLANE\K{\_u}~laneidx \\ &&|&
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\text{i8x16.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I8X16.\REPLACELANE~laneidx \\ &&|&
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\text{i16x8.extract\_lane\_s}~~laneidx{:}\Tu8 &\Rightarrow& \I16X8.\EXTRACTLANE\K{\_s}~laneidx \\ &&|&
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\text{i16x8.extract\_lane\_u}~~laneidx{:}\Tu8 &\Rightarrow& \I16X8.\EXTRACTLANE\K{\_u}~laneidx \\ &&|&
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\text{i16x8.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I16X8.\REPLACELANE~laneidx \\ &&|&
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\text{i32x4.extract\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I32X4.\EXTRACTLANE~laneidx \\ &&|&
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\text{i32x4.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I32X4.\REPLACELANE~laneidx \\ &&|&
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\text{i64x2.extract\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I64X2.\EXTRACTLANE~laneidx \\ &&|&
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\text{i64x2.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \I64X2.\REPLACELANE~laneidx \\ &&|&
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\text{f32x4.extract\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \F32X4.\EXTRACTLANE~laneidx \\ &&|&
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\text{f32x4.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \F32X4.\REPLACELANE~laneidx \\ &&|&
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\text{f64x2.extract\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \F64X2.\EXTRACTLANE~laneidx \\ &&|&
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\text{f64x2.replace\_lane}~~laneidx{:}\Tu8 &\Rightarrow& \F64X2.\REPLACELANE~laneidx \\
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\end{array}
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.. _text-virelop:
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i8x16.eq} &\Rightarrow& \I8X16.\VEQ\\ &&|&
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\text{i8x16.ne} &\Rightarrow& \I8X16.\VNE\\ &&|&
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\text{i8x16.lt\_s} &\Rightarrow& \I8X16.\VLT\K{\_s}\\ &&|&
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\text{i8x16.lt\_u} &\Rightarrow& \I8X16.\VLT\K{\_u}\\ &&|&
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\text{i8x16.gt\_s} &\Rightarrow& \I8X16.\VGT\K{\_s}\\ &&|&
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\text{i8x16.gt\_u} &\Rightarrow& \I8X16.\VGT\K{\_u}\\ &&|&
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\text{i8x16.le\_s} &\Rightarrow& \I8X16.\VLE\K{\_s}\\ &&|&
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\text{i8x16.le\_u} &\Rightarrow& \I8X16.\VLE\K{\_u}\\ &&|&
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\text{i8x16.ge\_s} &\Rightarrow& \I8X16.\VGE\K{\_s}\\ &&|&
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\text{i8x16.ge\_u} &\Rightarrow& \I8X16.\VGE\K{\_u}\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i16x8.eq} &\Rightarrow& \I16X8.\VEQ\\ &&|&
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\text{i16x8.ne} &\Rightarrow& \I16X8.\VNE\\ &&|&
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\text{i16x8.lt\_s} &\Rightarrow& \I16X8.\VLT\K{\_s}\\ &&|&
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\text{i16x8.lt\_u} &\Rightarrow& \I16X8.\VLT\K{\_u}\\ &&|&
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\text{i16x8.gt\_s} &\Rightarrow& \I16X8.\VGT\K{\_s}\\ &&|&
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\text{i16x8.gt\_u} &\Rightarrow& \I16X8.\VGT\K{\_u}\\ &&|&
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\text{i16x8.le\_s} &\Rightarrow& \I16X8.\VLE\K{\_s}\\ &&|&
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\text{i16x8.le\_u} &\Rightarrow& \I16X8.\VLE\K{\_u}\\ &&|&
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\text{i16x8.ge\_s} &\Rightarrow& \I16X8.\VGE\K{\_s}\\ &&|&
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\text{i16x8.ge\_u} &\Rightarrow& \I16X8.\VGE\K{\_u}\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i32x4.eq} &\Rightarrow& \I32X4.\VEQ\\ &&|&
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\text{i32x4.ne} &\Rightarrow& \I32X4.\VNE\\ &&|&
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\text{i32x4.lt\_s} &\Rightarrow& \I32X4.\VLT\K{\_s}\\ &&|&
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\text{i32x4.lt\_u} &\Rightarrow& \I32X4.\VLT\K{\_u}\\ &&|&
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\text{i32x4.gt\_s} &\Rightarrow& \I32X4.\VGT\K{\_s}\\ &&|&
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\text{i32x4.gt\_u} &\Rightarrow& \I32X4.\VGT\K{\_u}\\ &&|&
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\text{i32x4.le\_s} &\Rightarrow& \I32X4.\VLE\K{\_s}\\ &&|&
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\text{i32x4.le\_u} &\Rightarrow& \I32X4.\VLE\K{\_u}\\ &&|&
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\text{i32x4.ge\_s} &\Rightarrow& \I32X4.\VGE\K{\_s}\\ &&|&
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\text{i32x4.ge\_u} &\Rightarrow& \I32X4.\VGE\K{\_u}\\
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\end{array}
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.. _text-vfrelop:
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{f32x4.eq} &\Rightarrow& \F32X4.\VEQ\\ &&|&
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\text{f32x4.ne} &\Rightarrow& \F32X4.\VNE\\ &&|&
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\text{f32x4.lt} &\Rightarrow& \F32X4.\VLT\\ &&|&
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\text{f32x4.gt} &\Rightarrow& \F32X4.\VGT\\ &&|&
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\text{f32x4.le} &\Rightarrow& \F32X4.\VLE\\ &&|&
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\text{f32x4.ge} &\Rightarrow& \F32X4.\VGE\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{f64x2.eq} &\Rightarrow& \F64X2.\VEQ\\ &&|&
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\text{f64x2.ne} &\Rightarrow& \F64X2.\VNE\\ &&|&
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\text{f64x2.lt} &\Rightarrow& \F64X2.\VLT\\ &&|&
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\text{f64x2.gt} &\Rightarrow& \F64X2.\VGT\\ &&|&
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\text{f64x2.le} &\Rightarrow& \F64X2.\VLE\\ &&|&
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\text{f64x2.ge} &\Rightarrow& \F64X2.\VGE\\
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\end{array}
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.. _text-vsunop:
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.. _text-vsbinop:
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.. _text-vsternop:
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{v128.not} &\Rightarrow& \V128.\VNOT\\ &&|&
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\text{v128.and} &\Rightarrow& \V128.\VAND\\ &&|&
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\text{v128.andnot} &\Rightarrow& \V128.\VANDNOT\\ &&|&
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\text{v128.or} &\Rightarrow& \V128.\VOR\\ &&|&
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\text{v128.xor} &\Rightarrow& \V128.\VXOR\\ &&|&
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\text{v128.bitselect} &\Rightarrow& \V128.\BITSELECT
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\end{array}
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.. _text-vtestop:
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.. _text-vshiftop:
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.. _text-viunop:
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.. _text-vibinop:
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.. _text-viminmaxop:
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.. _text-vsatbinop:
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i8x16.abs} &\Rightarrow& \I8X16.\VABS\\ &&|&
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\text{i8x16.neg} &\Rightarrow& \I8X16.\VNEG\\ &&|&
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\text{i8x16.any\_true} &\Rightarrow& \I8X16.\ANYTRUE\\ &&|&
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\text{i8x16.all\_true} &\Rightarrow& \I8X16.\ALLTRUE\\ &&|&
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\text{i8x16.bitmask} &\Rightarrow& \I8X16.\BITMASK\\ &&|&
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\text{i8x16.narrow\_i16x8\_s} &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_s}\\ &&|&
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\text{i8x16.narrow\_i16x8\_u} &\Rightarrow& \I8X16.\NARROW\K{\_i16x8\_u}\\ &&|&
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\text{i8x16.shl} &\Rightarrow& \I8X16.\VSHL\\ &&|&
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\text{i8x16.shr\_s} &\Rightarrow& \I8X16.\VSHR\K{\_s}\\ &&|&
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\text{i8x16.shr\_u} &\Rightarrow& \I8X16.\VSHR\K{\_u}\\ &&|&
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\text{i8x16.add} &\Rightarrow& \I8X16.\VADD\\ &&|&
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\text{i8x16.add\_sat\_s} &\Rightarrow& \I8X16.\VADD\K{\_sat\_s}\\ &&|&
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\text{i8x16.add\_sat\_u} &\Rightarrow& \I8X16.\VADD\K{\_sat\_u}\\ &&|&
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\text{i8x16.sub} &\Rightarrow& \I8X16.\VSUB\\ &&|&
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\text{i8x16.sub\_sat\_s} &\Rightarrow& \I8X16.\VSUB\K{\_sat\_s}\\ &&|&
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\text{i8x16.sub\_sat\_u} &\Rightarrow& \I8X16.\VSUB\K{\_sat\_u}\\ &&|&
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\text{i8x16.min\_s} &\Rightarrow& \I8X16.\VMIN\K{\_s}\\ &&|&
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\text{i8x16.min\_u} &\Rightarrow& \I8X16.\VMIN\K{\_u}\\ &&|&
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\text{i8x16.max\_s} &\Rightarrow& \I8X16.\VMAX\K{\_s}\\ &&|&
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\text{i8x16.max\_u} &\Rightarrow& \I8X16.\VMAX\K{\_u}\\ &&|&
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\text{i8x16.avgr\_u} &\Rightarrow& \I8X16.\AVGR\K{\_u}\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i16x8.abs} &\Rightarrow& \I16X8.\VABS\\ &&|&
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\text{i16x8.neg} &\Rightarrow& \I16X8.\VNEG\\ &&|&
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\text{i16x8.any\_true} &\Rightarrow& \I16X8.\ANYTRUE\\ &&|&
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\text{i16x8.all\_true} &\Rightarrow& \I16X8.\ALLTRUE\\ &&|&
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\text{i16x8.bitmask} &\Rightarrow& \I16X8.\BITMASK\\ &&|&
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\text{i16x8.narrow\_i32x4\_s} &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s}\\ &&|&
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\text{i16x8.narrow\_i32x4\_u} &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_u}\\ &&|&
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\text{i16x8.widen\_low\_i8x16\_s} &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_s}\\ &&|&
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\text{i16x8.widen\_high\_i8x16\_s} &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_s}\\ &&|&
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\text{i16x8.widen\_low\_i8x16\_u} &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_u}\\ &&|&
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\text{i16x8.widen\_high\_i8x16\_u} &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_u}\\ &&|&
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\text{i16x8.shl} &\Rightarrow& \I16X8.\VSHL\\ &&|&
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\text{i16x8.shr\_s} &\Rightarrow& \I16X8.\VSHR\K{\_s}\\ &&|&
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\text{i16x8.shr\_u} &\Rightarrow& \I16X8.\VSHR\K{\_u}\\ &&|&
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\text{i16x8.add} &\Rightarrow& \I16X8.\VADD\\ &&|&
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\text{i16x8.add\_sat\_s} &\Rightarrow& \I16X8.\VADD\K{\_sat\_s}\\ &&|&
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\text{i16x8.add\_sat\_u} &\Rightarrow& \I16X8.\VADD\K{\_sat\_u}\\ &&|&
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\text{i16x8.sub} &\Rightarrow& \I16X8.\VSUB\\ &&|&
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\text{i16x8.sub\_sat\_s} &\Rightarrow& \I16X8.\VSUB\K{\_sat\_s}\\ &&|&
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\text{i16x8.sub\_sat\_u} &\Rightarrow& \I16X8.\VSUB\K{\_sat\_u}\\ &&|&
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\text{i16x8.mul} &\Rightarrow& \I16X8.\VMUL\\ &&|&
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\text{i16x8.min\_s} &\Rightarrow& \I16X8.\VMIN\K{\_s}\\ &&|&
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\text{i16x8.min\_u} &\Rightarrow& \I16X8.\VMIN\K{\_u}\\ &&|&
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\text{i16x8.max\_s} &\Rightarrow& \I16X8.\VMAX\K{\_s}\\ &&|&
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\text{i16x8.max\_u} &\Rightarrow& \I16X8.\VMAX\K{\_u}\\ &&|&
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\text{i16x8.avgr\_u} &\Rightarrow& \I16X8.\AVGR\K{\_u}\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i32x4.abs} &\Rightarrow& \I32X4.\VABS\\ &&|&
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\text{i32x4.neg} &\Rightarrow& \I32X4.\VNEG\\ &&|&
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\text{i32x4.any\_true} &\Rightarrow& \I32X4.\ANYTRUE\\ &&|&
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\text{i32x4.all\_true} &\Rightarrow& \I32X4.\ALLTRUE\\ &&|&
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\text{i32x4.bitmask} &\Rightarrow& \I32X4.\BITMASK\\ &&|&
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\text{i32x4.widen\_low\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s}\\ &&|&
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\text{i32x4.widen\_high\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s}\\ &&|&
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\text{i32x4.widen\_low\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u}\\ &&|&
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\text{i32x4.widen\_high\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u}\\ &&|&
683+
\text{i32x4.shl} &\Rightarrow& \I32X4.\VSHL\\ &&|&
684+
\text{i32x4.shr\_s} &\Rightarrow& \I32X4.\VSHR\K{\_s}\\ &&|&
685+
\text{i32x4.shr\_u} &\Rightarrow& \I32X4.\VSHR\K{\_u}\\ &&|&
686+
\text{i32x4.add} &\Rightarrow& \I32X4.\VADD\\ &&|&
687+
\text{i32x4.sub} &\Rightarrow& \I32X4.\VSUB\\ &&|&
688+
\text{i32x4.mul} &\Rightarrow& \I32X4.\VMUL\\ &&|&
689+
\text{i32x4.min\_s} &\Rightarrow& \I32X4.\VMIN\K{\_s}\\ &&|&
690+
\text{i32x4.min\_u} &\Rightarrow& \I32X4.\VMIN\K{\_u}\\ &&|&
691+
\text{i32x4.max\_s} &\Rightarrow& \I32X4.\VMAX\K{\_s}\\ &&|&
692+
\text{i32x4.max\_u} &\Rightarrow& \I32X4.\VMAX\K{\_u}\\
693+
\end{array}
694+
695+
.. math::
696+
\begin{array}{llclll}
697+
\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
698+
\text{i64x2.neg} &\Rightarrow& \I64X2.\VNEG\\ &&|&
699+
\text{i64x2.shl} &\Rightarrow& \I64X2.\VSHL\\ &&|&
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\text{i64x2.shr\_s} &\Rightarrow& \I64X2.\VSHR\K{\_s}\\ &&|&
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\text{i64x2.shr\_u} &\Rightarrow& \I64X2.\VSHR\K{\_u}\\ &&|&
702+
\text{i64x2.add} &\Rightarrow& \I64X2.\VADD\\ &&|&
703+
\text{i64x2.sub} &\Rightarrow& \I64X2.\VSUB\\ &&|&
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\text{i64x2.mul} &\Rightarrow& \I64X2.\VMUL\\
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\end{array}
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.. _text-vfunop:
708+
.. _text-vfbinop:
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{f32x4.abs} &\Rightarrow& \F32X4.\VABS\\ &&|&
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\text{f32x4.neg} &\Rightarrow& \F32X4.\VNEG\\ &&|&
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\text{f32x4.sqrt} &\Rightarrow& \F32X4.\VSQRT\\ &&|&
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\text{f32x4.add} &\Rightarrow& \F32X4.\VADD\\ &&|&
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\text{f32x4.sub} &\Rightarrow& \F32X4.\VSUB\\ &&|&
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\text{f32x4.mul} &\Rightarrow& \F32X4.\VMUL\\ &&|&
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\text{f32x4.div} &\Rightarrow& \F32X4.\VDIV\\ &&|&
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\text{f32x4.min} &\Rightarrow& \F32X4.\VMIN\\ &&|&
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\text{f32x4.max} &\Rightarrow& \F32X4.\VMAX\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
727+
\text{f64x2.abs} &\Rightarrow& \F64X2.\VABS\\ &&|&
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\text{f64x2.neg} &\Rightarrow& \F64X2.\VNEG\\ &&|&
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\text{f64x2.sqrt} &\Rightarrow& \F64X2.\VSQRT\\ &&|&
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\text{f64x2.add} &\Rightarrow& \F64X2.\VADD\\ &&|&
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\text{f64x2.sub} &\Rightarrow& \F64X2.\VSUB\\ &&|&
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\text{f64x2.mul} &\Rightarrow& \F64X2.\VMUL\\ &&|&
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\text{f64x2.div} &\Rightarrow& \F64X2.\VDIV\\ &&|&
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\text{f64x2.min} &\Rightarrow& \F64X2.\VMIN\\ &&|&
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\text{f64x2.max} &\Rightarrow& \F64X2.\VMAX\\
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\end{array}
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.. math::
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\begin{array}{llclll}
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\phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
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\text{i32x4.trunc\_sat\_f32x4\_s} &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_s}\\ &&|&
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\text{i32x4.trunc\_sat\_f32x4\_u} &\Rightarrow& \I32X4.\TRUNC\K{\_sat\_f32x4\_u}\\ &&|&
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\text{f32x4.convert\_i32x4\_s} &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_s}\\ &&|&
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\text{f32x4.convert\_i32x4\_u} &\Rightarrow& \F32X4.\CONVERT\K{\_i32x4\_u}\\
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\end{array}
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.. index:: ! folded instruction, S-expression
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.. _text-foldedinstr:
452750

‎document/core/util/macros.def

+2
Original file line numberDiff line numberDiff line change
@@ -652,6 +652,8 @@
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.. |Ts64| mathdef:: \xref{text/values}{text-int}{\TsX{\T{64}}}
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.. |TiN| mathdef:: \xref{text/values}{text-int}{\TiX{N}}
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.. |Ti8| mathdef:: \xref{text/values}{text-int}{\TiX{\T{8}}}
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.. |Ti16| mathdef:: \xref{text/values}{text-int}{\TiX{\T{16}}}
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.. |Ti32| mathdef:: \xref{text/values}{text-int}{\TiX{\T{32}}}
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.. |Ti64| mathdef:: \xref{text/values}{text-int}{\TiX{\T{64}}}
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