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ngzhianngzhian
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[interpreter] Implement SIMD extended multiply instructions
These were accepted into the proposal in #376. There are 12 instructions in total: - i16x8.extmul_{low,high}_i8x16_{s,u} - i32x4.extmul_{low,high}_i16x8_{s,u} - i64x2.extmul_{low,high}_i32x4_{s,u} The implementation is straightforward, widen (using existing operations), then a multiply with the wider shape. The binary opcodes are not decided yet, they currently follow the ones used in V8, when those are finalized, we can change it to match. Added a test generation script that reuses some logic in the generator for arithmetic instructions. Since these instructions have different src and dst shapes, I tweaked the base class to allow for having different shapes.
1 parent 0cd0a20 commit 61ae7cd

15 files changed

+1435
-18
lines changed

‎interpreter/binary/decode.ml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -365,7 +365,11 @@ let simd_prefix s =
365365
| 0x97l -> i16x8_min_u
366366
| 0x98l -> i16x8_max_s
367367
| 0x99l -> i16x8_max_u
368+
| 0x9al -> i16x8_extmul_low_i8x16_s
368369
| 0x9bl -> i16x8_avgr_u
370+
| 0x9dl -> i16x8_extmul_high_i8x16_s
371+
| 0x9el -> i16x8_extmul_low_i8x16_u
372+
| 0x9fl -> i16x8_extmul_high_i8x16_u
369373
| 0xa0l -> i32x4_abs
370374
| 0xa1l -> i32x4_neg
371375
| 0xa3l -> i32x4_all_true
@@ -385,12 +389,20 @@ let simd_prefix s =
385389
| 0xb8l -> i32x4_max_s
386390
| 0xb9l -> i32x4_max_u
387391
| 0xbal -> i32x4_dot_i16x8_s
392+
| 0xbbl -> i32x4_extmul_low_i16x8_s
393+
| 0xbdl -> i32x4_extmul_high_i16x8_s
394+
| 0xbel -> i32x4_extmul_low_i16x8_u
395+
| 0xbfl -> i32x4_extmul_high_i16x8_u
388396
| 0xc1l -> i64x2_neg
389397
| 0xcbl -> i64x2_shl
390398
| 0xccl -> i64x2_shr_s
391399
| 0xcdl -> i64x2_shr_u
392400
| 0xcel -> i64x2_add
393401
| 0xd1l -> i64x2_sub
402+
| 0xd2l -> i64x2_extmul_low_i32x4_s
403+
| 0xd3l -> i64x2_extmul_high_i32x4_s
404+
| 0xd6l -> i64x2_extmul_low_i32x4_u
405+
| 0xd7l -> i64x2_extmul_high_i32x4_u
394406
| 0xd5l -> i64x2_mul
395407
| 0xd8l -> f32x4_ceil
396408
| 0xd9l -> f32x4_floor

‎interpreter/binary/encode.ml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -467,6 +467,10 @@ let encode m =
467467
| Binary (V128 V128Op.(I16x8 MaxS)) -> simd_op 0x98l
468468
| Binary (V128 V128Op.(I16x8 MaxU)) -> simd_op 0x99l
469469
| Binary (V128 V128Op.(I16x8 AvgrU)) -> simd_op 0x9bl
470+
| Binary (V128 V128Op.(I16x8 ExtMulLowS)) -> simd_op 0x9al
471+
| Binary (V128 V128Op.(I16x8 ExtMulHighS)) -> simd_op 0x9dl
472+
| Binary (V128 V128Op.(I16x8 ExtMulLowU)) -> simd_op 0x9el
473+
| Binary (V128 V128Op.(I16x8 ExtMulHighU)) -> simd_op 0x9fl
470474
| Binary (V128 V128Op.(I32x4 Add)) -> simd_op 0xael
471475
| Binary (V128 V128Op.(I32x4 Sub)) -> simd_op 0xb1l
472476
| Binary (V128 V128Op.(I32x4 MinS)) -> simd_op 0xb6l
@@ -485,9 +489,17 @@ let encode m =
485489
| Binary (V128 V128Op.(I32x4 LeU)) -> simd_op 0x3el
486490
| Binary (V128 V128Op.(I32x4 GeS)) -> simd_op 0x3fl
487491
| Binary (V128 V128Op.(I32x4 GeU)) -> simd_op 0x40l
492+
| Binary (V128 V128Op.(I32x4 ExtMulLowS)) -> simd_op 0xbbl
493+
| Binary (V128 V128Op.(I32x4 ExtMulHighS)) -> simd_op 0xbdl
494+
| Binary (V128 V128Op.(I32x4 ExtMulLowU)) -> simd_op 0xbel
495+
| Binary (V128 V128Op.(I32x4 ExtMulHighU)) -> simd_op 0xbfl
488496
| Binary (V128 V128Op.(I64x2 Add)) -> simd_op 0xcel
489497
| Binary (V128 V128Op.(I64x2 Sub)) -> simd_op 0xd1l
490498
| Binary (V128 V128Op.(I64x2 Mul)) -> simd_op 0xd5l
499+
| Binary (V128 V128Op.(I64x2 ExtMulLowS)) -> simd_op 0xd2l
500+
| Binary (V128 V128Op.(I64x2 ExtMulHighS)) -> simd_op 0xd3l
501+
| Binary (V128 V128Op.(I64x2 ExtMulLowU)) -> simd_op 0xd6l
502+
| Binary (V128 V128Op.(I64x2 ExtMulHighU)) -> simd_op 0xd7l
491503
| Binary (V128 V128Op.(F32x4 Eq)) -> simd_op 0x41l
492504
| Binary (V128 V128Op.(F32x4 Ne)) -> simd_op 0x42l
493505
| Binary (V128 V128Op.(F32x4 Lt)) -> simd_op 0x43l

‎interpreter/exec/eval_simd.ml

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Original file line numberDiff line numberDiff line change
@@ -101,6 +101,10 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
101101
| I16x8 MaxS -> SXX.I16x8.max_s
102102
| I16x8 MaxU -> SXX.I16x8.max_u
103103
| I16x8 AvgrU -> SXX.I16x8.avgr_u
104+
| I16x8 ExtMulLowS -> SXX.I16x8_convert.extmul_low_s
105+
| I16x8 ExtMulHighS -> SXX.I16x8_convert.extmul_high_s
106+
| I16x8 ExtMulLowU -> SXX.I16x8_convert.extmul_low_u
107+
| I16x8 ExtMulHighU -> SXX.I16x8_convert.extmul_high_u
104108
| I32x4 Add -> SXX.I32x4.add
105109
| I32x4 Sub -> SXX.I32x4.sub
106110
| I32x4 MinS -> SXX.I32x4.min_s
@@ -119,9 +123,17 @@ module SimdOp (SXX : Simd.S) (Value : ValueType with type t = SXX.t) = struct
119123
| I32x4 GeS -> SXX.I32x4.ge_s
120124
| I32x4 GeU -> SXX.I32x4.ge_u
121125
| I32x4 DotI16x8S -> SXX.I32x4_convert.dot_i16x8_s
126+
| I32x4 ExtMulLowS -> SXX.I32x4_convert.extmul_low_s
127+
| I32x4 ExtMulHighS -> SXX.I32x4_convert.extmul_high_s
128+
| I32x4 ExtMulLowU -> SXX.I32x4_convert.extmul_low_u
129+
| I32x4 ExtMulHighU -> SXX.I32x4_convert.extmul_high_u
122130
| I64x2 Add -> SXX.I64x2.add
123131
| I64x2 Sub -> SXX.I64x2.sub
124132
| I64x2 Mul -> SXX.I64x2.mul
133+
| I64x2 ExtMulLowS -> SXX.I64x2_convert.extmul_low_s
134+
| I64x2 ExtMulHighS -> SXX.I64x2_convert.extmul_high_s
135+
| I64x2 ExtMulLowU -> SXX.I64x2_convert.extmul_low_u
136+
| I64x2 ExtMulHighU -> SXX.I64x2_convert.extmul_high_u
125137
| F32x4 Eq -> SXX.F32x4.eq
126138
| F32x4 Ne -> SXX.F32x4.ne
127139
| F32x4 Lt -> SXX.F32x4.lt

‎interpreter/exec/simd.ml

Lines changed: 34 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -177,6 +177,10 @@ sig
177177
val widen_high_s : t -> t
178178
val widen_low_u : t -> t
179179
val widen_high_u : t -> t
180+
val extmul_low_s : t -> t -> t
181+
val extmul_high_s : t -> t -> t
182+
val extmul_low_u : t -> t -> t
183+
val extmul_high_u : t -> t -> t
180184
end
181185
module I32x4_convert : sig
182186
val trunc_sat_f32x4_s : t -> t
@@ -186,10 +190,20 @@ sig
186190
val widen_low_u : t -> t
187191
val widen_high_u : t -> t
188192
val dot_i16x8_s : t -> t -> t
193+
val extmul_low_s : t -> t -> t
194+
val extmul_high_s : t -> t -> t
195+
val extmul_low_u : t -> t -> t
196+
val extmul_high_u : t -> t -> t
189197
end
190198
module I64x2_convert : sig
191199
val widen_low_s : t -> t
200+
val widen_high_s : t -> t
192201
val widen_low_u : t -> t
202+
val widen_high_u : t -> t
203+
val extmul_low_s : t -> t -> t
204+
val extmul_high_s : t -> t -> t
205+
val extmul_low_u : t -> t -> t
206+
val extmul_high_u : t -> t -> t
193207
end
194208
module F32x4_convert : sig
195209
val convert_i32x4_s : t -> t
@@ -417,6 +431,10 @@ struct
417431
let widen_low_u = widen Lib.List.take 0xffl
418432
let widen_high_u = widen Lib.List.drop 0xffl
419433

434+
let extmul_low_s x y = I16x8.mul (widen_low_s x) (widen_low_s y)
435+
let extmul_high_s x y = I16x8.mul (widen_high_s x) (widen_high_s y)
436+
let extmul_low_u x y = I16x8.mul (widen_low_u x) (widen_low_u y)
437+
let extmul_high_u x y = I16x8.mul (widen_high_u x) (widen_high_u y)
420438
end
421439

422440
module I32x4_convert = struct
@@ -441,16 +459,28 @@ struct
441459
| [], [] -> []
442460
| _, _ -> assert false
443461
in Rep.of_i32x4 (dot xs ys)
462+
463+
let extmul_low_s x y = I32x4.mul (widen_low_s x) (widen_low_s y)
464+
let extmul_high_s x y = I32x4.mul (widen_high_s x) (widen_high_s y)
465+
let extmul_low_u x y = I32x4.mul (widen_low_u x) (widen_low_u y)
466+
let extmul_high_u x y = I32x4.mul (widen_high_u x) (widen_high_u y)
444467
end
445468

446469
module I64x2_convert = struct
447-
let widen mask x =
470+
let widen take_or_drop mask x =
448471
Rep.of_i64x2
449472
(List.map
450473
(fun i32 -> Int64.(logand mask (of_int32 i32)))
451-
(Lib.List.take 2 (Rep.to_i32x4 x)))
452-
let widen_low_s = widen 0xffffffffffffffffL
453-
let widen_low_u = widen 0xffffffffL
474+
(take_or_drop 2 (Rep.to_i32x4 x)))
475+
let widen_low_s = widen Lib.List.take 0xffffffffffffffffL
476+
let widen_high_s = widen Lib.List.drop 0xffffffffffffffffL
477+
let widen_low_u = widen Lib.List.take 0xffffffffL
478+
let widen_high_u = widen Lib.List.drop 0xffffffffL
479+
480+
let extmul_low_s x y = I64x2.mul (widen_low_s x) (widen_low_s y)
481+
let extmul_high_s x y = I64x2.mul (widen_high_s x) (widen_high_s y)
482+
let extmul_low_u x y = I64x2.mul (widen_low_u x) (widen_low_u y)
483+
let extmul_high_u x y = I64x2.mul (widen_high_u x) (widen_high_u y)
454484
end
455485

456486
module F32x4_convert = struct

‎interpreter/syntax/ast.ml

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Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ struct
5555
| Swizzle | Shuffle of int list | NarrowS | NarrowU
5656
| AddSatS | AddSatU | SubSatS | SubSatU
5757
| DotI16x8S
58+
| ExtMulLowS | ExtMulHighS | ExtMulLowU | ExtMulHighU
5859
type funop = Abs | Neg | Sqrt
5960
| Ceil | Floor | Trunc | Nearest
6061
| ConvertI32x4S | ConvertI32x4U

‎interpreter/syntax/operators.ml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,10 @@ let i16x8_min_u = Binary (V128 V128Op.(I16x8 MinU))
340340
let i16x8_max_s = Binary (V128 V128Op.(I16x8 MaxS))
341341
let i16x8_max_u = Binary (V128 V128Op.(I16x8 MaxU))
342342
let i16x8_avgr_u = Binary (V128 V128Op.(I16x8 AvgrU))
343+
let i16x8_extmul_low_i8x16_s = Binary (V128 V128Op.(I16x8 ExtMulLowS))
344+
let i16x8_extmul_high_i8x16_s = Binary (V128 V128Op.(I16x8 ExtMulHighS))
345+
let i16x8_extmul_low_i8x16_u = Binary (V128 V128Op.(I16x8 ExtMulLowU))
346+
let i16x8_extmul_high_i8x16_u = Binary (V128 V128Op.(I16x8 ExtMulHighU))
343347

344348
let i32x4_splat = Convert (V128 V128Op.(I32x4 Splat))
345349
let i32x4_extract_lane imm = SimdExtract (V128Op.I32x4 (ZX, imm))
@@ -375,6 +379,10 @@ let i32x4_mul = Binary (V128 V128Op.(I32x4 Mul))
375379
let i32x4_trunc_sat_f32x4_s = Unary (V128 V128Op.(I32x4 TruncSatF32x4S))
376380
let i32x4_trunc_sat_f32x4_u = Unary (V128 V128Op.(I32x4 TruncSatF32x4U))
377381
let i32x4_dot_i16x8_s = Binary (V128 V128Op.(I32x4 DotI16x8S))
382+
let i32x4_extmul_low_i16x8_s = Binary (V128 V128Op.(I32x4 ExtMulLowS))
383+
let i32x4_extmul_high_i16x8_s = Binary (V128 V128Op.(I32x4 ExtMulHighS))
384+
let i32x4_extmul_low_i16x8_u = Binary (V128 V128Op.(I32x4 ExtMulLowU))
385+
let i32x4_extmul_high_i16x8_u = Binary (V128 V128Op.(I32x4 ExtMulHighU))
378386

379387
let i64x2_splat = Convert (V128 V128Op.(I64x2 Splat))
380388
let i64x2_extract_lane imm = SimdExtract (V128Op.I64x2 (ZX, imm))
@@ -386,6 +394,10 @@ let i64x2_mul = Binary (V128 V128Op.(I64x2 Mul))
386394
let i64x2_shl = SimdShift V128Op.(I64x2 Shl)
387395
let i64x2_shr_s = SimdShift V128Op.(I64x2 ShrS)
388396
let i64x2_shr_u = SimdShift V128Op.(I64x2 ShrU)
397+
let i64x2_extmul_low_i32x4_s = Binary (V128 V128Op.(I64x2 ExtMulLowS))
398+
let i64x2_extmul_high_i32x4_s = Binary (V128 V128Op.(I64x2 ExtMulHighS))
399+
let i64x2_extmul_low_i32x4_u = Binary (V128 V128Op.(I64x2 ExtMulLowU))
400+
let i64x2_extmul_high_i32x4_u = Binary (V128 V128Op.(I64x2 ExtMulHighU))
389401

390402
let f32x4_splat = Convert (V128 V128Op.(F32x4 Splat))
391403
let f32x4_extract_lane imm = SimdExtract (V128Op.F32x4 (ZX, imm))

‎interpreter/text/arrange.ml

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Original file line numberDiff line numberDiff line change
@@ -296,6 +296,10 @@ struct
296296
| I16x8 MaxS -> "i16x8.max_s"
297297
| I16x8 MaxU -> "i16x8.max_u"
298298
| I16x8 AvgrU -> "i16x8.avgr_u"
299+
| I16x8 ExtMulLowS -> "i16x8.extmul_low_i8x16_s"
300+
| I16x8 ExtMulHighS -> "i16x8.extmul_high_i8x16_s"
301+
| I16x8 ExtMulLowU -> "i16x8.extmul_low_i8x16_u"
302+
| I16x8 ExtMulHighU -> "i16x8.extmul_high_i8x16_u"
299303
| I32x4 Add -> "i32x4.add"
300304
| I32x4 Sub -> "i32x4.sub"
301305
| I32x4 Mul -> "i32x4.mul"
@@ -304,9 +308,17 @@ struct
304308
| I32x4 MaxS -> "i32x4.max_s"
305309
| I32x4 MaxU -> "i32x4.max_u"
306310
| I32x4 DotI16x8S -> "i32x4.dot_i16x8_s"
311+
| I32x4 ExtMulLowS -> "i32x4.extmul_low_i16x8_s"
312+
| I32x4 ExtMulHighS -> "i32x4.extmul_high_i16x8_s"
313+
| I32x4 ExtMulLowU -> "i32x4.extmul_low_i16x8_u"
314+
| I32x4 ExtMulHighU -> "i32x4.extmul_high_i16x8_u"
307315
| I64x2 Add -> "i64x2.add"
308316
| I64x2 Sub -> "i64x2.sub"
309317
| I64x2 Mul -> "i64x2.mul"
318+
| I64x2 ExtMulLowS -> "i64x2.extmul_low_i32x4_s"
319+
| I64x2 ExtMulHighS -> "i64x2.extmul_high_i32x4_s"
320+
| I64x2 ExtMulLowU -> "i64x2.extmul_low_i32x4_u"
321+
| I64x2 ExtMulHighU -> "i64x2.extmul_high_i32x4_u"
310322
| F32x4 Eq -> "f32x4.eq"
311323
| F32x4 Ne -> "f32x4.ne"
312324
| F32x4 Lt -> "f32x4.lt"

‎interpreter/text/lexer.mll

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -578,6 +578,19 @@ rule token = parse
578578
| "i32x4.dot_i16x8_s"
579579
{ BINARY i32x4_dot_i16x8_s }
580580

581+
| "i16x8.extmul_low_i8x16_"(sign as s)
582+
{ BINARY (ext s i16x8_extmul_low_i8x16_s i16x8_extmul_low_i8x16_u) }
583+
| "i16x8.extmul_high_i8x16_"(sign as s)
584+
{ BINARY (ext s i16x8_extmul_high_i8x16_s i16x8_extmul_high_i8x16_u) }
585+
| "i32x4.extmul_low_i16x8_"(sign as s)
586+
{ BINARY (ext s i32x4_extmul_low_i16x8_s i32x4_extmul_low_i16x8_u) }
587+
| "i32x4.extmul_high_i16x8_"(sign as s)
588+
{ BINARY (ext s i32x4_extmul_high_i16x8_s i32x4_extmul_high_i16x8_u) }
589+
| "i64x2.extmul_low_i32x4_"(sign as s)
590+
{ BINARY (ext s i64x2_extmul_low_i32x4_s i64x2_extmul_low_i32x4_u) }
591+
| "i64x2.extmul_high_i32x4_"(sign as s)
592+
{ BINARY (ext s i64x2_extmul_high_i32x4_s i64x2_extmul_high_i32x4_u) }
593+
581594
| (simd_shape as s) { SIMD_SHAPE (simd_shape s) }
582595

583596
| name as s { VAR s }

‎test/core/simd/meta/gen_tests.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@
3232
'simd_f64x2_pmin_pmax',
3333
'simd_i32x4_dot_i16x8',
3434
'simd_load_lane',
35+
'simd_ext_mul',
3536
)
3637

3738

‎test/core/simd/meta/simd_arithmetic.py

Lines changed: 17 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -35,14 +35,27 @@ def __str__(self):
3535
def lane(self):
3636
return self.LANE_VALUE.get(self.LANE_TYPE)
3737

38+
@property
39+
def dst_lane(self):
40+
return self.lane
41+
42+
@property
43+
def src_lane(self):
44+
# Used for arithmetic that extends the lane, e.g. i16x8 lanes, which
45+
# are extended multiply to i32x4.
46+
if hasattr(self, 'SRC_LANE_TYPE'):
47+
return self.LANE_VALUE.get(self.SRC_LANE_TYPE)
48+
else:
49+
return self.lane
50+
3851
@property
3952
def normal_unary_op_test_data(self):
40-
lane = self.lane
53+
lane = self.src_lane
4154
return [0, 1, -1, lane.max - 1, lane.min + 1, lane.min, lane.max, lane.mask]
4255

4356
@property
4457
def normal_binary_op_test_data(self):
45-
lane = self.lane
58+
lane = self.src_lane
4659
return [
4760
(0, 0),
4861
(0, 1),
@@ -170,7 +183,7 @@ def get_case_data(self):
170183
for data_group, v128_forms in self.bin_test_data:
171184
for data in data_group:
172185
case_data.append([op_name, [str(data[0]), str(data[1])],
173-
str(o.binary_op(data[0], data[1], self.lane)),
186+
str(o.binary_op(data[0], data[1], self.src_lane, self.dst_lane)),
174187
v128_forms])
175188
for data_group in self.full_bin_test_data:
176189
for data in data_group.get(op_name):
@@ -183,7 +196,7 @@ def get_case_data(self):
183196
for data_group, v128_forms in self.unary_test_data:
184197
for data in data_group:
185198
case_data.append([op_name, [str(data)],
186-
str(o.unary_op(data, self.lane)),
199+
str(o.unary_op(data, self.dst_lane)),
187200
v128_forms])
188201

189202
return case_data

‎test/core/simd/meta/simd_ext_mul.py

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#!/usr/bin/env python3
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""" Base class for generating extended multiply instructions. These
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instructions 2 inputs of the same (narrower) lane shape, multiplies
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corresponding lanes with extension (no overflow/wraparound), producing 1 output
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of a (wider) shape. These instructions can choose to work on the low or high
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halves of the inputs, and perform signed or unsigned multiply.
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Subclasses need to define 3 attributes:
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- LANE_TYPE (this is the output shape)
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- SRC_LANE_TYPE (this is the input (narrower) shape)
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- BINARY_OPS (list of operations)
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"""
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from simd_arithmetic import SimdArithmeticCase
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class SimdExtMulCase(SimdArithmeticCase):
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UNARY_OPS = ()
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@property
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def full_bin_test_data(self):
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return []
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def get_combine_cases(self):
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return ''
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@property
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def bin_test_data(self):
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lane_forms = [self.SRC_LANE_TYPE, self.SRC_LANE_TYPE, self.LANE_TYPE]
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return [(self.normal_binary_op_test_data, lane_forms)]
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@property
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def hex_binary_op_test_data(self):
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return []
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def gen_test_cases(self):
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wast_filename = '../simd_{wide}_extmul_{narrow}.wast'.format(
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wide=self.LANE_TYPE, narrow=self.SRC_LANE_TYPE)
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with open(wast_filename, 'w') as fp:
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fp.write(self.get_all_cases())
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class SimdI16x8ExtMulCase(SimdExtMulCase):
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LANE_TYPE = 'i16x8'
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SRC_LANE_TYPE = 'i8x16'
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BINARY_OPS = ('extmul_low_i8x16_s', 'extmul_high_i8x16_s',
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'extmul_low_i8x16_u', 'extmul_high_i8x16_u')
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class SimdI32x4ExtMulCase(SimdExtMulCase):
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LANE_TYPE = 'i32x4'
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SRC_LANE_TYPE = 'i16x8'
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BINARY_OPS = ('extmul_low_i16x8_s', 'extmul_high_i16x8_s',
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'extmul_low_i16x8_u', 'extmul_high_i16x8_u')
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class SimdI64x2ExtMulCase(SimdExtMulCase):
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LANE_TYPE = 'i64x2'
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SRC_LANE_TYPE = 'i32x4'
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BINARY_OPS = ('extmul_low_i32x4_s', 'extmul_high_i32x4_s',
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'extmul_low_i32x4_u', 'extmul_high_i32x4_u')
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def gen_test_cases():
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simd_i16x8_ext_mul_case = SimdI16x8ExtMulCase()
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simd_i16x8_ext_mul_case.gen_test_cases()
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simd_i32x4_ext_mul_case = SimdI32x4ExtMulCase()
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simd_i32x4_ext_mul_case.gen_test_cases()
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simd_i64x2_ext_mul_case = SimdI64x2ExtMulCase()
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simd_i64x2_ext_mul_case.gen_test_cases()
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if __name__ == '__main__':
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gen_test_cases()

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