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[spectext] Rename integer widen instructions to integer extend
Changes to interpreter will come in a follow-up patch. Fixed #467.
1 parent 958c09b commit 64b8775

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+132
-132
lines changed

‎document/core/appendix/gen-index-instructions.py

+12-12
Original file line numberDiff line numberDiff line change
@@ -446,10 +446,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\I16X8.\BITMASK', r'\hex{FD}~~132', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
447447
Instruction(r'\I16X8.\NARROW\K{\_i16x8\_s}', r'\hex{FD}~~133', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
448448
Instruction(r'\I16X8.\NARROW\K{\_i16x8\_u}', r'\hex{FD}~~134', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-simd-narrow'),
449-
Instruction(r'\I16X8.\WIDEN\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
450-
Instruction(r'\I16X8.\WIDEN\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
451-
Instruction(r'\I16X8.\WIDEN\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
452-
Instruction(r'\I16X8.\WIDEN\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
449+
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_s}', r'\hex{FD}~~135', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
450+
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_s}', r'\hex{FD}~~136', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
451+
Instruction(r'\I16X8.\VEXTEND\K{\_low\_i8x16\_u}', r'\hex{FD}~~137', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
452+
Instruction(r'\I16X8.\VEXTEND\K{\_high\_i8x16\_u}', r'\hex{FD}~~138', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
453453
Instruction(r'\I16X8.\VSHL', r'\hex{FD}~~139', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
454454
Instruction(r'\I16X8.\VSHR\K{\_s}', r'\hex{FD}~~140', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
455455
Instruction(r'\I16X8.\VSHR\K{\_u}', r'\hex{FD}~~141', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
@@ -474,10 +474,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
474474
Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
475475
Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'),
476476
Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
477-
Instruction(r'\I32X4.\WIDEN\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
478-
Instruction(r'\I32X4.\WIDEN\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
479-
Instruction(r'\I32X4.\WIDEN\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
480-
Instruction(r'\I32X4.\WIDEN\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
477+
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
478+
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
479+
Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
480+
Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_u}', r'\hex{FD}~~170', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
481481
Instruction(r'\I32X4.\VSHL', r'\hex{FD}~~171', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
482482
Instruction(r'\I32X4.\VSHR\K{\_s}', r'\hex{FD}~~172', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
483483
Instruction(r'\I32X4.\VSHR\K{\_u}', r'\hex{FD}~~173', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),
@@ -495,10 +495,10 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
495495
Instruction(r'\I64X2.\VABS', r'\hex{FD}~~162', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
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Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
497497
Instruction(r'\I64X2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
498-
Instruction(r'\I64X2.\WIDEN\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
499-
Instruction(r'\I64X2.\WIDEN\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
500-
Instruction(r'\I64X2.\WIDEN\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
501-
Instruction(r'\I64X2.\WIDEN\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-widen'),
498+
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_s}', r'\hex{FD}~~199', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
499+
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_s}', r'\hex{FD}~~200', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
500+
Instruction(r'\I64X2.\VEXTEND\K{\_low\_i32x4\_u}', r'\hex{FD}~~201', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
501+
Instruction(r'\I64X2.\VEXTEND\K{\_high\_i32x4\_u}', r'\hex{FD}~~202', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
502502
Instruction(r'\I64X2.\VSHL', r'\hex{FD}~~203', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
503503
Instruction(r'\I64X2.\VSHR\K{\_s}', r'\hex{FD}~~204', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_s'),
504504
Instruction(r'\I64X2.\VSHR\K{\_u}', r'\hex{FD}~~205', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishr_u'),

‎document/core/appendix/index-instructions.rst

+12-12
Original file line numberDiff line numberDiff line change
@@ -394,10 +394,10 @@ Instruction Binary Opcode Type
394394
:math:`\I16X8.\BITMASK` :math:`\hex{FD}~~132` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
395395
:math:`\I16X8.\NARROW\K{\_i16x8\_s}` :math:`\hex{FD}~~133` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-simd-narrow>`
396396
:math:`\I16X8.\NARROW\K{\_i16x8\_u}` :math:`\hex{FD}~~134` :math:`[\V128~\V128] \to [\V128]` :ref:`validation <valid-vbinop>` :ref:`execution <exec-simd-narrow>`
397-
:math:`\I16X8.\WIDEN\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~135` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
398-
:math:`\I16X8.\WIDEN\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~136` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
399-
:math:`\I16X8.\WIDEN\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~137` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
400-
:math:`\I16X8.\WIDEN\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~138` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
397+
:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_s}` :math:`\hex{FD}~~135` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
398+
:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_s}` :math:`\hex{FD}~~136` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
399+
:math:`\I16X8.\VEXTEND\K{\_low\_i8x16\_u}` :math:`\hex{FD}~~137` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
400+
:math:`\I16X8.\VEXTEND\K{\_high\_i8x16\_u}` :math:`\hex{FD}~~138` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
401401
:math:`\I16X8.\VSHL` :math:`\hex{FD}~~139` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
402402
:math:`\I16X8.\VSHR\K{\_s}` :math:`\hex{FD}~~140` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
403403
:math:`\I16X8.\VSHR\K{\_u}` :math:`\hex{FD}~~141` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`
@@ -422,10 +422,10 @@ Instruction Binary Opcode Type
422422
:math:`\I32X4.\VNEG` :math:`\hex{FD}~~161` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-ineg>`
423423
:math:`\I32X4.\ALLTRUE` :math:`\hex{FD}~~163` :math:`[\V128] \to [\I32]` :ref:`validation <valid-vitestop>` :ref:`execution <exec-vitestop>`
424424
:math:`\I32X4.\BITMASK` :math:`\hex{FD}~~164` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
425-
:math:`\I32X4.\WIDEN\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
426-
:math:`\I32X4.\WIDEN\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~168` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
427-
:math:`\I32X4.\WIDEN\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~169` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
428-
:math:`\I32X4.\WIDEN\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~170` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
425+
:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_s}` :math:`\hex{FD}~~167` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
426+
:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_s}` :math:`\hex{FD}~~168` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
427+
:math:`\I32X4.\VEXTEND\K{\_low\_i16x8\_u}` :math:`\hex{FD}~~169` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
428+
:math:`\I32X4.\VEXTEND\K{\_high\_i16x8\_u}` :math:`\hex{FD}~~170` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
429429
:math:`\I32X4.\VSHL` :math:`\hex{FD}~~171` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
430430
:math:`\I32X4.\VSHR\K{\_s}` :math:`\hex{FD}~~172` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
431431
:math:`\I32X4.\VSHR\K{\_u}` :math:`\hex{FD}~~173` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`
@@ -443,10 +443,10 @@ Instruction Binary Opcode Type
443443
:math:`\I64X2.\VABS` :math:`\hex{FD}~~162` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-iabs>`
444444
:math:`\I64X2.\VNEG` :math:`\hex{FD}~~193` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-vunop>`, :ref:`operator <op-ineg>`
445445
:math:`\I64X2.\BITMASK` :math:`\hex{FD}~~196` :math:`[\V128] \to [\I32]` :ref:`validation <valid-simd-bitmask>` :ref:`execution <exec-simd-bitmask>`
446-
:math:`\I64X2.\WIDEN\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~199` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
447-
:math:`\I64X2.\WIDEN\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~200` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
448-
:math:`\I64X2.\WIDEN\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~201` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
449-
:math:`\I64X2.\WIDEN\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~202` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-widen>`
446+
:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_s}` :math:`\hex{FD}~~199` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
447+
:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_s}` :math:`\hex{FD}~~200` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
448+
:math:`\I64X2.\VEXTEND\K{\_low\_i32x4\_u}` :math:`\hex{FD}~~201` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
449+
:math:`\I64X2.\VEXTEND\K{\_high\_i32x4\_u}` :math:`\hex{FD}~~202` :math:`[\V128] \to [\V128]` :ref:`validation <valid-vunop>` :ref:`execution <exec-simd-extend>`
450450
:math:`\I64X2.\VSHL` :math:`\hex{FD}~~203` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`
451451
:math:`\I64X2.\VSHR\K{\_s}` :math:`\hex{FD}~~204` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_s>`
452452
:math:`\I64X2.\VSHR\K{\_u}` :math:`\hex{FD}~~205` :math:`[\V128~\I32] \to [\V128]` :ref:`validation <valid-vshiftop>` :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishr_u>`

‎document/core/binary/instructions.rst

+12-12
Original file line numberDiff line numberDiff line change
@@ -640,10 +640,10 @@ All other SIMD instructions are plain opcodes without any immediates.
640640
\hex{FD}~~132{:}\Bu32 &\Rightarrow& \I16X8.\BITMASK \\ &&|&
641641
\hex{FD}~~133{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_s} \\ &&|&
642642
\hex{FD}~~134{:}\Bu32 &\Rightarrow& \I16X8.\NARROW\K{\_i32x4\_u} \\ &&|&
643-
\hex{FD}~~135{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_s} \\ &&|&
644-
\hex{FD}~~136{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_s} \\ &&|&
645-
\hex{FD}~~137{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_low\_i8x16\_u} \\ &&|&
646-
\hex{FD}~~138{:}\Bu32 &\Rightarrow& \I16X8.\WIDEN\K{\_high\_i8x16\_u} \\ &&|&
643+
\hex{FD}~~135{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_low\_i8x16\_s} \\ &&|&
644+
\hex{FD}~~136{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_high\_i8x16\_s} \\ &&|&
645+
\hex{FD}~~137{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_low\_i8x16\_u} \\ &&|&
646+
\hex{FD}~~138{:}\Bu32 &\Rightarrow& \I16X8.\VEXTEND\K{\_high\_i8x16\_u} \\ &&|&
647647
\hex{FD}~~139{:}\Bu32 &\Rightarrow& \I16X8.\VSHL \\ &&|&
648648
\hex{FD}~~140{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_s} \\ &&|&
649649
\hex{FD}~~141{:}\Bu32 &\Rightarrow& \I16X8.\VSHR\K{\_u} \\ &&|&
@@ -673,10 +673,10 @@ All other SIMD instructions are plain opcodes without any immediates.
673673
\hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|&
674674
\hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|&
675675
\hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|&
676-
\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s} \\ &&|&
677-
\hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s} \\ &&|&
678-
\hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u} \\ &&|&
679-
\hex{FD}~~170{:}\Bu32 &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u} \\ &&|&
676+
\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s} \\ &&|&
677+
\hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s} \\ &&|&
678+
\hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u} \\ &&|&
679+
\hex{FD}~~170{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_u} \\ &&|&
680680
\hex{FD}~~171{:}\Bu32 &\Rightarrow& \I32X4.\VSHL \\ &&|&
681681
\hex{FD}~~172{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_s} \\ &&|&
682682
\hex{FD}~~173{:}\Bu32 &\Rightarrow& \I32X4.\VSHR\K{\_u} \\ &&|&
@@ -699,10 +699,10 @@ All other SIMD instructions are plain opcodes without any immediates.
699699
\hex{FD}~~162{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|&
700700
\hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
701701
\hex{FD}~~196{:}\Bu32 &\Rightarrow& \I64X2.\BITMASK \\ &&|&
702-
\hex{FD}~~199{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_low\_i32x4\_s} \\ &&|&
703-
\hex{FD}~~200{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_high\_i32x4\_s} \\ &&|&
704-
\hex{FD}~~201{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_low\_i32x4\_u} \\ &&|&
705-
\hex{FD}~~202{:}\Bu32 &\Rightarrow& \I64X2.\WIDEN\K{\_high\_i32x4\_u} \\ &&|&
702+
\hex{FD}~~199{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_low\_i32x4\_s} \\ &&|&
703+
\hex{FD}~~200{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_high\_i32x4\_s} \\ &&|&
704+
\hex{FD}~~201{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_low\_i32x4\_u} \\ &&|&
705+
\hex{FD}~~202{:}\Bu32 &\Rightarrow& \I64X2.\VEXTEND\K{\_high\_i32x4\_u} \\ &&|&
706706
\hex{FD}~~203{:}\Bu32 &\Rightarrow& \I64X2.\VSHL \\ &&|&
707707
\hex{FD}~~204{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_s} \\ &&|&
708708
\hex{FD}~~205{:}\Bu32 &\Rightarrow& \I64X2.\VSHR\K{\_u} \\ &&|&

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