Skip to content
This repository was archived by the owner on Dec 22, 2021. It is now read-only.

Commit 7384f2a

Browse files
committed
i64x2.abs instruction
1 parent b6ca6b2 commit 7384f2a

File tree

4 files changed

+5
-2
lines changed

4 files changed

+5
-2
lines changed

proposals/simd/BinarySIMD.md

+2-1
Original file line numberDiff line numberDiff line change
@@ -179,6 +179,7 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
179179
| `i32x4.max_s` | `0xb8`| - |
180180
| `i32x4.max_u` | `0xb9`| - |
181181
| `i32x4.dot_i16x8_s` | `0xba`| - |
182+
| `i64x2.abs` | `0xc0`| - |
182183
| `i64x2.neg` | `0xc1`| - |
183184
| `i64x2.bitmask` | `0xc4`| - |
184185
| `i64x2.widen_low_i32x4_s` | `0xc7`| - |
@@ -262,4 +263,4 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive).
262263
| `i16x8.extadd_pairwise_i8x16_s` | `TBD`| - |
263264
| `i16x8.extadd_pairwise_i8x16_u` | `TBD`| - |
264265
| `i32x4.extadd_pairwise_i16x8_s` | `TBD`| - |
265-
| `i32x4.extadd_pairwise_i16x8_u` | `TBD`| - |
266+
| `i32x4.extadd_pairwise_i16x8_u` | `TBD`| - |

proposals/simd/ImplementationStatus.md

+1
Original file line numberDiff line numberDiff line change
@@ -149,6 +149,7 @@
149149
| `i32x4.max_u` | `-msimd128` | :heavy_check_mark: | | | :heavy_check_mark: |
150150
| `i32x4.dot_i16x8_s` | | :heavy_check_mark: | | | :heavy_check_mark: |
151151
| `i64x2.eq` | | | | | |
152+
| `i64x2.abs` | | | | | |
152153
| `i64x2.neg` | `-msimd128` | :heavy_check_mark: | | :heavy_check_mark: | :heavy_check_mark: |
153154
| `i64x2.all_true` | | | | | |
154155
| `i64x2.bitmask` | | :heavy_check_mark: | | | |

proposals/simd/NewOpcodes.md

+1-1
Original file line numberDiff line numberDiff line change
@@ -80,7 +80,7 @@
8080

8181
| i8x16 Op | opcode | i16x8 Op | opcode | i32x4 Op | opcode | i64x2 Op | opcode |
8282
| -------------------- | ------ | ------------------------ | ------ | ------------------------ | ------ | ------------------------ | ------ |
83-
| i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | ------------- | 0xc0 |
83+
| i8x16.abs | 0x60 | i16x8.abs | 0x80 | i32x4.abs | 0xa0 | i64x2.abs | 0xc0 |
8484
| i8x16.neg | 0x61 | i16x8.neg | 0x81 | i32x4.neg | 0xa1 | i64x2.neg | 0xc1 |
8585
| ------------- | 0x62 | ------------- | 0x82 | ------------- | 0xa2 | ------------- | 0xc2 |
8686
| i8x16.all_true | 0x63 | i16x8.all_true | 0x83 | i32x4.all_true | 0xa3 | (i64x2.all_true) [TBD] | 0xc3 |

proposals/simd/SIMD.md

+1
Original file line numberDiff line numberDiff line change
@@ -593,6 +593,7 @@ def S.avgr_u(a, b):
593593
* `i8x16.abs(a: v128) -> v128`
594594
* `i16x8.abs(a: v128) -> v128`
595595
* `i32x4.abs(a: v128) -> v128`
596+
* `i64x2.abs(a: v128) -> v128`
596597

597598
Lane-wise wrapping absolute value.
598599

0 commit comments

Comments
 (0)