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[spectext] Add extended pairwise add instructions
This was merged in #380.
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‎document/core/appendix/gen-index-instructions.py

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@@ -470,10 +470,14 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
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Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_s}', r'\hex{FD}~~157', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'),
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Instruction(r'\I16X8.\EXTMUL\K{\_low\_i8x16\_u}', r'\hex{FD}~~158', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'),
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Instruction(r'\I16X8.\EXTMUL\K{\_high\_i8x16\_u}', r'\hex{FD}~~159', r'[\V128~\V128] \to [\V128]', r'valid-simd-vextmul', r'exec-simd-vextmul'),
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Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}', r'\hex{FD}~~194', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
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Instruction(r'\I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}', r'\hex{FD}~~195', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
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Instruction(r'\I32X4.\VABS', r'\hex{FD}~~160', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
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Instruction(r'\I32X4.\VNEG', r'\hex{FD}~~161', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
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Instruction(r'\I32X4.\ALLTRUE', r'\hex{FD}~~163', r'[\V128] \to [\I32]', r'valid-vitestop', r'exec-vitestop'),
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Instruction(r'\I32X4.\BITMASK', r'\hex{FD}~~164', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
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Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}', r'\hex{FD}~~165', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
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Instruction(r'\I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}', r'\hex{FD}~~166', r'[\V128] \to [\V128]', r'valid-simd-extaddpairwise', r'exec-simd-extaddpairwise'),
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Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_s}', r'\hex{FD}~~167', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
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Instruction(r'\I32X4.\VEXTEND\K{\_high\_i16x8\_s}', r'\hex{FD}~~168', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),
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Instruction(r'\I32X4.\VEXTEND\K{\_low\_i16x8\_u}', r'\hex{FD}~~169', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-simd-extend'),

‎document/core/appendix/index-instructions.rst

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‎document/core/binary/instructions.rst

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@@ -663,7 +663,9 @@ All other SIMD instructions are plain opcodes without any immediates.
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\hex{FD}~~156{:}\Bu32 &\Rightarrow& \I16X8.\Q15MULRSAT\K{\_s} \\ &&|&
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\hex{FD}~~157{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_s}\\ &&|&
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\hex{FD}~~158{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_u}\\ &&|&
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\hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\
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\hex{FD}~~159{:}\Bu32 &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ &&|&
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\hex{FD}~~194{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|&
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\hex{FD}~~195{:}\Bu32 &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\
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\end{array}
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.. math::
@@ -673,6 +675,8 @@ All other SIMD instructions are plain opcodes without any immediates.
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\hex{FD}~~161{:}\Bu32 &\Rightarrow& \I32X4.\VNEG \\ &&|&
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\hex{FD}~~163{:}\Bu32 &\Rightarrow& \I32X4.\ALLTRUE \\ &&|&
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\hex{FD}~~164{:}\Bu32 &\Rightarrow& \I32X4.\BITMASK \\ &&|&
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\hex{FD}~~165{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|&
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\hex{FD}~~166{:}\Bu32 &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_u}\\ &&|&
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\hex{FD}~~167{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s} \\ &&|&
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\hex{FD}~~168{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s} \\ &&|&
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\hex{FD}~~169{:}\Bu32 &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u} \\ &&|&

‎document/core/exec/instructions.rst

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@@ -674,7 +674,7 @@ SIMD instructions are defined in terms of generic numeric operators applied lane
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.. _exec-simd-extend:
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:math:`t_2\K{x}N\K{.}\VEXTEND\_\K{low}\_t_1\K{x}M\_\sx`
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.....................................................
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.......................................................
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1. Assert: due to :ref:`validation <valid-vitestop>`, a value of :ref:`value type <syntax-valtype>` |V128| is on the top of the stack.
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@@ -700,7 +700,7 @@ SIMD instructions are defined in terms of generic numeric operators applied lane
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:math:`t_2\K{x}N\K{.}\VEXTEND\_\K{high}\_t_1\K{x}M\_\sx`
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......................................................
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........................................................
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1. Assert: due to :ref:`validation <valid-vitestop>`, a value of :ref:`value type <syntax-valtype>` |V128| is on the top of the stack.
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@@ -776,6 +776,37 @@ SIMD instructions are defined in terms of generic numeric operators applied lane
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\end{array}
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.. _exec-simd-extaddpairwise:
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:math:`t_2\K{x}N\K{.}\EXTADDPAIRWISE\_t_1\K{x}M\_\sx`
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.....................................................
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1. Assert: due to :ref:`validation <valid-vitestop>`, a value of :ref:`value type <syntax-valtype>` |V128| is on the top of the stack.
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2. Pop the value :math:`\V128.\VCONST~c_1` from the stack.
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3. Let :math:`(i_1~i_2)^\ast` be the sequence :math:`\extend^{\sx}_{M,N}(\lanes_{t_1\K{x}M}(c_1))`.
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4. Let :math:`j^\ast` be the result of computing :math:`\iadd_{N}(i_1, i_2)^\ast`.
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5. Let `c` be the result of computing :math:`\lanes^{-1}_{t_2\K{x}N}(j^\ast)`.
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6. Push the value :math:`\V128.\VCONST~c` to the stack.
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.. math::
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\begin{array}{l}
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\begin{array}{lcl@{\qquad}l}
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(\V128\K{.}\VCONST~c_1)~t_2\K{x}N\K{.}\EXTADDPAIRWISE\_t_1\K{x}M\_\sx &\stepto& (\V128\K{.}\VCONST~c) \\
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\end{array}
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\\ \qquad
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\begin{array}[t]{@{}r@{~}l@{}}
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(\iff & (i_1~i_2)^\ast = \extend^{\sx}_{M,N}(\lanes_{t_1\K{x}M}(c_1)) \\
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\wedge & j^\ast = \iadd_{N}(i_1, i_2)^\ast \\
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\wedge & c = \lanes^{-1}_{t_2\K{x}N}(j^\ast)
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\end{array}
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\end{array}
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.. index:: parametric instructions, value
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pair: execution; instruction
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single: abstract syntax; instruction

‎document/core/syntax/instructions.rst

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@@ -266,6 +266,8 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
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\K{i32x4.}\EXTMUL\K{\_high}\K{\_i16x8\_}\sx \\&&|&
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\K{i64x2.}\EXTMUL\K{\_low}\K{\_i32x4\_}\sx ~|~
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\K{i64x2.}\EXTMUL\K{\_high}\K{\_i32x4\_}\sx \\&&|&
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\K{i16x8.}\EXTADDPAIRWISE\K{\_i8x16\_}\sx ~|~
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\K{i32x4.}\EXTADDPAIRWISE\K{\_i16x8\_}\sx \\ &&|&
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\fshape\K{.}\vfbinop \\&&|&
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\K{i32x4.}\VTRUNC\K{\_sat\_f32x4\_}\sx \\ &&|&
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\K{f32x4.}\VCONVERT\K{\_i32x4\_}\sx \\&&|&

‎document/core/text/instructions.rst

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@@ -696,7 +696,9 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
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\text{i16x8.extmul\_low\_i8x16\_s} &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_s}\\ &&|&
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\text{i16x8.extmul\_high\_i8x16\_s} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_s}\\ &&|&
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\text{i16x8.extmul\_low\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_low\_i8x16\_u}\\ &&|&
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\text{i16x8.extmul\_high\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\
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\text{i16x8.extmul\_high\_i8x16\_u} &\Rightarrow& \I16X8.\EXTMUL\K{\_high\_i8x16\_u}\\ &&|&
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\text{i16x8.extadd\_pairwise\_i8x16\_s} &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_s}\\ &&|&
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\text{i16x8.extadd\_pairwise\_i8x16\_u} &\Rightarrow& \I16X8.\EXTADDPAIRWISE\K{\_i8x16\_u}\\
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\end{array}
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.. math::
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\text{i32x4.neg} &\Rightarrow& \I32X4.\VNEG\\ &&|&
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\text{i32x4.all\_true} &\Rightarrow& \I32X4.\ALLTRUE\\ &&|&
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\text{i32x4.bitmask} &\Rightarrow& \I32X4.\BITMASK\\ &&|&
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\text{i32x4.extend\_low\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_s}\\ &&|&
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\text{i32x4.extend\_high\_i16x8\_s} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_s}\\ &&|&
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\text{i32x4.extend\_low\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_low\_i16x8\_u}\\ &&|&
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\text{i32x4.extend\_high\_i16x8\_u} &\Rightarrow& \I32X4.\VEXTEND\K{\_high\_i16x8\_u}\\ &&|&
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\text{i32x4.extadd\_pairwise\_i16x8\_s} &\Rightarrow& \I32X4.\EXTADDPAIRWISE\K{\_i16x8\_s}\\ &&|&
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\text{i32x4.widen\_low\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_s}\\ &&|&
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\text{i32x4.widen\_high\_i16x8\_s} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_s}\\ &&|&
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\text{i32x4.widen\_low\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_low\_i16x8\_u}\\ &&|&
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\text{i32x4.widen\_high\_i16x8\_u} &\Rightarrow& \I32X4.\WIDEN\K{\_high\_i16x8\_u}\\ &&|&
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\text{i32x4.shl} &\Rightarrow& \I32X4.\VSHL\\ &&|&
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\text{i32x4.shr\_s} &\Rightarrow& \I32X4.\VSHR\K{\_s}\\ &&|&
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\text{i32x4.shr\_u} &\Rightarrow& \I32X4.\VSHR\K{\_u}\\ &&|&

‎document/core/util/macros.def

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@@ -429,6 +429,7 @@
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.. |VTRUNC| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{trunc}}
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.. |VCONVERT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{convert}}
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.. |Q15MULRSAT| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{q15mulr\_sat}}
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.. |EXTADDPAIRWISE| mathdef:: \xref{syntax/instructions}{syntax-instr-simd}{\K{extadd\_pairwise}}
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.. Instructions, non-terminals

‎document/core/valid/instructions.rst

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@@ -464,6 +464,20 @@ We also define an auxiliary function to get number of packed numeric types in a
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}
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.. _valid-simd-extaddpairwise:
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:math:`\ishape\K{.}\EXTADDPAIRWISE\K{\_}\ishape\K{\_}\sx`
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.........................................................
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* The instruction is valid with type :math:`[\V128] \to [\V128]`.
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.. math::
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\frac{
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}{
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C \vdashinstr \ishape\K{.}\EXTADDPAIRWISE\K{\_}\ishape\K{\_}\sx : [\V128] \to [\V128]
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}
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.. index:: parametric instructions, value type, polymorphism
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pair: validation; instruction
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single: abstract syntax; instruction

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