diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md
index 16277829d..b4675950a 100644
--- a/proposals/simd/SIMD.md
+++ b/proposals/simd/SIMD.md
@@ -665,6 +665,11 @@ natural alignment.
 
 Load a `v128` vector from the given heap address.
 
+```python
+def S.load(memarg):
+    return S.from_bytes(memory[memarg.offset:memarg.offset + 16])
+```
+
 ### Load and Splat
 
 * `v8x16.load_splat(memarg) -> v128`
@@ -674,6 +679,12 @@ Load a `v128` vector from the given heap address.
 
 Load a single element and splat to all lanes of a `v128` vector.
 
+```python
+def S.load_splat(memarg):
+    val_bytes = memory[memarg.offset:memarg.offset + S.LaneBytes])
+    return S.splat(S.LaneType.from_bytes(val_bytes))
+```
+
 ### Load and Extend
 
 * `i16x8.load8x8_u(memarg) -> v128`: load eight 8-bit integers and zero extend each one to a 16-bit lane
@@ -685,12 +696,32 @@ Load a single element and splat to all lanes of a `v128` vector.
 
 Fetch consequtive integers up to 32-bit wide and produce a vector with lanes up to 64 bits.
 
+```python
+def S.load_extend(ext, memarg):
+    result = S.New()
+    bytes = memory[memarg.offset:memarg.offset + 8])
+    for i in range(S.Lanes):
+        result[i] = ext(S.LaneType.from_bytes(bytes[(i * S.LaneBytes/2):((i+1) * S.LaneBytes/2)]))
+    return result
+
+def S.load_extend_s(memarg):
+    return S.load_extend(Sext, memarg)
+
+def S.load_extend_u(memarg):
+    return S.load_extend(Zext, memarg)
+```
+
 ### Store
 
 * `v128.store(memarg, data: v128)`
 
 Store a `v128` vector to the given heap address.
 
+```python
+def S.store(memarg, a):
+    memory[memarg.offset:memarg.offset + 16] = bytes(a)
+```
+
 ## Floating-point sign bit operations
 
 These floating point operations are simple manipulations of the sign bit. No