diff --git a/document/core/appendix/gen-index-instructions.py b/document/core/appendix/gen-index-instructions.py
index 5daed1211..8bbe203a2 100755
--- a/document/core/appendix/gen-index-instructions.py
+++ b/document/core/appendix/gen-index-instructions.py
@@ -468,6 +468,7 @@ def Instruction(name, opcode, type=None, validation=None, execution=None, operat
     Instruction(r'\I32X4.\VMIN\K{\_u}', r'\hex{FD}~~183', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imin_u'),
     Instruction(r'\I32X4.\VMAX\K{\_s}', r'\hex{FD}~~184', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_s'),
     Instruction(r'\I32X4.\VMAX\K{\_u}', r'\hex{FD}~~185', r'[\V128~\V128] \to [\V128]', r'valid-vbinop', r'exec-vbinop', r'op-imax_u'),
+    Instruction(r'\I64X2.\VABS', r'\hex{FD}~~162', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-iabs'),
     Instruction(r'\I64X2.\VNEG', r'\hex{FD}~~193', r'[\V128] \to [\V128]', r'valid-vunop', r'exec-vunop', r'op-ineg'),
     Instruction(r'\I64X2.\BITMASK', r'\hex{FD}~~196', r'[\V128] \to [\I32]', r'valid-simd-bitmask', r'exec-simd-bitmask'),
     Instruction(r'\I64X2.\VSHL', r'\hex{FD}~~203', r'[\V128~\I32] \to [\V128]', r'valid-vshiftop', r'exec-vshiftop', r'op-ishl'),
diff --git a/document/core/appendix/index-instructions.rst b/document/core/appendix/index-instructions.rst
index 46055cda9..6f12e4794 100644
--- a/document/core/appendix/index-instructions.rst
+++ b/document/core/appendix/index-instructions.rst
@@ -416,6 +416,7 @@ Instruction                                  Binary Opcode          Type
 :math:`\I32X4.\VMIN\K{\_u}`                  :math:`\hex{FD}~~183`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-imin_u>`      
 :math:`\I32X4.\VMAX\K{\_s}`                  :math:`\hex{FD}~~184`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-imax_s>`      
 :math:`\I32X4.\VMAX\K{\_u}`                  :math:`\hex{FD}~~185`  :math:`[\V128~\V128] \to [\V128]`              :ref:`validation <valid-vbinop>`             :ref:`execution <exec-vbinop>`, :ref:`operator <op-imax_u>`      
+:math:`\I64X2.\VABS`                         :math:`\hex{FD}~~162`  :math:`[\V128] \to [\V128]`                    :ref:`validation <valid-vunop>`              :ref:`execution <exec-vunop>`, :ref:`operator <op-iabs>`         
 :math:`\I64X2.\VNEG`                         :math:`\hex{FD}~~193`  :math:`[\V128] \to [\V128]`                    :ref:`validation <valid-vunop>`              :ref:`execution <exec-vunop>`, :ref:`operator <op-ineg>`         
 :math:`\I64X2.\BITMASK`                      :math:`\hex{FD}~~196`  :math:`[\V128] \to [\I32]`                     :ref:`validation <valid-simd-bitmask>`       :ref:`execution <exec-simd-bitmask>`                             
 :math:`\I64X2.\VSHL`                         :math:`\hex{FD}~~203`  :math:`[\V128~\I32] \to [\V128]`               :ref:`validation <valid-vshiftop>`           :ref:`execution <exec-vshiftop>`, :ref:`operator <op-ishl>`      
diff --git a/document/core/binary/instructions.rst b/document/core/binary/instructions.rst
index 291cb5c88..d0dd01582 100644
--- a/document/core/binary/instructions.rst
+++ b/document/core/binary/instructions.rst
@@ -666,6 +666,7 @@ All other SIMD instructions are plain opcodes without any immediates.
 .. math::
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Binstr} &\phantom{::=}& \phantom{\dots} && \phantom{simdhaslongerinstructionnames} \\[-2ex] &&|&
+     \hex{FD}~~162{:}\Bu32 &\Rightarrow& \I64X2.\VABS \\ &&|&
      \hex{FD}~~193{:}\Bu32 &\Rightarrow& \I64X2.\VNEG \\ &&|&
      \hex{FD}~~196{:}\Bu32 &\Rightarrow& \I64X2.\BITMASK \\ &&|&
      \hex{FD}~~203{:}\Bu32 &\Rightarrow& \I64X2.\VSHL \\ &&|&
diff --git a/document/core/syntax/instructions.rst b/document/core/syntax/instructions.rst
index 293d54e26..cf10a67bc 100644
--- a/document/core/syntax/instructions.rst
+++ b/document/core/syntax/instructions.rst
@@ -233,9 +233,9 @@ SIMD instructions provide basic operations over :ref:`values <syntax-value>` of
      \fshape\K{.}\vfrelop \\&&|&
      \K{i8x16.}\viunop ~|~
      \K{i16x8.}\viunop ~|~
-     \K{i32x4.}\viunop \\&&|&
+     \K{i32x4.}\viunop ~|~
+     \K{i64x2.}\viunop \\&&|&
      \K{i8x16.}\VPOPCNT \\&&|&
-     \K{i64x2.}\VNEG \\&&|&
      \fshape\K{.}\vfunop \\&&|&
      \ishape\K{.}\vitestop \\ &&|&
      \ishape\K{.}\BITMASK \\ &&|&
diff --git a/document/core/text/instructions.rst b/document/core/text/instructions.rst
index 0419a3075..ca66fbabf 100644
--- a/document/core/text/instructions.rst
+++ b/document/core/text/instructions.rst
@@ -700,6 +700,7 @@ SIMD const instructions have a mandatory :ref:`shape <syntax-simd-shape>` descri
 .. math::
    \begin{array}{llclll}
    \phantom{\production{instruction}} & \phantom{\Tplaininstr_I} &\phantom{::=}& \phantom{averylonginstructionnameforsimdtext} && \phantom{simdhasreallylonginstructionnames} \\[-2ex] &&|&
+     \text{i64x2.abs} &\Rightarrow& \I64X2.\VABS\\ &&|&
      \text{i64x2.neg} &\Rightarrow& \I64X2.\VNEG\\ &&|&
      \text{i64x2.all\_true} &\Rightarrow& \I64X2.\ALLTRUE\\ &&|&
      \text{i64x2.bitmask} &\Rightarrow& \I64X2.\BITMASK\\ &&|&