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can.h
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/**
* \file
*
* \brief Component description for CAN
*
* Copyright (c) 2019 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#ifndef _SAME51_CAN_COMPONENT_
#define _SAME51_CAN_COMPONENT_
/* ========================================================================== */
/** SOFTWARE API DEFINITION FOR CAN */
/* ========================================================================== */
/** \addtogroup SAME51_CAN Control Area Network */
/*@{*/
#define CAN_U2003
#define REV_CAN 0x321
/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :20; /*!< bit: 0..19 Reserved */
uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */
uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */
uint32_t REL:4; /*!< bit: 28..31 Core Release */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_CREL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */
#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */
#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */
#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos)
#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos))
#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */
#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos)
#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos))
#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */
#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos)
#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos))
#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */
/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_ENDN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */
#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */
#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */
#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos)
#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos))
#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */
/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_MRCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */
#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */
#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */
#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos)
#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos))
#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */
#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */
#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */
#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */
#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos)
#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos)
#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos)
#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos)
#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */
/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */
uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */
uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */
uint32_t :2; /*!< bit: 21..22 Reserved */
uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_DBTP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */
#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */
#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */
#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos)
#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos))
#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */
#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos)
#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos))
#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */
#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos)
#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos))
#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */
#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos)
#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos))
#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */
#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos)
#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */
/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :4; /*!< bit: 0.. 3 Reserved */
uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */
uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */
uint32_t RX:1; /*!< bit: 7 Receive Pin */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TEST_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */
#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */
#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */
#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos)
#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */
#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos)
#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos))
#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */
#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */
#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */
#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */
#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos)
#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos)
#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos)
#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos)
#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */
#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos)
#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */
/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */
uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_RWD_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */
#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */
#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */
#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos)
#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos))
#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */
#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos)
#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos))
#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */
/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t INIT:1; /*!< bit: 0 Initialization */
uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */
uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */
uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */
uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */
uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */
uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */
uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */
uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */
uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */
uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */
uint32_t TXP:1; /*!< bit: 14 Transmit Pause */
uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_CCCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */
#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */
#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */
#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos)
#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */
#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos)
#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */
#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos)
#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */
#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos)
#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */
#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos)
#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */
#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos)
#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */
#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos)
#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */
#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos)
#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */
#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos)
#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */
#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos)
#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */
#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos)
#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */
#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos)
#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */
#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos)
#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */
#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos)
#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */
/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */
uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */
uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_NBTP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */
#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */
#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */
#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos)
#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos))
#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */
#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos)
#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos))
#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */
#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos)
#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos))
#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */
#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos)
#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos))
#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */
/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */
uint32_t :14; /*!< bit: 2..15 Reserved */
uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TSCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */
#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */
#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */
#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos)
#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos))
#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */
#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */
#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */
#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos)
#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos)
#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos)
#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */
#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos)
#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos))
#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */
/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TSCV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */
#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */
#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */
#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos)
#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos))
#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */
/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */
uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TOCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */
#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */
#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */
#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos)
#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */
#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos)
#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos))
#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */
#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */
#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */
#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */
#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos)
#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos)
#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos)
#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos)
#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */
#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos)
#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos))
#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */
/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TOCV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */
#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */
#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */
#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos)
#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos))
#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */
/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */
uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */
uint32_t RP:1; /*!< bit: 15 Receive Error Passive */
uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_ECR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */
#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */
#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */
#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos)
#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos))
#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */
#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos)
#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos))
#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */
#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos)
#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */
#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos)
#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos))
#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */
/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */
uint32_t ACT:2; /*!< bit: 3.. 4 Activity */
uint32_t EP:1; /*!< bit: 5 Error Passive */
uint32_t EW:1; /*!< bit: 6 Warning Status */
uint32_t BO:1; /*!< bit: 7 Bus_Off Status */
uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */
uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */
uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */
uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */
uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */
uint32_t :1; /*!< bit: 15 Reserved */
uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_PSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */
#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */
#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */
#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos))
#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos)
#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */
#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos)
#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos))
#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */
#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */
#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */
#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */
#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos)
#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos)
#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos)
#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos)
#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */
#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos)
#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */
#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos)
#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */
#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos)
#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */
#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos))
#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */
#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */
#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */
#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */
#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */
#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */
#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */
#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */
#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos)
#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */
#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos)
#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */
#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos)
#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */
#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos)
#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */
#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos)
#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */
#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos)
#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos))
#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */
/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */
uint32_t :17; /*!< bit: 15..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_TDCR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */
#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */
#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */
#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos)
#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos))
#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */
#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos)
#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos))
#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */
/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */
uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */
uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */
uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */
uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */
uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */
uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */
uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */
uint32_t HPM:1; /*!< bit: 8 High Priority Message */
uint32_t TC:1; /*!< bit: 9 Timestamp Completed */
uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */
uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */
uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */
uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */
uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */
uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */
uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */
uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */
uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */
uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */
uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */
uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */
uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */
uint32_t EP:1; /*!< bit: 23 Error Passive */
uint32_t EW:1; /*!< bit: 24 Warning Status */
uint32_t BO:1; /*!< bit: 25 Bus_Off Status */
uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */
uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */
uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */
uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_IR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */
#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */
#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */
#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos)
#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */
#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos)
#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */
#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos)
#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */
#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos)
#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */
#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos)
#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */
#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos)
#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */
#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos)
#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */
#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos)
#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */
#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos)
#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */
#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos)
#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */
#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos)
#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */
#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos)
#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */
#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos)
#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */
#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos)
#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */
#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos)
#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */
#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos)
#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */
#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos)
#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */
#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos)
#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */
#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos)
#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */
#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos)
#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */
#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos)
#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */
#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos)
#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */
#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos)
#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */
#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos)
#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */
#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos)
#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */
#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos)
#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */
#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos)
#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */
#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos)
#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */
#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos)
#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */
#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos)
#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */
/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */
uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */
uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */
uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */
uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */
uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */
uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */
uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */
uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */
uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */
uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */
uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */
uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */
uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */
uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */
uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */
uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */
uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */
uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */
uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */
uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */
uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */
uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */
uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */
uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */
uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */
uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */
uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */
uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */
uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_IE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */
#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */
#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */
#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos)
#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */
#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos)
#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */
#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos)
#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */
#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos)
#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */
#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos)
#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */
#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos)
#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */
#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos)
#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */
#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos)
#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */
#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos)
#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */
#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos)
#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */
#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos)
#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */
#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos)
#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */
#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos)
#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */
#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos)
#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */
#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos)
#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */
#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos)
#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */
#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos)
#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */
#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos)
#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */
#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos)
#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */
#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos)
#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */
#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos)
#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */
#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos)
#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */
#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos)
#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */
#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos)
#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */
#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos)
#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */
#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos)
#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */
#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos)
#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */
#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos)
#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */
#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos)
#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */
#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos)
#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */
/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */
uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */
uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */
uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */
uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */
uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */
uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */
uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */
uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */
uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */
uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */
uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */
uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */
uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */
uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */
uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */
uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */
uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */
uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */
uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */
uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */
uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */
uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */
uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */
uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */
uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */
uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */
uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */
uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */
uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */
uint32_t :2; /*!< bit: 30..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_ILS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */
#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */
#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */
#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos)
#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */
#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos)
#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */
#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos)
#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */
#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos)
#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */
#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos)
#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */
#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos)
#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */
#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos)
#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */
#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos)
#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */
#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos)
#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */
#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos)
#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */
#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos)
#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */
#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos)
#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */
#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos)
#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */
#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos)
#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */
#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos)
#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */
#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos)
#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */
#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos)
#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */
#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos)
#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */
#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos)
#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */
#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos)
#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */
#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos)
#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */
#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos)
#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */
#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos)
#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */
#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos)
#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */
#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos)
#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */
#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos)
#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */
#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos)
#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */
#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos)
#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */
#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos)
#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */
#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos)
#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */
/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */
uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */
uint32_t :30; /*!< bit: 2..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_ILE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */
#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */
#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */
#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos)
#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */
#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos)
#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */
/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */
uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */
uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */
uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */
uint32_t :26; /*!< bit: 6..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_GFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */
#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */
#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */
#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos)
#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */
#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos)
#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */
#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos)
#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos))
#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos)
#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos)
#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos)
#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */
#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos)
#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos))
#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */
#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */
#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */
#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos)
#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos)
#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos)
#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */
/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */
uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_SIDFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */
#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */
#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */
#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos)
#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos))
#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */
#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos)
#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos))
#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */
/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */
uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_XIDFC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */
#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */
#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */
#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos)
#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos))
#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */
#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos)
#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos))
#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */
/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */
uint32_t :3; /*!< bit: 29..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_XIDAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */
#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */
#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */
#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos)
#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos))
#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */
/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */
uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */
uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */
uint32_t FLST:1; /*!< bit: 15 Filter List */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} CAN_HPMS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */