@@ -1925,6 +1925,7 @@ def SYCLIntelFPGAMaxConcurrency : DeclOrStmtAttr {
1925
1925
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
1926
1926
let HasCustomTypeTransform = 1;
1927
1927
let Documentation = [SYCLIntelFPGAMaxConcurrencyAttrDocs];
1928
+ let SupportsNonconformingLambdaSyntax = 1;
1928
1929
}
1929
1930
1930
1931
def SYCLIntelFPGALoopCoalesce : StmtAttr {
@@ -1949,6 +1950,15 @@ def SYCLIntelFPGADisableLoopPipelining : DeclOrStmtAttr {
1949
1950
let Documentation = [SYCLIntelFPGADisableLoopPipeliningAttrDocs];
1950
1951
let SupportsNonconformingLambdaSyntax = 1;
1951
1952
}
1953
+ def : MutualExclusions<[SYCLIntelFPGAInitiationInterval,
1954
+ SYCLIntelFPGADisableLoopPipelining]>;
1955
+ def : MutualExclusions<[SYCLIntelFPGAIVDep,
1956
+ SYCLIntelFPGADisableLoopPipelining]>;
1957
+ def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
1958
+ SYCLIntelFPGADisableLoopPipelining]>;
1959
+
1960
+ def : MutualExclusions<[SYCLIntelFPGAMaxConcurrency,
1961
+ SYCLIntelFPGADisableLoopPipelining]>;
1952
1962
1953
1963
def SYCLIntelFPGAMaxInterleaving : StmtAttr {
1954
1964
let Spellings = [CXX11<"intelfpga","max_interleaving">,
@@ -1960,6 +1970,8 @@ def SYCLIntelFPGAMaxInterleaving : StmtAttr {
1960
1970
let HasCustomTypeTransform = 1;
1961
1971
let Documentation = [SYCLIntelFPGAMaxInterleavingAttrDocs];
1962
1972
}
1973
+ def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
1974
+ SYCLIntelFPGAMaxInterleaving]>;
1963
1975
1964
1976
def SYCLIntelFPGASpeculatedIterations : StmtAttr {
1965
1977
let Spellings = [CXX11<"intelfpga","speculated_iterations">,
@@ -1971,6 +1983,8 @@ def SYCLIntelFPGASpeculatedIterations : StmtAttr {
1971
1983
let HasCustomTypeTransform = 1;
1972
1984
let Documentation = [SYCLIntelFPGASpeculatedIterationsAttrDocs];
1973
1985
}
1986
+ def : MutualExclusions<[SYCLIntelFPGADisableLoopPipelining,
1987
+ SYCLIntelFPGASpeculatedIterations]>;
1974
1988
1975
1989
def SYCLIntelFPGANofusion : StmtAttr {
1976
1990
let Spellings = [CXX11<"intel","nofusion">];
@@ -1998,12 +2012,12 @@ def IntelFPGAConstVar : SubsetSubject<Var,
1998
2012
LangAS::opencl_constant)}],
1999
2013
"constant variables">;
2000
2014
2001
- def IntelFPGALocalStaticSlaveMemVar : SubsetSubject<Var,
2015
+ def IntelFPGALocalStaticAgentMemVar : SubsetSubject<Var,
2002
2016
[{S->getKind() != Decl::ImplicitParam &&
2003
2017
S->getKind() != Decl::NonTypeTemplateParm &&
2004
- (S->getStorageClass() == SC_Static ||
2005
- S->hasLocalStorage())}],
2006
- "local variables, static variables, slave memory arguments">;
2018
+ (S->getStorageClass() == SC_Static ||
2019
+ S->hasLocalStorage())}],
2020
+ "local variables, static variables, agent memory arguments">;
2007
2021
2008
2022
def IntelFPGALocalOrStaticVar : SubsetSubject<Var,
2009
2023
[{S->getKind() != Decl::ImplicitParam &&
@@ -2046,7 +2060,7 @@ def IntelFPGAMemory : Attr {
2046
2060
}
2047
2061
}
2048
2062
}];
2049
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2063
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2050
2064
Field], ErrorDiag>;
2051
2065
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2052
2066
let Documentation = [IntelFPGAMemoryAttrDocs];
@@ -2060,23 +2074,26 @@ def IntelFPGARegister : Attr {
2060
2074
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2061
2075
let Documentation = [IntelFPGARegisterAttrDocs];
2062
2076
}
2077
+ def : MutualExclusions<[IntelFPGADoublePump, IntelFPGASinglePump,
2078
+ IntelFPGARegister]>;
2063
2079
2064
2080
// One integral argument.
2065
2081
def IntelFPGABankWidth : Attr {
2066
2082
let Spellings = [CXX11<"intelfpga","bankwidth">,
2067
2083
CXX11<"intel","bankwidth">];
2068
2084
let Args = [ExprArgument<"Value">];
2069
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2085
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2070
2086
Field], ErrorDiag>;
2071
2087
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2072
2088
let Documentation = [IntelFPGABankWidthAttrDocs];
2073
2089
}
2090
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGABankWidth]>;
2074
2091
2075
2092
def IntelFPGANumBanks : Attr {
2076
2093
let Spellings = [CXX11<"intelfpga","numbanks">,
2077
2094
CXX11<"intel","numbanks">];
2078
2095
let Args = [ExprArgument<"Value">];
2079
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2096
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2080
2097
Field], ErrorDiag>;
2081
2098
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2082
2099
let Documentation = [IntelFPGANumBanksAttrDocs];
@@ -2090,6 +2107,7 @@ def IntelFPGAPrivateCopies : InheritableAttr {
2090
2107
let Subjects = SubjectList<[IntelFPGALocalNonConstVar, Field], ErrorDiag>;
2091
2108
let Documentation = [IntelFPGAPrivateCopiesAttrDocs];
2092
2109
}
2110
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGAPrivateCopies]>;
2093
2111
2094
2112
// Two string arguments.
2095
2113
def IntelFPGAMerge : Attr {
@@ -2101,25 +2119,28 @@ def IntelFPGAMerge : Attr {
2101
2119
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2102
2120
let Documentation = [IntelFPGAMergeAttrDocs];
2103
2121
}
2122
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGAMerge]>;
2104
2123
2105
2124
def IntelFPGAMaxReplicates : InheritableAttr {
2106
2125
let Spellings = [CXX11<"intelfpga","max_replicates">,
2107
2126
CXX11<"intel","max_replicates">];
2108
2127
let Args = [ExprArgument<"Value">];
2109
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2128
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2110
2129
Field], ErrorDiag>;
2111
2130
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2112
2131
let Documentation = [IntelFPGAMaxReplicatesAttrDocs];
2113
2132
}
2133
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGAMaxReplicates]>;
2114
2134
2115
2135
def IntelFPGASimpleDualPort : Attr {
2116
2136
let Spellings = [CXX11<"intelfpga","simple_dual_port">,
2117
2137
CXX11<"intel","simple_dual_port">];
2118
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2138
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2119
2139
Field], ErrorDiag>;
2120
2140
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2121
2141
let Documentation = [IntelFPGASimpleDualPortAttrDocs];
2122
2142
}
2143
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGASimpleDualPort]>;
2123
2144
2124
2145
def SYCLFPGAPipe : TypeAttr {
2125
2146
let Spellings = [GNU<"pipe">];
@@ -2141,21 +2162,23 @@ def IntelFPGABankBits : Attr {
2141
2162
let Spellings = [CXX11<"intelfpga", "bank_bits">,
2142
2163
CXX11<"intel", "bank_bits">];
2143
2164
let Args = [VariadicExprArgument<"Args">];
2144
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2165
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2145
2166
Field], ErrorDiag>;
2146
2167
let LangOpts = [SYCLIsDevice, SYCLIsHost];
2147
2168
let Documentation = [IntelFPGABankBitsDocs];
2148
2169
}
2170
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGABankBits]>;
2149
2171
2150
2172
def IntelFPGAForcePow2Depth : InheritableAttr {
2151
2173
let Spellings = [CXX11<"intelfpga","force_pow2_depth">,
2152
2174
CXX11<"intel","force_pow2_depth">];
2153
2175
let Args = [ExprArgument<"Value">];
2154
- let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticSlaveMemVar ,
2176
+ let Subjects = SubjectList<[IntelFPGAConstVar, IntelFPGALocalStaticAgentMemVar ,
2155
2177
Field], ErrorDiag>;
2156
2178
let LangOpts = [SYCLIsDevice, SilentlyIgnoreSYCLIsHost];
2157
2179
let Documentation = [IntelFPGAForcePow2DepthAttrDocs];
2158
2180
}
2181
+ def : MutualExclusions<[IntelFPGARegister, IntelFPGAForcePow2Depth]>;
2159
2182
2160
2183
def Naked : InheritableAttr {
2161
2184
let Spellings = [GCC<"naked">, Declspec<"naked">];
0 commit comments