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mbed_patches: allow lptimer reconfiguration on stm32
1 parent 2aad912 commit b3e2ca7

2 files changed

+219
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lines changed

‎patches/0175-STM32-lpticker-allow-dynamic-configuration.patch

+194
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From ff38953e8e678c697b52ddbe62bc99fe445a1c74 Mon Sep 17 00:00:00 2001
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From: Martino Facchin <[email protected]>
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Date: Thu, 7 Oct 2021 17:00:27 +0200
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Subject: [PATCH 175/176] STM32: lpticker: allow dynamic configuration
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Step1: allow automatic fallback to LSI if LSE is not functional
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Step2: expose two reconfiguration APIs, so the user can check if LSE is precise enough and eventually revert to LSI
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---
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targets/TARGET_STM/lp_ticker.c | 121 ++++++++++++++++++++++-----------
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1 file changed, 83 insertions(+), 38 deletions(-)
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diff --git a/targets/TARGET_STM/lp_ticker.c b/targets/TARGET_STM/lp_ticker.c
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index d5292566e5..6dc806ccf6 100644
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--- a/targets/TARGET_STM/lp_ticker.c
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+++ b/targets/TARGET_STM/lp_ticker.c
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@@ -126,20 +126,35 @@
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LPTIM_HandleTypeDef LptimHandle;
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+static uint8_t using_lse = MBED_CONF_TARGET_LSE_AVAILABLE;
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-const ticker_info_t *lp_ticker_get_info()
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+static const ticker_info_t *lp_ticker_get_info_lse()
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{
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- static const ticker_info_t info = {
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-#if MBED_CONF_TARGET_LSE_AVAILABLE
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+ const static ticker_info_t info = {
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LSE_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK,
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-#else
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+ 16
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+ };
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+ return &info;
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+}
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+
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+static const ticker_info_t *lp_ticker_get_info_lsi()
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+{
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+ const static ticker_info_t info = {
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LSI_VALUE / MBED_CONF_TARGET_LPTICKER_LPTIM_CLOCK,
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-#endif
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16
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};
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return &info;
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}
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+const ticker_info_t *lp_ticker_get_info()
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+{
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+ if (using_lse) {
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+ return lp_ticker_get_info_lse();
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+ } else {
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+ return lp_ticker_get_info_lsi();
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+ }
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+}
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+
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volatile uint8_t lp_Fired = 0;
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/* Flag and stored counter to handle delayed programing at low level */
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volatile bool lp_delayed_prog = false;
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@@ -154,71 +169,101 @@ volatile bool sleep_manager_locked = false;
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static int LPTICKER_inited = 0;
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static void LPTIM_IRQHandler(void);
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-void lp_ticker_init(void)
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-{
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- /* Check if LPTIM is already configured */
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- if (LPTICKER_inited) {
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- lp_ticker_disable_interrupt();
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- return;
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- }
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- LPTICKER_inited = 1;
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-
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- RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
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- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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-
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-#if MBED_CONF_TARGET_LSE_AVAILABLE
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+static void configureClocksLSE(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct,
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+ RCC_OscInitTypeDef* RCC_OscInitStruct){
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/* Enable LSE clock */
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- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
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+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSE;
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#if MBED_CONF_TARGET_LSE_BYPASS
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- RCC_OscInitStruct.LSEState = RCC_LSE_BYPASS;
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+ RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
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#else
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- RCC_OscInitStruct.LSEState = RCC_LSE_ON;
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+ RCC_OscInitStruct->LSEState = RCC_LSE_ON;
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#endif
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- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE;
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/* Select the LSE clock as LPTIM peripheral clock */
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- RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM;
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+ RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM;
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#if (TARGET_STM32L0)
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- RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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+ RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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#else
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#if (LPTIM_MST_BASE == LPTIM1_BASE)
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- RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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+ RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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#elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE)
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- RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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+ RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSE;
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#endif /* LPTIM_MST_BASE == LPTIM1 */
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#endif /* TARGET_STM32L0 */
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-#else /* MBED_CONF_TARGET_LSE_AVAILABLE */
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+}
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+
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+static void configureClocksLSI(RCC_PeriphCLKInitTypeDef* RCC_PeriphCLKInitStruct,
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+ RCC_OscInitTypeDef* RCC_OscInitStruct){
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/* Enable LSI clock */
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#if TARGET_STM32WB
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- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI1;
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+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI1;
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#else
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- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI;
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+ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_LSI;
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#endif
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- RCC_OscInitStruct.LSIState = RCC_LSI_ON;
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- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
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+ RCC_OscInitStruct->LSIState = RCC_LSI_ON;
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+ RCC_OscInitStruct->PLL.PLLState = RCC_PLL_NONE;
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/* Select the LSI clock as LPTIM peripheral clock */
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- RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPTIM;
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+ RCC_PeriphCLKInitStruct->PeriphClockSelection = RCC_PERIPHCLK_LPTIM;
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#if (TARGET_STM32L0)
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- RCC_PeriphCLKInitStruct.LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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+ RCC_PeriphCLKInitStruct->LptimClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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#else
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#if (LPTIM_MST_BASE == LPTIM1_BASE)
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- RCC_PeriphCLKInitStruct.Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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+ RCC_PeriphCLKInitStruct->Lptim1ClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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#elif (LPTIM_MST_BASE == LPTIM3_BASE) || (LPTIM_MST_BASE == LPTIM4_BASE) || (LPTIM_MST_BASE == LPTIM5_BASE)
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- RCC_PeriphCLKInitStruct.Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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+ RCC_PeriphCLKInitStruct->Lptim345ClockSelection = RCC_LPTIMCLKSOURCE_LSI;
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#endif /* LPTIM_MST_BASE == LPTIM1 */
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#endif /* TARGET_STM32L0 */
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+}
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+
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+void lp_ticker_reconfigure_with_lsi() {
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+ lp_ticker_disable_interrupt();
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+ LPTICKER_inited = 0;
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+ using_lse = 0;
145+
+ lp_ticker_init();
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+}
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+
148+
+void lp_ticker_reconfigure_with_lse() {
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+ lp_ticker_disable_interrupt();
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+ LPTICKER_inited = 0;
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+ using_lse = 1;
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+ lp_ticker_init();
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+}
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+
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+void lp_ticker_init(void)
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+{
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+ /* Check if LPTIM is already configured */
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+ if (LPTICKER_inited) {
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+ lp_ticker_disable_interrupt();
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+ return;
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+ }
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+ LPTICKER_inited = 1;
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+
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+ RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = {0};
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+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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+
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+ if (using_lse) {
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+ configureClocksLSE(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct);
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+ } else {
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+ configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct);
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+ }
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-#endif /* MBED_CONF_TARGET_LSE_AVAILABLE */
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#if defined(DUAL_CORE) && (TARGET_STM32H7)
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID)) {
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}
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#endif /* DUAL_CORE */
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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- error("HAL_RCC_OscConfig ERROR\n");
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- return;
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+
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+ // retry with LSI
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+ using_lse = 0;
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+ configureClocksLSI(&RCC_PeriphCLKInitStruct, &RCC_OscInitStruct);
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+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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+ error("HAL_RCC_OscConfig ERROR\n");
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+ return;
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+ }
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}
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) {
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--
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2.37.1
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‎patches/0176-Portenta-use-LSE-for-low-power-ticker.patch

+25
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From 0c7a86e2041971dc3d247c54e85870b6056c03fb Mon Sep 17 00:00:00 2001
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From: Martino Facchin <[email protected]>
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Date: Thu, 7 Oct 2021 17:02:45 +0200
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Subject: [PATCH 176/176] Portenta: use LSE for low power ticker
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---
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targets/targets.json | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/targets/targets.json b/targets/targets.json
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index c998e1d8f0..7274f5d03e 100644
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--- a/targets/targets.json
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+++ b/targets/targets.json
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@@ -3483,7 +3483,7 @@
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"overrides": {
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"system_power_supply": "PWR_SMPS_1V8_SUPPLIES_LDO",
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"clock_source": "USE_PLL_HSE_EXTC",
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- "lse_available": 0,
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+ "lse_available": 1,
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"lpticker_delay_ticks": 0,
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"network-default-interface-type": "ETHERNET",
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"i2c_timing_value_algo": true
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--
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2.37.1
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