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lines changed Original file line number Diff line number Diff line change 52
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// The datasheet specifies a typical SPI SCK period (tSCK) of 42 ns,
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// see "Table 36-48. SPI Timing Characteristics and Requirements",
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// which translates into a maximum SPI clock of 23.8 MHz.
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- // Conservatively, the divider is set for a 12 MHz maximum SPI clock.
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+ // We'll permit use of 24 MHz SPI even though this is slightly out
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+ // of spec. Given how clock dividers work, the next "sensible"
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+ // threshold would be a substantial drop down to 12 MHz.
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#if !defined(MAX_SPI)
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- #define MAX_SPI 12000000
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+ #define MAX_SPI 24000000
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#endif
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#define SPI_MIN_CLOCK_DIVIDER (uint8_t )(1 + ((F_CPU - 1 ) / MAX_SPI))
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#endif
@@ -81,7 +83,7 @@ class SPISettings {
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#if defined(__SAMD51__)
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this ->clockFreq = clock ; // Clipping handled in SERCOM.cpp
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#else
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- this ->clockFreq = ( clock >= ( MAX_SPI * 2 / SPI_MIN_CLOCK_DIVIDER) ? MAX_SPI * 2 / SPI_MIN_CLOCK_DIVIDER : clock ) ;
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+ this ->clockFreq = clock >= MAX_SPI ? MAX_SPI : clock ;
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#endif
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this ->bitOrder = (bitOrder == MSBFIRST ? MSB_FIRST : LSB_FIRST);
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