Remove ASSIGN_TYPE for iadd reg imm generation

This PR complements #4 for generating iadd with immediate
source operand.

Immediates from LLVM IR are mapped to G_CONSTANT in GMIR,
and in the SPIRV implementation, ASSIGN_TYPE is used to assign
the register type to instruction destination. For example, the
following code sequence represents a constant with type assignment:

```
%1:type(s32) = OpTypeInt 16, 0
%11:_(s32) = G_CONSTANT i32 5
%5:anyreg(s32) = ASSIGN_TYPE %11:_(s32), %1:type(s32)
```

With this PR, ASSIGN_TYPE is removed and the type of the G_CONSTANT
destination is set directly from src operand ``i32 5``. New code
sequence is:

```
$11:reg32b(s32) = G_CONSTANT i32 5
```

Author: jfuentes

llvm/lib/Target/pISA/pISAPreLegalizer.cpp

@@ -222,83 +222,6 @@ Register insertAssignInstr(Register Reg, Type *Ty, pISAType *pISATy,
 }
 } // namespace llvm
 
-static void generateAssignInstrs(MachineFunction &MF, pISAGlobalRegistry *GR,
-                                 MachineIRBuilder MIB) {
-  MachineRegisterInfo &MRI = MF.getRegInfo();
-  SmallVector<MachineInstr *, 10> ToErase;
-
-  for (MachineBasicBlock *MBB : post_order(&MF)) {
-    if (MBB->empty())
-      continue;
-
-    bool ReachedBegin = false;
-    for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
-         !ReachedBegin;) {
-      MachineInstr &MI = *MII;
-
-      if (ispISAIntrinsic(MI, Intrinsic::pisa_assign_type)) {
-        Register Reg = MI.getOperand(1).getReg();
-        Type *Ty = getMDOperandAsType(MI.getOperand(2).getMetadata(), 0);
-        MachineInstr *Def = MRI.getVRegDef(Reg);
-        assert(Def && "Expecting an instruction that defines the register");
-        // G_GLOBAL_VALUE already has type info.
-        if (Def->getOpcode() != TargetOpcode::G_GLOBAL_VALUE)
-          insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MF.getRegInfo());
-        ToErase.push_back(&MI);
-      } else if (MI.getOpcode() == TargetOpcode::G_CONSTANT ||
-                 MI.getOpcode() == TargetOpcode::G_FCONSTANT ||
-                 MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR) {
-        // %rc = G_CONSTANT ty Val
-        // ===>
-        // %cty = OpType* ty
-        // %rctmp = G_CONSTANT ty Val
-        // %rc = ASSIGN_TYPE %rctmp, %cty
-        Register Reg = MI.getOperand(0).getReg();
-        if (MRI.hasOneUse(Reg)) {
-          MachineInstr &UseMI = *MRI.use_instr_begin(Reg);
-          if (ispISAIntrinsic(UseMI, Intrinsic::pisa_assign_type) ||
-              ispISAIntrinsic(UseMI, Intrinsic::pisa_assign_name))
-            continue;
-        }
-        Type *Ty = nullptr;
-        if (MI.getOpcode() == TargetOpcode::G_CONSTANT)
-          Ty = MI.getOperand(1).getCImm()->getType();
-        else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT)
-          Ty = MI.getOperand(1).getFPImm()->getType();
-        else {
-          assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR);
-          Type *ElemTy = nullptr;
-          MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg());
-          assert(ElemMI);
-
-          if (ElemMI->getOpcode() == TargetOpcode::G_CONSTANT)
-            ElemTy = ElemMI->getOperand(1).getCImm()->getType();
-          else if (ElemMI->getOpcode() == TargetOpcode::G_FCONSTANT)
-            ElemTy = ElemMI->getOperand(1).getFPImm()->getType();
-          else
-            llvm_unreachable("Unexpected opcode");
-          unsigned NumElts =
-              MI.getNumExplicitOperands() - MI.getNumExplicitDefs();
-          Ty = VectorType::get(ElemTy, NumElts, false);
-        }
-        insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI);
-      } else if (MI.getOpcode() == TargetOpcode::G_TRUNC ||
-                 MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
-                 MI.getOpcode() == TargetOpcode::COPY ||
-                 MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) {
-        propagatepISAType(&MI, GR, MRI, MIB);
-      }
-
-      if (MII == Begin)
-        ReachedBegin = true;
-      else
-        --MII;
-    }
-  }
-  for (MachineInstr *MI : ToErase)
-    MI->eraseFromParent();
-}
-
 static std::pair<Register, unsigned>
 createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI,
                const pISAGlobalRegistry &GR) {
@@ -328,18 +251,28 @@ createNewIdReg(Register ValReg, unsigned Opcode, MachineRegisterInfo &MRI,
 }
 
 static std::pair<Register, unsigned>
-updateDstRegFromOperand(Register DstReg, Register ValReg, unsigned Opcode,
+updateDstRegFromOperand(MachineOperand &Dst, MachineOperand &Src, unsigned Opcode,
                MachineRegisterInfo &MRI, const pISAGlobalRegistry &GR) {
-  pISAType *pISAType = GR.getpISATypeForVReg(ValReg);
-  assert(pISAType && "VReg is expected to have pISA type");
-  auto bitSize = MRI.getType(ValReg).getSizeInBits();
+  unsigned BitSize = 32;
+  if (Src.isReg()) {
+    // Src operand is a virtual register of known bit-width
+    auto SrcReg = Src.getReg();
+    auto pISAType = GR.getpISATypeForVReg(SrcReg);
+    assert(pISAType && "Src is expected to have pISA type");
+    BitSize = MRI.getType(SrcReg).getSizeInBits();
+  } else if (Src.isCImm()) {
+    // Src operand is a constant immediate
+    BitSize = Src.getCImm()->getBitWidth();
+  } else {
+    llvm_unreachable("Src operand can only be a virtual register or immediate");
+  }
 
   LLT NewT = LLT::scalar(32);
   auto GetIdOp = pISA::GET_Reg32b;
   auto DstClass = &pISA::Reg32bRegClass;
 
   // TODO: Handle other bitwidths if needed
-  switch (bitSize) {
+  switch (BitSize) {
   case 16:
     NewT = LLT::scalar(16);
     GetIdOp = pISA::GET_Reg16b;
@@ -354,9 +287,10 @@ updateDstRegFromOperand(Register DstReg, Register ValReg, unsigned Opcode,
     DstClass = &pISA::Reg64bRegClass;
     break;
   default:
-    assert(false && "Bit size not supported for new reg var");
+    llvm_unreachable("Bit size not supported for new reg var");
   }
 
+  auto DstReg = Dst.getReg();
   MRI.setRegClass(DstReg, DstClass);
   MRI.setType(DstReg, NewT);
   MRI.noteNewVirtualRegister(DstReg);
@@ -374,8 +308,8 @@ static void processInstr(MachineInstr &MI, MachineIRBuilder &MIB,
   //    all instructions operands at once.
   unsigned Opc = MI.getOpcode();
   auto NewReg =
-      updateDstRegFromOperand(MI.getOperand(0).getReg(),
-                              MI.getOperand(1).getReg(), Opc, MRI, *GR)
+      updateDstRegFromOperand(MI.getOperand(0),
+                              MI.getOperand(1), Opc, MRI, *GR)
           .first;
 
   MI.getOperand(0).setReg(NewReg);
@@ -397,30 +331,6 @@ static void processInstrsWithTypeFolding(MachineFunction &MF,
         processInstr(MI, MIB, MRI, GR);
     }
   }
-  for (MachineBasicBlock &MBB : MF) {
-    for (MachineInstr &MI : MBB) {
-      // We need to rewrite dst types for ASSIGN_TYPE instrs to be able
-      // to perform tblgen'erated selection and we can't do that on Legalizer
-      // as it operates on gMIR only.
-      if (MI.getOpcode() != pISA::ASSIGN_TYPE)
-        continue;
-      Register SrcReg = MI.getOperand(1).getReg();
-      unsigned Opcode = MRI.getVRegDef(SrcReg)->getOpcode();
-      if (!isTypeFoldingSupported(Opcode))
-        continue;
-      Register DstReg = MI.getOperand(0).getReg();
-      if (MRI.getType(DstReg).isVector())
-        MRI.setRegClass(DstReg, &pISA::Reg32bRegClass);
-      // Don't need to reset type of register holding constant and used in
-      // G_ADDRSPACE_CAST, since it braaks legalizer.
-      if (Opcode == TargetOpcode::G_CONSTANT && MRI.hasOneUse(DstReg)) {
-        MachineInstr &UseMI = *MRI.use_instr_begin(DstReg);
-        if (UseMI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST)
-          continue;
-      }
-      MRI.setType(DstReg, LLT::scalar(32));
-    }
-  }
 }
 
 static void processSwitches(MachineFunction &MF, pISAGlobalRegistry *GR,
@@ -587,7 +497,6 @@ bool pISAPreLegalizer::runOnMachineFunction(MachineFunction &MF) {
   addConstantsToTrack(MF, GR);
   foldConstantsIntoIntrinsics(MF);
   insertBitcasts(MF, GR, MIB);
-  generateAssignInstrs(MF, GR, MIB);
   processSwitches(MF, GR, MIB);
   processInstrsWithTypeFolding(MF, GR, MIB);
 

llvm/test/CodeGen/MIR/pISA/iadd.ll

@@ -0,0 +1,19 @@
+; RUN: llc -march=pisa64 -stop-after=finalize-isel -o %t.mir %s
+; RUN: llc -march=pisa64 -run-pass=none %t.mir -o - | FileCheck %s
+
+; This MIR test if for checking instruction selection for iadd after
+; finalize-isel pass.
+
+; CHECK-LABEL: {{^}}name: test_iadd32
+define i32 @test_iadd32(i32 %a, i32 %b) {
+  ; CHECK: %{{[0-9]+}}:reg32b = iadd32rr %{{[0-9]+}}, %{{[0-9]+}}
+  %result = add i32 %a, %b
+  ret i32 %result
+  }
+
+; CHECK-LABEL: {{^}}name: test_iadd32imm
+define i32 @test_iadd32imm(i32 %a) {
+  ; CHECK: %{{[0-9]+}}:reg32b = iadd32ri %{{[0-9]+}}, 5
+  %result = add i32 %a, 5
+  ret i32 %result
+}

llvm/test/CodeGen/pISA/iadd-fadd.ll renamed to llvm/test/CodeGen/pISA/iadd.ll

@@ -22,4 +22,29 @@ define i16 @test_iadd16(i16 %a, i16 %b) {
 ; ADD-NEXT:   return [[RES]]
   %result = add i16 %a, %b
   ret i16 %result
-}
+}
+
+; CHECK-LABEL: @test_iadd64imm
+define i64 @test_iadd64imm(i64 %a) {
+; ADD:        iadd.64b [[RES:%r[0-9]+]], %r{{[0-9]+}}, 5
+; ADD-NEXT:   return [[RES]]
+  %result = add i64 %a, 5
+  ret i64 %result
+}
+
+; CHECK-LABEL: @test_iadd32imm
+define i32 @test_iadd32imm(i32 %a) {
+; ADD:        iadd.32b [[RES:%r[0-9]+]], %r{{[0-9]+}}, 5
+; ADD-NEXT:   return [[RES]]
+  %result = add i32 %a, 5
+  ret i32 %result
+}
+
+; CHECK-LABEL: @test_iadd16imm
+define i16 @test_iadd16imm(i16 %a) {
+; ADD:        iadd.16b [[RES:%r[0-9]+]], %r{{[0-9]+}}, 5
+; ADD-NEXT:   return [[RES]]
+  %result = add i16 %a, 5
+  ret i16 %result
+}
+