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iclsrc
committed
Merge from 'sycl' to 'sycl-web' (#1)
2 parents 07b7ea9 + 4fed824 commit 3246c4b

28 files changed

+103
-73
lines changed

‎clang/include/clang/Driver/Options.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5493,7 +5493,8 @@ def fopenmp_host_ir_file_path : Separate<["-"], "fopenmp-host-ir-file-path">,
54935493

54945494
def fsycl_is_device : Flag<["-"], "fsycl-is-device">,
54955495
HelpText<"Generate code for SYCL device.">,
5496-
MarshallingInfoFlag<LangOpts<"SYCLIsDevice">>;
5496+
MarshallingInfoFlag<LangOpts<"SYCLIsDevice">>,
5497+
ShouldParseIf<fsycl.KeyPath>;
54975498
def fsycl_is_host : Flag<["-"], "fsycl-is-host">,
54985499
HelpText<"SYCL host compilation">,
54995500
MarshallingInfoFlag<LangOpts<"SYCLIsHost">>;

‎clang/lib/Driver/ToolChains/SYCL.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -350,10 +350,10 @@ void SYCL::fpga::BackendCompiler::ConstructJob(
350350
if (types::isSrcFile(Ty) || Ty == types::TY_Object) {
351351
// The project report is created in CWD, so strip off any directory
352352
// information if provided with the input file.
353-
ArgName = llvm::sys::path::filename(ArgName);
353+
StringRef TrimmedArgName = llvm::sys::path::filename(ArgName);
354354
if (types::isSrcFile(Ty)) {
355355
SmallString<128> DepName(
356-
C.getDriver().getFPGATempDepFile(std::string(ArgName)));
356+
C.getDriver().getFPGATempDepFile(std::string(TrimmedArgName)));
357357
if (!DepName.empty())
358358
FPGADepFiles.push_back(InputInfo(types::TY_Dependencies,
359359
Args.MakeArgString(DepName),

‎clang/test/Driver/sycl-offload-intelfpga.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,7 @@
347347
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
348348
// RUN: %clang_cl -### -fsycl -fintelfpga %t_dir/dummy.cpp 2>&1 \
349349
// RUN: | FileCheck -DOUTDIR=%t_dir -check-prefix=CHK-FPGA-REPORT-OPT2 %s
350-
// CHK-FPGA-REPORT-OPT2: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d" "-output-report-folder=dummy.prj"
350+
// CHK-FPGA-REPORT-OPT2: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d" "-output-report-folder={{.*}}dummy.prj"
351351
// CHK-FPGA-REPORT-OPT2-NOT: aoc{{.*}} "-sycl" {{.*}}_dir{{.*}}
352352

353353
/// -fintelfpga dependency files from multiple source
@@ -356,7 +356,7 @@
356356
// RUN: | FileCheck -check-prefix=CHK-FPGA-MULTI-DEPS %s
357357
// RUN: %clang_cl -### -fsycl -fintelfpga %t_dir/dummy.cpp dummy2.cpp 2>&1 \
358358
// RUN: | FileCheck -check-prefix=CHK-FPGA-MULTI-DEPS %s
359-
// CHK-FPGA-MULTI-DEPS: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d,{{.+}}dummy2-{{.+}}.d" "-output-report-folder=dummy.prj"
359+
// CHK-FPGA-MULTI-DEPS: aoc{{.*}} "-sycl"{{.*}} "-dep-files={{.+}}dummy-{{.+}}.d,{{.+}}dummy2-{{.+}}.d" "-output-report-folder={{.*}}dummy.prj"
360360

361361
/// -fintelfpga output report file should be based on first input (src/obj)
362362
// RUN: mkdir -p %t_dir
@@ -372,7 +372,7 @@
372372
// RUN: | FileCheck -check-prefix=CHK-FPGA-REPORT-NAME %s
373373
// RUN: %clang_cl -### -fsycl -fintelfpga %t_dir/dummy2.cpp %t_dir/dummy1.o 2>&1 \
374374
// RUN: | FileCheck -check-prefix=CHK-FPGA-REPORT-NAME %s
375-
// CHK-FPGA-REPORT-NAME: aoc{{.*}} "-sycl"{{.*}} "-output-report-folder=dummy2.prj"
375+
// CHK-FPGA-REPORT-NAME: aoc{{.*}} "-sycl"{{.*}} "-output-report-folder={{.*}}dummy2.prj"
376376

377377
/// Check for implied options (-g -O0)
378378
// RUN: %clang -### -target x86_64-unknown-linux-gnu -fsycl -fintelfpga -g -O0 -Xs "-DFOO1 -DFOO2" %s 2>&1 \

‎llvm-spirv/.github/workflows/check-in-tree-build.yml

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ jobs:
6565
uses: actions/checkout@v2
6666
with:
6767
repository: llvm/llvm-project
68-
ref: master
68+
ref: main
6969
path: llvm-project
7070
- name: Checkout the translator sources
7171
uses: actions/checkout@v2
@@ -110,7 +110,7 @@ jobs:
110110
uses: actions/checkout@v2
111111
with:
112112
repository: llvm/llvm-project
113-
ref: master
113+
ref: main
114114
path: llvm-project
115115
- name: Checkout the translator sources
116116
uses: actions/checkout@v2
@@ -152,7 +152,7 @@ jobs:
152152
uses: actions/checkout@v2
153153
with:
154154
repository: llvm/llvm-project
155-
ref: master
155+
ref: main
156156
path: llvm-project
157157
- name: Checkout the translator sources
158158
uses: actions/checkout@v2

‎llvm-spirv/README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ The files/directories related to the translator:
2222
## Build Instructions
2323

2424
The `master` branch of this repo is aimed to be buildable with the latest
25-
LLVM `master` revision.
25+
LLVM `main` revision.
2626

2727
### Build with pre-installed LLVM
2828

@@ -187,7 +187,7 @@ More information can be found in
187187
## Branching strategy
188188
189189
Code on the master branch in this repository is intended to be compatible with
190-
the master branch of the [llvm](https://github.com/llvm/llvm-project)
190+
the main branch of the [llvm](https://github.com/llvm/llvm-project)
191191
project. That is, for an OpenCL kernel compiled to llvm bitcode by the latest
192192
git revision of Clang it should be possible to translate it to SPIR-V with the
193193
llvm-spirv tool.

‎llvm-spirv/include/LLVMSPIRVExtensions.inc

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,7 @@ EXT(SPV_INTEL_arbitrary_precision_integers)
2222
EXT(SPV_INTEL_optimization_hints)
2323
EXT(SPV_INTEL_float_controls2)
2424
EXT(SPV_INTEL_vector_compute)
25+
EXT(SPV_INTEL_fast_composite)
2526
EXT(SPV_INTEL_usm_storage_classes)
2627
EXT(SPV_INTEL_fpga_buffer_location)
2728
EXT(SPV_INTEL_arbitrary_precision_fixed_point)

‎llvm-spirv/lib/SPIRV/LLVMToSPIRVDbgTran.cpp

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -437,6 +437,21 @@ SPIRVWord transDebugFlags(const DINode *DN) {
437437
return Flags;
438438
}
439439

440+
/// Clang doesn't emit access flags for members with default access specifier
441+
/// See clang/lib/CodeGen/CGDebugInfo.cpp: getAccessFlag()
442+
/// In SPIR-V we set the flags even for members with default access specifier
443+
SPIRVWord adjustAccessFlags(DIScope *Scope, SPIRVWord Flags) {
444+
if (Scope && (Flags & SPIRVDebug::FlagAccess) == 0) {
445+
unsigned Tag = Scope->getTag();
446+
if (Tag == dwarf::DW_TAG_class_type)
447+
Flags |= SPIRVDebug::FlagIsPrivate;
448+
else if (Tag == dwarf::DW_TAG_structure_type ||
449+
Tag == dwarf::DW_TAG_union_type)
450+
Flags |= SPIRVDebug::FlagIsPublic;
451+
}
452+
return Flags;
453+
}
454+
440455
/// The following methods (till the end of the file) implement translation of
441456
/// debug instrtuctions described in the spec.
442457

@@ -666,7 +681,7 @@ SPIRVEntry *LLVMToSPIRVDbgTran::transDbgMemberType(const DIDerivedType *MT) {
666681
Ops[OffsetIdx] = SPIRVWriter->transValue(Offset, nullptr)->getId();
667682
ConstantInt *Size = getUInt(M, MT->getSizeInBits());
668683
Ops[SizeIdx] = SPIRVWriter->transValue(Size, nullptr)->getId();
669-
Ops[FlagsIdx] = transDebugFlags(MT);
684+
Ops[FlagsIdx] = adjustAccessFlags(MT->getScope(), transDebugFlags(MT));
670685
if (MT->isStaticMember()) {
671686
if (llvm::Constant *C = MT->getConstant()) {
672687
SPIRVValue *Val = SPIRVWriter->transValue(C, nullptr);
@@ -816,7 +831,7 @@ SPIRVEntry *LLVMToSPIRVDbgTran::transDbgFunction(const DISubprogram *Func) {
816831
else
817832
Ops[ParentIdx] = getScope(Scope)->getId();
818833
Ops[LinkageNameIdx] = BM->getString(Func->getLinkageName().str())->getId();
819-
Ops[FlagsIdx] = transDebugFlags(Func);
834+
Ops[FlagsIdx] = adjustAccessFlags(Scope, transDebugFlags(Func));
820835

821836
SPIRVEntry *DebugFunc = nullptr;
822837
if (!Func->isDefinition()) {

‎llvm-spirv/lib/SPIRV/PreprocessMetadata.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -328,10 +328,7 @@ void PreprocessMetadata::preprocessVectorComputeMetadata(Module *M,
328328
.done();
329329
}
330330
if (Attrs.hasFnAttribute(kVCMetadata::VCFCEntry)) {
331-
EM.addOp()
332-
.add(&F)
333-
.add(spv::ExecutionModeVectorComputeFastCompositeKernelINTEL)
334-
.done();
331+
EM.addOp().add(&F).add(spv::ExecutionModeFastCompositeKernelINTEL).done();
335332
}
336333
}
337334
}

‎llvm-spirv/lib/SPIRV/SPIRVReader.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3906,6 +3906,12 @@ bool SPIRVToLLVM::transMetadata() {
39063906
transVectorComputeMetadata(BF);
39073907
transFPGAFunctionMetadata(BF, F);
39083908

3909+
if (BF->hasDecorate(DecorationCallableFunctionINTEL))
3910+
F->addFnAttr(kVCMetadata::VCCallable);
3911+
if (isKernel(BF) &&
3912+
BF->getExecutionMode(ExecutionModeFastCompositeKernelINTEL))
3913+
F->addFnAttr(kVCMetadata::VCFCEntry);
3914+
39093915
if (F->getCallingConv() != CallingConv::SPIR_KERNEL)
39103916
continue;
39113917

@@ -4084,11 +4090,6 @@ bool SPIRVToLLVM::transVectorComputeMetadata(SPIRVFunction *BF) {
40844090
SPIRVWord SIMTMode = 0;
40854091
if (BF->hasDecorate(DecorationSIMTCallINTEL, 0, &SIMTMode))
40864092
F->addFnAttr(kVCMetadata::VCSIMTCall, std::to_string(SIMTMode));
4087-
if (BF->hasDecorate(DecorationVectorComputeCallableFunctionINTEL))
4088-
F->addFnAttr(kVCMetadata::VCCallable);
4089-
if (isKernel(BF) &&
4090-
BF->getExecutionMode(ExecutionModeVectorComputeFastCompositeKernelINTEL))
4091-
F->addFnAttr(kVCMetadata::VCFCEntry);
40924093

40934094
auto SEVAttr = Attribute::get(*Context, kVCMetadata::VCSingleElementVector);
40944095
if (BF->hasDecorate(DecorationSingleElementVectorINTEL))

‎llvm-spirv/lib/SPIRV/SPIRVWriter.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -619,6 +619,11 @@ SPIRVFunction *LLVMToSPIRV::transFunctionDecl(Function *F) {
619619
BF->addDecorate(DecorationReferencedIndirectlyINTEL);
620620
}
621621

622+
if (Attrs.hasFnAttribute(kVCMetadata::VCCallable) &&
623+
BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite)) {
624+
BF->addDecorate(DecorationCallableFunctionINTEL);
625+
}
626+
622627
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
623628
transVectorComputeMetadata(F);
624629

@@ -652,10 +657,6 @@ void LLVMToSPIRV::transVectorComputeMetadata(Function *F) {
652657
BF->addDecorate(DecorationSIMTCallINTEL, SIMTMode);
653658
}
654659

655-
if (Attrs.hasFnAttribute(kVCMetadata::VCCallable)) {
656-
BF->addDecorate(DecorationVectorComputeCallableFunctionINTEL);
657-
}
658-
659660
if (Attrs.hasAttribute(AttributeList::ReturnIndex,
660661
kVCMetadata::VCSingleElementVector)) {
661662
auto *RT = BF->getType();
@@ -2132,6 +2133,7 @@ bool LLVMToSPIRV::isKnownIntrinsic(Intrinsic::ID Id) {
21322133
case Intrinsic::ctlz:
21332134
case Intrinsic::cttz:
21342135
case Intrinsic::expect:
2136+
case Intrinsic::experimental_noalias_scope_decl:
21352137
case Intrinsic::experimental_constrained_fadd:
21362138
case Intrinsic::experimental_constrained_fsub:
21372139
case Intrinsic::experimental_constrained_fmul:
@@ -2747,6 +2749,7 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
27472749
break;
27482750
}
27492751
// We can just ignore/drop some intrinsics, like optimizations hint.
2752+
case Intrinsic::experimental_noalias_scope_decl:
27502753
case Intrinsic::invariant_start:
27512754
case Intrinsic::invariant_end:
27522755
case Intrinsic::dbg_label:
@@ -3403,8 +3406,8 @@ bool LLVMToSPIRV::transExecutionMode() {
34033406
BF->addExecutionMode(BM->add(new SPIRVExecutionMode(
34043407
BF, static_cast<ExecutionMode>(EMode), TargetWidth)));
34053408
} break;
3406-
case spv::ExecutionModeVectorComputeFastCompositeKernelINTEL: {
3407-
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_vector_compute))
3409+
case spv::ExecutionModeFastCompositeKernelINTEL: {
3410+
if (BM->isAllowedToUseExtension(ExtensionID::SPV_INTEL_fast_composite))
34083411
BF->addExecutionMode(BM->add(
34093412
new SPIRVExecutionMode(BF, static_cast<ExecutionMode>(EMode))));
34103413
} break;

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRV.debug.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -50,8 +50,8 @@ enum Instruction {
5050
};
5151

5252
enum Flag {
53-
FlagIsPrivate = 1 << 0,
54-
FlagIsProtected = 1 << 1,
53+
FlagIsProtected = 1 << 0,
54+
FlagIsPrivate = 1 << 1,
5555
FlagIsPublic = FlagIsPrivate | FlagIsProtected,
5656
FlagAccess = FlagIsPublic,
5757
FlagIsLocal = 1 << 2,

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVDecorate.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -190,6 +190,8 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
190190
return ExtensionID::SPV_INTEL_fpga_cluster_attributes;
191191
case DecorationFuseLoopsInFunctionINTEL:
192192
return ExtensionID::SPV_INTEL_loop_fuse;
193+
case DecorationCallableFunctionINTEL:
194+
return ExtensionID::SPV_INTEL_fast_composite;
193195
default:
194196
return {};
195197
}

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEntry.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -842,6 +842,8 @@ class SPIRVCapability : public SPIRVEntryNoId<OpCapability> {
842842
case CapabilityVectorComputeINTEL:
843843
case CapabilityVectorAnyINTEL:
844844
return ExtensionID::SPV_INTEL_vector_compute;
845+
case CapabilityFastCompositeINTEL:
846+
return ExtensionID::SPV_INTEL_fast_composite;
845847
default:
846848
return {};
847849
}

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -252,8 +252,8 @@ template <> inline void SPIRVMap<SPIRVExecutionModeKind, SPIRVCapVec>::init() {
252252
{CapabilityFloatingPointModeINTEL});
253253
ADD_VEC_INIT(ExecutionModeSharedLocalMemorySizeINTEL,
254254
{CapabilityVectorComputeINTEL});
255-
ADD_VEC_INIT(ExecutionModeVectorComputeFastCompositeKernelINTEL,
256-
{CapabilityVectorComputeINTEL});
255+
ADD_VEC_INIT(ExecutionModeFastCompositeKernelINTEL,
256+
{CapabilityFastCompositeINTEL});
257257
}
258258

259259
template <> inline void SPIRVMap<SPIRVMemoryModelKind, SPIRVCapVec>::init() {
@@ -416,8 +416,7 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
416416
{CapabilityFunctionFloatControlINTEL});
417417
ADD_VEC_INIT(DecorationSingleElementVectorINTEL,
418418
{CapabilityVectorComputeINTEL});
419-
ADD_VEC_INIT(DecorationVectorComputeCallableFunctionINTEL,
420-
{CapabilityVectorComputeINTEL});
419+
ADD_VEC_INIT(DecorationCallableFunctionINTEL, {CapabilityFastCompositeINTEL});
421420
ADD_VEC_INIT(DecorationStallEnableINTEL,
422421
{CapabilityFPGAClusterAttributesINTEL});
423422
ADD_VEC_INIT(DecorationFuseLoopsInFunctionINTEL, {CapabilityLoopFuseINTEL});

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -165,8 +165,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
165165
add(DecorationFunctionFloatingPointModeINTEL,
166166
"FunctionFloatingPointModeINTEL");
167167
add(DecorationSingleElementVectorINTEL, "SingleElementVectorINTEL");
168-
add(DecorationVectorComputeCallableFunctionINTEL,
169-
"VectorComputeCallableFunctionINTEL");
168+
add(DecorationCallableFunctionINTEL, "CallableFunctionINTEL");
170169
add(DecorationStallEnableINTEL, "StallEnableINTEL");
171170
add(DecorationFuseLoopsInFunctionINTEL, "FuseLoopsInFunctionINTEL");
172171
add(DecorationMax, "Max");
@@ -513,6 +512,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
513512
add(CapabilityLoopFuseINTEL, "LoopFuseINTEL");
514513
add(CapabilityMax, "Max");
515514
add(CapabilityLongConstantCompositeINTEL, "LongConstantCompositeINTEL");
515+
add(CapabilityFastCompositeINTEL, "FastCompositeINTEL");
516516
}
517517
SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)
518518

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVStream.cpp

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -296,4 +296,29 @@ spv_ostream &operator<<(spv_ostream &O, const SPIRVNL &E) {
296296
return O;
297297
}
298298

299+
// Read the next word from the stream and if OpCode matches the argument,
300+
// decode the whole instruction. Multiple such instructions are possible. If
301+
// OpCode doesn't match the argument, set position of the next character to be
302+
// extracted from the stream to the beginning of the non-matching instruction.
303+
// Returns vector of extracted instructions.
304+
// Used to decode SPIRVTypeStructContinuedINTEL,
305+
// SPIRVConstantCompositeContinuedINTEL and
306+
// SPIRVSpecConstantCompositeContinuedINTEL.
307+
std::vector<SPIRVEntry *>
308+
SPIRVDecoder::getContinuedInstructions(const spv::Op ContinuedOpCode) {
309+
std::vector<SPIRVEntry *> ContinuedInst;
310+
std::streampos Pos = IS.tellg(); // remember position
311+
getWordCountAndOpCode();
312+
while (OpCode == ContinuedOpCode) {
313+
SPIRVEntry *Entry = getEntry();
314+
assert(Entry && "Failed to decode entry! Invalid instruction!");
315+
M.add(Entry);
316+
ContinuedInst.push_back(Entry);
317+
Pos = IS.tellg();
318+
getWordCountAndOpCode();
319+
}
320+
IS.seekg(Pos); // restore position
321+
return ContinuedInst;
322+
}
323+
299324
} // namespace SPIRV

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVStream.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,8 @@ class SPIRVDecoder {
7676
void validate() const;
7777
void ignore(size_t N);
7878
void ignoreInstruction();
79+
std::vector<SPIRVEntry *>
80+
getContinuedInstructions(const spv::Op ContinuedOpCode);
7981

8082
std::istream &IS;
8183
SPIRVModule &M;

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVType.h

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -700,18 +700,8 @@ class SPIRVTypeStruct : public SPIRVType {
700700
Decoder >> Id >> MemberTypeIdVec;
701701
Module->add(this);
702702

703-
Decoder.getWordCountAndOpCode();
704-
while (!I.eof()) {
705-
SPIRVEntry *Entry = Decoder.getEntry();
706-
if (Entry != nullptr)
707-
Module->add(Entry);
708-
if (Entry && Decoder.OpCode == ContinuedOpCode) {
709-
auto ContinuedInst = static_cast<ContinuedInstType>(Entry);
710-
addContinuedInstruction(ContinuedInst);
711-
Decoder.getWordCountAndOpCode();
712-
} else {
713-
break;
714-
}
703+
for (SPIRVEntry *E : Decoder.getContinuedInstructions(ContinuedOpCode)) {
704+
addContinuedInstruction(static_cast<ContinuedInstType>(E));
715705
}
716706
}
717707

‎llvm-spirv/lib/SPIRV/libSPIRV/SPIRVValue.h

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -344,18 +344,8 @@ template <spv::Op OC> class SPIRVConstantCompositeBase : public SPIRVValue {
344344
SPIRVDecoder Decoder = getDecoder(I);
345345
Decoder >> Type >> Id >> Elements;
346346

347-
Decoder.getWordCountAndOpCode();
348-
while (!I.eof()) {
349-
SPIRVEntry *Entry = Decoder.getEntry();
350-
if (Entry != nullptr)
351-
Module->add(Entry);
352-
if (Entry && Decoder.OpCode == ContinuedOpCode) {
353-
auto ContinuedInst = static_cast<ContinuedInstType>(Entry);
354-
addContinuedInstruction(ContinuedInst);
355-
Decoder.getWordCountAndOpCode();
356-
} else {
357-
break;
358-
}
347+
for (SPIRVEntry *E : Decoder.getContinuedInstructions(ContinuedOpCode)) {
348+
addContinuedInstruction(static_cast<ContinuedInstType>(E));
359349
}
360350
}
361351

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