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afonso360afonso360
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riscv64: Add sextend+Arithmetic rules
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‎cranelift/codegen/src/isa/riscv64/lower.isle

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -399,6 +399,38 @@
399399
(rule (lower (has_type out_ty (sextend val @ (value_type in_ty))))
400400
(sext val in_ty out_ty))
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402+
;; The instructions below are present in RV64I and sign-extend the result to 64 bits.
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(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (iadd x y)))))
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(alu_rrr (AluOPRRR.Addw) x y))
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(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (isub x y)))))
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(alu_rrr (AluOPRRR.Subw) x y))
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(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ishl x y)))))
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(alu_rrr (AluOPRRR.Sllw) x y))
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(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (ushr x y)))))
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(alu_rrr (AluOPRRR.Srlw) x y))
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(rule 1 (lower (has_type $I64 (sextend (has_type $I32 (sshr x y)))))
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(alu_rrr (AluOPRRR.Sraw) x y))
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(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (iadd x (imm12_from_value y))))))
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(alu_rr_imm12 (AluOPRRI.Addiw) x y))
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(rule 3 (lower (has_type $I64 (sextend (has_type $I32 (iadd (imm12_from_value x) y)))))
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(alu_rr_imm12 (AluOPRRI.Addiw) y x))
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(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ishl x (imm12_from_value y))))))
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(alu_rr_imm12 (AluOPRRI.Slliw) x y))
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(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (ushr x (imm12_from_value y))))))
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(alu_rr_imm12 (AluOPRRI.SrliW) x y))
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(rule 2 (lower (has_type $I64 (sextend (has_type $I32 (sshr x (imm12_from_value y))))))
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(alu_rr_imm12 (AluOPRRI.Sraiw) x y))
402434

403435
;;;; Rules for `popcnt` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
404436
(rule (lower (has_type (fits_in_64 ty) (popcnt x)))

‎cranelift/filetests/filetests/isa/riscv64/arithmetic-extends.clif

Lines changed: 161 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,161 @@
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test compile precise-output
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set unwind_info=false
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target riscv64
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function %sext_add_i32(i32, i32) -> i64 {
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block0(v0: i32, v1: i32):
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v2 = iadd.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; addw a0,a0,a1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; addw a0, a0, a1
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; ret
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function %sext_sub_i32(i32, i32) -> i64 {
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block0(v0: i32, v1: i32):
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v2 = isub.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; subw a0,a0,a1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; subw a0, a0, a1
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; ret
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function %sext_ishl_i32(i32, i32) -> i64 {
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block0(v0: i32, v1: i32):
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v2 = ishl.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; sllw a0,a0,a1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; sllw a0, a0, a1
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; ret
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function %sext_ushr_i32(i32, i32) -> i64 {
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block0(v0: i32, v1: i32):
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v2 = ushr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; srlw a0,a0,a1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; srlw a0, a0, a1
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; ret
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function %sext_sshr_i32(i32, i32) -> i64 {
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block0(v0: i32, v1: i32):
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v2 = sshr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; sraw a0,a0,a1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; sraw a0, a0, a1
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; ret
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function %sext_add_const_i32(i32) -> i64 {
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block0(v0: i32):
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v1 = iconst.i32 -1
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v2 = iadd.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; addiw a0,a0,-1
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; addiw a0, a0, -1
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; ret
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function %sext_ishl_const_i32(i32) -> i64 {
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block0(v0: i32):
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v1 = iconst.i32 31
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v2 = ishl.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; slliw a0,a0,31
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; slliw a0, a0, 0x1f
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; ret
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function %sext_ushr_const_i32(i32) -> i64 {
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block0(v0: i32):
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v1 = iconst.i32 31
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v2 = ushr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; srliw a0,a0,31
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; srliw a0, a0, 0x1f
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; ret
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function %sext_sshr_const_i32(i32) -> i64 {
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block0(v0: i32):
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v1 = iconst.i32 31
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v2 = sshr.i32 v0, v1
148+
v3 = sextend.i64 v2
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return v3
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}
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; VCode:
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; block0:
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; sraiw a0,a0,31
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; ret
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;
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; Disassembled:
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; block0: ; offset 0x0
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; sraiw a0, a0, 0x1f
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; ret
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‎cranelift/filetests/filetests/runtests/arithmetic-extends.clif

Lines changed: 85 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,4 +148,88 @@ block0(v0: i64, v1: i32):
148148
}
149149
; run: %add_uext_ishl_3(0x0123_4567, 0x8000_0000) == 0x0123_4567
150150
; run: %add_uext_ishl_3(0x0123_4567, 0xC000_0000) == 0x0123_4567
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; run: %add_uext_ishl_3(0x0123_4567, 0xE000_0000) == 0x0123_4567
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; run: %add_uext_ishl_3(0x0123_4567, 0xE000_0000) == 0x0123_4567
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;; These tests perform the operations in 32bits but then sign extend the results to 64bits
155+
function %sext_add_i32(i32, i32) -> i64 {
156+
block0(v0: i32, v1: i32):
157+
v2 = iadd.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
160+
}
161+
; run: %sext_add_i32(1, 0) == 1
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; run: %sext_add_i32(0, -1) == -1
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function %sext_sub_i32(i32, i32) -> i64 {
166+
block0(v0: i32, v1: i32):
167+
v2 = isub.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_sub_i32(1, 0) == 1
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; run: %sext_sub_i32(0, 1) == -1
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function %sext_ishl_i32(i32, i32) -> i64 {
176+
block0(v0: i32, v1: i32):
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v2 = ishl.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_ishl_i32(1, 31) == 0xFFFFFFFF80000000
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function %sext_ushr_i32(i32, i32) -> i64 {
184+
block0(v0: i32, v1: i32):
185+
v2 = ushr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_ushr_i32(0x8000_0000, 0) == 0xFFFFFFFF80000000
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; run: %sext_ushr_i32(0x8000_0000, 32) == 0xFFFFFFFF80000000
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function %sext_sshr_i32(i32, i32) -> i64 {
193+
block0(v0: i32, v1: i32):
194+
v2 = sshr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_sshr_i32(0x8000_0000, 0) == 0xFFFFFFFF80000000
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; run: %sext_sshr_i32(0x8000_0000, 32) == 0xFFFFFFFF80000000
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function %sext_add_const_i32(i32) -> i64 {
202+
block0(v0: i32):
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v1 = iconst.i32 -1
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v2 = iadd.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_add_const_i32(0) == -1
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function %sext_ishl_const_i32(i32) -> i64 {
211+
block0(v0: i32):
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v1 = iconst.i32 31
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v2 = ishl.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_ishl_const_i32(1) == 0xFFFFFFFF80000000
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function %sext_ushr_const_i32(i32) -> i64 {
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block0(v0: i32):
221+
v1 = iconst.i32 32
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v2 = ushr.i32 v0, v1
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v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_ushr_const_i32(0x8000_0000) == 0xFFFFFFFF80000000
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function %sext_sshr_const_i32(i32) -> i64 {
229+
block0(v0: i32):
230+
v1 = iconst.i32 32
231+
v2 = sshr.i32 v0, v1
232+
v3 = sextend.i64 v2
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return v3
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}
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; run: %sext_sshr_const_i32(0x8000_0000) == 0xFFFFFFFF80000000

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