[RISCV] Add Hazard3 Core as taped out for RP2350 (llvm#102452)

Luke Wren's Hazard3 is a configurable, open-source 32-bit RISC-V core.
The core's source code and docs are available on github:
https://github.com/wren6991/hazard3

This is the RISC-V core used in the RP2350, a recently announced SoC by
Raspberry Pi (which also contains Arm cores):
https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf

We have agreed to name this `-mcpu` option `rp2350-hazard3`, and it
reflects exactly the options configured in the RP2350 chips. Notably,
the Zbc is not configured, and nor is B because the `misa.B` bit is not
either.

Author: lenary

clang/test/Driver/riscv-cpus.c

@@ -402,6 +402,21 @@
 // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
 // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s
+// MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3"
+// MCPU-HAZARD3-SAME: "-target-feature" "+m"
+// MCPU-HAZARD3-SAME: "-target-feature" "+a"
+// MCPU-HAZARD3-SAME: "-target-feature" "+c"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zicsr"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zifencei"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zcmp"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zba"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbkb"
+// MCPU-HAZARD3-SAME: "-target-feature" "+zbs"
+// MCPU-HAZARD3-SAME: "-target-abi" "ilp32"
+
 // Check failed cases
 
 // RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s

clang/test/Misc/target-invalid-cpu-note/riscv.c

@@ -7,6 +7,7 @@
 // RISCV32-NEXT: note: valid target CPU values are:
 // RISCV32-SAME: {{^}} generic-rv32
 // RISCV32-SAME: {{^}}, rocket-rv32
+// RISCV32-SAME: {{^}}, rp2350-hazard3
 // RISCV32-SAME: {{^}}, sifive-e20
 // RISCV32-SAME: {{^}}, sifive-e21
 // RISCV32-SAME: {{^}}, sifive-e24
@@ -48,6 +49,7 @@
 // TUNE-RISCV32-NEXT: note: valid target CPU values are:
 // TUNE-RISCV32-SAME: {{^}} generic-rv32
 // TUNE-RISCV32-SAME: {{^}}, rocket-rv32
+// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
 // TUNE-RISCV32-SAME: {{^}}, sifive-e20
 // TUNE-RISCV32-SAME: {{^}}, sifive-e21
 // TUNE-RISCV32-SAME: {{^}}, sifive-e24

llvm/docs/ReleaseNotes.rst

@@ -108,6 +108,8 @@ Changes to the RISC-V Backend
   fill value) rather than NOPs.
 * Added Syntacore SCR4 and SCR5 CPUs: ``-mcpu=syntacore-scr4/5-rv32/64``
 * ``-mcpu=sifive-p470`` was added.
+* Added Hazard3 CPU as taped out for RP2350: ``-mcpu=rp2350-hazard3`` (32-bit
+  only).
 * Fixed length vector support using RVV instructions now requires VLEN>=64. This
   means Zve32x and Zve32f will also require Zvl64b. The prior support was
   largely untested.

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -454,3 +454,19 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
                                         FeatureStdExtZvkt,
                                         FeatureStdExtZvl256b]),
                                        [TuneDLenFactor2]>;
+
+def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3",
+                                         NoSchedModel,
+                                         [Feature32Bit,
+                                          FeatureStdExtI,
+                                          FeatureStdExtM,
+                                          FeatureStdExtA,
+                                          FeatureStdExtC,
+                                          FeatureStdExtZicsr,
+                                          FeatureStdExtZifencei,
+                                          FeatureStdExtZba,
+                                          FeatureStdExtZbb,
+                                          FeatureStdExtZbs,
+                                          FeatureStdExtZbkb,
+                                          FeatureStdExtZcb,
+                                          FeatureStdExtZcmp]>;