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Stabilize cmpxchg16b instrinsic (rust-lang#1358)
Resolves rust-lang/stdarch#827
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crates/core_arch/src/x86_64/cmpxchg16b.rs

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@@ -37,11 +37,12 @@ use stdarch_test::assert_instr;
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/// The failure ordering must be [`Ordering::SeqCst`], [`Ordering::Acquire`] or
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/// [`Ordering::Relaxed`], or this function call is undefined. See the `Atomic*`
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/// documentation's `compare_exchange` function for more information. When
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/// `compare_exchange` panics, this is undefined behavior. Currently this
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/// function aborts the process with an undefined instruction.
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/// `compare_exchange` panics, this is undefined behavior.
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#[inline]
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#[cfg_attr(miri, track_caller)] // even without panics, this helps for Miri backtraces
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#[cfg_attr(test, assert_instr(cmpxchg16b, success = Ordering::SeqCst, failure = Ordering::SeqCst))]
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#[target_feature(enable = "cmpxchg16b")]
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#[stable(feature = "cmpxchg16b_instrinsic", since = "1.67.0")]
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pub unsafe fn cmpxchg16b(
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dst: *mut u128,
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old: u128,
@@ -53,6 +54,8 @@ pub unsafe fn cmpxchg16b(
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debug_assert!(dst as usize % 16 == 0);
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// Copied from `atomic_compare_exchange` in `core`.
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// https://github.com/rust-lang/rust/blob/f8a2e49/library/core/src/sync/atomic.rs#L3046-L3079
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let (val, _ok) = match (success, failure) {
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(Relaxed, Relaxed) => intrinsics::atomic_cxchg_relaxed_relaxed(dst, old, new),
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(Relaxed, Acquire) => intrinsics::atomic_cxchg_relaxed_acquire(dst, old, new),
@@ -69,11 +72,12 @@ pub unsafe fn cmpxchg16b(
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(SeqCst, Relaxed) => intrinsics::atomic_cxchg_seqcst_relaxed(dst, old, new),
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(SeqCst, Acquire) => intrinsics::atomic_cxchg_seqcst_acquire(dst, old, new),
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(SeqCst, SeqCst) => intrinsics::atomic_cxchg_seqcst_seqcst(dst, old, new),
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(_, AcqRel) => panic!("there is no such thing as an acquire-release failure ordering"),
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(_, Release) => panic!("there is no such thing as a release failure ordering"),
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// The above block is all copied from libcore, and this statement is
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// also copied from libcore except that it's a panic in libcore and we
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// have a little bit more of a lightweight panic here.
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_ => crate::core_arch::x86::ud2(),
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// `atomic::Ordering` is non_exhaustive. It warns when `core_arch` is built as a part of `core`.
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#[allow(unreachable_patterns)]
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(_, _) => unreachable!(),
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};
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val
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}

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