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[RISCV] Another length changing shuffle lowering case
"32" is currently a special number - it's one past the maximum representable immediate on a vslidedown.vi and thus the first sub-vector we do *not* consider "cheap" in RISCVTargetLowering::isExtractSubvectorCheap.
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‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll

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@@ -308,3 +308,244 @@ define <32 x i32> @v32i32_v4i32(<4 x i32>) {
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%2 = shufflevector <4 x i32> %0, <4 x i32> poison, <32 x i32> <i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 2, i32 3, i32 0, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3, i32 1, i32 2, i32 0, i32 3, i32 1, i32 1, i32 2, i32 0, i32 3>
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ret <32 x i32> %2
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}
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; TODO: This case should be a simple vnsrl, but gets scalarized instead
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define <32 x i8> @vnsrl_v32i8_v64i8(<64 x i8> %in) {
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; RV32-LABEL: v32i8_v64i8:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -128
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; RV32-NEXT: .cfi_def_cfa_offset 128
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; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill
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; RV32-NEXT: .cfi_offset ra, -4
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; RV32-NEXT: .cfi_offset s0, -8
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; RV32-NEXT: addi s0, sp, 128
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; RV32-NEXT: .cfi_def_cfa s0, 0
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; RV32-NEXT: andi sp, sp, -64
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; RV32-NEXT: li a0, 64
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; RV32-NEXT: mv a1, sp
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; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; RV32-NEXT: vse8.v v8, (a1)
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v10, v8, 1
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; RV32-NEXT: vmv.x.s a0, v10
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; RV32-NEXT: li a1, 32
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vmv.v.x v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 3
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 5
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 7
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 9
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 11
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 13
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV32-NEXT: vslidedown.vi v12, v8, 15
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 17
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 19
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 21
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 23
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 25
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 27
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v12, v8, 29
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; RV32-NEXT: vmv.x.s a0, v12
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; RV32-NEXT: vslide1down.vx v10, v10, a0
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; RV32-NEXT: vslidedown.vi v8, v8, 31
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; RV32-NEXT: vmv.x.s a0, v8
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; RV32-NEXT: vslide1down.vx v8, v10, a0
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; RV32-NEXT: lbu a0, 33(sp)
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; RV32-NEXT: lbu a1, 35(sp)
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; RV32-NEXT: lbu a2, 37(sp)
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; RV32-NEXT: lbu a3, 39(sp)
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: lbu a0, 41(sp)
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; RV32-NEXT: lbu a1, 43(sp)
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; RV32-NEXT: lbu a2, 45(sp)
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; RV32-NEXT: lbu a3, 47(sp)
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: lbu a0, 49(sp)
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; RV32-NEXT: lbu a1, 51(sp)
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; RV32-NEXT: lbu a2, 53(sp)
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; RV32-NEXT: lbu a3, 55(sp)
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: lbu a0, 57(sp)
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; RV32-NEXT: lbu a1, 59(sp)
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; RV32-NEXT: lbu a2, 61(sp)
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; RV32-NEXT: lbu a3, 63(sp)
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: addi sp, s0, -128
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; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 128
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; RV32-NEXT: ret
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;
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; RV64-LABEL: v32i8_v64i8:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -128
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; RV64-NEXT: .cfi_def_cfa_offset 128
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; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill
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; RV64-NEXT: .cfi_offset ra, -8
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; RV64-NEXT: .cfi_offset s0, -16
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; RV64-NEXT: addi s0, sp, 128
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; RV64-NEXT: .cfi_def_cfa s0, 0
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; RV64-NEXT: andi sp, sp, -64
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; RV64-NEXT: li a0, 64
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; RV64-NEXT: mv a1, sp
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; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma
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; RV64-NEXT: vse8.v v8, (a1)
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v10, v8, 1
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; RV64-NEXT: vmv.x.s a0, v10
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; RV64-NEXT: li a1, 32
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vmv.v.x v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 3
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 5
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 7
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 9
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 11
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 13
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma
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; RV64-NEXT: vslidedown.vi v12, v8, 15
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 17
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 19
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 21
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 23
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 25
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 27
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v12, v8, 29
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; RV64-NEXT: vmv.x.s a0, v12
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; RV64-NEXT: vslide1down.vx v10, v10, a0
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; RV64-NEXT: vslidedown.vi v8, v8, 31
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; RV64-NEXT: vmv.x.s a0, v8
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; RV64-NEXT: vslide1down.vx v8, v10, a0
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; RV64-NEXT: lbu a0, 33(sp)
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; RV64-NEXT: lbu a1, 35(sp)
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; RV64-NEXT: lbu a2, 37(sp)
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; RV64-NEXT: lbu a3, 39(sp)
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a3
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; RV64-NEXT: lbu a0, 41(sp)
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; RV64-NEXT: lbu a1, 43(sp)
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; RV64-NEXT: lbu a2, 45(sp)
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; RV64-NEXT: lbu a3, 47(sp)
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a3
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; RV64-NEXT: lbu a0, 49(sp)
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; RV64-NEXT: lbu a1, 51(sp)
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; RV64-NEXT: lbu a2, 53(sp)
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; RV64-NEXT: lbu a3, 55(sp)
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a3
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; RV64-NEXT: lbu a0, 57(sp)
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; RV64-NEXT: lbu a1, 59(sp)
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; RV64-NEXT: lbu a2, 61(sp)
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; RV64-NEXT: lbu a3, 63(sp)
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a3
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; RV64-NEXT: addi sp, s0, -128
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; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 128
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; RV64-NEXT: ret
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%res = shufflevector <64 x i8> %in, <64 x i8> poison, <32 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31, i32 33, i32 35, i32 37, i32 39, i32 41, i32 43, i32 45, i32 47, i32 49, i32 51, i32 53, i32 55, i32 57, i32 59, i32 61, i32 63>
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ret <32 x i8> %res
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}

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