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jeremy avnetbrainsik
jeremy avnet
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brainsik
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Patches working with qemu-kvm 1.0 as received from René Rebe
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Diff for: ‎03-qemu-lpc.patch

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# --- T2-COPYRIGHT-NOTE-BEGIN ---
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# This copyright note is auto-generated by ./scripts/Create-CopyPatch.
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#
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# T2 SDE: package/.../kvm/03-qemu-lpc.patch
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# Copyright (C) 2011 The T2 SDE Project
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#
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# More information can be found in the files COPYING and README.
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#
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# This patch file is dual-licensed. It is available under the license the
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# patched project is licensed under, as long as it is an OpenSource license
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# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
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# of the GNU General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option) any later
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# version.
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# --- T2-COPYRIGHT-NOTE-END ---
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From: Alexander Graf <[email protected]>
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Date: Tue, 30 Nov 2010 14:24:04 +0000 (+0100)
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Subject: Add LPC device emulation
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X-Git-Url: http://repo.or.cz/w/qemu/agraf.git/commitdiff_plain/71f1f25277f2e2035eec1badf76b6035a0390efa
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Add LPC device emulation
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Signed-off-by: Alexander Graf <[email protected]>
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---
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--- qemu-kvm-0.15.0/Makefile.objs.vanilla 2011-12-07 19:15:50.237204501 +0000
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+++ qemu-kvm-0.15.0/Makefile.objs 2011-12-07 19:16:32.413199084 +0000
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@@ -205,7 +205,7 @@
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hw-obj-$(CONFIG_APM) += pm_smbus.o apm.o
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hw-obj-$(CONFIG_DMA) += dma.o
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hw-obj-$(CONFIG_HPET) += hpet.o
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-hw-obj-$(CONFIG_APPLESMC) += applesmc.o
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+hw-obj-$(CONFIG_APPLESMC) += applesmc.o lpc.o
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hw-obj-$(CONFIG_SMARTCARD) += usb-ccid.o ccid-card-passthru.o
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hw-obj-$(CONFIG_SMARTCARD_NSS) += ccid-card-emulated.o
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hw-obj-$(CONFIG_USB_REDIR) += usb-redir.o
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--- /dev/null
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+++ b/hw/lpc.c
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@@ -0,0 +1,200 @@
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+/*
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+ * Low Pin Count emulation
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+ *
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+ * Copyright (c) 2007 Alexander Graf
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+ *
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+ * This library is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU Lesser General Public
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+ * License as published by the Free Software Foundation; either
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+ * version 2 of the License, or (at your option) any later version.
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+ *
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+ * This library is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * Lesser General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU Lesser General Public
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+ * License along with this library; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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+ *
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+ * *****************************************************************
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+ *
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+ * This driver emulates an ICH-7 LPC partially. The LPC is basically the
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+ * same as the ISA-bridge in the existing PIIX implementation, but
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+ * more recent and includes support for HPET and Power Management.
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+ *
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+ *
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+ * 00:1f.0 0601: 8086:27b9 (rev 02)
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+ * Subsystem: 1025:0107
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+ * Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B-
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+ * Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
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+ * Latency: 0
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+ * Capabilities: [e0] Vendor Specific Information
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+ * 00: 86 80 b9 27 07 01 10 02 02 00 01 06 00 00 80 00
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+ * 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ * 20: 00 00 00 00 00 00 00 00 00 00 00 00 25 10 07 01
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+ * 30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00
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+ * 40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00
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+ * 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ * 60: 80 80 80 80 90 00 00 00 80 80 80 80 00 00 00 00
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+ * 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ * 80: 10 00 02 3f 00 00 00 00 01 12 04 00 00 00 00 00
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+ * 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ * a0: 24 06 00 00 01 00 00 00 13 1c 0a 00 00 03 00 00
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+ * b0: 00 00 f0 00 00 00 00 00 00 80 09 00 00 00 00 00
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+ * c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+ * d0: 33 22 11 00 67 45 00 00 cf ff 00 00 00 00 00 00
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+ * e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00
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+ * f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00
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+ */
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+#include "hw.h"
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+#include "pci.h"
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+#include "console.h"
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+
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+#define RCBA_BASE 0xFED1C000
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+
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+typedef struct LPCState {
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+ PCIDevice card;
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+} LPCState;
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+
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+static uint32_t rcba_ram_readl(void *opaque, target_phys_addr_t addr)
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+{
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+ printf("qemu: rcba_read l at %#lx\n", addr);
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+ if(addr == RCBA_BASE + 0x3404) { /* This is the HPET config pointer */
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+ printf("qemu: rcba_read HPET_CONFIG_POINTER\n");
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+ return 0xf0; // enabled at 0xfed00000
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+ } else if(addr == RCBA_BASE + 0x3410) { /* This is the HPET config pointer */
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+ printf("qemu: rcba_read GCS\n");
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+ return 0;
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+ } else {
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+ return 0x0;
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+ }
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+}
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+
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+static void rcba_ram_writel(void *opaque, target_phys_addr_t addr,
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+ uint32_t value)
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+{
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+ printf("qemu: rcba_write l %#lx = %#x\n", addr, value);
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+}
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+
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+static CPUReadMemoryFunc *rcba_ram_read[] = {
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+ NULL,
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+ NULL,
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+ rcba_ram_readl,
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+};
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+
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+static CPUWriteMemoryFunc *rcba_ram_write[] = {
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+ NULL,
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+ NULL,
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+ rcba_ram_writel,
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+};
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+
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+static int lpc_init(PCIDevice *dev)
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+{
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+ int iomemtype;
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+ uint8_t *pci_conf;
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+
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+#if 0
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+ /* register a function 1 of PIIX3 */
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+ d = (PCIDevice *)pci_register_device(bus, "LPC",
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+ sizeof(PCIDevice),
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+ 31 << 3,
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+ NULL, NULL);
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+#endif
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+ pci_conf = dev->config;
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+ pci_conf[0x00] = 0x86;
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+ pci_conf[0x01] = 0x80;
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+ pci_conf[0x02] = 0xb9;
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+ pci_conf[0x03] = 0x27;
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+ pci_conf[0x08] = 0x02; // Revision 2
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+
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+ pci_conf[0x0a] = 0x01; // PCI-to-ISA Bridge
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+ pci_conf[0x0b] = 0x06; // Bridge
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+
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+ pci_conf[0x0e] = 0xf0;
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+
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+ // Subsystem
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+ pci_conf[0x2c] = 0x86;
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+ pci_conf[0x2d] = 0x80;
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+ pci_conf[0x2e] = 0x70;
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+ pci_conf[0x2f] = 0x72;
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+
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+ pci_conf[0x3d] = 0x03;
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+
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+ // PMBASE
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+ pci_conf[0x40] = 0x01;
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+ pci_conf[0x41] = 0x0b;
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+
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+ pci_set_long(pci_conf + 0xf0, RCBA_BASE | 1);
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+
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+ /* RCBA Area */
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+
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+ iomemtype = cpu_register_io_memory(rcba_ram_read, rcba_ram_write, dev, DEVICE_NATIVE_ENDIAN);
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+
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+ cpu_register_physical_memory(RCBA_BASE, 0x4000, iomemtype);
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+#if 0
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+ cpu_register_physical_memory(0x00CDA000, 0x4000, iomemtype);
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+#endif
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+
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+ pci_conf[0x04] = 0x07; // master, memory and I/O
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+ pci_conf[0x05] = 0x00;
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+ pci_conf[0x06] = 0x00;
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+ pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
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+ pci_conf[0x4c] = 0x4d;
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+ pci_conf[0x4e] = 0x03;
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+ pci_conf[0x4f] = 0x00;
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+ pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
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+ pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
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+ pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
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+ pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
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+ pci_conf[0x69] = 0x02;
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+ pci_conf[0x70] = 0x80;
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+ pci_conf[0x76] = 0x0c;
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+ pci_conf[0x77] = 0x0c;
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+ pci_conf[0x78] = 0x02;
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+ pci_conf[0x79] = 0x00;
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+ pci_conf[0x80] = 0x00;
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+ pci_conf[0x82] = 0x00;
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+ pci_conf[0xa0] = 0x08;
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+ pci_conf[0xa2] = 0x00;
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+ pci_conf[0xa3] = 0x00;
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+ pci_conf[0xa4] = 0x00;
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+ pci_conf[0xa5] = 0x00;
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+ pci_conf[0xa6] = 0x00;
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+ pci_conf[0xa7] = 0x00;
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+ pci_conf[0xa8] = 0x0f;
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+ pci_conf[0xaa] = 0x00;
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+ pci_conf[0xab] = 0x00;
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+ pci_conf[0xac] = 0x00;
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+ pci_conf[0xae] = 0x00;
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+
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+#if 0
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+ register_ioport_read(0x1000, 128, 1, pmbase_readb, d);
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+ register_ioport_write(0x1000, 128, 1, pmbase_writeb, d);
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+ register_ioport_read(0x1000, 64, 2, pmbase_readw, d);
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+ register_ioport_write(0x1000, 64, 2, pmbase_writew, d);
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+ register_ioport_read(0x1000, 32, 4, pmbase_readl, d);
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+ register_ioport_write(0x1000, 32, 5, pmbase_writel, d);
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+#endif
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+
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+ return 0;
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+}
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+
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+static int lpc_uninit(PCIDevice *dev)
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+{
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+ return 0;
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+}
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+
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+static PCIDeviceInfo lpc_info = {
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+ .qdev.name = "lpc",
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+ .qdev.size = sizeof(LPCState),
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+ .init = lpc_init,
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+ .exit = lpc_uninit,
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+};
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+
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+static void lpc_register_device(void)
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+{
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+ pci_qdev_register(&lpc_info);
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+}
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+
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+device_init(lpc_register_device)

Diff for: ‎16-bios.patch

+60
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# --- T2-COPYRIGHT-NOTE-BEGIN ---
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# This copyright note is auto-generated by ./scripts/Create-CopyPatch.
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#
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# T2 SDE: package/.../kvm/16-bios.patch
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# Copyright (C) 2010 - 2012 The T2 SDE Project
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#
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# More information can be found in the files COPYING and README.
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#
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# This patch file is dual-licensed. It is available under the license the
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# patched project is licensed under, as long as it is an OpenSource license
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# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
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# of the GNU General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option) any later
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# version.
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# --- T2-COPYRIGHT-NOTE-END ---
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# Send to upstream BOCHS
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This ACPI BIOS patch provides:
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- Enable AHCI support
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- The PCI bus definition for PIC, HPET, RTC, SMC and OSYS and SMIF
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- An PBLK which provides the size of the L2 and L3 caches
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Signed-off-by: Alex Graf - http://alex.csgraf.de
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Index: qemu-kvm-0.12.1.2/roms/seabios-mac/src/acpi-dsdt.dsl
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===================================================================
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--- qemu-kvm-0.12.1.2.orig/roms/seabios-mac/src/acpi-dsdt.dsl
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+++ qemu-kvm-0.12.1.2/roms/seabios-mac/src/acpi-dsdt.dsl
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@@ -194,6 +194,7 @@ DefinitionBlock (
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Device(HPET) {
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Name(_HID, EISAID("PNP0103"))
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+ Name(_CID, 0x010CD041)
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Name(_UID, 0)
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Method (_STA, 0, NotSerialized) {
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Return(0x0F)
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@@ -210,6 +211,23 @@ DefinitionBlock (
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)
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})
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}
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+ Device (SMC)
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+ {
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+ Name (_HID, EisaId ("APP0001"))
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+ Name (_CID, "smc-napa")
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+ Name (_STA, 0x0B)
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+ Name (_CRS, ResourceTemplate ()
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+ {
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+ IO (Decode16,
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+ 0x0300, // Range Minimum
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+ 0x0300, // Range Maximum
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+ 0x01, // Alignment
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+ 0x20, // Length
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+ )
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+ IRQNoFlags ()
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+ {6}
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+ })
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+ }
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}
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Scope(\_SB.PCI0) {

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