[vm/ffi] Support Linux on Arm 32-bit (hardfp)

Implement the hardfp calling convention.

Tested QEMU locally as the bots are not online yet.

tools/test.py -m debug -a arm -c dartkp --use-qemu ffi_2 ; tools/test.py -m debug -a arm -c dartk --use-qemu ffi_2
Test configuration:
    custom configuration(architecture: arm, compiler: dartkp, mode: debug, runtime: dart_precompiled, system: linux, use-qemu)
Suites tested: ffi_2
[00:45 | 100% | +  189 | -    0]
Test configuration:
    custom configuration(architecture: arm, compiler: dartk, mode: debug, runtime: vm, system: linux, use-qemu)
Suites tested: ffi_2
[09:52 | 100% | +  189 | -    0]

Fixes: #36309

Change-Id: Ic34175bdf9b9f359f1126aeb157362e76443921a
Cq-Include-Trybots: luci.dart.try:vm-ffi-android-debug-arm-try,vm-ffi-android-debug-arm64-try,app-kernel-linux-debug-x64-try,vm-kernel-linux-debug-ia32-try,vm-kernel-win-debug-x64-try,vm-kernel-win-debug-ia32-try,vm-kernel-precomp-linux-debug-x64-try,vm-dartkb-linux-release-x64-abi-try,vm-kernel-precomp-android-release-arm64-try,vm-kernel-asan-linux-release-x64-try,vm-kernel-linux-release-simarm-try,vm-kernel-linux-release-simarm64-try,vm-kernel-precomp-android-release-arm_x64-try,vm-kernel-precomp-obfuscate-linux-release-x64-try,dart-sdk-linux-try,analyzer-analysis-server-linux-try,analyzer-linux-release-try,front-end-linux-release-x64-try,vm-kernel-precomp-win-release-x64-try
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/124136
Commit-Queue: Daco Harkes <[email protected]>
Reviewed-by: Martin Kustermann <[email protected]>

Author: dcharkes

runtime/vm/compiler/assembler/assembler_arm.cc

@@ -3160,6 +3160,13 @@ void Assembler::AddImmediateSetFlags(Register rd,
   }
 }
 
+void Assembler::SubImmediate(Register rd,
+                             Register rn,
+                             int32_t value,
+                             Condition cond) {
+  AddImmediate(rd, rn, -value, cond);
+}
+
 void Assembler::SubImmediateSetFlags(Register rd,
                                      Register rn,
                                      int32_t value,

runtime/vm/compiler/assembler/assembler_arm.h

@@ -757,6 +757,10 @@ class Assembler : public AssemblerBase {
                             Register rn,
                             int32_t value,
                             Condition cond = AL);
+  void SubImmediate(Register rd,
+                    Register rn,
+                    int32_t value,
+                    Condition cond = AL);
   void SubImmediateSetFlags(Register rd,
                             Register rn,
                             int32_t value,

runtime/vm/compiler/backend/flow_graph_compiler.cc

@@ -2522,20 +2522,21 @@ void FlowGraphCompiler::EmitNativeMove(
         src_container_size >= dst_container_size) {
       // The upper bits of the source are already properly sign or zero
       // extended, so just copy the required amount of bits.
-      return EmitNativeMove(
-          destination.WithOtherRep(dst_container_type, dst_container_type,
-                                   zone_),
-          source.WithOtherRep(dst_container_type, dst_container_type, zone_),
-          temp);
+      return EmitNativeMove(destination.WithOtherNativeType(
+                                dst_container_type, dst_container_type, zone_),
+                            source.WithOtherNativeType(
+                                dst_container_type, dst_container_type, zone_),
+                            temp);
     }
     if (src_payload_size >= dst_payload_size &&
         dst_container_size > dst_payload_size) {
       // The upper bits of the source are not properly sign or zero extended
       // to be copied to the target, so regard the source as smaller.
       return EmitNativeMove(
-          destination.WithOtherRep(dst_container_type, dst_container_type,
-                                   zone_),
-          source.WithOtherRep(dst_payload_type, dst_payload_type, zone_), temp);
+          destination.WithOtherNativeType(dst_container_type,
+                                          dst_container_type, zone_),
+          source.WithOtherNativeType(dst_payload_type, dst_payload_type, zone_),
+          temp);
     }
     UNREACHABLE();
   }
@@ -2578,7 +2579,7 @@ void FlowGraphCompiler::EmitNativeMove(
   if (sign_or_zero_extend && destination.IsStack()) {
     ASSERT(source.IsRegisters());
     const auto& intermediate =
-        source.WithOtherRep(dst_payload_type, dst_container_type, zone_);
+        source.WithOtherNativeType(dst_payload_type, dst_container_type, zone_);
     EmitNativeMove(intermediate, source, temp);
     EmitNativeMove(destination, intermediate, temp);
     return;
@@ -2588,8 +2589,8 @@ void FlowGraphCompiler::EmitNativeMove(
   // Arm does not support sign extending from a memory location, x86 does.
   if (sign_or_zero_extend && source.IsStack()) {
     ASSERT(destination.IsRegisters());
-    const auto& intermediate =
-        destination.WithOtherRep(src_payload_type, src_container_type, zone_);
+    const auto& intermediate = destination.WithOtherNativeType(
+        src_payload_type, src_container_type, zone_);
     EmitNativeMove(intermediate, source, temp);
     EmitNativeMove(destination, intermediate, temp);
     return;

runtime/vm/compiler/backend/flow_graph_compiler_arm.cc

@@ -1602,9 +1602,10 @@ void FlowGraphCompiler::EmitNativeMoveArchitecture(
           __ vmovq(dst.fpu_reg(), src.fpu_reg());
           return;
         case 8:
-          // TODO(36309): Use the proper register instead of asuming even.
-          __ vmovd(EvenDRegisterOf(dst.fpu_reg()),
-                   EvenDRegisterOf(src.fpu_reg()));
+          __ vmovd(dst.fpu_as_d_reg(), src.fpu_as_d_reg());
+          return;
+        case 4:
+          __ vmovs(dst.fpu_as_s_reg(), src.fpu_as_s_reg());
           return;
         default:
           UNREACHABLE();
@@ -1616,14 +1617,12 @@ void FlowGraphCompiler::EmitNativeMoveArchitecture(
       const auto& dst = destination.AsStack();
       switch (dst_size) {
         case 8:
-          // TODO(36309): Use the proper register instead of asuming even.
-          __ StoreDToOffset(EvenDRegisterOf(src.fpu_reg()), dst.base_register(),
+          __ StoreDToOffset(src.fpu_as_d_reg(), dst.base_register(),
                             dst.offset_in_bytes());
           return;
         case 4:
-          // TODO(36309): Use the proper register instead of asuming even.
-          __ StoreSToOffset(EvenSRegisterOf(EvenDRegisterOf(src.fpu_reg())),
-                            dst.base_register(), dst.offset_in_bytes());
+          __ StoreSToOffset(src.fpu_as_s_reg(), dst.base_register(),
+                            dst.offset_in_bytes());
           return;
         default:
           // TODO(dartbug.com/37470): Case 16 for simd packed data.
@@ -1650,14 +1649,12 @@ void FlowGraphCompiler::EmitNativeMoveArchitecture(
       const auto& dst = destination.AsFpuRegisters();
       switch (src_size) {
         case 8:
-          // TODO(36309): Use the proper register instead of asuming even.
-          __ LoadDFromOffset(EvenDRegisterOf(dst.fpu_reg()),
-                             src.base_register(), src.offset_in_bytes());
+          __ LoadDFromOffset(dst.fpu_as_d_reg(), src.base_register(),
+                             src.offset_in_bytes());
           return;
         case 4:
-          // TODO(36309): Use the proper register instead of asuming even.
-          __ LoadSFromOffset(EvenSRegisterOf(EvenDRegisterOf(dst.fpu_reg())),
-                             src.base_register(), src.offset_in_bytes());
+          __ LoadSFromOffset(dst.fpu_as_s_reg(), src.base_register(),
+                             src.offset_in_bytes());
           return;
         default:
           UNIMPLEMENTED();

runtime/vm/compiler/backend/il_arm.cc

@@ -1235,35 +1235,31 @@ void NativeReturnInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
   __ set_constant_pool_allowed(true);
 }
 
-static void save_argument(FlowGraphCompiler* compiler, Location loc) {
-  if (loc.IsPairLocation()) {
-    // Save higher-order component first, so bytes are in little-endian layout
-    // overall.
-    for (intptr_t i : {1, 0}) {
-      save_argument(compiler, loc.Component(i));
-    }
-    return;
-  }
-
-  if (loc.HasStackIndex()) return;
-
-  if (loc.IsRegister()) {
-    __ Push(loc.reg());
-  } else if (loc.IsFpuRegister()) {
-    const DRegister src = EvenDRegisterOf(loc.fpu_reg());
-    __ SubImmediateSetFlags(SPREG, SPREG, 8, AL);
-    __ StoreDToOffset(src, SPREG, 0);
-  } else {
-    UNREACHABLE();
-  }
-}
-
 void NativeEntryInstr::SaveArgument(
     FlowGraphCompiler* compiler,
     const compiler::ffi::NativeLocation& nloc) const {
-  const Location loc = nloc.WidenTo4Bytes(compiler->zone()).AsLocation();
+  if (nloc.IsFpuRegisters()) {
+    auto const& fpu_loc = nloc.AsFpuRegisters();
+    ASSERT(fpu_loc.fpu_reg_kind() != compiler::ffi::kQuadFpuReg);
+    const intptr_t size = fpu_loc.payload_type().SizeInBytes();
+    // TODO(dartbug.com/40469): Reduce code size.
+    __ SubImmediate(SPREG, SPREG, 8);
+    if (size == 8) {
+      __ StoreDToOffset(fpu_loc.fpu_d_reg(), SPREG, 0);
+    } else {
+      ASSERT(size == 4);
+      __ StoreSToOffset(fpu_loc.fpu_s_reg(), SPREG, 0);
+    }
 
-  save_argument(compiler, loc);
+  } else if (nloc.IsRegisters()) {
+    const auto& reg_loc = nloc.WidenTo4Bytes(compiler->zone()).AsRegisters();
+    const intptr_t num_regs = reg_loc.num_regs();
+    // Save higher-order component first, so bytes are in little-endian layout
+    // overall.
+    for (intptr_t i = num_regs - 1; i >= 0; i--) {
+      __ Push(reg_loc.reg_at(i));
+    }
+  }
 }
 
 void NativeEntryInstr::EmitNativeCode(FlowGraphCompiler* compiler) {

runtime/vm/compiler/backend/il_x64.cc

@@ -1019,6 +1019,7 @@ void NativeEntryInstr::SaveArgument(
     ASSERT(regs_loc.num_regs() == 1);
     __ pushq(regs_loc.reg_at(0));
   } else if (nloc.IsFpuRegisters()) {
+    // TODO(dartbug.com/40469): Reduce code size.
     __ movq(TMP, nloc.AsFpuRegisters().fpu_reg());
     __ pushq(TMP);
   } else {

runtime/vm/compiler/ffi/marshaller.cc

@@ -38,14 +38,26 @@ Location CallMarshaller::LocInFfiCall(intptr_t arg_index) const {
                          RepInFfiCall(arg_index) == kUnboxedFloat;
 
   const NativeLocation& loc = this->Location(arg_index);
-
+  // Don't pin stack locations, they need to be moved anyway.
   if (loc.IsStack()) {
     if (loc.payload_type().SizeInBytes() == 2 * compiler::target::kWordSize &&
         !is_atomic) {
       return Location::Pair(Location::Any(), Location::Any());
     }
     return Location::Any();
   }
+
+#if defined(TARGET_ARCH_ARM)
+  // Only pin FPU register if it is the lowest bits.
+  if (loc.IsFpuRegisters()) {
+    const auto& fpu_loc = loc.AsFpuRegisters();
+    if (fpu_loc.IsLowestBits()) {
+      return fpu_loc.WidenToQFpuRegister(zone_).AsLocation();
+    }
+    return Location::Any();
+  }
+#endif  // defined(TARGET_ARCH_ARM)
+
   return loc.AsLocation();
 }
 

runtime/vm/compiler/ffi/marshaller.h

@@ -60,13 +60,13 @@ class BaseMarshaller : public NativeCallingConvention {
 
   // Requires boxing or unboxing.
   bool IsPointer(intptr_t arg_index) const {
-    return AbstractType::Handle(zone_, Type(arg_index)).type_class_id() ==
+    return AbstractType::Handle(zone_, CType(arg_index)).type_class_id() ==
            kFfiPointerCid;
   }
 
   // Treated as a null constant in Dart.
   bool IsVoid(intptr_t arg_index) const {
-    return AbstractType::Handle(zone_, Type(arg_index)).type_class_id() ==
+    return AbstractType::Handle(zone_, CType(arg_index)).type_class_id() ==
            kFfiVoidCid;
   }