Update repo name

Author: gnzlbg

.travis.yml

@@ -13,14 +13,14 @@ matrix:
       env: TARGET=x86_64-unknown-linux-gnu
       install: true
     - name: "x86_64-unknown-linux-gnu-emulated (runs all assert_instr tests)"
-      env: TARGET=x86_64-unknown-linux-gnu-emulated STDSIMD_TEST_EVERYTHING=1 RUSTFLAGS="--cfg stdsimd_intel_sde"
+      env: TARGET=x86_64-unknown-linux-gnu-emulated STDARCH_TEST_EVERYTHING=1 RUSTFLAGS="--cfg stdarch_intel_sde"
       install: true
     - name: "x86_64-linux-android - no assert_instr"
-      env: TARGET=x86_64-linux-android STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=x86_64-linux-android STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "arm-unknown-linux-gnueabihf"
       env: TARGET=arm-unknown-linux-gnueabihf
     - name: "arm-linux-androideabi - no assert_instr"
-      env: TARGET=arm-linux-androideabi STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=arm-linux-androideabi STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "armv7-unknown-linux-gnueabihf - NEON"
       env: TARGET=armv7-unknown-linux-gnueabihf RUSTFLAGS="-C target-feature=+neon"
     - name: "aarch64-unknown-linux-gnu"
@@ -34,13 +34,13 @@ matrix:
     - name: "mips64el-unknown-linux-gnuabi64 - build-only"
       env: TARGET=mips64el-unknown-linux-gnuabi64 NORUN=1
     - name: "aarch64-linux-android - no assert_instr"
-      env: TARGET=aarch64-linux-android STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=aarch64-linux-android STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "powerpc-unknown-linux-gnu - no assert_instr"
-      env: TARGET=powerpc-unknown-linux-gnu STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=powerpc-unknown-linux-gnu STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "powerpc64-unknown-linux-gnu - no assert_instr"
-      env: TARGET=powerpc64-unknown-linux-gnu STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=powerpc64-unknown-linux-gnu STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "powerpc64le-unknown-linux-gnu - no assert_instr"
-      env: TARGET=powerpc64le-unknown-linux-gnu STDSIMD_DISABLE_ASSERT_INSTR=1
+      env: TARGET=powerpc64le-unknown-linux-gnu STDARCH_DISABLE_ASSERT_INSTR=1
     - name: "s390x-unknown-linux-gnu"
       env: TARGET=s390x-unknown-linux-gnu
     - name: "i686-apple-darwin"
@@ -90,7 +90,7 @@ matrix:
       install: true
       script: ci/dox.sh
     - name: "Automatic verification: x86 / x86_64 / arm / aarch64 / mips*"
-      script: cargo test --manifest-path crates/stdsimd-verify/Cargo.toml
+      script: cargo test --manifest-path crates/stdarch-verify/Cargo.toml
       install: true
     - name: "rustfmt"
       install: true

CONTRIBUTING.md

@@ -1,11 +1,11 @@
-# Contributing to stdsimd
+# Contributing to stdarch
 
-The `stdsimd` crate is more than willing to accept contributions! First you'll
+The `stdarch` crate is more than willing to accept contributions! First you'll
 probably want to check out the repository and make sure that tests pass for you:
 
 ```
-$ git clone https://github.com/rust-lang-nursery/stdsimd
-$ cd stdsimd
+$ git clone https://github.com/rust-lang/stdarch
+$ cd stdarch
 $ cargo +nightly test
 ```
 
@@ -29,7 +29,7 @@ around! Feel free to ping either @BurntSushi or @alexcrichton with questions.
 
 [gitter]: https://gitter.im/rust-impl-period/WG-libs-simd
 
-# How to write examples for stdsimd intrinsics
+# How to write examples for stdarch intrinsics
 
 There are a few features that must be enabled for the given intrinsic to work
 properly and the example must only be run by `cargo test --doc` when the feature
@@ -44,9 +44,9 @@ to ensure your example works as expected.
 /// # // We need target_feature for the intrinsic to work
 /// # #![feature(target_feature)]
 /// #
-/// # // rustdoc by default uses `extern crate stdsimd`, but we need the
+/// # // rustdoc by default uses `extern crate stdarch`, but we need the
 /// # // `#[macro_use]`
-/// # #[macro_use] extern crate stdsimd;
+/// # #[macro_use] extern crate stdarch;
 /// #
 /// # // The real main function
 /// # fn main() {
@@ -69,12 +69,12 @@ to ensure your example works as expected.
 If some of the above syntax does not look familiar, the [Documentation as tests] section
 of the [Rust Book] describes the `rustdoc` syntax quite well. As always, feel free
 to [join us on gitter][gitter] and ask us if you hit any snags, and thank you for helping
-to improve the documentation of `stdsimd`!
+to improve the documentation of `stdarch`!
 
-[new]: https://github.com/rust-lang-nursery/stdsimd/issues/new
-[issues]: https://github.com/rust-lang-nursery/stdsimd/issues
-[help]: https://github.com/rust-lang-nursery/stdsimd/issues?q=is%3Aissue+is%3Aopen+label%3A%22help+wanted%22
-[impl]: https://github.com/rust-lang-nursery/stdsimd/issues?q=is%3Aissue+is%3Aopen+label%3Aimpl-period
-[vendor]: https://github.com/rust-lang-nursery/stdsimd/issues/40
+[new]: https://github.com/rust-lang/stdarch/issues/new
+[issues]: https://github.com/rust-lang/stdarch/issues
+[help]: https://github.com/rust-lang/stdarch/issues?q=is%3Aissue+is%3Aopen+label%3A%22help+wanted%22
+[impl]: https://github.com/rust-lang/stdarch/issues?q=is%3Aissue+is%3Aopen+label%3Aimpl-period
+[vendor]: https://github.com/rust-lang/stdarch/issues/40
 [Documentation as tests]: https://doc.rust-lang.org/book/first-edition/documentation.html#documentation-as-tests
 [Rust Book]: https://doc.rust-lang.org/book/first-edition

Cargo.toml

@@ -1,6 +1,6 @@
 [workspace]
 members = [
-  "crates/stdsimd-verify",
+  "crates/stdarch-verify",
   "crates/core_arch",
   "crates/std_detect",
   "examples/"

QUESTIONS.md

@@ -2,10 +2,10 @@ This program emits `psllw` instead of `pslliw` instruction. `pslliw` should be
 usable here since `imm8` is a constant:
 
 ```rust
-extern crate stdsimd;
+extern crate stdarch;
 
 use std::env;
-use stdsimd as s;
+use stdarch as s;
 
 fn main() {
     let imm8: i32 = env::args().nth(1).unwrap().parse().unwrap();

README.md

@@ -1,4 +1,4 @@
-stdsimd - Rust's standard library SIMD components
+stdarch - Rust's standard library SIMD components
 =======
 
 [![Travis-CI Status]][travis] [![Appveyor Status]][appveyor] 
@@ -29,9 +29,9 @@ To do a release of the `core_arch` and `std_detect` crates,
   https://github.com/rust-lang/cargo/issues/4242),
 * publish the crates.
 
-[travis]: https://travis-ci.com/rust-lang-nursery/stdsimd
-[Travis-CI Status]: https://travis-ci.com/rust-lang-nursery/stdsimd.svg?branch=master
-[appveyor]: https://ci.appveyor.com/project/rust-lang-libs/stdsimd/branch/master
+[travis]: https://travis-ci.com/rust-lang/stdarch
+[Travis-CI Status]: https://travis-ci.com/rust-lang/stdarch.svg?branch=master
+[appveyor]: https://ci.appveyor.com/project/rust-lang-libs/stdarch/branch/master
 [Appveyor Status]: https://ci.appveyor.com/api/projects/status/ix74qhmilpibn00x/branch/master?svg=true
 [core_arch_crate_badge]: https://img.shields.io/crates/v/core_arch.svg
 [core_arch_crate_link]: https://crates.io/crates/core_arch

ci/run-docker.sh

@@ -8,7 +8,7 @@ set -ex
 run() {
     target=$(echo "${1}" | sed 's/-emulated//')
     echo "Building docker container for TARGET=${1}"
-    docker build -t stdsimd -f "ci/docker/${1}/Dockerfile" ci/
+    docker build -t stdarch -f "ci/docker/${1}/Dockerfile" ci/
     mkdir -p target
     echo "Running docker"
     # shellcheck disable=SC2016
@@ -20,18 +20,18 @@ run() {
       --env CARGO_HOME=/cargo-h \
       --volume "$(rustc --print sysroot)":/rust:ro \
       --env TARGET="${target}" \
-      --env STDSIMD_TEST_EVERYTHING \
-      --env STDSIMD_ASSERT_INSTR_IGNORE \
-      --env STDSIMD_DISABLE_ASSERT_INSTR \
+      --env STDARCH_TEST_EVERYTHING \
+      --env STDARCH_ASSERT_INSTR_IGNORE \
+      --env STDARCH_DISABLE_ASSERT_INSTR \
       --env NOSTD \
       --env NORUN \
       --env RUSTFLAGS \
-      --env STDSIMD_TEST_NORUN \
+      --env STDARCH_TEST_NORUN \
       --volume "$(pwd)":/checkout:ro \
       --volume "$(pwd)"/target:/checkout/target \
       --workdir /checkout \
       --privileged \
-      stdsimd \
+      stdarch \
       bash \
       -c 'PATH=/rust/bin:$PATH exec ci/run.sh'
 }

ci/run.sh

@@ -10,7 +10,7 @@ set -ex
 #export RUST_TEST_NOCAPTURE=1
 #export RUST_TEST_THREADS=1
 
-RUSTFLAGS="$RUSTFLAGS --cfg stdsimd_strict"
+RUSTFLAGS="$RUSTFLAGS --cfg stdarch_strict"
 
 case ${TARGET} in
     # On 32-bit use a static relocation model which avoids some extra
@@ -33,8 +33,8 @@ esac
 echo "RUSTFLAGS=${RUSTFLAGS}"
 echo "FEATURES=${FEATURES}"
 echo "OBJDUMP=${OBJDUMP}"
-echo "STDSIMD_DISABLE_ASSERT_INSTR=${STDSIMD_DISABLE_ASSERT_INSTR}"
-echo "STDSIMD_TEST_EVERYTHING=${STDSIMD_TEST_EVERYTHING}"
+echo "STDARCH_DISABLE_ASSERT_INSTR=${STDARCH_DISABLE_ASSERT_INSTR}"
+echo "STDARCH_TEST_EVERYTHING=${STDARCH_TEST_EVERYTHING}"
 
 cargo_test() {
     cmd="cargo"
@@ -49,7 +49,7 @@ cargo_test() {
 
 CORE_ARCH="--manifest-path=crates/core_arch/Cargo.toml"
 STD_DETECT="--manifest-path=crates/std_detect/Cargo.toml"
-STDSIMD_EXAMPLES="--manifest-path=examples/Cargo.toml"
+STDARCH_EXAMPLES="--manifest-path=examples/Cargo.toml"
 cargo_test "${CORE_ARCH} --release"
 
 if [ "$NOSTD" != "1" ]; then
@@ -61,14 +61,14 @@ if [ "$NOSTD" != "1" ]; then
     cargo_test "${STD_DETECT} --no-default-features --features=std_detect_dlsym_getauxval"
     cargo_test "${STD_DETECT} --no-default-features --features=std_detect_dlsym_getauxval,std_detect_file_io"
 
-    cargo_test "${STDSIMD_EXAMPLES}"
-    cargo_test "${STDSIMD_EXAMPLES} --release"
+    cargo_test "${STDARCH_EXAMPLES}"
+    cargo_test "${STDARCH_EXAMPLES} --release"
 fi
 
 # Test targets compiled with extra features.
 case ${TARGET} in
     x86*)
-        export STDSIMD_DISABLE_ASSERT_INSTR=1
+        export STDARCH_DISABLE_ASSERT_INSTR=1
         export RUSTFLAGS="${RUSTFLAGS} -C target-feature=+avx"
         cargo_test "--release"
         ;;

crates/assert-instr-macro/src/lib.rs

@@ -1,6 +1,6 @@
 //! Implementation of the `#[assert_instr]` macro
 //!
-//! This macro is used when testing the `stdsimd` crate and is used to generate
+//! This macro is used when testing the `stdarch` crate and is used to generate
 //! test cases to assert that functions do indeed contain the instructions that
 //! we're expecting them to contain.
 //!
@@ -41,7 +41,7 @@ pub fn assert_instr(
     // Disable assert_instr for x86 targets compiled with avx enabled, which
     // causes LLVM to generate different intrinsics that the ones we are
     // testing for.
-    let disable_assert_instr = std::env::var("STDSIMD_DISABLE_ASSERT_INSTR").is_ok();
+    let disable_assert_instr = std::env::var("STDARCH_DISABLE_ASSERT_INSTR").is_ok();
 
     // If instruction tests are disabled avoid emitting this shim at all, just
     // return the original item without our attribute.
@@ -57,7 +57,7 @@ pub fn assert_instr(
     let assert_name = syn::Ident::new(&format!("assert_{}_{}", name, instr_str), name.span());
     // These name has to be unique enough for us to find it in the disassembly later on:
     let shim_name = syn::Ident::new(
-        &format!("stdsimd_test_shim_{}_{}", name, instr_str),
+        &format!("stdarch_test_shim_{}_{}", name, instr_str),
         name.span(),
     );
     let mut inputs = Vec::new();
@@ -123,7 +123,7 @@ pub fn assert_instr(
             // generate some code that's hopefully very tight in terms of
             // codegen but is otherwise unique to prevent code from being
             // folded.
-            ::stdsimd_test::_DONT_DEDUP.store(
+            ::stdarch_test::_DONT_DEDUP.store(
                 std::mem::transmute(#shim_name_str.as_bytes().as_ptr()),
                 std::sync::atomic::Ordering::Relaxed,
             );
@@ -142,7 +142,7 @@ pub fn assert_instr(
             // code:
             unsafe { asm!("" : : "r"(#shim_name as usize) : "memory" : "volatile") };
 
-            ::stdsimd_test::assert(#shim_name as usize,
+            ::stdarch_test::assert(#shim_name as usize,
                                    stringify!(#shim_name),
                                    #instr);
         }

crates/core_arch/Cargo.toml

@@ -8,8 +8,8 @@ authors = [
 ]
 description = "`core::arch` - Rust's core library architecture-specific intrinsics."
 documentation = "https://docs.rs/core_arch"
-homepage = "https://github.com/rust-lang-nursery/stdsimd"
-repository = "https://github.com/rust-lang-nursery/stdsimd"
+homepage = "https://github.com/rust-lang/stdarch"
+repository = "https://github.com/rust-lang/stdarch"
 readme = "README.md"
 keywords = ["core", "simd", "arch", "intrinsics"]
 categories = ["hardware-support", "no-std"]
@@ -18,14 +18,14 @@ build = "build.rs"
 edition = "2018"
 
 [badges]
-travis-ci = { repository = "rust-lang-nursery/stdsimd" }
-appveyor = { repository = "rust-lang-nursery/stdsimd"  }
-is-it-maintained-issue-resolution = { repository = "rust-lang-nursery/stdsimd" }
-is-it-maintained-open-issues = { repository = "rust-lang-nursery/stdsimd" }
+travis-ci = { repository = "rust-lang/stdarch" }
+appveyor = { repository = "rust-lang/stdarch"  }
+is-it-maintained-issue-resolution = { repository = "rust-lang/stdarch" }
+is-it-maintained-open-issues = { repository = "rust-lang/stdarch" }
 maintenance = { status = "experimental" }
 
 [dev-dependencies]
-stdsimd-test = { version = "0.*", path = "../stdsimd-test" }
+stdarch-test = { version = "0.*", path = "../stdarch-test" }
 std_detect = { version = "0.*", path = "../std_detect" }
 
 [target.wasm32-unknown-unknown.dev-dependencies]

crates/core_arch/README.md

@@ -39,14 +39,14 @@ are:
 * [How to get started][contrib]
 * [How to help implement intrinsics][help-implement]
 
-[contrib]: https://github.com/rust-lang-nursery/stdsimd/blob/master/CONTRIBUTING.md
-[help-implement]: https://github.com/rust-lang-nursery/stdsimd/issues/40
-[i686]: https://rust-lang-nursery.github.io/stdsimd/i686/core_arch/
-[x86_64]: https://rust-lang-nursery.github.io/stdsimd/x86_64/core_arch/
-[arm]: https://rust-lang-nursery.github.io/stdsimd/arm/core_arch/
-[aarch64]: https://rust-lang-nursery.github.io/stdsimd/aarch64/core_arch/
-[powerpc]: https://rust-lang-nursery.github.io/stdsimd/powerpc/core_arch/
-[powerpc64]: https://rust-lang-nursery.github.io/stdsimd/powerpc64/core_arch/
+[contrib]: https://github.com/rust-lang/stdarch/blob/master/CONTRIBUTING.md
+[help-implement]: https://github.com/rust-lang/stdarch/issues/40
+[i686]: https://rust-lang.github.io/stdarch/i686/core_arch/
+[x86_64]: https://rust-lang.github.io/stdarch/x86_64/core_arch/
+[arm]: https://rust-lang.github.io/stdarch/arm/core_arch/
+[aarch64]: https://rust-lang.github.io/stdarch/aarch64/core_arch/
+[powerpc]: https://rust-lang.github.io/stdarch/powerpc/core_arch/
+[powerpc64]: https://rust-lang.github.io/stdarch/powerpc64/core_arch/
 
 # License
 
@@ -62,9 +62,9 @@ Unless you explicitly state otherwise, any contribution intentionally submitted
 for inclusion in `core_arch` by you, as defined in the Apache-2.0 license,
 shall be dual licensed as above, without any additional terms or conditions.
 
-[travis]: https://travis-ci.com/rust-lang-nursery/stdsimd
-[Travis-CI Status]: https://travis-ci.com/rust-lang-nursery/stdsimd.svg?branch=master
-[appveyor]: https://ci.appveyor.com/project/rust-lang-libs/stdsimd/branch/master
+[travis]: https://travis-ci.com/rust-lang/stdarch
+[Travis-CI Status]: https://travis-ci.com/rust-lang/stdarch.svg?branch=master
+[appveyor]: https://ci.appveyor.com/project/rust-lang-libs/stdarch/branch/master
 [Appveyor Status]: https://ci.appveyor.com/api/projects/status/ix74qhmilpibn00x/branch/master?svg=true
 [core_arch_crate_badge]: https://img.shields.io/crates/v/core_arch.svg
 [core_arch_crate_link]: https://crates.io/crates/core_arch

crates/core_arch/src/aarch64/crc.rs

@@ -19,7 +19,7 @@ extern "C" {
 }
 
 #[cfg(test)]
-use stdsimd_test::assert_instr;
+use stdarch_test::assert_instr;
 
 /// CRC32 single round checksum for bytes (8 bits).
 #[inline]
@@ -89,7 +89,7 @@ pub unsafe fn __crc32cd(crc: u32, data: u64) -> u32 {
 mod tests {
     use crate::core_arch::{aarch64::*, simd::*};
     use std::mem;
-    use stdsimd_test::simd_test;
+    use stdarch_test::simd_test;
 
     #[simd_test(enable = "crc")]
     unsafe fn test_crc32b() {

crates/core_arch/src/aarch64/crypto.rs

@@ -35,7 +35,7 @@ extern "C" {
 }
 
 #[cfg(test)]
-use stdsimd_test::assert_instr;
+use stdarch_test::assert_instr;
 
 /// AES single round encryption.
 #[inline]
@@ -165,7 +165,7 @@ pub unsafe fn vsha256su1q_u32(
 mod tests {
     use crate::core_arch::{aarch64::*, simd::*};
     use std::mem;
-    use stdsimd_test::simd_test;
+    use stdarch_test::simd_test;
 
     #[simd_test(enable = "crypto")]
     unsafe fn test_vaeseq_u8() {

crates/core_arch/src/aarch64/mod.rs

@@ -21,7 +21,7 @@ pub use self::crc::*;
 pub use super::acle::*;
 
 #[cfg(test)]
-use stdsimd_test::assert_instr;
+use stdarch_test::assert_instr;
 
 /// Generates the trap instruction `BRK 1`
 #[cfg_attr(test, assert_instr(brk))]

crates/core_arch/src/aarch64/neon.rs

@@ -9,7 +9,7 @@ use crate::{
     mem::{transmute, zeroed},
 };
 #[cfg(test)]
-use stdsimd_test::assert_instr;
+use stdarch_test::assert_instr;
 
 types! {
     /// ARM-specific 64-bit wide vector of one packed `f64`.
@@ -1546,7 +1546,7 @@ pub unsafe fn vqtbx4q_p8(a: poly8x16_t, t: poly8x16x4_t, idx: uint8x16_t) -> pol
 mod tests {
     use crate::core_arch::{aarch64::*, simd::*};
     use std::mem::transmute;
-    use stdsimd_test::simd_test;
+    use stdarch_test::simd_test;
 
     #[simd_test(enable = "neon")]
     unsafe fn test_vadd_f64() {