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earlephilhowerearlephilhower
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BREAKING - Use IRAM_ATTR in place of ICACHE_RAM_ATTR (esp8266#7921)
Update the core to use the define that the ESP32 uses, IRAM_ATTR, for placing code in DRAM.
1 parent 6743a65 commit 656a33e

26 files changed

+126
-126
lines changed

Diff for: ‎cores/esp8266/FunctionalInterrupt.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ typedef void (*voidFuncPtrArg)(void*);
1010
extern "C" void __attachInterruptFunctionalArg(uint8_t pin, voidFuncPtr userFunc, void*fp, int mode, bool functional);
1111

1212

13-
void ICACHE_RAM_ATTR interruptFunctional(void* arg)
13+
void IRAM_ATTR interruptFunctional(void* arg)
1414
{
1515
ArgStructure* localArg = (ArgStructure*)arg;
1616
if (localArg->functionInfo->reqScheduledFunction)

Diff for: ‎cores/esp8266/cbuf.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ size_t cbuf::resize(size_t newSize) {
6767
return _size;
6868
}
6969

70-
size_t ICACHE_RAM_ATTR cbuf::available() const {
70+
size_t IRAM_ATTR cbuf::available() const {
7171
if(_end >= _begin) {
7272
return _end - _begin;
7373
}
@@ -108,7 +108,7 @@ size_t cbuf::peek(char *dst, size_t size) {
108108
return size_read;
109109
}
110110

111-
int ICACHE_RAM_ATTR cbuf::read() {
111+
int IRAM_ATTR cbuf::read() {
112112
if(empty())
113113
return -1;
114114

@@ -133,7 +133,7 @@ size_t cbuf::read(char* dst, size_t size) {
133133
return size_read;
134134
}
135135

136-
size_t ICACHE_RAM_ATTR cbuf::write(char c) {
136+
size_t IRAM_ATTR cbuf::write(char c) {
137137
if(full())
138138
return 0;
139139

Diff for: ‎cores/esp8266/cont_util.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@ void cont_init(cont_t* cont) {
4242
}
4343
}
4444

45-
int ICACHE_RAM_ATTR cont_check(cont_t* cont) {
45+
int IRAM_ATTR cont_check(cont_t* cont) {
4646
if(cont->stack_guard1 != CONT_STACKGUARD || cont->stack_guard2 != CONT_STACKGUARD) return 1;
4747

4848
return 0;
@@ -62,7 +62,7 @@ int cont_get_free_stack(cont_t* cont) {
6262
return freeWords * 4;
6363
}
6464

65-
bool ICACHE_RAM_ATTR cont_can_yield(cont_t* cont) {
65+
bool IRAM_ATTR cont_can_yield(cont_t* cont) {
6666
return !ETS_INTR_WITHINISR() &&
6767
cont->pc_ret != 0 && cont->pc_yield == 0;
6868
}

Diff for: ‎cores/esp8266/core_esp8266_i2s.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ typedef struct i2s_state {
6161
uint32_t * curr_slc_buf; // Current buffer for writing
6262
uint32_t curr_slc_buf_pos; // Position in the current buffer
6363
void (*callback) (void);
64-
// Callback function should be defined as 'void ICACHE_RAM_ATTR function_name()',
64+
// Callback function should be defined as 'void IRAM_ATTR function_name()',
6565
// and be placed in IRAM for faster execution. Avoid long computational tasks in this
6666
// function, use it to set flags and process later.
6767
bool driveClocks;
@@ -139,7 +139,7 @@ uint16_t i2s_rx_available(){
139139
}
140140

141141
// Pop the top off of the queue and return it
142-
static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
142+
static uint32_t * IRAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
143143
uint8_t i;
144144
uint32_t *item = ch->slc_queue[0];
145145
ch->slc_queue_len--;
@@ -150,7 +150,7 @@ static uint32_t * ICACHE_RAM_ATTR i2s_slc_queue_next_item(i2s_state_t *ch) {
150150
}
151151

152152
// Append an item to the end of the queue from receive
153-
static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
153+
static void IRAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t *item) {
154154
// Shift everything up, except for the one corresponding to this item
155155
for (int i=0, dest=0; i < ch->slc_queue_len; i++) {
156156
if (ch->slc_queue[i] != item) {
@@ -164,7 +164,7 @@ static void ICACHE_RAM_ATTR i2s_slc_queue_append_item(i2s_state_t *ch, uint32_t
164164
}
165165
}
166166

167-
static void ICACHE_RAM_ATTR i2s_slc_isr(void) {
167+
static void IRAM_ATTR i2s_slc_isr(void) {
168168
ETS_SLC_INTR_DISABLE();
169169
uint32_t slc_intr_status = SLCIS;
170170
SLCIC = 0xFFFFFFFF;

Diff for: ‎cores/esp8266/core_esp8266_phy.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -300,10 +300,10 @@ static const uint8_t ICACHE_FLASH_ATTR phy_init_data[128] =
300300
static bool spoof_init_data = false;
301301

302302
extern int __real_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
303-
extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
303+
extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size);
304304
extern int __get_adc_mode();
305305

306-
extern int ICACHE_RAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
306+
extern int IRAM_ATTR __wrap_spi_flash_read(uint32_t addr, uint32_t* dst, size_t size)
307307
{
308308
if (!spoof_init_data || size != 128) {
309309
return __real_spi_flash_read(addr, dst, size);
@@ -354,6 +354,6 @@ void user_rf_pre_init()
354354
}
355355

356356

357-
void ICACHE_RAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
357+
void IRAM_ATTR user_spi_flash_dio_to_qio_pre_init() {}
358358

359359
};

Diff for: ‎cores/esp8266/core_esp8266_si2c.cpp

+15-15
Original file line numberDiff line numberDiff line change
@@ -103,23 +103,23 @@ class Twi
103103
ETSTimer timer;
104104

105105
// Event/IRQ callbacks, so they can't use "this" and need to be static
106-
static void ICACHE_RAM_ATTR onSclChange(void);
107-
static void ICACHE_RAM_ATTR onSdaChange(void);
106+
static void IRAM_ATTR onSclChange(void);
107+
static void IRAM_ATTR onSdaChange(void);
108108
static void eventTask(ETSEvent *e);
109-
static void ICACHE_RAM_ATTR onTimer(void *unused);
109+
static void IRAM_ATTR onTimer(void *unused);
110110

111111
// Allow not linking in the slave code if there is no call to setAddress
112112
bool _slaveEnabled = false;
113113

114114
// Internal use functions
115-
void ICACHE_RAM_ATTR busywait(unsigned int v);
115+
void IRAM_ATTR busywait(unsigned int v);
116116
bool write_start(void);
117117
bool write_stop(void);
118118
bool write_bit(bool bit);
119119
bool read_bit(void);
120120
bool write_byte(unsigned char byte);
121121
unsigned char read_byte(bool nack);
122-
void ICACHE_RAM_ATTR onTwipEvent(uint8_t status);
122+
void IRAM_ATTR onTwipEvent(uint8_t status);
123123

124124
// Handle the case where a slave needs to stretch the clock with a time-limited busy wait
125125
inline void WAIT_CLOCK_STRETCH()
@@ -149,8 +149,8 @@ class Twi
149149
uint8_t transmit(const uint8_t* data, uint8_t length);
150150
void attachSlaveRxEvent(void (*function)(uint8_t*, size_t));
151151
void attachSlaveTxEvent(void (*function)(void));
152-
void ICACHE_RAM_ATTR reply(uint8_t ack);
153-
void ICACHE_RAM_ATTR releaseBus(void);
152+
void IRAM_ATTR reply(uint8_t ack);
153+
void IRAM_ATTR releaseBus(void);
154154
void enableSlave();
155155
};
156156

@@ -229,7 +229,7 @@ void Twi::enableSlave()
229229
}
230230
}
231231

232-
void ICACHE_RAM_ATTR Twi::busywait(unsigned int v)
232+
void IRAM_ATTR Twi::busywait(unsigned int v)
233233
{
234234
unsigned int i;
235235
for (i = 0; i < v; i++) // loop time is 5 machine cycles: 31.25ns @ 160MHz, 62.5ns @ 80MHz
@@ -472,9 +472,9 @@ void Twi::attachSlaveTxEvent(void (*function)(void))
472472
}
473473

474474
// DO NOT INLINE, inlining reply() in combination with compiler optimizations causes function breakup into
475-
// parts and the ICACHE_RAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
475+
// parts and the IRAM_ATTR isn't propagated correctly to all parts, which of course causes crashes.
476476
// TODO: test with gcc 9.x and if it still fails, disable optimization with -fdisable-ipa-fnsplit
477-
void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
477+
void IRAM_ATTR Twi::reply(uint8_t ack)
478478
{
479479
// transmit master read ready signal, with or without ack
480480
if (ack)
@@ -492,7 +492,7 @@ void ICACHE_RAM_ATTR Twi::reply(uint8_t ack)
492492
}
493493

494494

495-
void ICACHE_RAM_ATTR Twi::releaseBus(void)
495+
void IRAM_ATTR Twi::releaseBus(void)
496496
{
497497
// release bus
498498
//TWCR = _BV(TWEN) | _BV(TWIE) | _BV(TWEA) | _BV(TWINT);
@@ -505,7 +505,7 @@ void ICACHE_RAM_ATTR Twi::releaseBus(void)
505505
}
506506

507507

508-
void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
508+
void IRAM_ATTR Twi::onTwipEvent(uint8_t status)
509509
{
510510
twip_status = status;
511511
switch (status)
@@ -612,7 +612,7 @@ void ICACHE_RAM_ATTR Twi::onTwipEvent(uint8_t status)
612612
}
613613
}
614614

615-
void ICACHE_RAM_ATTR Twi::onTimer(void *unused)
615+
void IRAM_ATTR Twi::onTimer(void *unused)
616616
{
617617
(void)unused;
618618
twi.releaseBus();
@@ -662,7 +662,7 @@ void Twi::eventTask(ETSEvent *e)
662662
// Shorthand for if the state is any of the or'd bitmask x
663663
#define IFSTATE(x) if (twip_state_mask & (x))
664664

665-
void ICACHE_RAM_ATTR Twi::onSclChange(void)
665+
void IRAM_ATTR Twi::onSclChange(void)
666666
{
667667
unsigned int sda;
668668
unsigned int scl;
@@ -860,7 +860,7 @@ void ICACHE_RAM_ATTR Twi::onSclChange(void)
860860
}
861861
}
862862

863-
void ICACHE_RAM_ATTR Twi::onSdaChange(void)
863+
void IRAM_ATTR Twi::onSdaChange(void)
864864
{
865865
unsigned int sda;
866866
unsigned int scl;

Diff for: ‎cores/esp8266/core_esp8266_timer.cpp

+11-11
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ extern "C" {
3131

3232
static volatile timercallback timer1_user_cb = NULL;
3333

34-
void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
34+
void IRAM_ATTR timer1_isr_handler(void *para, void *frame) {
3535
(void) para;
3636
(void) frame;
3737
if ((T1C & ((1 << TCAR) | (1 << TCIT))) == 0) TEIE &= ~TEIE1;//edge int disable
@@ -45,32 +45,32 @@ void ICACHE_RAM_ATTR timer1_isr_handler(void *para, void *frame) {
4545
}
4646
}
4747

48-
void ICACHE_RAM_ATTR timer1_isr_init(){
48+
void IRAM_ATTR timer1_isr_init(){
4949
ETS_FRC_TIMER1_INTR_ATTACH(timer1_isr_handler, NULL);
5050
}
5151

52-
void ICACHE_RAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
52+
void IRAM_ATTR timer1_attachInterrupt(timercallback userFunc) {
5353
timer1_user_cb = userFunc;
5454
ETS_FRC1_INTR_ENABLE();
5555
}
5656

57-
void ICACHE_RAM_ATTR timer1_detachInterrupt() {
57+
void IRAM_ATTR timer1_detachInterrupt() {
5858
timer1_user_cb = 0;
5959
TEIE &= ~TEIE1;//edge int disable
6060
ETS_FRC1_INTR_DISABLE();
6161
}
6262

63-
void ICACHE_RAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
63+
void IRAM_ATTR timer1_enable(uint8_t divider, uint8_t int_type, uint8_t reload){
6464
T1C = (1 << TCTE) | ((divider & 3) << TCPD) | ((int_type & 1) << TCIT) | ((reload & 1) << TCAR);
6565
T1I = 0;
6666
}
6767

68-
void ICACHE_RAM_ATTR timer1_write(uint32_t ticks){
68+
void IRAM_ATTR timer1_write(uint32_t ticks){
6969
T1L = ((ticks)& 0x7FFFFF);
7070
if ((T1C & (1 << TCIT)) == 0) TEIE |= TEIE1;//edge int enable
7171
}
7272

73-
void ICACHE_RAM_ATTR timer1_disable(){
73+
void IRAM_ATTR timer1_disable(){
7474
T1C = 0;
7575
T1I = 0;
7676
}
@@ -80,7 +80,7 @@ void ICACHE_RAM_ATTR timer1_disable(){
8080

8181
static volatile timercallback timer0_user_cb = NULL;
8282

83-
void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
83+
void IRAM_ATTR timer0_isr_handler(void *para, void *frame) {
8484
(void) para;
8585
(void) frame;
8686
if (timer0_user_cb) {
@@ -92,16 +92,16 @@ void ICACHE_RAM_ATTR timer0_isr_handler(void *para, void *frame) {
9292
}
9393
}
9494

95-
void ICACHE_RAM_ATTR timer0_isr_init(){
95+
void IRAM_ATTR timer0_isr_init(){
9696
ETS_CCOMPARE0_INTR_ATTACH(timer0_isr_handler, NULL);
9797
}
9898

99-
void ICACHE_RAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
99+
void IRAM_ATTR timer0_attachInterrupt(timercallback userFunc) {
100100
timer0_user_cb = userFunc;
101101
ETS_CCOMPARE0_ENABLE();
102102
}
103103

104-
void ICACHE_RAM_ATTR timer0_detachInterrupt() {
104+
void IRAM_ATTR timer0_detachInterrupt() {
105105
timer0_user_cb = NULL;
106106
ETS_CCOMPARE0_DISABLE();
107107
}

Diff for: ‎cores/esp8266/core_esp8266_waveform.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ int stopWaveform(uint8_t pin);
112112
// to determine whether or not to perform an operation.
113113
// Pass in NULL to disable the callback and, if no other waveforms being
114114
// generated, stop the timer as well.
115-
// Make sure the CB function has the ICACHE_RAM_ATTR decorator.
115+
// Make sure the CB function has the IRAM_ATTR decorator.
116116
void setTimer1Callback(uint32_t (*fn)());
117117

118118

Diff for: ‎cores/esp8266/core_esp8266_waveform_phase.cpp

+5-5
Original file line numberDiff line numberDiff line change
@@ -111,7 +111,7 @@ namespace {
111111
}
112112

113113
// Interrupt on/off control
114-
static ICACHE_RAM_ATTR void timer1Interrupt();
114+
static IRAM_ATTR void timer1Interrupt();
115115

116116
// Non-speed critical bits
117117
#pragma GCC optimize ("Os")
@@ -125,7 +125,7 @@ static void initTimer() {
125125
timer1_write(IRQLATENCYCCYS); // Cause an interrupt post-haste
126126
}
127127

128-
static void ICACHE_RAM_ATTR deinitTimer() {
128+
static void IRAM_ATTR deinitTimer() {
129129
ETS_FRC_TIMER1_NMI_INTR_ATTACH(NULL);
130130
timer1_disable();
131131
timer1_isr_init();
@@ -218,7 +218,7 @@ int startWaveformClockCycles_weak(uint8_t pin, uint32_t highCcys, uint32_t lowCc
218218
}
219219

220220
// Stops a waveform on a pin
221-
ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
221+
IRAM_ATTR int stopWaveform_weak(uint8_t pin) {
222222
// Can't possibly need to stop anything if there is no timer active
223223
if (!waveform.timer1Running) {
224224
return false;
@@ -252,7 +252,7 @@ ICACHE_RAM_ATTR int stopWaveform_weak(uint8_t pin) {
252252

253253
// For dynamic CPU clock frequency switch in loop the scaling logic would have to be adapted.
254254
// Using constexpr makes sure that the CPU clock frequency is compile-time fixed.
255-
static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
255+
static inline IRAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool isCPU2X) {
256256
if (ISCPUFREQ160MHZ) {
257257
return isCPU2X ? ccys : (ccys >> 1);
258258
}
@@ -261,7 +261,7 @@ static inline ICACHE_RAM_ATTR int32_t scaleCcys(const int32_t ccys, const bool i
261261
}
262262
}
263263

264-
static ICACHE_RAM_ATTR void timer1Interrupt() {
264+
static IRAM_ATTR void timer1Interrupt() {
265265
const uint32_t isrStartCcy = ESP.getCycleCount();
266266
int32_t clockDrift = isrStartCcy - waveform.nextEventCcy;
267267
const bool isCPU2X = CPU2X & 1;

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