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michalderkaczmichalderkacz
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Merge pull request #6 from clktmr/mips
Support GOARCH=mips64
2 parents bc94d09 + be0dfbb commit 4027ff1

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42 files changed

+1748
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lines changed

‎src/cmd/asm/internal/arch/arch.go

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -471,9 +471,6 @@ func archMips64(linkArch *obj.LinkArch) *Arch {
471471
for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
472472
register[obj.Rconv(i)] = int16(i)
473473
}
474-
for i := mips.REG_W0; i <= mips.REG_W31; i++ {
475-
register[obj.Rconv(i)] = int16(i)
476-
}
477474
register["HI"] = mips.REG_HI
478475
register["LO"] = mips.REG_LO
479476
// Pseudo-registers.
@@ -491,7 +488,6 @@ func archMips64(linkArch *obj.LinkArch) *Arch {
491488
"FCR": true,
492489
"M": true,
493490
"R": true,
494-
"W": true,
495491
}
496492

497493
instructions := make(map[string]obj.As)

‎src/cmd/asm/internal/arch/mips.go

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -63,10 +63,6 @@ func mipsRegisterNumber(name string, n int16) (int16, bool) {
6363
if 0 <= n && n <= 31 {
6464
return mips.REG_R0 + n, true
6565
}
66-
case "W":
67-
if 0 <= n && n <= 31 {
68-
return mips.REG_W0 + n, true
69-
}
7066
}
7167
return 0, false
7268
}

‎src/cmd/asm/internal/asm/testdata/mips.s

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -429,11 +429,6 @@ label4:
429429
CLZ R1, R2 // 70221020
430430
CLO R1, R2 // 70221021
431431

432-
WSBH R1, R2 // 7c0110a0
433-
434-
SEB R1, R2 // 7c011420
435-
SEH R1, R2 // 7c011620
436-
437432
// to (Hi, Lo)
438433
MADD R2, R1 // 70220000
439434
MSUB R2, R1 // 70220004

‎src/cmd/asm/internal/asm/testdata/mips64.s

Lines changed: 0 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -587,50 +587,8 @@ label4:
587587
CALL foo(SB)
588588
RET foo(SB)
589589

590-
// unary operation
591590
NEGW R1, R2 // 00011023
592591
NEGV R1, R2 // 0001102f
593-
594-
WSBH R1, R2 // 7c0110a0
595-
DSBH R1, R2 // 7c0110a4
596-
DSHD R1, R2 // 7c011164
597-
598-
SEB R1, R2 // 7c011420
599-
SEH R1, R2 // 7c011620
600-
601-
RET
602-
603-
// MSA VMOVI
604-
VMOVB $511, W0 // 7b0ff807
605-
VMOVH $24, W23 // 7b20c5c7
606-
VMOVW $-24, W15 // 7b5f43c7
607-
VMOVD $-511, W31 // 7b700fc7
608-
609-
VMOVB (R0), W8 // 78000220
610-
VMOVB 511(R3), W0 // 79ff1820
611-
VMOVB -512(R12), W21 // 7a006560
612-
VMOVH (R24), W12 // 7800c321
613-
VMOVH 110(R19), W8 // 78379a21
614-
VMOVH -70(R12), W3 // 7bdd60e1
615-
VMOVW (R3), W31 // 78001fe2
616-
VMOVW 64(R20), W16 // 7810a422
617-
VMOVW -104(R17), W24 // 7be68e22
618-
VMOVD (R3), W2 // 780018a3
619-
VMOVD 128(R23), W19 // 7810bce3
620-
VMOVD -256(R31), W0 // 7be0f823
621-
622-
VMOVB W8, (R0) // 78000224
623-
VMOVB W0, 511(R3) // 79ff1824
624-
VMOVB W21, -512(R12) // 7a006564
625-
VMOVH W12, (R24) // 7800c325
626-
VMOVH W8, 110(R19) // 78379a25
627-
VMOVH W3, -70(R12) // 7bdd60e5
628-
VMOVW W31, (R3) // 78001fe6
629-
VMOVW W16, 64(R20) // 7810a426
630-
VMOVW W24, -104(R17) // 7be68e26
631-
VMOVD W2, (R3) // 780018a7
632-
VMOVD W19, 128(R23) // 7810bce7
633-
VMOVD W0, -256(R31) // 7be0f827
634592
RET
635593

636594
// END

‎src/cmd/dist/build.go

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1743,6 +1743,7 @@ var cgoEnabled = map[string]bool{
17431743
"windows/arm64": true,
17441744
"noos/thumb": false,
17451745
"noos/riscv64": false,
1746+
"noos/mips64": false,
17461747
}
17471748

17481749
// List of platforms that are marked as broken ports.

‎src/cmd/internal/obj/mips/a.out.go

Lines changed: 0 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,6 @@ const (
4343
NSYM = 50
4444
NREG = 32 /* number of general registers */
4545
NFREG = 32 /* number of floating point registers */
46-
NWREG = 32 /* number of MSA registers */
4746
)
4847

4948
const (
@@ -181,41 +180,6 @@ const (
181180
REG_FCR30
182181
REG_FCR31
183182

184-
// MSA registers
185-
// The lower bits of W registers are alias to F registers
186-
REG_W0 // must be a multiple of 32
187-
REG_W1
188-
REG_W2
189-
REG_W3
190-
REG_W4
191-
REG_W5
192-
REG_W6
193-
REG_W7
194-
REG_W8
195-
REG_W9
196-
REG_W10
197-
REG_W11
198-
REG_W12
199-
REG_W13
200-
REG_W14
201-
REG_W15
202-
REG_W16
203-
REG_W17
204-
REG_W18
205-
REG_W19
206-
REG_W20
207-
REG_W21
208-
REG_W22
209-
REG_W23
210-
REG_W24
211-
REG_W25
212-
REG_W26
213-
REG_W27
214-
REG_W28
215-
REG_W29
216-
REG_W30
217-
REG_W31
218-
219183
REG_HI
220184
REG_LO
221185

@@ -253,8 +217,6 @@ func init() {
253217
f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers -- see cmd/compile/internal/ssa/gen/MIPSOps.go
254218
MIPSDWARFRegisters[REG_HI] = 64
255219
MIPSDWARFRegisters[REG_LO] = 65
256-
// The lower bits of W registers are alias to F registers
257-
f(REG_W0, REG_W31, 32)
258220
}
259221

260222
const (
@@ -281,7 +243,6 @@ const (
281243
C_FREG
282244
C_FCREG
283245
C_MREG /* special processor register */
284-
C_WREG /* MSA registers */
285246
C_HI
286247
C_LO
287248
C_ZCON
@@ -394,8 +355,6 @@ const (
394355
AROTRV
395356
ASC
396357
ASCV
397-
ASEB
398-
ASEH
399358
ASGT
400359
ASGTU
401360
ASLL
@@ -417,7 +376,6 @@ const (
417376
ATLBWR
418377
ATNE
419378
AWORD
420-
AWSBH
421379
AXOR
422380

423381
/* 64-bit */
@@ -437,8 +395,6 @@ const (
437395
AADDVU
438396
ASUBV
439397
ASUBVU
440-
ADSBH
441-
ADSHD
442398

443399
/* 64-bit FP */
444400
ATRUNCFV
@@ -451,12 +407,6 @@ const (
451407
AMOVVF
452408
AMOVVD
453409

454-
/* MSA */
455-
AVMOVB
456-
AVMOVH
457-
AVMOVW
458-
AVMOVD
459-
460410
ALAST
461411

462412
// aliases
@@ -482,7 +432,4 @@ func init() {
482432
if REG_FCR0%32 != 0 {
483433
panic("REG_FCR0 is not a multiple of 32")
484434
}
485-
if REG_W0%32 != 0 {
486-
panic("REG_W0 is not a multiple of 32")
487-
}
488435
}

‎src/cmd/internal/obj/mips/anames.go

Lines changed: 0 additions & 9 deletions
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‎src/cmd/internal/obj/mips/anames0.go

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@ var cnames0 = []string{
1010
"FREG",
1111
"FCREG",
1212
"MREG",
13-
"WREG",
1413
"HI",
1514
"LO",
1615
"ZCON",

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