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John DoeJohn Doe
John Doe
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John Doe
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register and clock changes
1 parent 1501818 commit 6ab3c76

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7 files changed

+67
-49
lines changed

7 files changed

+67
-49
lines changed

Diff for: ‎cores/esp8266/HardwareSerial.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -262,7 +262,7 @@ void uart_set_baudrate(uart_t* uart, int baud_rate) {
262262
if(uart == 0)
263263
return;
264264
uart->baud_rate = baud_rate;
265-
USD(uart->uart_nr) = (80000000UL / uart->baud_rate);
265+
USD(uart->uart_nr) = (ESP8266_CLOCK / uart->baud_rate);
266266
}
267267

268268
int uart_get_baudrate(uart_t* uart) {
@@ -359,15 +359,15 @@ void uart_swap(uart_t* uart) {
359359
if(uart->txPin == 1 && uart->rxPin == 3) {
360360
pinMode(15, FUNCTION_4); //TX
361361
pinMode(13, FUNCTION_4); //RX
362-
USWAP |= (1 << USWAP0);
362+
IOSWAP |= (1 << IOSWAPU0);
363363
pinMode(1, INPUT); //TX
364364
pinMode(3, INPUT); //RX
365365
uart->rxPin = 13;
366366
uart->txPin = 15;
367367
} else {
368368
pinMode(1, SPECIAL); //TX
369369
pinMode(3, SPECIAL); //RX
370-
USWAP &= ~(1 << USWAP0);
370+
IOSWAP &= ~(1 << IOSWAPU0);
371371
pinMode(15, INPUT); //TX
372372
pinMode(13, INPUT); //RX
373373
uart->rxPin = 3;

Diff for: ‎cores/esp8266/core_esp8266_wiring_pwm.c

+1-1
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ void prep_pwm_steps(){
8383
pwm_steps_len = pwm_temp_steps_len;
8484
ets_memcpy(pwm_steps, pwm_temp_steps, (pwm_temp_steps_len + 1) * 2);
8585
ets_memcpy(pwm_steps_mask, pwm_temp_masks, pwm_temp_steps_len * 4);
86-
pwm_multiplier = F_CPU/(PWMRANGE * pwm_freq);
86+
pwm_multiplier = ESP8266_CLOCK/(PWMRANGE * pwm_freq);
8787
ETS_FRC1_INTR_ENABLE();
8888
}
8989

Diff for: ‎cores/esp8266/esp8266_peri.h

+49-30
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,15 @@
2525

2626
#define ESP8266_REG(addr) *((volatile uint32_t *)(0x60000000+(addr)))
2727
#define ESP8266_DREG(addr) *((volatile uint32_t *)(0x3FF00000+(addr)))
28+
#define ESP8266_CLOCK 80000000UL
29+
30+
//CPU Register
31+
#define CPU2X ESP8266_DREG(0x14) //when bit 0 is set, F_CPU = 160MHz
32+
33+
//OTP Registers
34+
#define MAC0 ESP8266_DREG(0x50)
35+
#define MAC1 ESP8266_DREG(0x54)
36+
#define CHIPID ESP8266_DREG(0x58)
2837

2938
//GPIO (0-15) Control Registers
3039
#define GPO ESP8266_REG(0x300) //GPIO_OUT R/W (Output Level)
@@ -149,20 +158,26 @@ extern uint8_t esp8266_gpioToFn[16];
149158
#define TCIT 0 //Interrupt Type 0:edge, 1:level
150159

151160
//RTC Registers
152-
#define RTCMEM(i) ESP8266_REG(0x1100 + (((i) & 0xFF) * 4)) //RTC RAM 768 bytes, 192 registers
153161
#define RTCSV ESP8266_REG(0x704) //RTC SLEEP COUNTER Target Value
154162
#define RTCCV ESP8266_REG(0x71C) //RTC SLEEP COUNTER Value
155163
#define RTCIS ESP8266_REG(0x720) //RTC INT Status
156164
#define RTCIC ESP8266_REG(0x724) //RTC INT Clear
157165
#define RTCIE ESP8266_REG(0x728) //RTC INT Enable
158-
#define RTCS0 ESP8266_REG(0x730) //RTC SCRATCH 0
159-
#define RTCS1 ESP8266_REG(0x734) //RTC SCRATCH 1
160-
#define RTCS2 ESP8266_REG(0x738) //RTC SCRATCH 2
161-
#define RTCS3 ESP8266_REG(0x73C) //RTC SCRATCH 3
162166

163-
//UART SWAP Register
164-
#define USWAP ESP8266_DREG(0x28)
165-
#define USWAP0 2 //BIT 2 swaps UART 0
167+
//IO SWAP Register
168+
#define IOSWAP ESP8266_DREG(0x28)
169+
#define IOSWAPU 0 //Swaps UART
170+
#define IOSWAPS 1 //Swaps SPI
171+
#define IOSWAPU0 2 //Swaps UART 0 pins (u0rxd <-> u0cts), (u0txd <-> u0rts)
172+
#define IOSWAPU1 3 //Swaps UART 1 pins (u1rxd <-> u1cts), (u1txd <-> u1rts)
173+
#define IOSWAPHS 5 //Sets HSPI with higher prio
174+
#define IOSWAP2HS 6 //Sets Two SPI Masters on HSPI
175+
#define IOSWAP2CS 7 //Sets Two SPI Masters on CSPI
176+
177+
//UART INT Status
178+
#define UIS ESP8266_DREG(0x20020)
179+
#define UIS0 0
180+
#define UIS1 2
166181

167182
//UART 0 Registers
168183
#define U0F ESP8266_REG(0x000) //UART FIFO
@@ -227,45 +242,49 @@ extern uint8_t esp8266_gpioToFn[16];
227242
#define UIFF 0 //RX FIFO Full
228243

229244
//UART STATUS Registers Bits
230-
#define USTX 31 //TX PIN Level
231-
#define USRTS 30 //RTS PIN Level
232-
#define USDTR 39 //DTR PIN Level
245+
#define USTX 31 //TX PIN Level
246+
#define USRTS 30 //RTS PIN Level
247+
#define USDTR 39 //DTR PIN Level
233248
#define USTXC 16 //TX FIFO COUNT (8bit)
234249
#define USRXD 15 //RX PIN Level
235250
#define USCTS 14 //CTS PIN Level
236251
#define USDSR 13 //DSR PIN Level
237252
#define USRXC 0 //RX FIFO COUNT (8bit)
238253

239254
//UART CONF0 Registers Bits
240-
#define UCDTRI 24 //Invert DTR
241-
#define UCRTSI 23 //Invert RTS
242-
#define UCTXI 22 //Invert TX
243-
#define UCDSRI 21 //Invert DSR
244-
#define UCCTSI 20 //Invert CTS
245-
#define UCRXI 19 //Invert RX
255+
#define UCDTRI 24 //Invert DTR
256+
#define UCRTSI 23 //Invert RTS
257+
#define UCTXI 22 //Invert TX
258+
#define UCDSRI 21 //Invert DSR
259+
#define UCCTSI 20 //Invert CTS
260+
#define UCRXI 19 //Invert RX
246261
#define UCTXRST 18 //Reset TX FIFO
247262
#define UCRXRST 17 //Reset RX FIFO
248263
#define UCTXHFE 15 //TX Harware Flow Enable
249-
#define UCLBE 14 //LoopBack Enable
250-
#define UCBRK 8 //Send Break on the TX line
264+
#define UCLBE 14 //LoopBack Enable
265+
#define UCBRK 8 //Send Break on the TX line
251266
#define UCSWDTR 7 //Set this bit to assert DTR
252267
#define UCSWRTS 6 //Set this bit to assert RTS
253-
#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit
254-
#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit
255-
#define UCPAE 1 //Parity Enable
256-
#define UCPA 0 //Parity 0:even, 1:odd
268+
#define UCSBN 4 //StopBits Count (2bit) 0:disable, 1:1bit, 2:1.5bit, 3:2bit
269+
#define UCBN 2 //DataBits Count (2bin) 0:5bit, 1:6bit, 2:7bit, 3:8bit
270+
#define UCPAE 1 //Parity Enable
271+
#define UCPA 0 //Parity 0:even, 1:odd
257272

258273
//UART CONF1 Registers Bits
259-
#define UCTOE 31 //RX TimeOut Enable
260-
#define UCTOT 24 //RX TimeOut Treshold (7bit)
274+
#define UCTOE 31 //RX TimeOut Enable
275+
#define UCTOT 24 //RX TimeOut Treshold (7bit)
261276
#define UCRXHFE 23 //RX Harware Flow Enable
262277
#define UCRXHFT 16 //RX Harware Flow Treshold (7bit)
263-
#define UCFET 8 //TX FIFO Empty Treshold (7bit)
264-
#define UCFFT 0 //RX FIFO Full Treshold (7bit)
278+
#define UCFET 8 //TX FIFO Empty Treshold (7bit)
279+
#define UCFFT 0 //RX FIFO Full Treshold (7bit)
280+
281+
//WDT Feed (the dog) Register
282+
#define WDTFEED ESP8266_REG(0x914)
283+
#define WDT_FEED() (WDTFEED = 0x73)
265284

266-
//WDT Register used for UART
267-
#define WDTRST ESP8266_REG(0x914)
268-
#define WDT_RESET() (WDTRST = 0x73)
285+
//SPI_READY
286+
#define SPIRDY ESP8266_DREG(0x0C)
287+
#define SPIBUSY 9 //wait SPI idle
269288

270289
//SPI0 Registers (SPI0 is used for the flash)
271290
#define SPI0CMD ESP8266_REG(0x200)

Diff for: ‎doc/rgisters_dump.txt

+8-9
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,14 @@
55
0x3FF00000 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
66
0x3FF00004 | 00000000000000000000000000000101 | 0x00000005 | 5 | | TEIE
77
0x3FF00008 | 00000000000000000000100000001111 | 0x0000080F | 2063 | . |
8-
0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | |
8+
0x3FF0000C | 00000100000000000000000100000010 | 0x04000102 | 67109122 | | SPIRDY
99
0x3FF00010 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
10-
0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
10+
0x3FF00014 | 00000000000000000000000000000000 | 0x00000000 | 0 | | CPU2X
1111
0x3FF00018 | 11111111111111110000000011111111 | 0xFFFF00FF | 4294902015 | .. . |
1212
0x3FF0001C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
1313
0x3FF00020 | 00000000000000000000000000010000 | 0x00000010 | 16 | . | SPIIR
1414
0x3FF00024 | 00000000000000000000000000011010 | 0x0000001A | 26 | . |
15-
0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | USWAP
15+
0x3FF00028 | 00000000000000000000000000000000 | 0x00000000 | 0 | | IOSWAP
1616
0x3FF0002C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
1717
0x3FF00030 | 00000000000000000100000001000000 | 0x00004040 | 16448 | @@ |
1818
0x3FF00034 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
@@ -22,9 +22,9 @@
2222
0x3FF00044 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
2323
0x3FF00048 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
2424
0x3FF0004C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
25-
0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. |
26-
0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. |
27-
0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . |
25+
0x3FF00050 | 10011101111011100000000000000000 | 0x9DEE0000 | 2649620480 | .. | MAC0
26+
0x3FF00054 | 00000010000000001001110011000010 | 0x02009CC2 | 33594562 | .. | MAC1
27+
0x3FF00058 | 00000000000000001010000000000000 | 0x0000A000 | 40960 | . | CHIPID
2828
0x3FF0005C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
2929
0x3FF00060 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
3030
0x3FF00064 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
@@ -687,14 +687,13 @@
687687
0x60000908 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
688688
0x6000090C | 00000000000000111001000001110010 | 0x00039072 | 233586 | r |
689689
0x60000910 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
690-
0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTRST
690+
0x60000914 | 00000000000000000000000000000000 | 0x00000000 | 0 | | WDTFEED
691691
0x60000918 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
692692
0x6000091C | 00000000000000000000000000000000 | 0x00000000 | 0 | |
693693
0x60000920 | 00000000000000000000000000111001 | 0x00000039 | 57 | 9 |
694694
0x60000924 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
695695
0x60000928 | 00000000000000000000000000001011 | 0x0000000B | 11 | |
696-
0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 |Ÿ
697-
ê|
696+
0x6000092C | 00000111100111110000110111101010 | 0x079F0DEA | 127864298 | Ÿê |
698697
0x60000930 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
699698
0x60000934 | 00000000000000000000000000000000 | 0x00000000 | 0 | |
700699
0x60000938 | 00000000000000000000000000000000 | 0x00000000 | 0 | |

Diff for: ‎libraries/SPI/SPI.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -121,14 +121,14 @@ void SPIClass::setBitOrder(uint8_t bitOrder) {
121121
* @return
122122
*/
123123
static uint32_t ClkRegToFreq(spiClk_t * reg) {
124-
return (SPI_MAX_SPEED / ((reg->regPre + 1) * (reg->regN + 1)));
124+
return (ESP8266_CLOCK / ((reg->regPre + 1) * (reg->regN + 1)));
125125
}
126126

127127
void SPIClass::setFrequency(uint32_t freq) {
128128
static uint32_t lastSetFrequency = 0;
129129
static uint32_t lastSetRegister = 0;
130130

131-
if(freq >= SPI_MAX_SPEED) {
131+
if(freq >= ESP8266_CLOCK) {
132132
setClockDivider(0x80000000);
133133
return;
134134
}
@@ -164,7 +164,7 @@ void SPIClass::setFrequency(uint32_t freq) {
164164
reg.regN = calN;
165165

166166
while(calPreVari++ <= 1) { // test different variants for Pre (we calculate in int so we miss the decimals, testing is the easyest and fastest way)
167-
calPre = (((SPI_MAX_SPEED / (reg.regN + 1)) / freq) - 1) + calPreVari;
167+
calPre = (((ESP8266_CLOCK / (reg.regN + 1)) / freq) - 1) + calPreVari;
168168
if(calPre > 0x1FFF) {
169169
reg.regPre = 0x1FFF; // 8191
170170
} else if(calPre <= 0) {

Diff for: ‎libraries/SPI/SPI.h

-2
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,6 @@
4545
#define SPI_CLOCK_DIV64 0x04fc1001 //250 KHz
4646
#endif
4747

48-
#define SPI_MAX_SPEED (80000000L)
49-
5048
const uint8_t SPI_MODE0 = 0x00; ///< CPOL: 0 CPHA: 0
5149
const uint8_t SPI_MODE1 = 0x01; ///< CPOL: 0 CPHA: 1
5250
const uint8_t SPI_MODE2 = 0x10; ///< CPOL: 1 CPHA: 0

Diff for: ‎tools/sdk/include/ets_sys.h

+3-1
Original file line numberDiff line numberDiff line change
@@ -39,11 +39,13 @@ typedef struct _ETSTIMER_ {
3939

4040
typedef void (*int_handler_t)(void*);
4141

42-
#define ETS_SPI_INUM 2
42+
#define ETS_SPI_INUM 2
4343
#define ETS_GPIO_INUM 4
4444
#define ETS_UART_INUM 5
4545
#define ETS_UART1_INUM 5
4646
#define ETS_CCOMPARE0_INUM 6
47+
#define ETS_SOFT_INUM 7
48+
#define ETS_WDT_INUM 8
4749
#define ETS_FRC_TIMER1_INUM 9 /* use edge*/
4850

4951
#define ETS_INTR_LOCK() \

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