Finalize fix for PUYA flash and preSDK use of Cache_Read_Enable.

This resolves the exception 0 issue with PUYA flash when using
flash/ICACHE for umm_init and/or using HWDT Stack Dump.

Author: mhightower83

Diff for: cores/esp8266/mmu_iram.cpp

@@ -196,17 +196,17 @@ extern void Cache_Read_Disable(void);
 extern void Cache_Read_Enable(uint8_t map, uint8_t p, uint8_t v);
 #endif  // #if (MMU_ICACHE_SIZE == 0x4000)
 
-#if 1 // New experimental code
 /*
  * This wrapper is for running code early from IROM (flash) before the SDK
  * starts. Since the NONOS SDK will do a full and proper flash device init for
  * speed and mode, we only do a minimum to make ICACHE functional, keeping IRAM
  * use to a minimum. After the SDK has started, this function is not needed and
- * should not be called.
+ * must not be called.
  */
 void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) {
-  //?? If the problem is not resolved add this line back.
-  //?? Cache_Read_Disable();
+  // Cache Read must be disabled. This is always the case on entry when called
+  // from the right context.
+  // Cache_Read_Disable();
 
   // The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK
   // as part of flash init/configuration. It may be necessary for some flash
@@ -218,28 +218,20 @@ void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) {
   // defaults to 1.
   SPI0U |= SPIUCSSETUP; // SPI_CS_SETUP or BIT5
 
-  // I am not sure what this is does. It appears to be the key function called
-  // from `fix_cache_bug` in the NONOS SDK - Will this help PUYA Flash work?
-  // It appears to do some, lowlevel undocumented register maniplation and
-  // device specific init based on OTP CHIPID model bits.
+  // phy_get_bb_evm is the key function, called from fix_cache_bug in the NONOS
+  // SDK. This addition resolves the PUYA Flash issue with exception 0, when
+  // early Cache_Read_Enable is used.
   extern uint32_t phy_get_bb_evm(void); // undocumented
   phy_get_bb_evm();
 
-  // For early Cache_Read_Enable only do ICACHE_SIZE_16. The affected registers
-  // are fully restored when Cache_Read_Disable is called. With ICACHE_SIZE_32
-  // one bit is missed at disable. Leave the full commitment to ICACHE_SIZE_32
-  // for the NONOS SDK.
+  // For early Cache_Read_Enable, only do ICACHE_SIZE_16. With this option,
+  // Cache_Read_Disable will fully restore the original register states. With
+  // ICACHE_SIZE_32, one bit is missed when disabling. Leave the full access
+  // calls for the NONOS SDK.
   // This only works with image slice 0, which is all we do presently.
   Cache_Read_Enable(0, 0, ICACHE_SIZE_16);
   fn();
   Cache_Read_Disable();
 }
-#else
-void IRAM_ATTR mmu_wrap_irom_fn(void (*fn)(void)) {
-  Cache_Read_Enable(0, 0, ICACHE_SIZE_16);
-  fn();
-  Cache_Read_Disable();
-}
-#endif
 
 };