Synopsys ARC Processors and GNU Toolchains for Them

Synopsys ARC Processors

Synopsys ARC processors are represented by three generations of Instruction Set Architectures (ISA). Each ISA consists of one or more processor families with different microarchitectures. All cores may be configured to support little or big endianness. All cores except ARC EM family may be configured to support running complex operation systems like Linux. Some of them are listed here:

1. ARCv1 ISA:

   • ARC 600 Processor Family of 32-bit cores
   • ARC 700 Processor Family of 32-bit cores

2. ARCv2 ISA:

   • ARC EM Processor Family of 32-bit cores
   • ARC HS Processor Family of 32-bit cores (HS3x, HS4x, HS4xD)

3. ARCv3 ISA:

   • ARC HS Processor Family of 32-bit cores (HS5x, HS5xD)
   • ARC HS Processor Family of 64-bit cores (HS6x)

You can find programmer's reference manuals and datasheets for each core on corresponding web pages.

Toolchains for Baremetal Targets

GNU toolchains for ARC processors consist of GCC, Binutils and GDB. Newlib standard library is used for building baremetal applications. This table depicts which GCC driver should be used depending on ARC CPU family:

Family	Driver/Triplet
ARCv1	arc-elf32-gcc
ARCv2	arc-elf32-gcc
ARCv3	arc64-elf-gcc