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BrunoASMauricioclaziss
BrunoASMauricio
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Feature: Add FPUv2 instructions
Decoder: Renamed FPUv2 instruction mnemonics There are instructions for FPU that have the same mnemonic and base functionality in ARCv2 and ARCv3 but differ in operand amount (i.e. FDMADD) This requires internal renaming of mnemonics as the semantic function mapping is shared between all versions. Structure: Separated base FPU from ARCv3 FPU FPU for ARCv2 shares some functionality with ARCv3, so it makes sense to create a shared fpu.c/h for that. TCG: Added semantic function support for ARCv2 FPU instructions Signed-off-by: Bruno Mauricio <[email protected]>
1 parent e03e6a4 commit 76e0fa9

18 files changed

+1331
-287
lines changed

‎target/arc/cpu.c

Lines changed: 1 addition & 1 deletion
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@@ -123,7 +123,7 @@ static void arc_cpu_reset(DeviceState *dev)
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/* FPU init */
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/* TODO: Make init_fpu parameters based on options. */
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init_fpu(env, true, true, true);
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init_fpu(cpu, true, true, true);
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arc_resetTIMER(cpu);
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arc_resetIRQ(cpu);

‎target/arc/cpu.h

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@@ -381,6 +381,7 @@ struct ArchCPU {
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uint32_t norm_build; /* Normalize instruction configuration register. */
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uint32_t barrel_build; /* Barrel shifter configuration register. */
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uint32_t isa_config; /* Instruction Set Configuration Register. */
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uint32_t fpu_build_config; /* FPU build register */
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uint8_t core_id; /* Core id holder. */
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‎target/arc/decoder_fragments/arc-tbl.h

Lines changed: 80 additions & 80 deletions
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‎target/arc/fpu-helper-v2.c

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@@ -0,0 +1,270 @@
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/*
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* QEMU ARC CPU
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*
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* Copyright (c) 2023 Synopsys Inc.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* http://www.gnu.org/licenses/lgpl-2.1.html
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "fpu/softfloat.h"
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#include "fpu.h"
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#include "qemu/log.h"
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enum arc_fcvt32 {
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ARC_FCVT32_FS2INT = 0b000011,
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ARC_FCVT32_FS2INT_RZ = 0b001011,
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ARC_FCVT32_FINT2S = 0b000010,
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ARC_FCVT32_FS2UINT = 0b000001,
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ARC_FCVT32_FS2UINT_RZ = 0b001001,
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ARC_FCVT32_FUINT2S = 0b000000,
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ARC_FCVT32_FH2S = 0b010101,
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ARC_FCVT32_FS2H = 0b010100
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};
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enum arc_fcvt32_64 {
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ARC_FCVT32_64_FS2L = 0b000011,
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ARC_FCVT32_64_FS2L_RZ = 0b001011,
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ARC_FCVT32_64_FS2UL = 0b000001,
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ARC_FCVT32_64_FS2UL_RZ = 0b001001,
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ARC_FCVT32_64_FINT2D = 0b000010,
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ARC_FCVT32_64_FUINT2D = 0b000000,
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ARC_FCVT32_64_FS2D = 0b000100
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};
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enum arc_fcvt64 {
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ARC_FCVT64_FD2L = 0b000011,
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ARC_FCVT64_FD2L_RZ = 0b001011,
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ARC_FCVT64_FL2D = 0b000010,
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ARC_FCVT64_FD2UL = 0b000001,
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ARC_FCVT64_FD2UL_RZ = 0b001001,
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ARC_FCVT64_FUL2D = 0b000000
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};
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enum arc_fcvt64_32 {
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ARC_FCVT64_32_FD2INT = 0b000011,
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ARC_FCVT64_32_FD2INT_RZ = 0b001011,
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ARC_FCVT64_32_FD2UINT = 0b000001,
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ARC_FCVT64_32_FD2UINT_RZ = 0b001001,
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ARC_FCVT64_32_FL2S = 0b000010,
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ARC_FCVT64_32_FUL2S = 0b000000,
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ARC_FCVT64_32_FD2S = 0b000100
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};
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/* Soft fpu helper of type floatSIZE_operation */
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#define FLOAT_INST3_HELPERS(NAME, HELPER, SIZE) \
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uint32_t helper_##NAME(CPUARCState *env, uint32_t frs1, uint32_t frs2) \
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{ \
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uint32_t ret = float##SIZE##_##HELPER(frs1, frs2, &env->fp_status); \
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check_fpu_raise_exception(env); \
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return ret; \
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}
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FLOAT_INST3_HELPERS(fsadd32, add, 32)
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FLOAT_INST3_HELPERS(fssub32, sub, 32)
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FLOAT_INST3_HELPERS(fsmul32, mul, 32)
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FLOAT_INST3_HELPERS(fsdiv32, div, 32)
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FLOAT_INST3_HELPERS(fsmin32, minnum, 32)
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FLOAT_INST3_HELPERS(fsmax32, maxnum, 32)
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/* Helper for the 32 bit Single precision floating point square root */
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uint32_t helper_fssqrt32(CPUARCState *env, uint32_t src) {
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uint32_t ret = float32_sqrt(src, &env->fp_status);
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check_fpu_raise_exception(env);
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return ret;
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}
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/* Helper for the 32 bit - 32 bit conversions */
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uint32_t helper_fcvt32(CPUARCState *env, uint32_t src, uint32_t operation) {
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uint32_t ret = 0;
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switch (operation) {
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case ARC_FCVT32_FS2INT:
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ret = float32_to_int32(src, &env->fp_status);
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break;
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case ARC_FCVT32_FS2INT_RZ:
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ret = float32_to_int32_round_to_zero(src, &env->fp_status);
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break;
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case ARC_FCVT32_FINT2S:
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ret = int32_to_float32(src, &env->fp_status);
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break;
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case ARC_FCVT32_FS2UINT:
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ret = float32_to_uint32(src, &env->fp_status);
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break;
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case ARC_FCVT32_FS2UINT_RZ:
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ret = float32_to_uint32_round_to_zero(src, &env->fp_status);
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break;
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case ARC_FCVT32_FUINT2S:
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ret = uint32_to_float32(src, &env->fp_status);
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break;
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case ARC_FCVT32_FH2S:
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error_report("Half-precision (FH2S) not implemented for arcv2!");
124+
exit(EXIT_FAILURE);
125+
break;
126+
127+
case ARC_FCVT32_FS2H:
128+
error_report("Half-precision (FS2H) not implemented for arcv2!");
129+
exit(EXIT_FAILURE);
130+
break;
131+
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default:
133+
error_report("FCVT32 operation not supported!");
134+
exit(EXIT_FAILURE);
135+
}
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137+
check_fpu_raise_exception(env);
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139+
return ret;
140+
}
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/* Helper for the 32 bit - 64 bit conversions */
143+
uint64_t helper_fcvt32_64(CPUARCState *env, uint32_t src, uint32_t operation) {
144+
uint64_t ret = 0;
145+
146+
switch (operation) {
147+
148+
case ARC_FCVT32_64_FS2L:
149+
ret = float32_to_int64(src, &env->fp_status);
150+
break;
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case ARC_FCVT32_64_FS2L_RZ:
153+
ret = float32_to_int64_round_to_zero(src, &env->fp_status);
154+
break;
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case ARC_FCVT32_64_FS2UL:
157+
ret = float32_to_uint64(src, &env->fp_status);
158+
break;
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160+
case ARC_FCVT32_64_FS2UL_RZ:
161+
ret = float32_to_uint64_round_to_zero(src, &env->fp_status);
162+
break;
163+
164+
case ARC_FCVT32_64_FINT2D:
165+
ret = int32_to_float64(src, &env->fp_status);
166+
break;
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168+
case ARC_FCVT32_64_FUINT2D:
169+
ret = uint32_to_float64(src, &env->fp_status);
170+
break;
171+
172+
case ARC_FCVT32_64_FS2D:
173+
ret = float32_to_float64(src, &env->fp_status);
174+
break;
175+
176+
default:
177+
178+
error_report("FCVT32_64 operation not supported!");
179+
exit(EXIT_FAILURE);
180+
}
181+
182+
check_fpu_raise_exception(env);
183+
184+
return ret;
185+
}
186+
187+
/* Helper for the 64 bit - 64 bit conversions */
188+
uint64_t helper_fcvt64(CPUARCState *env, uint64_t src, uint32_t operation) {
189+
uint64_t ret = 0;
190+
191+
switch (operation) {
192+
193+
case ARC_FCVT64_FD2L:
194+
ret = float64_to_int64(src, &env->fp_status);
195+
break;
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197+
case ARC_FCVT64_FD2L_RZ:
198+
ret = float64_to_int64_round_to_zero(src, &env->fp_status);
199+
break;
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case ARC_FCVT64_FL2D:
202+
ret = int64_to_float64(src, &env->fp_status);
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break;
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case ARC_FCVT64_FD2UL:
206+
ret = float64_to_uint64(src, &env->fp_status);
207+
break;
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209+
case ARC_FCVT64_FD2UL_RZ:
210+
ret = float64_to_uint64_round_to_zero(src, &env->fp_status);
211+
break;
212+
213+
case ARC_FCVT64_FUL2D:
214+
ret = uint64_to_float64(src, &env->fp_status);
215+
break;
216+
217+
default:
218+
error_report("FCVT64 operation not supported!");
219+
exit(EXIT_FAILURE);
220+
}
221+
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check_fpu_raise_exception(env);
223+
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return ret;
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}
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/* Helper for the 64 bit - 32 bit conversions */
228+
uint32_t helper_fcvt64_32(CPUARCState *env, uint64_t src, uint32_t operation) {
229+
uint32_t ret = 0;
230+
231+
switch (operation) {
232+
233+
case ARC_FCVT64_32_FD2INT:
234+
ret = float64_to_int32(src, &env->fp_status);
235+
break;
236+
237+
case ARC_FCVT64_32_FD2INT_RZ:
238+
ret = float64_to_int32_round_to_zero(src, &env->fp_status);
239+
break;
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case ARC_FCVT64_32_FD2UINT:
242+
ret = float64_to_uint32(src, &env->fp_status);
243+
break;
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case ARC_FCVT64_32_FD2UINT_RZ:
246+
ret = float64_to_uint32_round_to_zero(src, &env->fp_status);
247+
break;
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case ARC_FCVT64_32_FL2S:
250+
ret = int64_to_float32(src, &env->fp_status);
251+
break;
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case ARC_FCVT64_32_FUL2S:
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ret = uint64_to_float32(src, &env->fp_status);
255+
break;
256+
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case ARC_FCVT64_32_FD2S:
258+
ret = float64_to_float32(src, &env->fp_status);
259+
break;
260+
261+
default:
262+
error_report("FCVT64_32 operation not supported!");
263+
exit(EXIT_FAILURE);
264+
}
265+
266+
check_fpu_raise_exception(env);
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return ret;
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}
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