cmd/internal/obj/mips: add SEB/SEH instructions

Add support for SEB/SEH instructions, which are introduced in mips32r2.

SEB/SEH can be used to sign-extend byte/halfword in registers directly without passing through memory.

Ref: The MIPS32 Instruction Set, Revision 5.04: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00086-2B-MIPS32BIS-AFP-05.04.pdf

Updates #60072

Change-Id: I33175ae9d943ead5983ac004bd2a158039046d65
Reviewed-on: https://go-review.googlesource.com/c/go/+/515475
TryBot-Result: Gopher Robot <[email protected]>
Reviewed-by: Michael Knyszek <[email protected]>
Reviewed-by: Cherry Mui <[email protected]>
Run-TryBot: Joel Sing <[email protected]>

Author: HeliC829

src/cmd/asm/internal/asm/testdata/mips.s

@@ -428,8 +428,12 @@ label4:
 	NEGW	R1, R2 // 00011023
 	CLZ	R1, R2 // 70221020
 	CLO	R1, R2 // 70221021
+
 	WSBH	R1, R2 // 7c0110a0
 
+	SEB	R1, R2 // 7c011420
+	SEH	R1, R2 // 7c011620
+
 	// to (Hi, Lo)
 	MADD	R2, R1 // 70220000
 	MSUB	R2, R1 // 70220004

src/cmd/asm/internal/asm/testdata/mips64.s

@@ -590,10 +590,14 @@ label4:
 	// unary operation
 	NEGW	R1, R2 // 00011023
 	NEGV	R1, R2 // 0001102f
+
 	WSBH	R1, R2 // 7c0110a0
 	DSBH	R1, R2 // 7c0110a4
 	DSHD	R1, R2 // 7c011164
 
+	SEB	R1, R2 // 7c011420
+	SEH	R1, R2 // 7c011620
+
 	RET
 
 // MSA VMOVI

src/cmd/internal/obj/mips/a.out.go

@@ -394,6 +394,8 @@ const (
 	AROTRV
 	ASC
 	ASCV
+	ASEB
+	ASEH
 	ASGT
 	ASGTU
 	ASLL

src/cmd/internal/obj/mips/anames.go

@@ -1084,7 +1084,6 @@ func buildop(ctxt *obj.Link) {
 			ANEGW,
 			ANEGV,
 			AWORD,
-			AWSBH,
 			obj.ANOP,
 			obj.ATEXT,
 			obj.AUNDEF,
@@ -1106,6 +1105,10 @@ func buildop(ctxt *obj.Link) {
 		case ATEQ:
 			opset(ATNE, r0)
 
+		case AWSBH:
+			opset(ASEB, r0)
+			opset(ASEH, r0)
+
 		case ADSBH:
 			opset(ADSHD, r0)
 		}
@@ -1899,6 +1902,10 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
 		return SP(3, 7) | OP(20, 4)
 	case ADSHD:
 		return SP(3, 7) | OP(44, 4)
+	case ASEB:
+		return SP(3, 7) | OP(132, 0)
+	case ASEH:
+		return SP(3, 7) | OP(196, 0)
 	}
 
 	if a < 0 {