internal/runtime/atomic: add Xchg8 for mips64x

For #69735

Change-Id: Ide6b3077768a96b76078e5d4f6460596b8ff1560
Reviewed-on: https://go-review.googlesource.com/c/go/+/631756
Reviewed-by: Keith Randall <[email protected]>
Reviewed-by: Michael Knyszek <[email protected]>
Reviewed-by: Keith Randall <[email protected]>
LUCI-TryBot-Result: Go LUCI <[email protected]>
Auto-Submit: Keith Randall <[email protected]>

Author: HeliC829

src/internal/runtime/atomic/atomic_mips64x.go

@@ -20,6 +20,9 @@ func Xadduintptr(ptr *uintptr, delta uintptr) uintptr
 //go:noescape
 func Xchg(ptr *uint32, new uint32) uint32
 
+//go:noescape
+func Xchg8(ptr *uint8, new uint8) uint8
+
 //go:noescape
 func Xchg64(ptr *uint64, new uint64) uint64
 

src/internal/runtime/atomic/atomic_mips64x.s

@@ -147,6 +147,39 @@ TEXT ·Xadd64(SB), NOSPLIT, $0-24
 	SYNC
 	RET
 
+// uint8 Xchg(ptr *uint8, new uint8)
+// Atomically:
+//	old := *ptr;
+//	*ptr = new;
+//	return old;
+TEXT ·Xchg8(SB), NOSPLIT, $0-17
+	MOVV	ptr+0(FP), R2
+	MOVBU	new+8(FP), R5
+#ifdef GOARCH_mips64
+	// Big endian.  ptr = ptr ^ 3
+	XOR	$3, R2
+#endif
+	// R4 = ((ptr & 3) * 8)
+	AND	$3, R2, R4
+	SLLV	$3, R4
+	// Shift val for aligned ptr. R7 = (0xFF << R4) ^ (-1)
+	MOVV	$0xFF, R7
+	SLLV	R4, R7
+	XOR	$-1, R7
+	AND	$~3, R2
+	SLLV	R4, R5
+
+	SYNC
+	LL	(R2), R9
+	AND	R7, R9, R8
+	OR	R5, R8
+	SC	R8, (R2)
+	BEQ	R8, -5(PC)
+	SYNC
+	SRLV	R4, R9
+	MOVBU	R9, ret+16(FP)
+	RET
+
 // uint32 Xchg(ptr *uint32, new uint32)
 // Atomically:
 //	old := *ptr;

src/internal/runtime/atomic/xchg8_test.go

@@ -2,7 +2,7 @@
 // Use of this source code is governed by a BSD-style
 // license that can be found in the LICENSE file.
 
-//go:build 386 || amd64 || arm || arm64 || loong64 || ppc64 || ppc64le || riscv64
+//go:build 386 || amd64 || arm || arm64 || loong64 || mips64 || mips64le || ppc64 || ppc64le || riscv64
 
 package atomic_test