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cmd/internal/obj/riscv: add support for vector fixed-point arithmetic instructions
Add support for vector fixed-point arithmetic instructions to the RISC-V assembler. This includes single width saturating addition and subtraction, averaging addition and subtraction and scaling shift instructions. Change-Id: I9aa27e9565ad016ba5bb2b479e1ba70db24e4ff5 Reviewed-on: https://go-review.googlesource.com/c/go/+/646776 Reviewed-by: Mark Ryan <[email protected]> Reviewed-by: Carlos Amedee <[email protected]> Reviewed-by: Dmitri Shuralyov <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]>
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Diff for: ‎src/cmd/asm/internal/asm/testdata/riscv64.s

+74
Original file line numberDiff line numberDiff line change
@@ -863,6 +863,80 @@ start:
863863
VMVVX X10, V3 // d741055e
864864
VMVVI $15, V3 // d7b1075e
865865

866+
// 31.12.1: Vector Single-Width Saturating Add and Subtract
867+
VSADDUVV V1, V2, V3 // d7812082
868+
VSADDUVV V1, V2, V0, V3 // d7812080
869+
VSADDUVX X10, V2, V3 // d7412582
870+
VSADDUVX X10, V2, V0, V3 // d7412580
871+
VSADDUVI $15, V2, V3 // d7b12782
872+
VSADDUVI $15, V2, V0, V3 // d7b12780
873+
VSADDVV V1, V2, V3 // d7812086
874+
VSADDVV V1, V2, V0, V3 // d7812084
875+
VSADDVX X10, V2, V3 // d7412586
876+
VSADDVX X10, V2, V0, V3 // d7412584
877+
VSADDVI $15, V2, V3 // d7b12786
878+
VSADDVI $15, V2, V0, V3 // d7b12784
879+
VSSUBUVV V1, V2, V3 // d781208a
880+
VSSUBUVV V1, V2, V0, V3 // d7812088
881+
VSSUBUVX X10, V2, V3 // d741258a
882+
VSSUBUVX X10, V2, V0, V3 // d7412588
883+
VSSUBVV V1, V2, V3 // d781208e
884+
VSSUBVV V1, V2, V0, V3 // d781208c
885+
VSSUBVX X10, V2, V3 // d741258e
886+
VSSUBVX X10, V2, V0, V3 // d741258c
887+
888+
// 31.12.2: Vector Single-Width Averaging Add and Subtract
889+
VAADDUVV V1, V2, V3 // d7a12022
890+
VAADDUVV V1, V2, V0, V3 // d7a12020
891+
VAADDUVX X10, V2, V3 // d7612522
892+
VAADDUVX X10, V2, V0, V3 // d7612520
893+
VAADDVV V1, V2, V3 // d7a12026
894+
VAADDVV V1, V2, V0, V3 // d7a12024
895+
VAADDVX X10, V2, V3 // d7612526
896+
VAADDVX X10, V2, V0, V3 // d7612524
897+
VASUBUVV V1, V2, V3 // d7a1202a
898+
VASUBUVV V1, V2, V0, V3 // d7a12028
899+
VASUBUVX X10, V2, V3 // d761252a
900+
VASUBUVX X10, V2, V0, V3 // d7612528
901+
VASUBVV V1, V2, V3 // d7a1202e
902+
VASUBVV V1, V2, V0, V3 // d7a1202c
903+
VASUBVX X10, V2, V3 // d761252e
904+
VASUBVX X10, V2, V0, V3 // d761252c
905+
906+
// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
907+
VSMULVV V1, V2, V3 // d781209e
908+
VSMULVV V1, V2, V0, V3 // d781209c
909+
VSMULVX X10, V2, V3 // d741259e
910+
VSMULVX X10, V2, V0, V3 // d741259c
911+
912+
// 31.12.4: Vector Single-Width Scaling Shift Instructions
913+
VSSRLVV V1, V2, V3 // d78120aa
914+
VSSRLVV V1, V2, V0, V3 // d78120a8
915+
VSSRLVX X10, V2, V3 // d74125aa
916+
VSSRLVX X10, V2, V0, V3 // d74125a8
917+
VSSRLVI $15, V2, V3 // d7b127aa
918+
VSSRLVI $15, V2, V0, V3 // d7b127a8
919+
VSSRAVV V1, V2, V3 // d78120ae
920+
VSSRAVV V1, V2, V0, V3 // d78120ac
921+
VSSRAVX X10, V2, V3 // d74125ae
922+
VSSRAVX X10, V2, V0, V3 // d74125ac
923+
VSSRAVI $16, V2, V3 // d73128ae
924+
VSSRAVI $16, V2, V0, V3 // d73128ac
925+
926+
// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
927+
VNCLIPUWV V1, V2, V3 // d78120ba
928+
VNCLIPUWV V1, V2, V0, V3 // d78120b8
929+
VNCLIPUWX X10, V2, V3 // d74125ba
930+
VNCLIPUWX X10, V2, V0, V3 // d74125b8
931+
VNCLIPUWI $16, V2, V3 // d73128ba
932+
VNCLIPUWI $16, V2, V0, V3 // d73128b8
933+
VNCLIPWV V1, V2, V3 // d78120be
934+
VNCLIPWV V1, V2, V0, V3 // d78120bc
935+
VNCLIPWX X10, V2, V3 // d74125be
936+
VNCLIPWX X10, V2, V0, V3 // d74125bc
937+
VNCLIPWI $16, V2, V3 // d73128be
938+
VNCLIPWI $16, V2, V0, V3 // d73128bc
939+
866940
//
867941
// Privileged ISA
868942
//

Diff for: ‎src/cmd/asm/internal/asm/testdata/riscv64error.s

+32
Original file line numberDiff line numberDiff line change
@@ -221,5 +221,37 @@ TEXT errors(SB),$0
221221
VMVVV V1, V2, V3 // ERROR "too many operands for instruction"
222222
VMVVX X10, V2, V3 // ERROR "too many operands for instruction"
223223
VMVVI $15, V2, V3 // ERROR "too many operands for instruction"
224+
VSADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
225+
VSADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
226+
VSADDUVI $15, V2, V4, V3 // ERROR "invalid vector mask register"
227+
VSADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
228+
VSADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
229+
VSADDVI $15, V2, V4, V3 // ERROR "invalid vector mask register"
230+
VSSUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
231+
VSSUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
232+
VSSUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
233+
VSSUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
234+
VAADDUVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
235+
VAADDUVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
236+
VAADDVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
237+
VAADDVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
238+
VASUBUVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
239+
VASUBUVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
240+
VASUBVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
241+
VASUBVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
242+
VSMULVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
243+
VSMULVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
244+
VSSRLVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
245+
VSSRLVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
246+
VSSRLVI $15, V2, V4, V3 // ERROR "invalid vector mask register"
247+
VSSRAVV V1, V2, V4, V3 // ERROR "invalid vector mask register"
248+
VSSRAVX X10, V2, V4, V3 // ERROR "invalid vector mask register"
249+
VSSRAVI $15, V2, V4, V3 // ERROR "invalid vector mask register"
250+
VNCLIPUWV V1, V2, V4, V3 // ERROR "invalid vector mask register"
251+
VNCLIPUWX X10, V2, V4, V3 // ERROR "invalid vector mask register"
252+
VNCLIPUWI $16, V2, V4, V3 // ERROR "invalid vector mask register"
253+
VNCLIPWV V1, V2, V4, V3 // ERROR "invalid vector mask register"
254+
VNCLIPWX X10, V2, V4, V3 // ERROR "invalid vector mask register"
255+
VNCLIPWI $16, V2, V4, V3 // ERROR "invalid vector mask register"
224256

225257
RET

Diff for: ‎src/cmd/asm/internal/asm/testdata/riscv64validation.s

+32
Original file line numberDiff line numberDiff line change
@@ -237,5 +237,37 @@ TEXT validation(SB),$0
237237
VMVVX V1, V2 // ERROR "expected integer register in rs1 position"
238238
VMVVI $16, V2 // ERROR "signed immediate 16 must be in range [-16, 15]"
239239
VMVVI $-17, V2 // ERROR "signed immediate -17 must be in range [-16, 15]"
240+
VSADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
241+
VSADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
242+
VSADDUVI $16, V2, V3 // ERROR "signed immediate 16 must be in range [-16, 15]"
243+
VSADDUVI $-17, V2, V3 // ERROR "signed immediate -17 must be in range [-16, 15]"
244+
VSSUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
245+
VSSUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
246+
VAADDUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
247+
VAADDUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
248+
VAADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
249+
VAADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
250+
VASUBUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
251+
VASUBUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
252+
VASUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
253+
VASUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
254+
VSMULVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
255+
VSMULVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
256+
VSSRLVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
257+
VSSRLVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
258+
VSSRLVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]"
259+
VSSRLVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]"
260+
VSSRAVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
261+
VSSRAVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
262+
VSSRAVI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]"
263+
VSSRAVI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]"
264+
VNCLIPUWV X10, V2, V3 // ERROR "expected vector register in vs1 position"
265+
VNCLIPUWX V1, V2, V3 // ERROR "expected integer register in rs1 position"
266+
VNCLIPUWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]"
267+
VNCLIPUWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]"
268+
VNCLIPWV X10, V2, V3 // ERROR "expected vector register in vs1 position"
269+
VNCLIPWX V1, V2, V3 // ERROR "expected integer register in rs1 position"
270+
VNCLIPWI $32, V2, V3 // ERROR "signed immediate 32 must be in range [0, 31]"
271+
VNCLIPWI $-1, V2, V3 // ERROR "signed immediate -1 must be in range [0, 31]"
240272

241273
RET

Diff for: ‎src/cmd/internal/obj/riscv/obj.go

+48-3
Original file line numberDiff line numberDiff line change
@@ -2412,6 +2412,48 @@ var instructions = [ALAST & obj.AMask]instructionData{
24122412
AVMVVX & obj.AMask: {enc: rVIVEncoding},
24132413
AVMVVI & obj.AMask: {enc: rVViEncoding},
24142414

2415+
// 31.12.1: Vector Single-Width Saturating Add and Subtract
2416+
AVSADDUVV & obj.AMask: {enc: rVVVEncoding},
2417+
AVSADDUVX & obj.AMask: {enc: rVIVEncoding},
2418+
AVSADDUVI & obj.AMask: {enc: rVViEncoding},
2419+
AVSADDVV & obj.AMask: {enc: rVVVEncoding},
2420+
AVSADDVX & obj.AMask: {enc: rVIVEncoding},
2421+
AVSADDVI & obj.AMask: {enc: rVViEncoding},
2422+
AVSSUBUVV & obj.AMask: {enc: rVVVEncoding},
2423+
AVSSUBUVX & obj.AMask: {enc: rVIVEncoding},
2424+
AVSSUBVV & obj.AMask: {enc: rVVVEncoding},
2425+
AVSSUBVX & obj.AMask: {enc: rVIVEncoding},
2426+
2427+
// 31.12.2: Vector Single-Width Averaging Add and Subtract
2428+
AVAADDUVV & obj.AMask: {enc: rVVVEncoding},
2429+
AVAADDUVX & obj.AMask: {enc: rVIVEncoding},
2430+
AVAADDVV & obj.AMask: {enc: rVVVEncoding},
2431+
AVAADDVX & obj.AMask: {enc: rVIVEncoding},
2432+
AVASUBUVV & obj.AMask: {enc: rVVVEncoding},
2433+
AVASUBUVX & obj.AMask: {enc: rVIVEncoding},
2434+
AVASUBVV & obj.AMask: {enc: rVVVEncoding},
2435+
AVASUBVX & obj.AMask: {enc: rVIVEncoding},
2436+
2437+
// 31.12.3: Vector Single-Width Fractional Multiply with Rounding and Saturation
2438+
AVSMULVV & obj.AMask: {enc: rVVVEncoding},
2439+
AVSMULVX & obj.AMask: {enc: rVIVEncoding},
2440+
2441+
// 31.12.4: Vector Single-Width Scaling Shift Instructions
2442+
AVSSRLVV & obj.AMask: {enc: rVVVEncoding},
2443+
AVSSRLVX & obj.AMask: {enc: rVIVEncoding},
2444+
AVSSRLVI & obj.AMask: {enc: rVVuEncoding},
2445+
AVSSRAVV & obj.AMask: {enc: rVVVEncoding},
2446+
AVSSRAVX & obj.AMask: {enc: rVIVEncoding},
2447+
AVSSRAVI & obj.AMask: {enc: rVVuEncoding},
2448+
2449+
// 31.12.5: Vector Narrowing Fixed-Point Clip Instructions
2450+
AVNCLIPUWV & obj.AMask: {enc: rVVVEncoding},
2451+
AVNCLIPUWX & obj.AMask: {enc: rVIVEncoding},
2452+
AVNCLIPUWI & obj.AMask: {enc: rVVuEncoding},
2453+
AVNCLIPWV & obj.AMask: {enc: rVVVEncoding},
2454+
AVNCLIPWX & obj.AMask: {enc: rVIVEncoding},
2455+
AVNCLIPWI & obj.AMask: {enc: rVVuEncoding},
2456+
24152457
//
24162458
// Privileged ISA
24172459
//
@@ -3393,10 +3435,13 @@ func instructionsForProg(p *obj.Prog) []*instruction {
33933435
AVMINUVV, AVMINUVX, AVMINVV, AVMINVX, AVMAXUVV, AVMAXUVX, AVMAXVV, AVMAXVX,
33943436
AVMULVV, AVMULVX, AVMULHVV, AVMULHVX, AVMULHUVV, AVMULHUVX, AVMULHSUVV, AVMULHSUVX,
33953437
AVDIVUVV, AVDIVUVX, AVDIVVV, AVDIVVX, AVREMUVV, AVREMUVX, AVREMVV, AVREMVX,
3396-
AVWMULVV, AVWMULVX, AVWMULUVV, AVWMULUVX, AVWMULSUVV, AVWMULSUVX,
3397-
AVNSRLWV, AVNSRLWX, AVNSRAWV, AVNSRAWX,
3438+
AVWMULVV, AVWMULVX, AVWMULUVV, AVWMULUVX, AVWMULSUVV, AVWMULSUVX, AVNSRLWV, AVNSRLWX, AVNSRAWV, AVNSRAWX,
33983439
AVMACCVV, AVMACCVX, AVNMSACVV, AVNMSACVX, AVMADDVV, AVMADDVX, AVNMSUBVV, AVNMSUBVX,
3399-
AVWMACCUVV, AVWMACCUVX, AVWMACCVV, AVWMACCVX, AVWMACCSUVV, AVWMACCSUVX, AVWMACCUSVX:
3440+
AVWMACCUVV, AVWMACCUVX, AVWMACCVV, AVWMACCVX, AVWMACCSUVV, AVWMACCSUVX, AVWMACCUSVX,
3441+
AVSADDUVV, AVSADDUVX, AVSADDUVI, AVSADDVV, AVSADDVX, AVSADDVI, AVSSUBUVV, AVSSUBUVX, AVSSUBVV, AVSSUBVX,
3442+
AVAADDUVV, AVAADDUVX, AVAADDVV, AVAADDVX, AVASUBUVV, AVASUBUVX, AVASUBVV, AVASUBVX,
3443+
AVSMULVV, AVSMULVX, AVSSRLVV, AVSSRLVX, AVSSRLVI, AVSSRAVV, AVSSRAVX, AVSSRAVI,
3444+
AVNCLIPUWV, AVNCLIPUWX, AVNCLIPUWI, AVNCLIPWV, AVNCLIPWX, AVNCLIPWI:
34003445
// Set mask bit
34013446
switch {
34023447
case ins.rs3 == obj.REG_NONE:

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