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cmd/internal/obj/mips: add WSBH/DSBH/DSHD instructions
Add support for WSBH/DSBH/DSHD instructions, which are introduced in mips{32,64}r2. WSBH reverse bytes within halfwords for 32-bit word, DSBH reverse bytes within halfwords for 64-bit doubleword, and DSHD reverse halfwords within doublewords. These instructions can be used to optimize byte swaps. Ref: The MIPS64 Instruction Set, Revision 5.04: https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00087-2B-MIPS64BIS-AFP-05.04.pdf Updates #60072 Change-Id: I31c043150fe8ac03027f413ef4cb2f3e435775e1 Reviewed-on: https://go-review.googlesource.com/c/go/+/493816 TryBot-Result: Gopher Robot <[email protected]> Reviewed-by: Keith Randall <[email protected]> Reviewed-by: David Chase <[email protected]> Reviewed-by: Joel Sing <[email protected]> Reviewed-by: Cherry Mui <[email protected]> Run-TryBot: Joel Sing <[email protected]>
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src/cmd/asm/internal/asm/testdata/mips.s

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@@ -428,6 +428,7 @@ label4:
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NEGW R1, R2 // 00011023
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CLZ R1, R2 // 70221020
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CLO R1, R2 // 70221021
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WSBH R1, R2 // 7c0110a0
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// to (Hi, Lo)
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MADD R2, R1 // 70220000

src/cmd/asm/internal/asm/testdata/mips64.s

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@@ -587,8 +587,13 @@ label4:
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CALL foo(SB)
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RET foo(SB)
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// unary operation
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NEGW R1, R2 // 00011023
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NEGV R1, R2 // 0001102f
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WSBH R1, R2 // 7c0110a0
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DSBH R1, R2 // 7c0110a4
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DSHD R1, R2 // 7c011164
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RET
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// MSA VMOVI

src/cmd/internal/obj/mips/a.out.go

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@@ -415,6 +415,7 @@ const (
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ATLBWR
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ATNE
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AWORD
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AWSBH
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AXOR
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/* 64-bit */
@@ -434,6 +435,8 @@ const (
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AADDVU
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ASUBV
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ASUBVU
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ADSBH
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ADSHD
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/* 64-bit FP */
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ATRUNCFV

src/cmd/internal/obj/mips/anames.go

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src/cmd/internal/obj/mips/asm0.go

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@@ -382,6 +382,9 @@ var optab = []Optab{
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{AVMOVB, C_SOREG, C_NONE, C_WREG, 57, 4, 0, sys.MIPS64, 0},
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{AVMOVB, C_WREG, C_NONE, C_SOREG, 58, 4, 0, sys.MIPS64, 0},
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{AWSBH, C_REG, C_NONE, C_REG, 59, 4, 0, 0, 0},
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{ADSBH, C_REG, C_NONE, C_REG, 59, 4, 0, sys.MIPS64, 0},
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{ABREAK, C_REG, C_NONE, C_SEXT, 7, 4, REGSB, sys.MIPS64, 0}, /* really CACHE instruction */
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{ABREAK, C_REG, C_NONE, C_SAUTO, 7, 4, REGSP, sys.MIPS64, 0},
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{ABREAK, C_REG, C_NONE, C_SOREG, 7, 4, REGZERO, sys.MIPS64, 0},
@@ -1081,6 +1084,7 @@ func buildop(ctxt *obj.Link) {
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ANEGW,
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ANEGV,
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AWORD,
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AWSBH,
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obj.ANOP,
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obj.ATEXT,
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obj.AUNDEF,
@@ -1101,6 +1105,9 @@ func buildop(ctxt *obj.Link) {
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case ATEQ:
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opset(ATNE, r0)
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case ADSBH:
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opset(ADSHD, r0)
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}
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}
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}
@@ -1683,6 +1690,9 @@ func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
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case 58: /* vst wr, $soreg */
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v := c.lsoffset(p.As, c.regoff(&p.To))
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o1 = OP_VMI10(v, uint32(p.To.Reg), uint32(p.From.Reg), 9, c.twobitdf(p.As))
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case 59:
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o1 = OP_RRR(c.oprrr(p.As), p.From.Reg, REGZERO, p.To.Reg)
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}
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out[0] = o1
@@ -1883,6 +1893,12 @@ func (c *ctxt0) oprrr(a obj.As) uint32 {
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return SP(3, 4) | OP(0, 0)
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case AMSUB:
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return SP(3, 4) | OP(0, 4)
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case AWSBH:
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return SP(3, 7) | OP(20, 0)
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case ADSBH:
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return SP(3, 7) | OP(20, 4)
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case ADSHD:
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return SP(3, 7) | OP(44, 4)
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}
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if a < 0 {

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