@@ -6,21 +6,6 @@ package cpu
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const CacheLinePadSize = 64
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- // HWCap may be initialized by archauxv and
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- // should not be changed after it was initialized.
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- var HWCap uint
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-
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- // HWCAP bits. These are exposed by Linux.
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- const (
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- hwcap_AES = 1 << 3
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- hwcap_PMULL = 1 << 4
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- hwcap_SHA1 = 1 << 5
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- hwcap_SHA2 = 1 << 6
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- hwcap_CRC32 = 1 << 7
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- hwcap_ATOMICS = 1 << 8
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- hwcap_CPUID = 1 << 11
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- )
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-
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func doinit () {
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options = []option {
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{Name : "aes" , Feature : & ARM64 .HasAES },
@@ -34,86 +19,8 @@ func doinit() {
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{Name : "isZeus" , Feature : & ARM64 .IsZeus },
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}
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- switch GOOS {
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- case "linux" , "android" :
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- // HWCap was populated by the runtime from the auxiliary vector.
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- // Use HWCap information since reading aarch64 system registers
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- // is not supported in user space on older linux kernels.
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- ARM64 .HasAES = isSet (HWCap , hwcap_AES )
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- ARM64 .HasPMULL = isSet (HWCap , hwcap_PMULL )
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- ARM64 .HasSHA1 = isSet (HWCap , hwcap_SHA1 )
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- ARM64 .HasSHA2 = isSet (HWCap , hwcap_SHA2 )
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- ARM64 .HasCRC32 = isSet (HWCap , hwcap_CRC32 )
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- ARM64 .HasCPUID = isSet (HWCap , hwcap_CPUID )
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-
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- // The Samsung S9+ kernel reports support for atomics, but not all cores
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- // actually support them, resulting in SIGILL. See issue #28431.
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- // TODO(elias.naur): Only disable the optimization on bad chipsets on android.
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- ARM64 .HasATOMICS = isSet (HWCap , hwcap_ATOMICS ) && GOOS != "android"
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-
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- // Check to see if executing on a NeoverseN1 and in order to do that,
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- // check the AUXV for the CPUID bit. The getMIDR function executes an
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- // instruction which would normally be an illegal instruction, but it's
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- // trapped by the kernel, the value sanitized and then returned. Without
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- // the CPUID bit the kernel will not trap the instruction and the process
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- // will be terminated with SIGILL.
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- if ARM64 .HasCPUID {
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- midr := getMIDR ()
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- part_num := uint16 ((midr >> 4 ) & 0xfff )
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- implementor := byte ((midr >> 24 ) & 0xff )
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-
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- if implementor == 'A' && part_num == 0xd0c {
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- ARM64 .IsNeoverseN1 = true
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- }
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- if implementor == 'A' && part_num == 0xd40 {
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- ARM64 .IsZeus = true
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- }
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- }
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-
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- case "freebsd" :
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- // Retrieve info from system register ID_AA64ISAR0_EL1.
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- isar0 := getisar0 ()
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-
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- // ID_AA64ISAR0_EL1
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- switch extractBits (isar0 , 4 , 7 ) {
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- case 1 :
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- ARM64 .HasAES = true
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- case 2 :
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- ARM64 .HasAES = true
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- ARM64 .HasPMULL = true
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- }
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-
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- switch extractBits (isar0 , 8 , 11 ) {
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- case 1 :
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- ARM64 .HasSHA1 = true
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- }
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-
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- switch extractBits (isar0 , 12 , 15 ) {
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- case 1 , 2 :
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- ARM64 .HasSHA2 = true
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- }
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-
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- switch extractBits (isar0 , 16 , 19 ) {
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- case 1 :
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- ARM64 .HasCRC32 = true
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- }
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-
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- switch extractBits (isar0 , 20 , 23 ) {
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- case 2 :
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- ARM64 .HasATOMICS = true
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- }
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- default :
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- // Other operating systems do not support reading HWCap from auxiliary vector
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- // or reading privileged aarch64 system registers in user space.
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- }
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- }
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-
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- func extractBits (data uint64 , start , end uint ) uint {
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- return (uint )(data >> start ) & ((1 << (end - start + 1 )) - 1 )
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- }
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-
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- func isSet (hwc uint , value uint ) bool {
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- return hwc & value != 0
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+ // arm64 uses different ways to detect CPU features at runtime depending on the operating system.
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+ osInit ()
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}
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func getisar0 () uint64
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