Skip to content

Commit d45f24c

Browse files
committed
cmd/compile: use bounded shift information on ppc64x
Makes use of bounded shift information to generate more efficient shift instructions. Updates #25167 for ppc64x Change-Id: I7fc8d49a3fb3e0f273cc51bc767470b239cbdca7 Reviewed-on: https://go-review.googlesource.com/135380 Run-TryBot: Lynn Boger <[email protected]> TryBot-Result: Gobot Gobot <[email protected]> Reviewed-by: Michael Munday <[email protected]>
1 parent c381ba8 commit d45f24c

File tree

2 files changed

+803
-9
lines changed

2 files changed

+803
-9
lines changed

src/cmd/compile/internal/ssa/gen/PPC64.rules

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,20 @@
168168
(Rsh8x32 x (MOVDconst [c])) && uint32(c) < 8 -> (SRAWconst (SignExt8to32 x) [c])
169169
(Rsh8Ux32 x (MOVDconst [c])) && uint32(c) < 8 -> (SRWconst (ZeroExt8to32 x) [c])
170170

171+
// Lower bounded shifts first. No need to check shift value.
172+
(Lsh64x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLD x y)
173+
(Lsh32x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
174+
(Lsh16x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
175+
(Lsh8x(64|32|16|8) x y) && shiftIsBounded(v) -> (SLW x y)
176+
(Rsh64Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRD x y)
177+
(Rsh32Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW x y)
178+
(Rsh16Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW (MOVHZreg x) y)
179+
(Rsh8Ux(64|32|16|8) x y) && shiftIsBounded(v) -> (SRW (MOVBZreg x) y)
180+
(Rsh64x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAD x y)
181+
(Rsh32x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW x y)
182+
(Rsh16x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW (MOVHreg x) y)
183+
(Rsh8x(64|32|16|8) x y) && shiftIsBounded(v) -> (SRAW (MOVBreg x) y)
184+
171185
// non-constant rotates
172186
// These are subexpressions found in statements that can become rotates
173187
// In these cases the shift count is known to be < 64 so the more complicated expressions

0 commit comments

Comments
 (0)