Merge pull request #1003 from raphnet/verilog_tweaks

Verilog improvements

Author: isagalaev

src/languages/verilog.js

@@ -7,7 +7,7 @@ Description: Verilog is a hardware description language used in electronic desig
 function(hljs) {
   return {
     aliases: ['v'],
-    case_insensitive: true,
+    case_insensitive: false,
     keywords: {
       keyword:
         'always and assign begin buf bufif0 bufif1 case casex casez cmos deassign ' +
@@ -29,7 +29,7 @@ function(hljs) {
       hljs.QUOTE_STRING_MODE,
       {
         className: 'number',
-        begin: '\\b(\\d+\'(b|h|o|d|B|H|O|D))?[0-9xzXZ]+',
+        begin: '(\\b((\\d\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F\_]+))|(\\B((\'(b|h|o|d|B|H|O|D))[0-9xzXZa-fA-F\_]+))|(\\b([0-9xzXZ\_])+)',
         contains: [hljs.BACKSLASH_ESCAPE],
         relevance: 0
       },

test/markup/verilog/misc.expect.txt

@@ -0,0 +1,37 @@
+`<span class="hljs-keyword">timescale</span> <span class="hljs-number">1</span>ns / <span class="hljs-number">1</span>ps
+
+<span class="hljs-comment">/**
+ * counter: a generic clearable up-counter
+ */</span>
+
+<span class="hljs-keyword">module</span> counter
+    #(<span class="hljs-keyword">parameter</span> WIDTH=<span class="hljs-number">64</span>)
+    (
+        <span class="hljs-keyword">input</span> clk,
+        <span class="hljs-keyword">input</span> ce,
+        <span class="hljs-keyword">input</span> arst_n,
+        <span class="hljs-keyword">output</span> <span class="hljs-keyword">reg</span> [WIDTH-<span class="hljs-number">1</span>:<span class="hljs-number">0</span>] q
+    );
+
+    <span class="hljs-comment">// some child</span>
+    clock_buffer <span class="hljs-variable">#(WIDTH)</span> buffer_inst (
+      .clk(clk),
+      .ce(ce),
+      .reset(arst_n)
+    );
+
+    <span class="hljs-comment">// Simple gated up-counter with async clear</span>
+
+    <span class="hljs-keyword">always</span> @(<span class="hljs-keyword">posedge</span> clk <span class="hljs-keyword">or</span> <span class="hljs-keyword">negedge</span> arst_n) <span class="hljs-keyword">begin</span>
+        <span class="hljs-keyword">if</span> (arst_n == <span class="hljs-number">1'b0</span>) <span class="hljs-keyword">begin</span>
+            q &lt;= {WIDTH {<span class="hljs-number">1'b0</span>}};
+            <span class="hljs-keyword">end</span>
+        <span class="hljs-keyword">else</span> <span class="hljs-keyword">begin</span>
+            q &lt;= q;
+            <span class="hljs-keyword">if</span> (ce == <span class="hljs-number">1'b1</span>) <span class="hljs-keyword">begin</span>
+                q &lt;= q + <span class="hljs-number">1</span>;
+            <span class="hljs-keyword">end</span>
+        <span class="hljs-keyword">end</span>
+    <span class="hljs-keyword">end</span>
+
+<span class="hljs-keyword">endmodule</span>

test/markup/verilog/misc.txt

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+
+/**
+ * counter: a generic clearable up-counter
+ */
+
+module counter
+    #(parameter WIDTH=64)
+    (
+        input clk,
+        input ce,
+        input arst_n,
+        output reg [WIDTH-1:0] q
+    );
+
+    // some child
+    clock_buffer #(WIDTH) buffer_inst (
+      .clk(clk),
+      .ce(ce),
+      .reset(arst_n)
+    );
+
+    // Simple gated up-counter with async clear
+
+    always @(posedge clk or negedge arst_n) begin
+        if (arst_n == 1'b0) begin
+            q <= {WIDTH {1'b0}};
+            end
+        else begin
+            q <= q;
+            if (ce == 1'b1) begin
+                q <= q + 1;
+            end
+        end
+    end
+
+endmodule

test/markup/verilog/numbers.expect.txt

@@ -0,0 +1,8 @@
+a = <span class="hljs-number">'hff</span>;
+A = <span class="hljs-number">'HFF</span>;
+b = <span class="hljs-number">8'h33</span>;
+B = <span class="hljs-number">8'H33</span>;
+c = <span class="hljs-number">12</span>;
+d = <span class="hljs-number">'o755</span>;
+e = <span class="hljs-number">8'b1001_0001</span>;
+f = <span class="hljs-number">8'b1111zzzx</span>;

test/markup/verilog/numbers.txt

@@ -0,0 +1,8 @@
+a = 'hff;
+A = 'HFF;
+b = 8'h33;
+B = 8'H33;
+c = 12;
+d = 'o755;
+e = 8'b1001_0001;
+f = 8'b1111zzzx;