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Revert "[DAG] getNode() - remove oneuse limit from (zext (trunc (assertzext x))) -> (assertzext x) fold"
This reverts commit 05926a5. Caused AArch64 crash #12 0x00007f09eec09181 skipExtensionForVectorMULL(llvm::SDNode*, llvm::SelectionDAG&) #13 0x00007f09eec08289 llvm::AArch64TargetLowering::LowerMUL(llvm::SDValue, llvm::SelectionDAG&) const #14 0x00007f09eec1a3fd llvm::AArch64TargetLowering::LowerOperation(llvm::SDValue, llvm::SelectionDAG&) const #15 0x00007f09dc8586a7 (anonymous namespace)::VectorLegalizer::LowerOperationWrapper(llvm::SDNode*, llvm::SmallVectorImpl<llvm::SDValue>&)
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4 files changed

+7
-6
lines changed

4 files changed

+7
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llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -5700,7 +5700,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
57005700
if (OpOpcode == ISD::TRUNCATE) {
57015701
SDValue OpOp = N1.getOperand(0);
57025702
if (OpOp.getValueType() == VT) {
5703-
if (OpOp.getOpcode() == ISD::AssertZext) {
5703+
if (OpOp.getOpcode() == ISD::AssertZext && N1->hasOneUse()) {
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APInt HiBits = APInt::getBitsSetFrom(VT.getScalarSizeInBits(),
57055705
N1.getScalarValueSizeInBits());
57065706
if (MaskedValueIsZero(OpOp, HiBits)) {

llvm/lib/Target/X86/X86ISelLoweringCall.cpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -2645,8 +2645,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
26452645
for (;;) {
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// Look through nodes that don't alter the bits of the incoming value.
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unsigned Op = Arg.getOpcode();
2648-
if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST ||
2649-
Op == ISD::AssertZext) {
2648+
if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) {
26502649
Arg = Arg.getOperand(0);
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continue;
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}

llvm/test/CodeGen/AArch64/setcc_knownbits.ll

+2
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,8 @@
44
define i1 @load_bv_v4i8(i1 zeroext %a) {
55
; CHECK-LABEL: load_bv_v4i8:
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; CHECK: // %bb.0:
7+
; CHECK-NEXT: cmp w0, #0
8+
; CHECK-NEXT: cset w0, ne
79
; CHECK-NEXT: ret
810
%b = zext i1 %a to i32
911
%c = icmp eq i32 %b, 1

llvm/test/CodeGen/RISCV/rvv/fold-vp-fadd-and-vp-fmul.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -62,9 +62,9 @@ define <vscale x 1 x double> @fma_reassociate(<vscale x 1 x double> %a, <vscale
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; CHECK-LABEL: fma_reassociate:
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; CHECK: # %bb.0:
6464
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
65-
; CHECK-NEXT: vfmadd.vv v11, v10, v12, v0.t
66-
; CHECK-NEXT: vfmadd.vv v9, v8, v11, v0.t
67-
; CHECK-NEXT: vmv.v.v v8, v9
65+
; CHECK-NEXT: vfmadd.vv v9, v8, v12, v0.t
66+
; CHECK-NEXT: vfmadd.vv v11, v10, v9, v0.t
67+
; CHECK-NEXT: vmv.v.v v8, v11
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; CHECK-NEXT: ret
6969
%1 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %a, <vscale x 1 x double> %b, <vscale x 1 x i1> %m, i32 %vl)
7070
%2 = call fast <vscale x 1 x double> @llvm.vp.fmul.nxv1f64(<vscale x 1 x double> %c, <vscale x 1 x double> %d, <vscale x 1 x i1> %m, i32 %vl)

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