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Lu, John
committed
Revert opaquify changes for tests that run ESIMDLowerVecArg pass. This pass requires typed pointers.
Signed-off-by: Lu, John <[email protected]>
1 parent 509fe11 commit 887ab89

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7 files changed

+114
-98
lines changed

7 files changed

+114
-98
lines changed

‎llvm/test/SYCLLowerIR/ESIMD/global.ll

+38-32
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ $"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test" = comdat any
1414
@0 = dso_local global %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" zeroinitializer, align 64 #0
1515

1616
; Function Attrs: norecurse
17-
define weak_odr dso_local spir_kernel void @"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test"(ptr addrspace(1) %_arg_) local_unnamed_addr #1 comdat !kernel_arg_addr_space !8 !kernel_arg_access_qual !9 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !11 !sycl_explicit_simd !12 !intel_reqd_sub_group_size !8 {
17+
define weak_odr dso_local spir_kernel void @"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test"(i32 addrspace(1)* %_arg_) local_unnamed_addr #1 comdat !kernel_arg_addr_space !8 !kernel_arg_access_qual !9 !kernel_arg_type !10 !kernel_arg_base_type !10 !kernel_arg_type_qual !11 !sycl_explicit_simd !12 !intel_reqd_sub_group_size !8 {
1818
entry:
1919
%vc.i = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
2020
%agg.tmp.i = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
@@ -36,57 +36,63 @@ entry:
3636
%group.id.x.cast.ty.i.i.i.i.i = zext i32 %group.id.x.i.i.i.i.i to i64
3737
%mul.i4.i.i.i.i = mul nuw i64 %group.id.x.cast.ty.i.i.i.i.i, %wgsize.x.cast.ty.i.i.i.i.i
3838
%add.i5.i.i.i.i = add i64 %mul.i4.i.i.i.i, %local_id.x.cast.ty.i.i.i.i.i
39-
call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %agg.tmp.i)
40-
call void @llvm.lifetime.start.p0(i64 64, ptr nonnull %vc.i) #5
39+
%0 = bitcast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp.i to i8*
40+
call void @llvm.lifetime.start.p0i8(i64 64, i8* nonnull %0)
41+
%1 = bitcast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %vc.i to i8*
42+
call void @llvm.lifetime.start.p0i8(i64 64, i8* nonnull %1) #5
4143
%conv.i = trunc i64 %add.i5.i.i.i.i to i32
42-
%0 = addrspacecast ptr %vc.i to ptr addrspace(4)
44+
%2 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %vc.i to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
4345
%splat.splatinsert.i.i = insertelement <16 x i32> undef, i32 %conv.i, i32 0
4446
%splat.splat.i.i = shufflevector <16 x i32> %splat.splatinsert.i.i, <16 x i32> undef, <16 x i32> zeroinitializer
45-
store <16 x i32> %splat.splat.i.i, ptr addrspace(4) %0, align 64, !tbaa !13
47+
%M_data.i13.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %2, i64 0, i32 0
48+
store <16 x i32> %splat.splat.i.i, <16 x i32> addrspace(4)* %M_data.i13.i, align 64, !tbaa !13
4649
%conv3.i = trunc i64 %add.i.i.i.i.i to i32
4750
%splat.splatinsert.i20.i = insertelement <8 x i32> undef, i32 %conv3.i, i32 0
4851
%splat.splat.i21.i = shufflevector <8 x i32> %splat.splatinsert.i20.i, <8 x i32> undef, <8 x i32> zeroinitializer
49-
%call.esimd.i.i.i.i.i2 = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) %0) #5
52+
%call.esimd.i.i.i.i.i2 = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i13.i) #5
5053
%call4.esimd.i.i.i.i = call <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.i16.v8i1(<16 x i32> %call.esimd.i.i.i.i.i2, <8 x i32> %splat.splat.i21.i, i32 0, i32 8, i32 1, i16 0, i32 0, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>) #5
51-
call void @llvm.genx.vstore.v16i32.p4(<16 x i32> %call4.esimd.i.i.i.i, ptr addrspace(4) %0) #5
54+
call void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %call4.esimd.i.i.i.i, <16 x i32> addrspace(4)* %M_data.i13.i) #5
5255
%cmp.i = icmp eq i64 %add.i.i.i.i.i, 0
5356
%..i = select i1 %cmp.i, i64 %add.i5.i.i.i.i, i64 %add.i.i.i.i.i
5457
%conv9.i = trunc i64 %..i to i32
55-
; CHECK: store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, ptr addrspace(4) addrspacecast (ptr [[NEWGLOBAL]] to ptr addrspace(4)), align 64, !tbaa.struct !16
56-
store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, ptr addrspace(4) addrspacecast (ptr @0 to ptr addrspace(4)), align 64, !tbaa.struct !16
58+
; CHECK: store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds ({{.+}}, {{.+}}* bitcast (<16 x i32>* [[NEWGLOBAL]] to {{.+}}*), i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
59+
store <16 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
5760
%mul.i = shl nsw i32 %conv9.i, 4
5861
%idx.ext.i = sext i32 %mul.i to i64
59-
%add.ptr.i16 = getelementptr inbounds i32, ptr addrspace(1) %_arg_, i64 %idx.ext.i
60-
%add.ptr.i = addrspacecast ptr addrspace(1) %add.ptr.i16 to ptr addrspace(4)
61-
%1 = addrspacecast ptr %agg.tmp.i to ptr addrspace(4)
62-
%call.esimd.i.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) %0) #5
63-
call void @llvm.genx.vstore.v16i32.p4(<16 x i32> %call.esimd.i.i.i, ptr addrspace(4) %1) #5
64-
call spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(ptr addrspace(4) %add.ptr.i, ptr nonnull %agg.tmp.i) #5
65-
store <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, ptr addrspace(4) addrspacecast (ptr @0 to ptr addrspace(4)), align 64, !tbaa.struct !16
66-
call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %vc.i) #5
67-
call void @llvm.lifetime.end.p0(i64 64, ptr nonnull %agg.tmp.i)
62+
%add.ptr.i16 = getelementptr inbounds i32, i32 addrspace(1)* %_arg_, i64 %idx.ext.i
63+
%add.ptr.i = addrspacecast i32 addrspace(1)* %add.ptr.i16 to i32 addrspace(4)*
64+
%3 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp.i to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
65+
%call.esimd.i.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i13.i) #5
66+
%M_data.i2.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %3, i64 0, i32 0
67+
call void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %call.esimd.i.i.i, <16 x i32> addrspace(4)* %M_data.i2.i.i) #5
68+
call spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(i32 addrspace(4)* %add.ptr.i, %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* nonnull %agg.tmp.i) #5
69+
store <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>, <16 x i32> addrspace(4)* addrspacecast (<16 x i32>* getelementptr inbounds (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0, i64 0, i32 0) to <16 x i32> addrspace(4)*), align 64, !tbaa.struct !16
70+
call void @llvm.lifetime.end.p0i8(i64 64, i8* nonnull %1) #5
71+
call void @llvm.lifetime.end.p0i8(i64 64, i8* nonnull %0)
6872
ret void
6973
}
7074

7175
; Function Attrs: argmemonly nounwind willreturn
72-
declare void @llvm.lifetime.start.p0(i64 immarg %agg.tmp.i, ptr nocapture %vc.i) #2
76+
declare void @llvm.lifetime.start.p0i8(i64 immarg %0, i8* nocapture %1) #2
7377

7478
; Function Attrs: argmemonly nounwind willreturn
75-
declare void @llvm.lifetime.end.p0(i64 immarg %agg.tmp.i, ptr nocapture %vc.i) #2
79+
declare void @llvm.lifetime.end.p0i8(i64 immarg %0, i8* nocapture %1) #2
7680

7781
; Function Attrs: noinline norecurse nounwind
78-
define dso_local spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(ptr addrspace(4) %C, ptr %v) local_unnamed_addr #3 {
82+
define dso_local spir_func void @_Z3fooPiN2cl4sycl5INTEL3gpu4simdIiLi16EEE(i32 addrspace(4)* %C, %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %v) local_unnamed_addr #3 {
7983
entry:
8084
%agg.tmp = alloca %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", align 64
81-
%0 = addrspacecast ptr %v to ptr addrspace(4)
82-
%1 = addrspacecast ptr %agg.tmp to ptr addrspace(4)
83-
%call.esimd.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) %0), !noalias !17
84-
; CHECK: {{.+}} = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) addrspacecast (ptr [[NEWGLOBAL]] to ptr addrspace(4))), !noalias !17
85-
%call.esimd.i8.i = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) addrspacecast (ptr @0 to ptr addrspace(4))), !noalias !17
85+
%0 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %v to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
86+
%1 = addrspacecast %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* %agg.tmp to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*
87+
%M_data.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %0, i64 0, i32 0
88+
%call.esimd.i.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i.i), !noalias !17
89+
; CHECK: {{.+}} = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* getelementptr ({{.+}}, {{.+}} addrspace(4)* addrspacecast ({{.+}}* bitcast (<16 x i32>* [[NEWGLOBAL]] to {{.+}}*) to {{.+}} addrspace(4)*), i64 0, i32 0)), !noalias !17
90+
%call.esimd.i8.i = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* getelementptr (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* addrspacecast (%"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd"* @0 to %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)*), i64 0, i32 0)), !noalias !17
8691
%add.i = add <16 x i32> %call.esimd.i8.i, %call.esimd.i.i
87-
call void @llvm.genx.vstore.v16i32.p4(<16 x i32> %add.i, ptr addrspace(4) %1)
88-
%2 = ptrtoint ptr addrspace(4) %C to i64
89-
%call.esimd.i.i2 = call <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) %1)
92+
%M_data.i.i.i = getelementptr inbounds %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd", %"class._ZTSN2cl4sycl5INTEL3gpu4simdIiLi16EEE.cl::sycl::INTEL::gpu::simd" addrspace(4)* %1, i64 0, i32 0
93+
call void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %add.i, <16 x i32> addrspace(4)* %M_data.i.i.i)
94+
%2 = ptrtoint i32 addrspace(4)* %C to i64
95+
%call.esimd.i.i2 = call <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %M_data.i.i.i)
9096
call void @llvm.genx.svm.block.st.v16i32(i64 %2, <16 x i32> %call.esimd.i.i2)
9197
ret void
9298
}
@@ -95,10 +101,10 @@ entry:
95101
declare !genx_intrinsic_id !20 <16 x i32> @llvm.genx.wrregioni.v16i32.v8i32.i16.v8i1(<16 x i32> %0, <8 x i32> %1, i32 %2, i32 %3, i32 %4, i16 %5, i32 %6, <8 x i1> %7) #4
96102

97103
; Function Attrs: nounwind
98-
declare !genx_intrinsic_id !21 <16 x i32> @llvm.genx.vload.v16i32.p4(ptr addrspace(4) %0) #5
104+
declare !genx_intrinsic_id !21 <16 x i32> @llvm.genx.vload.v16i32.p4v16i32(<16 x i32> addrspace(4)* %0) #5
99105

100106
; Function Attrs: nounwind
101-
declare !genx_intrinsic_id !22 void @llvm.genx.vstore.v16i32.p4(<16 x i32> %0, ptr addrspace(4) %1) #5
107+
declare !genx_intrinsic_id !22 void @llvm.genx.vstore.v16i32.p4v16i32(<16 x i32> %0, <16 x i32> addrspace(4)* %1) #5
102108

103109
; Function Attrs: nounwind
104110
declare !genx_intrinsic_id !23 void @llvm.genx.svm.block.st.v16i32(i64 %0, <16 x i32> %1) #5
@@ -134,7 +140,7 @@ attributes #5 = { nounwind }
134140
!2 = !{i32 1, i32 2}
135141
!3 = !{i32 6, i32 100000}
136142
!4 = !{!"clang version 11.0.0"}
137-
!5 = !{ptr @"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test", !"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test", !6, i32 0, i32 0, !6, !7, i32 0, i32 0}
143+
!5 = !{void (i32 addrspace(1)*)* @"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test", !"_ZTSZZ4mainENK3$_0clERN2cl4sycl7handlerEE4Test", !6, i32 0, i32 0, !6, !7, i32 0, i32 0}
138144
!6 = !{i32 0}
139145
!7 = !{!"svmptr_t"}
140146
!8 = !{i32 1}

‎llvm/test/SYCLLowerIR/ESIMD/global_crash.ll

+6-4
Original file line numberDiff line numberDiff line change
@@ -14,11 +14,13 @@ target triple = "spir64-unknown-unknown"
1414

1515
define void @no_crash(<2512 x i32> %simd_val) {
1616
; CHECK-LABEL: @no_crash(
17-
; CHECK-NEXT: [[CAST:%.*]] = addrspacecast ptr @Global to ptr addrspace(4)
18-
; CHECK-NEXT: store <2512 x i32> [[SIMD_VAL:%.*]], ptr addrspace(4) [[CAST]], align 16384
17+
; CHECK-NEXT: [[CAST:%.*]] = addrspacecast %"class.cl::sycl::INTEL::gpu::simd"* bitcast (<2512 x i32>* @Global to %"class.cl::sycl::INTEL::gpu::simd"*) to %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)*
18+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr %"class.cl::sycl::INTEL::gpu::simd", %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)* [[CAST]], i64 0, i32 0
19+
; CHECK-NEXT: store <2512 x i32> [[SIMD_VAL:%.*]], <2512 x i32> addrspace(4)* [[GEP]], align 16384
1920
; CHECK-NEXT: ret void
2021
;
21-
%cast = addrspacecast ptr @Global to ptr addrspace(4)
22-
store <2512 x i32> %simd_val, ptr addrspace(4) %cast, align 16384
22+
%cast = addrspacecast %"class.cl::sycl::INTEL::gpu::simd"* @Global to %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)*
23+
%gep = getelementptr %"class.cl::sycl::INTEL::gpu::simd", %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)* %cast, i64 0, i32 0
24+
store <2512 x i32> %simd_val, <2512 x i32> addrspace(4)* %gep, align 16384
2325
ret void
2426
}

‎llvm/test/SYCLLowerIR/ESIMD/global_undef.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -14,9 +14,9 @@ target triple = "spir64-unknown-unknown"
1414

1515
define void @f(<2512 x i32> %simd_val) {
1616
; CHECK-LABEL: @f(
17-
; CHECK-NEXT: store <2512 x i32> [[SIMD_VAL:%.*]], ptr addrspace(4) addrspacecast (ptr @Global to ptr addrspace(4)), align 16384
17+
; CHECK-NEXT: store <2512 x i32> [[SIMD_VAL:%.*]], <2512 x i32> addrspace(4)* getelementptr (%"class.cl::sycl::INTEL::gpu::simd", %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)* addrspacecast (%"class.cl::sycl::INTEL::gpu::simd"* bitcast (<2512 x i32>* @Global to %"class.cl::sycl::INTEL::gpu::simd"*) to %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)*), i64 0, i32 0), align 16384
1818
; CHECK-NEXT: ret void
1919
;
20-
store <2512 x i32> %simd_val, ptr addrspace(4) addrspacecast (ptr @Global to ptr addrspace(4)), align 16384
20+
store <2512 x i32> %simd_val, <2512 x i32> addrspace(4)* getelementptr (%"class.cl::sycl::INTEL::gpu::simd", %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)* addrspacecast (%"class.cl::sycl::INTEL::gpu::simd"* @Global to %"class.cl::sycl::INTEL::gpu::simd" addrspace(4)*), i64 0, i32 0), align 16384
2121
ret void
2222
}

‎llvm/test/SYCLLowerIR/ESIMD/lower_vec_arg_fp.ll

+15-15
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66

77
%"cl::sycl::INTEL::gpu::simd" = type { <64 x i32> }
88

9-
define dso_local spir_func void @func(ptr %arg) {
9+
define dso_local spir_func void @func(%"cl::sycl::INTEL::gpu::simd"* %arg) {
1010
; CHECK-LABEL: @func(
1111
; CHECK-NEXT: entry:
1212
; CHECK-NEXT: ret void
@@ -15,44 +15,44 @@ entry:
1515
ret void
1616
}
1717

18-
define dso_local spir_func void @init_ptr(ptr %foo) !sycl_explicit_simd !1 {
18+
define dso_local spir_func void @init_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)** %foo) !sycl_explicit_simd !1 {
1919
; CHECK-LABEL: @init_ptr(
2020
; CHECK-NEXT: entry:
21-
; CHECK-NEXT: store ptr @func, ptr [[FOO:%.*]], align 8
21+
; CHECK-NEXT: store void (%"cl::sycl::INTEL::gpu::simd"*)* @func, void (%"cl::sycl::INTEL::gpu::simd"*)** [[FOO:%.*]], align 8
2222
; CHECK-NEXT: ret void
2323
;
2424
entry:
25-
store ptr @func, ptr %foo
25+
store void (%"cl::sycl::INTEL::gpu::simd"*)* @func, void (%"cl::sycl::INTEL::gpu::simd"*)** %foo
2626
ret void
2727
}
2828

29-
define dso_local spir_func void @use_ptr(ptr %foo) !sycl_explicit_simd !1 {
29+
define dso_local spir_func void @use_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)* %foo) !sycl_explicit_simd !1 {
3030
; CHECK-LABEL: @use_ptr(
3131
; CHECK-NEXT: entry:
3232
; CHECK-NEXT: [[AGG_TMP:%.*]] = alloca %"cl::sycl::INTEL::gpu::simd", align 256
33-
; CHECK-NEXT: call spir_func void [[FOO:%.*]](ptr [[AGG_TMP]])
33+
; CHECK-NEXT: call spir_func void [[FOO:%.*]](%"cl::sycl::INTEL::gpu::simd"* [[AGG_TMP]])
3434
; CHECK-NEXT: ret void
3535
;
3636
entry:
3737
%agg.tmp = alloca %"cl::sycl::INTEL::gpu::simd"
38-
call spir_func void %foo(ptr %agg.tmp)
38+
call spir_func void %foo(%"cl::sycl::INTEL::gpu::simd"* %agg.tmp)
3939
ret void
4040
}
4141

4242
define dso_local spir_func void @esimd_kernel() !sycl_explicit_simd !1 {
4343
; CHECK-LABEL: @esimd_kernel(
4444
; CHECK-NEXT: entry:
45-
; CHECK-NEXT: [[FP:%.*]] = alloca ptr, align 8
46-
; CHECK-NEXT: call spir_func void @init_ptr(ptr [[FP]])
47-
; CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP]], align 8
48-
; CHECK-NEXT: call spir_func void @use_ptr(ptr [[TMP0]])
45+
; CHECK-NEXT: [[FP:%.*]] = alloca void (%"cl::sycl::INTEL::gpu::simd"*)*, align 8
46+
; CHECK-NEXT: call spir_func void @init_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)** [[FP]])
47+
; CHECK-NEXT: [[TMP0:%.*]] = load void (%"cl::sycl::INTEL::gpu::simd"*)*, void (%"cl::sycl::INTEL::gpu::simd"*)** [[FP]], align 8
48+
; CHECK-NEXT: call spir_func void @use_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)* [[TMP0]])
4949
; CHECK-NEXT: ret void
5050
;
5151
entry:
52-
%fp = alloca ptr
53-
call spir_func void @init_ptr(ptr %fp)
54-
%0 = load ptr, ptr %fp
55-
call spir_func void @use_ptr(ptr %0)
52+
%fp = alloca void (%"cl::sycl::INTEL::gpu::simd"*)*
53+
call spir_func void @init_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)** %fp)
54+
%0 = load void (%"cl::sycl::INTEL::gpu::simd"*)*, void (%"cl::sycl::INTEL::gpu::simd"*)** %fp
55+
call spir_func void @use_ptr(void (%"cl::sycl::INTEL::gpu::simd"*)* %0)
5656
ret void
5757
}
5858

‎llvm/test/SYCLLowerIR/ESIMD/lower_vec_arg_fp_metadata.ll

+3-3
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,15 @@
66

77
$foo = comdat any
88

9-
define weak_odr dso_local spir_kernel void @foo(ptr addrspace(1) noundef align 16 %_arg_out) local_unnamed_addr comdat {
9+
define weak_odr dso_local spir_kernel void @foo(%"class.sycl::_V1::vec" addrspace(1)* noundef align 16 %_arg_out) local_unnamed_addr comdat {
1010
entry:
1111
ret void
1212
}
1313

1414
;CHECK: !genx.kernels = !{![[GenXMD:[0-9]+]]}
1515
!genx.kernels = !{!0}
1616

17-
;CHECK: ![[GenXMD]] = !{ptr @foo, {{.*}}}
18-
!0 = !{ptr @foo, !"foo", !1, i32 0, i32 0, !1, !2, i32 0, i32 0}
17+
;CHECK: ![[GenXMD]] = !{void (<2 x double> addrspace(1)*)* @foo, {{.*}}}
18+
!0 = !{void (%"class.sycl::_V1::vec" addrspace(1)*)* @foo, !"foo", !1, i32 0, i32 0, !1, !2, i32 0, i32 0}
1919
!1 = !{i32 0}
2020
!2 = !{!"svmptr_t"}

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